Memory device using semiconductor elements

Abstract

To achieve higher integration and higher performance of memory elements. [Solution] In a plan view, there are gate conductor layers WL, PL, and WL2 for word lines and plate lines that extend vertically between channel semiconductor layers 10a and 10b that are parallel to the substrate 1, and back gate conductor layers BG1 and BG2 on the outside. N is in contact with one end of the channel semiconductor layers 10a and 10b + Regions 11aa and 11ba are independently connected to source lines SL1 and SL2 that extend vertically, and the other end of N + Regions 11aa and 11ab are connected to a single bit line BL1 that extends horizontally. During data writing or reading, the source line voltage of one of the source lines SL1 and SL2 is set to be the same as the bit line voltage, and the voltage of the other source line is set to create a voltage difference between the source line and the bit line, thereby allowing current to flow between the source line and the bit line. This enables the writing or reading of logical "1" data from one of the memory cells in the channel semiconductor layers 10a1 and 10a2.

Description

Technical Field

[0001] The present invention relates to a memory device using semiconductor elements.

Background Art

[0002] In recent years, in the development of LSI (Large Scale Integration) technology, higher integration and higher performance of memory elements have been demanded.

[0003] As conventional memory elements, a DRAM (Dynamic Random Access Memory, see, for example, Non-Patent Document 2) with a capacitor connected using an SGT (Surrounding Gate Transistor, see Patent Document 1 and Non-Patent Document 1) as a selection transistor, a PCM (Phase Change Memory, see, for example, Non-Patent Document 3) with a resistive change element connected, a RRAM (Resistive Random Access Memory, see, for example, Non-Patent Document 4), and an MRAM (Magneto-resistive Random Access Memory, see, for example, Non-Patent Document 5) that changes the resistance by changing the direction of magnetic spin with current, etc. are available.

[0004] In addition, there are DRAM memory cells (see Patent Document 2 and Non-Patent Documents 6 to 10) composed of one MOS transistor without a capacitor. In such a DRAM memory cell, for example, among the holes and electrons generated by the impact ionization phenomenon in the channel due to the source-drain current of an N-channel MOS transistor, a part or all of the holes are retained in the channel to write the logical memory data "1". Then, the holes are removed from the channel to write the logical memory data "0". In this memory cell, for a common selection word line, there are randomly memory cells for writing "1" and memory cells for writing "0". When an on-voltage is applied to the selection word line, the floating body channel voltage of the selected memory cell connected to this selection word line varies greatly due to the capacitive coupling between the gate electrode and the channel. In this memory cell, improving the reduction of the operation margin due to the floating body channel voltage fluctuation and improving the reduction of the data retention characteristics due to the removal of a part of the holes, which are the signal charges stored in the channel, are issues.

[0005] In addition, there is a Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors on an SOI (Silicon On Insulator) layer (see, for example, Patent Documents 3 and 4 and Non-Patent Document 11). In these elements, the N + region serving as the source or drain that separates the floating body channels of the two MOS transistors is formed in contact with an insulating layer on the substrate side. By this N + region, the floating body channels of the two MOS transistors are electrically separated. The hole group, which is the signal charge, is accumulated only in the floating body channel of one MOS transistor. The other MOS transistor serves as a switch for reading the hole group of the signal stored in one MOS transistor.

[0006] Also, there is a dynamic flash memory cell 111 composed of MOS transistors without a capacitor, as shown in FIG. 7 (see Patent Documents 5 and 6, and Non-Patent Document 12). As shown in FIG. 6(a), there is a floating body semiconductor matrix 102 on the SiO2 layer 101 of the SOI substrate. At both ends of the floating body semiconductor matrix 102, there are N + regions 103 connected to the source line SL and N + regions 104 connected to the bit line BL. And there is a first gate insulating layer 109a that is connected to the N + region 103 and covers the floating body semiconductor matrix 102, and a second gate insulating layer 109b that is connected to the N + region 104 and is connected to the first gate insulating layer 109a via the slit insulating film 110 and covers the floating body semiconductor matrix 102. And there is a first gate conductor layer 105a that covers the first gate insulating layer 109a and is connected to the plate line PL, and a second gate conductor layer 105b that covers the second gate insulating layer 109b and is connected to the word line WL. And there is a slit insulating layer 110 between the first gate conductor layer 105a and the second gate conductor layer 105b. Thus, a memory cell 111 of DFM (Dynamic Flash Memory) is formed. Note that the source line SL may be connected to the N + region 104 and the bit line BL may be connected to the N + region 103.

[0007] [[ID=...]] And, as shown in FIG. 7(a), for example, a zero voltage is applied to the N + region 103, and N +A positive voltage is applied to region 104, causing the first N-channel MOS transistor region, consisting of a floating body semiconductor matrix 102 covered with a first gate conductor layer 105a, to operate in the linear region, and the second N-channel MOS transistor region, consisting of a floating body semiconductor matrix 102 covered with a second gate conductor layer 105b, to operate in the saturation region. As a result, an inversion layer 107b is formed over the entire surface of the second N-channel MOS transistor region without any pinch-off points. This inversion layer 107b, formed below the second gate conductor layer 105b connected to the word line WL, acts as a de facto drain of the first N-channel MOS transistor region. Consequently, the electric field is maximized in the channel region boundary region between the first N-channel MOS transistor region and the second N-channel MOS transistor region, and the impact ionization phenomenon occurs in this region. Then, as shown in Figure 7(b), the memory write operation is performed by removing the electron group from the electron-hole group generated by the impact ionization phenomenon from the floating body semiconductor matrix 102, and retaining some or all of the hole group 106 in the floating body semiconductor matrix 102. This state becomes logical memory data "1".

[0008] Then, as shown in Figure 7(c), for example, a positive voltage is applied to the plate line PL, a zero voltage to the word line WL and bit line BL, and a negative voltage to the source line SL to remove the hole group 106 from the floating body semiconductor matrix 102 and perform an erase operation. This state becomes logical memory data "0". Then, during data reading, by setting the voltage applied to the first gate conductor layer 105a connected to the plate line PL to be higher than the threshold voltage when the logical memory data is "1" and lower than the threshold voltage when the logical memory data is "0", a characteristic is obtained in which no current flows even if the voltage of the word line WL is increased when reading logical memory data "0", as shown in Figure 6(d). This characteristic allows for a significantly larger operating margin compared to memory cells. In this memory cell, the channels of the first and second N-channel MOS transistor regions, with the first gate conductor layer 105a connected to the plate line PL and the second gate conductor layer 105b connected to the word line WL as gates, are connected by a floating body semiconductor matrix 102. As a result, voltage fluctuations in the floating body semiconductor matrix 102 when a selective pulse voltage is applied to the word line WL are greatly suppressed. This greatly improves the problems of reduced operating margin or reduced data retention characteristics due to the removal of some of the hole group, which is the signal charge accumulated in the channel, in the aforementioned memory cell. High integration can be achieved by forming multiple dynamic flash memory cells perpendicular to the substrate (Patent Document 6). In such dynamic flash memory, memory cells are configured adjacent to each other in the vertical and horizontal directions, so measures are required to reduce interference between adjacent memory cells and to facilitate manufacturing. Furthermore, further improvement of characteristics and high integration are required.

[0009] In addition, during the "1" writing process, electron-hole pairs may be generated using the gate-induced drain leakage (GIDL) current described in Non-Patent Document 10, and the resulting group of holes may fill the floating body FB. [Prior art documents] [Patent Documents]

[0010] [License 1] Special Announcement No. 2-188966 [License 2] Special Announcement No. 3-171768 [License 3] US2008 / 0137394 A1 [License 4] US2003 / 0111681 A1 [Patent Document 5] Patent No. 7057032 [License 6] US2022 / 0208254 A1 [Non-licensed literature]

[0011] [Non-licensed Document 1] Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573-578 (1991) [Non-licensed Document 2] H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. Dong, J. Kim, YC Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung: “4F2 DRAM Cell with Vertical Pillar Transistor(VPT),” 2011 Proceeding of the European Solid-State Device Research Conference, (2011) [Non-licensed Document 3] HS Philip Wong, S. Raoux, S. Kim, Jiale Liang, JR Reifenberg, B. Rajendran, M. Asheghi and KE Goodson: “Phase Change Memory,” Proceeding of IEEE, Vol.

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[0012] One aspect of the present invention is a memory device having a first channel semiconductor layer and a second channel semiconductor layer that are spaced perpendicular to a substrate and stretched parallel to the horizontal direction, A first impurity region and a second impurity region are in contact with both ends of the first channel semiconductor layer, A third impurity region and a fourth impurity region are in contact with both ends of the second channel semiconductor layer, A first gate insulating layer located opposite the second channel semiconductor layer and in contact with the vertical side surface of the first channel semiconductor layer, A second gate insulating layer located on the second channel semiconductor layer side, in contact with the vertical side surface of the first channel semiconductor layer, A third gate insulating layer located on the first channel semiconductor layer side and in contact with the vertical side surface of the second channel semiconductor layer, A fourth gate insulating layer located opposite the first channel semiconductor layer and in contact with the vertical side surface of the second channel semiconductor layer, A first gate conductor layer consisting of two or three or more layers, which are in contact with the second gate insulating layer and the third gate insulating layer and are aligned in the stretching direction of the first channel semiconductor layer and the second channel semiconductor layer, A second gate conductor layer consisting of one or more layers in contact with the first gate insulating layer and arranged in the stretching direction, A third gate conductor layer consisting of one or more layers arranged in the stretching direction and in contact with the fourth gate insulating layer. It has, The first channel semiconductor layer and the second channel semiconductor layer are arranged to be aligned in substantially the same shape when viewed in a direction perpendicular to the stretching direction of the first channel semiconductor layer and the second channel semiconductor layer, and when viewed in a direction perpendicular to the stretching direction of the first channel semiconductor layer and the direction perpendicular to the substrate. The first memory cell includes the first channel semiconductor layer, the first impurity region, the second impurity region, the first gate insulating layer, the second gate insulating layer, the first gate conductor layer, and the second gate conductor layer. The second memory cell includes the second channel semiconductor layer, the third impurity region, the fourth impurity region, the third gate insulating layer, the fourth gate insulating layer, the second gate conductor layer, and the third gate conductor layer. The second gate conductor layer is shared by the first memory cell and the second memory cell. The first impurity region is connected to a first source line extending vertically, and the third impurity region is connected to a second source line extending vertically. The second and fourth impurity regions are connected to a first bit line that extends horizontally, During the data writing period and the data reading period, The memory device is configured to write or read logical "1" data in the memory cell of the first channel semiconductor layer by applying a first voltage to the first bit line, applying a second voltage to the first source line to allow an on-current to flow through the first channel semiconductor layer, and applying the same first voltage to the second source line as the first bit line, and then applying the same first voltage to the first bit line, applying a second voltage to the second source line to allow an on-current to flow through the second channel semiconductor layer, and applying the same first voltage to the first source line as the first bit line, thereby writing or reading logical "1" data in the memory cell of the second channel semiconductor layer. This invention provides a memory device using semiconductor elements characterized by the following features.

[0013] The memory device may be configured such that, when writing or reading the logic "1" data, a pulse voltage is applied to the second gate conductor layer, a fixed voltage is maintained in the first gate conductor layer and the third gate conductor layer, and when a pulse voltage is applied to the first gate conductor layer and the third gate conductor layer, a fixed voltage is maintained in the second gate conductor layer.

[0014] The first gate conductor layer, the second gate conductor layer, and the third gate conductor layer consist of three conductor layer portions arranged to be substantially identical in shape when viewed in a direction perpendicular to the stretching direction of the first channel semiconductor layer and the second channel semiconductor layer, and in a direction perpendicular to the stretching direction of the first channel semiconductor layer and the direction perpendicular to the substrate, and the conductor layer portions at both ends in the stretching direction of each of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer can be wired together.

[0015] In a plan view, the positions of both ends of the second gate conductor layer and the third gate conductor layer can be considered to coincide with the positions of both ends of the first gate conductor layer in the stretching direction of the first and second channel semiconductor layers.

[0016] In a plan view, in the stretching direction of the first and second channel semiconductor layers, the positions of both ends of the second gate conductor layer and the third gate conductor layer may coincide with the positions of both ends of any one of the multiple conductor layer portions of the first gate conductor layer.

[0017] In a plan view, in the stretching direction of the first and second channel semiconductor layers, the positions of both ends of the second gate conductor layer and the third gate conductor layer are located outside the positions of both ends that include the entirety of at least one partial conductor layer portion of the first gate conductor layer, and the positions of one end or both ends of the second gate conductor layer and the positions of one end or both ends of the third gate conductor layer are located inside the positions of both ends of the conductor layer portion of the first gate conductor layer other than the other at least one conductor layer portion.

[0018] The memory device may be configured such that, during the logic "1" data writing period and the logic "1" data reading period, if the signal charge is a group of holes, a voltage higher than the voltage applied to the first gate conductor layer is applied to the second and third gate conductor layers, and if the signal charge is a group of electrons, a voltage lower than the voltage applied to the first gate conductor layer is applied to the second and third gate conductor layers.

[0019] The memory device may, during the logic "1" data writing period, accumulate a group of holes or electrons, which are signals generated by the impact ionization phenomenon or gate-induced drain current, in the first channel semiconductor layer or the second channel semiconductor layer, by a current flowing through either the first channel semiconductor layer connected to the first source line or the second channel semiconductor layer connected to the second source line.

[0020] Multiple memory cell units, each comprising the first memory cell and the second memory cell, are arranged such that they are aligned in substantially the same shape when viewed in a direction perpendicular to the stretching direction of the first channel semiconductor layer and the second channel semiconductor layer and the direction perpendicular to the substrate. For each source line connected to each memory cell, there are multiple source line groups consisting of a predetermined number of source lines spaced apart. Each source wire constituting each source wire group extends in the same direction, and this same direction is either vertically upward or vertically downward. Each source line group can be considered to be connected to a mutually independent coupled source line corresponding to each of the source line groups.

[0021] The coupling source line may be positioned above or below the first channel semiconductor layer and the second semiconductor layer, separated vertically above the substrate.

[0022] The independent coupling source lines may be arranged on the same plane parallel to the substrate, vertically above the group of memory cells connected to the independent coupling source lines, or on the same plane vertically below the group of memory cells relative to the substrate.

[0023] The independent coupling source lines may be arranged on a plurality of planes parallel to the substrate and perpendicularly above the group of memory cells with respect to the substrate, or on a plurality of planes parallel to the substrate and perpendicularly below the group of memory cells with respect to the substrate.

[0024] The memory device may be configured such that, during the data erasure period, both the first channel semiconductor layer and the second channel semiconductor layer have a group of signal charges of holes or electrons indicating the logic "1" data, and in the operation to erase the logic "1" data from only one of them, the data erasure is performed on the group of signal charges of holes or electrons indicating the logic "1" data from both the first channel semiconductor layer and the second channel semiconductor layer, and then the logic "1" data is rewritten to either the first channel semiconductor layer or the second channel semiconductor layer that holds the logic "1" data.

[0025] The memory device may be configured such that, during the data erasure period, a plurality of memory cells including the first channel semiconductor layer and the second channel semiconductor layer are configured as a single block, and after block erasure in which the data of all the memory cells in the block is erased at once, the logical "1" data is written to a predetermined memory cell.

[0026] The memory device may be configured such that, during the data erasure period, the same voltage is applied to both the first bit line and the second source line, and if the signal charge group is a hole, a voltage lower than the voltage applied to the first bit line and the second source line is applied to the first source line, or if the signal charge group is an electron, a voltage higher than the voltage applied to the first bit line and the second source line is applied to the first source line.

[0027] The second gate conductor layer and the third gate conductor layer can be configured such that, in a plan view, they are separated into two gate conductor layers in the central portion in a direction perpendicular to the direction in which the first channel semiconductor layer and the second channel semiconductor layer are extended.

[0028] The memory device may be configured such that, during the period in which a pulse voltage is applied to one of the two gate conductor layers separated in the central part, a fixed voltage that does not change over time is applied to the other gate conductor layer.

[0029] The memory device is configured such that, during the data retention period, if the signal charge is a group of holes, the voltage applied to the second and third gate conductor layers is the same as or lower than the voltage applied to the first gate conductor layer, and if the signal charge is a group of electrons, the voltage applied to the second and third gate conductor layers is the same as or higher than the voltage applied to the first gate conductor layer.

[0030] The second gate conductor layer and the third gate conductor layer each have two separate conductor layer portions aligned in the stretching direction, and each of these two conductor layer portions is arranged to be substantially identical in shape when viewed in a direction perpendicular to the stretching direction and the direction perpendicular to the substrate. The memory device is During the data retention period, in the second and third gate conductor layers, where the signal charge is a group of holes and is separated into two, a voltage lower than the voltage applied to the other gate conductor layer may be applied to one gate conductor layer, and in the second and third gate conductor layers, where the signal charge is a group of electrons and is separated into two, a voltage higher than the voltage applied to the other gate conductor layer may be applied to one gate conductor layer.

[0031] The second gate conductor layer and the third gate conductor layer each have three separate conductor layer portions aligned in the stretching direction, and each of these three conductor layer portions is arranged to be substantially identical in shape when viewed in a direction perpendicular to the stretching direction of the first channel semiconductor layer and the second channel semiconductor layer and the direction perpendicular to the substrate. The memory device is During the data retention period, in the second and third gate conductor layers, where the signal charge is a group of holes and is separated into three parts, the central gate conductor layer may be subjected to a voltage lower than the voltage applied to the gate conductor layers on either side. In the second and third gate conductor layers, where the signal charge is a group of electrons and is separated into three memory parts, the central gate conductor layer may be subjected to a voltage higher than the voltage applied to the gate conductor layers on either side. [Brief explanation of the drawing]

[0032] [Figure 1A] This is a three-dimensional structural diagram of a dynamic flash memory according to the first embodiment. [Figure 1B] This is a structural diagram of a dynamic flash memory according to the first embodiment. [Figure 1C] This diagram illustrates the data writing and reading operations in a dynamic flash memory according to the first embodiment. [Figure 1D] This is a structural diagram of a four-row dynamic flash memory according to a modified example of the first embodiment. [Figure 2A] This is a three-dimensional structural diagram of a dynamic flash memory according to the second embodiment. [Figure 2B] This is a structural diagram of the dynamic flash memory according to the second embodiment. [Figure 2C] This is a diagram illustrating the operation of the dynamic flash memory according to the second embodiment. [Figure 3] This is a structural diagram of a dynamic flash memory according to the third embodiment. [Figure 4] This is a structural diagram of the dynamic flash memory according to the fourth embodiment. [Figure 5] This is a structural diagram of a dynamic flash memory according to the fifth embodiment. [Figure 6A] This diagram illustrates data writing and reading operations in another dynamic flash memory according to the sixth embodiment. [Figure 6B]This diagram illustrates data writing and reading operations in another dynamic flash memory according to the sixth embodiment. [Figure 7] This diagram illustrates the operating principle of conventional dynamic flash memory. [Modes for carrying out the invention]

[0033] Hereinafter, a memory device using semiconductor elements according to an embodiment of the present invention (hereinafter referred to as dynamic flash memory) will be described with reference to the drawings.

[0034] (First Embodiment) Figures 1A, 1B, and 1C illustrate the structure of a 2-row, 2-tier dynamic flash memory according to the first embodiment of the present invention, as well as its data writing and reading operations. Figure 1A is a three-dimensional structural diagram of a dynamic flash memory consisting of two vertical rows and two horizontal rows of memory cells. Figure 1B shows the plan view and cross-section of the three-dimensional structural diagram of Figure 1A. In Figure 1C, data writing and reading operations are explained using two memory cells arranged in a plane parallel to the substrate surface. Furthermore, Figure 1D illustrates the structure of a 4-row dynamic flash memory according to a modification of the first embodiment of the present invention. In this modification, data writing and reading operations are explained using four memory cells arranged in a plane parallel to the substrate surface. In actual dynamic flash memory, memory cells are arranged in large numbers in the horizontal and vertical directions.

[0035] Figure 1A shows a dynamic flash memory 100 (an example of a "memory device" in the claims) formed on a substrate 1 (an example of a "substrate" in the claims). Separated from the substrate 1 in the direction perpendicular to the substrate 1 (Z direction), there are two P-type conductive channel semiconductor layers 10a1 (an example of a "first channel semiconductor layer" in the claims) and 10a2 (an example of a "second channel semiconductor layer" in the claims) that are extended in parallel to the X direction in the horizontal plane (X-Y plane). There are two channel semiconductor layers 10b1 (not shown) and 10b2 that are arranged parallel to the channel semiconductor layers 10a1 and 10a2 in the direction perpendicular to the bottom. In a plan view, channel semiconductor layer 10a1 and channel semiconductor layer 10b1 are The channel semiconductor layers 10a1 and 10b2 are arranged to align in substantially the same shape, and similarly, the channel semiconductor layer 10a2 and 10b2 are arranged to align in substantially the same shape. Furthermore, in a view perpendicular to the stretching direction of the channel semiconductor layer 10a2 and the direction perpendicular to the substrate 1, the channel semiconductor layer 10a1 and 10b2 are arranged to align in substantially the same shape, and similarly, the channel semiconductor layer 10b1 and 10b2 are arranged to align in substantially the same shape. N containing a large amount of donor impurities is located at both ends of the channel semiconductor layer 10a1. + There are regions 11aa (an example of the "first impurity region" in the claims) and 11ab (an example of the "second impurity region" in the claims). N contains a large amount of donor impurities at both ends of the channel semiconductor layer 10a2. + There are regions 11ba (an example of the "third impurity region" in the claims) and 11bb (an example of the "fourth impurity region" in the claims). N contains a large amount of donor impurities at both ends of the channel semiconductor layer 10b1. + Regions 11ca (not shown) and 11cb are present. N, which contains many donor impurities, is located at both ends of the channel semiconductor layer 10b2. +There are regions 11da and 11dB. There is a gate insulating layer (not shown) in contact with both sides of the channel semiconductor layers 10a1 and 10a2 and the channel semiconductor layers 10b1 and 10b2. In contact with the gate insulating layer, sandwiched between the channel semiconductor layers 10a1 and 10b1 and the channel semiconductor layers 10a2 and 10b2, there is a first gate conductor layer (an example of the "first gate conductor layer" in the claims) consisting of a first word line gate conductor layer WL1 (an example of the "conductor layer portion" in the claims), a plate line gate conductor layer PL (an example of the "conductor layer portion" in the claims), and a second word line gate conductor layer WL2 (an example of the "conductor layer portion" in the claims). There is a first back gate conductor layer BG1 (an example of the "second gate conductor layer" or "conductor layer portion" in the claims) that is in contact with the gate insulating layer on one side of the channel semiconductor layers 10a1 and 10b1 and is connected vertically. There is a second back gate conductor layer BG2 (an example of the "third gate conductor layer" or "conductor layer portion" in the claims) that is in contact with the gate insulating layer on the other side of the channel semiconductor layers 10a2 and 10b2 and is connected vertically. In a plan view, the ends of the first and second back gate conductor layers BG1 and BG2 are located at the outer ends of the first word line gate conductor layer WL1 and the second word line gate conductor layer WL2. The memory cell 101a (an example of the "first memory cell" in the claims) is formed in the portion including the channel semiconductor layer 10a1. Then, the memory cell 101b (an example of the "second memory cell" in the claims) is formed in the portion including the channel semiconductor layer 10a2.

[0036] And then, N + Area 11aa, N + Region 11ca is connected to a first source line SL1 (an example of the "first source line" in the claims) which is connected vertically. + Area 11ba, N + Region 11da is connected to a second source line SL2 (an example of the “second source line” in the claims) which is connected vertically. + Area 11ab, N +Region 11bb is connected to a horizontally connected first bit line BL1 (an example of the "first bit line" in the claims). + Area 11cb, N + Region 11dB is connected to the second bit line BL2, which is connected horizontally.

[0037] Figure 1B(a) shows a plan view of the schematic three-dimensional diagram of the two-stage dynamic flash memory cell shown in Figure 1A. Figure 1B(b) shows a vertical cross-sectional view along the line X-X' in Figure 1B(a). And Figure 1B(c) shows a vertical cross-sectional view along the line Y-Y' in Figure 1B(a).

[0038] As shown in Figure 1B, there are two channel semiconductor layers 10a1 and 10a2 that are perpendicular to the substrate 1 and extended parallel to each other in the horizontal direction. There are two channel semiconductor layers 10b1 and 10b2 that are aligned parallel to each other in the vertical direction below the channel semiconductor layers 10a1 and 10a2. When viewed from above, channel semiconductor layers 10a1 and 10b1 are arranged to be aligned in substantially the same shape, and similarly, channel semiconductor layers 10a2 and 10b2 are arranged to be aligned in substantially the same shape. N2, which contains a large amount of donor impurities, is located at both ends of channel semiconductor layer 10a1. + Regions 11aa and 11ab are present. N contains a large amount of donor impurities at both ends of the channel semiconductor layer 10a2. + Regions 11ba and 11bb are present. N contains many donor impurities at both ends of the channel semiconductor layer 10b1. + Regions 11ca and 11cb are present. N contains many donor impurities at both ends of the channel semiconductor layer 10b2. +There are regions 11da and 11dB. There are insulating layers 12a1, 12a2, and 12a3 between channel semiconductor layers 10a1 and 10b1, and above and below them. There are insulating layers 12b1, 12b2, and 12b3 between channel semiconductor layers 10a2 and 10b2, and above and below them. There are gate insulating layers 13aa, 13ab, 13ba, and 13bb on both sides of channel semiconductor layers 10a1, 10b1 and insulating layers 12a1, 12a2, and 12a3, and on both sides of channel semiconductor layers 10a2, 10b2 and insulating layers 12b1, 12b2, and 12b3. The gate insulating layer 13aa (an example of the "first gate insulating layer" in the claims) is on the opposite side of the channel semiconductor layer 10a2 and in contact with the vertical side surface of the channel semiconductor layer 10a1; the gate insulating layer 13ab (an example of the "second gate insulating layer" in the claims) is on the channel semiconductor layer 10a2 side and in contact with the vertical side surface of the first channel semiconductor layer 10a1; the gate insulating layer 13ba (an example of the "third gate insulating layer" in the claims) is on the channel semiconductor layer 10a1 side and in contact with the vertical side surface of the channel semiconductor layer 10a2; and the gate insulating layer 13bb (an example of the "fourth gate insulating layer" in the claims) is on the opposite side of the channel semiconductor layer 10a1 and in contact with the vertical side surface of the channel semiconductor layer 10a2.

[0039] As shown in Figure 1B, a first word line gate conductor layer WL1, a plate line gate conductor layer PL, and a second word line gate conductor layer WL2 are sandwiched between channel semiconductor layers 10a1, 10b1 and channel semiconductor layers 10a2, 10b2, in contact with gate insulating layers 13ab, 13ba, and insulated from each other, and are extended perpendicular to the substrate. A first back gate conductor layer BG1 is in contact with the side of the gate insulating layer 13aa opposite to the channel semiconductor layers 10a1, 10b1 and is extended perpendicular to the substrate. A second back gate conductor layer BG2 is in contact with the side of the gate insulating layer 13bb opposite to the channel semiconductor layers 10a2, 10b2 and is extended perpendicular to the substrate. A memory cell 101a (an example of the "first memory cell" in the claims) is made up of channel semiconductor layers 10a1, N +Regions 11aa, 11ab, gate insulating layers 13aa, 13ab, first word line gate conductor layer WL1, plate line gate conductor layer PL, second word line gate conductor layer WL2, and first back gate conductor layer BG1 are formed. The memory cell 101b (an example of the "second memory cell" in the claims) is formed of channel semiconductor layer 10a2, N + It is formed from regions 11ba, 11bb, gate insulating layers 13ba, 13bb, a first word line gate conductor layer WL1, a plate line gate conductor layer PL, a second word line gate conductor layer WL2, and a first back gate conductor layer BG2. The first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 are common gate conductor layers for memory cell 101b and memory cell 101b. Below memory cell 101a, in a plan view, there is a channel semiconductor layer 10b1, N + There is a memory cell 102a formed from regions 11ca, 11cb, gate insulating layers 13aa, 13ab, a first word line gate conductor layer WL1, a plate line gate conductor layer PL, a second word line gate conductor layer WL2, and a first back gate conductor layer BG1. Below the memory cell 101b, in a plan view, there is a channel semiconductor layer 10b2, N, which has the same shape as the memory cell 101b. + The memory cell 102b is formed from regions 11da and 11db, gate insulating layers 13ba and 13bb, a first word line gate conductor layer WL1, a plate line gate conductor layer PL, a second word line gate conductor layer WL2, and a second back gate conductor layer BG2.

[0040] Figure 1C illustrates the operation of two memory cells formed in channel semiconductor layers 10a1 and 10a2 related to the present invention during the data writing period (an example of the "data writing period" in the claims). As shown in Figure 1C(a), N + A voltage Vs is applied to the first source line SL1 connected to region 11aa. N is connected to the second source line SL2. + A positive voltage V1 is applied to region 11ba. + The first bit line BL1 connected to regions 11ab and 11bb has N +The same positive voltage V1 as in region 11ba is applied. A positive on-voltage V2 is applied to the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2, which is necessary for current to flow through the channel semiconductor layers 10a1 and 10a2. A negative voltage Vb is applied to the back gate conductor layers BG1 and BG2. By applying the on-voltage V2 to the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2, the memory cells of the first and second channel semiconductor layers 10a1 and 10a2 on both sides of the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 are accessed simultaneously. However, in this case, as shown in Figure 1C(a), N + When a voltage (V1-Vs) is applied between regions 11aa and 11ab, an on-current 16a flows through the first channel semiconductor layer 10a1, but N + The same V1 is applied between regions 11aa and 11ab. + The second channel semiconductor layer 10a2 between regions 11aa and 11ab is in an off state where no current flows. As a result, only the memory cells of the first channel semiconductor layer 10a1 are accessed. In this case, Vs, V1, V2, and Vb are set to voltages that generate a group of holes, which are the signal, due to the impact ionization phenomenon similar to that explained using Figure 7 by the on current 16a, or by the GIDL current. In the first and second channel semiconductor layers 10a1 and 10b1, the group of holes, which are the signal charge for data "1", is accumulated on the first back gate conductor layer BG1 side. No group of holes is accumulated for data "0".

[0041] Next, as shown in Figure 1C(b), the voltage applied to the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 is set to V2, and the voltage applied to the first bit line BL1 is kept at V1. Then, the voltage applied to the first source line SL1 is set to V1, and the voltage applied to the second source line SL2 is set to Vs. As a result, only the memory cell of the second channel semiconductor layer 10a2 is accessed. In data "1" writing, N +A current 16b flows between regions 11ba and 11bb, and the data "1" is set by the impact ionization phenomenon or the group of holes generated by the GIDL current. No current flows when writing data "0". As a result, although the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 are common gates for the first and second channel semiconductor layers 10a1 and 10b2, data "1" or "0" is written only to the memory cell of the second channel semiconductor layer 16b. When writing "0" data, Vs, V1, V2, and Vb are set to voltages where the on-current 16a does not generate a group of holes due to the impact ionization phenomenon or the GIDL current. Note that when performing a refresh operation to write "0" data to the first and second channel semiconductor layers 16a and 16b for the first time, only the data "1" writing operation is necessary.

[0042] The operating mechanism of the data readout period (an example of the "data readout period" in the claims) of the two memory cells formed in the channel semiconductor layers 10a1 and 10a2 is basically the same as the data write operation described above. In the data write operation, when writing data "1", the voltage is set so that impact ionization occurs due to currents 16a and 16b within the channel semiconductor layers 10a1 and 10a2, or a group of holes, which is a signal caused by the GIDL current, is generated. In contrast, in the data readout operation, impact ionization by currents 16a and 16b, or a group of holes caused by the GIDL current, is not generated.

[0043] An on-voltage V2 is applied to the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2. The memory cells of the first and second channel semiconductor layers 10a1 and 10a2 on both sides of the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 are accessed simultaneously. However, in this case, as shown in Figure 1C(a), N + When (V1-Vs) is applied between regions 11aa and 11ab, an on-current 16a flows through the first channel semiconductor layer 10a1. +The second channel semiconductor layer 10a2 between regions 11aa and 11ab is in an off state where no current flows. As a result, only the memory cells of the channel semiconductor layer 10a1 are accessed. Note that when the data is "0" and no signal charge (hole group) is accumulated in the first channel semiconductor layer 10a1, the aforementioned "1" current does not flow, resulting in an off state. As a result, only the logical data "1" or "0" of the first channel semiconductor layer 10a1 is read out.

[0044] Next, as shown in Figure 1C(b), the voltage applied to the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 is kept at V2, and the voltage applied to the first bit line BL1 is kept at V1. Then, the voltage applied to the first source line SL1 is set to V1, and the voltage applied to the second source line SL2 is set to Vs. As a result, only the memory cell of the second channel semiconductor layer 10a2 is accessed. In the data "1" state, N + A current of "1" (16b) flows between regions 11ba and 11bb, and no current flows when the data is "0". As a result, although the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 are common gates for the first and second channel semiconductor layers 10a1 and 10b2, only the memory cell of the second channel semiconductor layer 10a2 is accessed, and only the logical data "1" or "0" of the second channel semiconductor layer 10a2 is read out.

[0045] Figure 1D shows a dynamic flash memory in which, in a plan view, a group of memory cells (a group of memory cells including channel semiconductor layers 10a3 and 10a4) with a structure similar to the group of memory cells including channel semiconductor layers 10a1 and 10a2 shown in Figure 1B are arranged adjacent to each other. N + Regions 11ca and 11cb are present, and N is present at both ends of the channel semiconductor layer 10a4. +There are regions 11da and 11dB. Between the channel semiconductor layers 10a3 and 10a4, sandwiched by gate insulating layers and separated by insulating layers, are the first word line gate conductor layer WL1a, the plate line gate conductor layer PLa, and the second word line gate conductor layer WL2a. Below the channel semiconductor layer 10a4 is the third back gate conductor layer BG3. Thus, above and below each channel semiconductor layer 10a1, 10a2, 10a3, and 10a4 are the gate conductor layers for the word lines and plate lines, and the back gate conductor layer. In this way, each word line and plate line gate conductor layer and each back gate conductor layer are the gate conductor layers of the channel semiconductor layers of the two memory cells above and below them. This enables high integration of memory cells.

[0046] In the data erasure operation in the memory cell shown in Figure 1D, for example, if a positive voltage is applied to the back gate conductor layer BG2, the signal hole groups in the channel semiconductor layers 10a2 and 10a3 on both sides of the back gate conductor layer BG2 will be removed. To erase only one of the signal hole groups in the channel semiconductor layers 10a2 and 10a3, it is necessary to write the signal hole group to the other channel semiconductor layer by some method.

[0047] There are signal hole groups with logical "1" data in both channel semiconductor layers 10a2 and 10a3. There are three methods to leave the signal hole groups with logical "1" data in one of the channel semiconductor layers 10a2 or 10a3. The first method is to erase the signal hole groups in both channel semiconductor layers 10a2 and 10a3, and then rewrite the logical "1" data to one of the channel semiconductor layers 10a2 or 10a3 again. The second method is to perform block erasure, which erases data from memory cells arranged horizontally and vertically at once. In this case, all memory cells within the block are erased to a logical "0" data state, and then data is written only to the memory cells with logical "1" data. A third method, for example, to retain the signal-hole group in channel semiconductor layer 10a3 and erase the signal-hole group in channel semiconductor layer 10a2, involves applying a first voltage to the bit line BL1 and source line SL3 that is greater than and equal to the potential of channel semiconductor layer 10a3 where the signal-hole group is located. This prevents the signal-hole group accumulated in channel semiconductor layer 10a3 from flowing out through source line SL3 and bit line BL1. Then, a second voltage is applied to source line SL2 that is lower than the first voltage and lower than the potential of channel semiconductor layer 10a. This removes the signal-hole group in the first channel semiconductor layer 10a2 from source line SL2. The same method can be used to erase the signal-hole group in channel semiconductor layer 10a3 and retain the signal-hole group in channel semiconductor layer 10a2. These methods are the same in other embodiments.

[0048] In the first embodiment using Figures 1A, 1B, and 1C, the explanation was given using an example of the first to third gate conductor layers WL1, PL, and WL2. However, the same operation applies to a structure composed of the first and second gate conductor layers WL1 and PL. This will be explained later.

[0049] Furthermore, in a plan view, the back gate conductor layers BG1, BG2, and BG3 may each be divided into multiple parts (for example, two or three parts) in the direction in which the channel semiconductor layers 10a1 to 10a4 extend. Alternatively, in a plan view, the back gate conductor layers BG1, BG2, and BG3 may each be divided into two insulated back gate conductor layers in a direction perpendicular to the direction in which the channel semiconductor layers 10a1 to 10a4 extend. In this case, the two divided back gate conductor layers can be driven independently of each other. These are also true in other embodiments.

[0050] Furthermore, not only a fixed voltage but also a time-varying pulse voltage may be applied to the back gate conductor layers BG1 and BG2. In this case, the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 may serve as electrostatic shielding electrodes to which a fixed voltage of, for example, 0V is applied.

[0051] Furthermore, Figure 1B shows an example in which, in a plan view, the first and second word line gate conductor layers WL1 and WL2 and the plate line gate conductor layer PL are connected and in contact with both sides of the gate insulating layers 13ab and 13ba. In contrast, the gate insulating layers 13ab and 13ba may be formed separately on the first and second word line gate conductor layers WL1 and WL2 and on the plate line gate conductor layer PL. This is also true in other embodiments.

[0052] Furthermore, during the logical "1" data write period and the logical "1" data read period, A voltage lower than that applied to the first and second word line gate conductor layers WL1 and WL2 and the plate line gate conductor layer PL may be applied to the back gate conductor layers BG1 and BG2. This causes the signal hole group to accumulate in the region of the channel semiconductor layers 10a1 and 10a2 on the back gate conductor layers BG1 and BG2 side. This separates the location of the accumulated signal hole group from the data writing and reading current paths. This enables more stable data writing and reading operations. If the signal charge is electrons, a voltage higher than that applied to the first and second word line gate conductor layers WL1 and WL2 and the plate line gate conductor layer PL may be applied to the back gate conductor layers BG1 and BG2 during the logic "1" data writing period and the logic "1" data reading period.

[0053] Furthermore, during the data retention period of the memory shown in Figure 1B, the voltage applied to the back gate conductor layers BG1 and BG2 may be kept lower than the voltage applied to the first and second word line gate conductor layers WL1 and WL2 and the plate line gate conductor layer PL. This allows the group of holes, which are the signal, to be retained in the channel semiconductor layer region on the back gate conductor layers BG1 and BG2 side. This enables stable operation. If the signal charge is electrons, the voltage applied to the back gate conductor layers BG1 and BG2 should be kept higher than the voltage applied to the first and second word line gate conductor layers WL1 and WL2 and the plate line gate conductor layer PL.

[0054] This embodiment has the following features. 1. As shown in Figure 1A, in the dynamic flash memory of the present invention, the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 are common gates for the first and second channel semiconductor layers 10a1 and 10a2, enabling high integration of memory cells in a plan view. 2. As shown in Figure 1D, in the dynamic flash memory of the present invention, the back gate conductor layer BG2 also serves as a common gate for the second channel semiconductor layer 10a2 and the third channel semiconductor layer 10a3. Thus, in the present invention, the gate conductor layers WL1, PL, WL2, WLa, PLa, WL2a and the back gate conductor layers BG1, BG2, BG3 serve as common gates for the upper and lower memory cells in a plan view. This enables high integration of memory cells in a plan view. 3. In the present invention, the group of holes, which are signal charges, can be accumulated on the back gate conductor layers BG1 and BG2 of the first channel semiconductor layer 10a1 and the second channel semiconductor layer 10a2, as shown in Figure 1C. This allows the group of holes, which are signal charges, to be separated from the data readout currents 16a and 16b, thereby preventing "1" data degradation due to a decrease in the group of signal holes during data readout. 4. The back gate conductor layers BG1 and BG2 can function as electrostatic shielding conductor layers. Furthermore, when a pulse voltage is applied to the back gate conductor layers BG1 and BG2, the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 can function as electrostatic shielding conductor layers by applying a fixed voltage of, for example, 0V to them. This contributes to the stable operation and improved characteristics of the dynamic flash memory.

[0055] (Second Embodiment) The structure and operation of the dynamic flash memory according to the second embodiment of the present invention will be explained using Figures 2A, 2B, and 2C.

[0056] In the memory cell shown in Figure 1, the channel semiconductor layers 10a1 to 10b2 are divided into conductor layer portions: a first word line gate conductor layer WL1, a plate line gate conductor layer PL, and a second word line gate conductor layer WL2, in the direction in which they are stretched. In contrast, the back gate conductor layers BG1 and BG2 facing these layers are not divided. On the other hand, as shown in Figure 2, the back gate conductor layer BG1 in Figure 1 is divided into conductor layer portions: back gate conductor layers BG1a, BG1b, and BG1c, and the back gate conductor layer BG2 in Figure 1 is divided into conductor layer portions: back gate conductor layers BG2a, BG2b, and BG2c.

[0057] In the dynamic flash memory shown in Figure 2B, BG1 shown in Figure 1D is divided into three back gate conductor layers BG1a, BG2a, and BG3a; BG2 is divided into three back gate conductor layers BG1b, BG2b, and BG3b; and BG3 is divided into three back gate conductor layers BG1c, BG2c, and BG3c. In the dynamic flash memory of this embodiment, on both sides of the first to fourth channel semiconductor layers 10a1, 10a2, 10a3, and 10a4, there are first word line gate conductor layers WL1, WL1a, plate line gate conductor layers PL, PLa, second word line gate conductor layers WL2, WL2a, and back gate conductor layers BG1a to BG1c, BG2a to BG2c, and BG3a to BG3c, all of the same shape. In the explanation using Figures 1C and 1D, the back gate conductor layers BG1 to BG3 served to accumulate the group of holes, which are signal charges, on the channel semiconductor layers 10a1 to 10a4 on the back gate conductor layers BG1 to BG3 side, and also acted as electrostatic shielding electrodes. In contrast, in the dynamic flash memory of this embodiment, during the data erasure operation, a positive voltage pulse of, for example, 1.5V is applied to the back gate conductor layers BG2a, BG2b, and BG2c, while a voltage lower than that applied to the back gate conductor layers BG2a, BG2b, and BG2c, for example, 0V, is applied to the gate conductor layers BG1a, BG3a, BG1b, BG3b, BG1c, and BG3c to erase the group of holes in the signal. + Layer 11aa~11da, N +Remove from either one or both of layers 11ab to 11db. In this case, by applying a fixed voltage, such as 0V, lower than the voltage applied to the back gate conductor layers BG2a, BG2b, BG2c, to the first word line gate conductor layers WL1, WL1a, plate line gate conductor layers PL, PLa, and second word line gate conductor layers WL2, WL2a, the first word line gate conductor layers WL1, WL1a, plate line gate conductor layers PL, PLa, and second word line gate conductor layers WL2, WL2a can be made to function as electrostatic shield electrodes.

[0058] As described above, when a positive pulse voltage is applied to one of the first word-line gate conductor layers WL1, WL1a, plate-line gate conductor layers PL, PLa, the second word-line gate conductor layers WL2, WL2a, and back-gate conductor layers BG1a~BG1c, BG2a~BG2c, BG3a~3c, a lower fixed voltage can be applied to the other, allowing the conductor layer to which the fixed voltage is applied to act as an electrostatic shield electrode. Furthermore, when the signal charge is electrons, when a negative pulse voltage is applied to one of the first word-line gate conductor layers WL1, WL1a, plate-line gate conductor layers PL, PLa, the second word-line gate conductor layers WL2, WL2a, and back-gate conductor layers BG1a~BG1c, BG2a~BG2c, BG3a~3c, a higher fixed voltage can be applied to the other, allowing the conductor layer to which the fixed voltage is applied to act as an electrostatic shield electrode.

[0059] Furthermore, during the data retention period and data readout period, a negative voltage is applied to the back gate conductor layers BG2a, BG2b, and BG2c, and a voltage of 0V is applied to the back gate conductor layers BG1a, BG3a, BG1b, BG3b, BG1c, and BG3c. This causes the group of holes, which are the signal charge, to be N + It can be stored in the channel semiconductor layers 10a1 to 10a4 on the BG2a, BG2b, and BG2c sides, separate from regions 11aa to 11da and 11ab to 11db.

[0060] As shown in Figure 2C, the back gate conductor layers BG1a and BG1c may be connected, the first word line gate conductor layer WL1 and the second word line gate conductor layer WL2 may be connected, and the back gate conductor layers BG2a and BG2c may be connected. This also allows for normal operation of the dynamic flash memory. Furthermore, it offers the advantage of reducing the number of external drive wires.

[0061] In Figure 2B, the divided back gate conductor layers BG1a, BG1b, BG1c, back gate conductor layers BG2a, BG2b, BG2c, and back gate conductor layers BG3a, BG3b, BG3c can each be driven with different waveform voltages.

[0062] Furthermore, during the data retention period in the memory shown in Figure 2A, the voltage applied to the back gate conductor layers BG1b and BG2b is set on both sides of the back gate conductor layers BG1b and BG2b. A voltage lower than that applied to the back gate conductor layers BG1a, BG1c, BG2a, and BG2c is applied. This causes the group of holes, which are the signal charge, to N + The data can be held in the channel semiconductor layer region 10a1-10dB on the back gate conductor layers BG1b and BG2b, away from the region 11aa-11dB. This ensures stable data readout operation. When the signal charge is electrons, during the data retention period, the voltage applied to the back gate conductor layers BG1b and BG2b is higher than the voltage applied to the back gate conductor layers BG1a, BG1c, BG2a, and BG2c on both sides of the back gate conductor layers BG1b and BG2b. This is the same in other embodiments.

[0063] (Third embodiment) Figure 3 shows a structural diagram of a 2-row, 2-tier dynamic flash memory according to the third embodiment of the present invention.

[0064] In the memory cell shown in Figure 1, the first word line gate conductor layer WL1, the plate line gate conductor layer PL, and the second word line gate conductor layer WL2 are formed in the direction in which the channel semiconductor layers 10a1 to 10b2 are stretched. In contrast, the first gate conductor layer may have a structure that excludes the second word line gate conductor layer WL2, as shown in Figure 3. In a plan view, both ends 102a1, 102a2, 102b1, and 102b2 of the back gate conductor layers BG1d and BG2d are the same as the source line side end 102c1 of the first word line gate conductor layer WL1 and the first bit line side end 102c2 of the plate line gate conductor layer PL in the direction in which the channel semiconductor layers 11aa to 11b2 are stretched. Even with this, normal operation of the dynamic flash memory can be achieved, as can be seen from the conventional example in Figure 7 and the first embodiment in Figures 1A to 1C. The same operation as described in Figures 1A to 1C is performed. In the case of the two-gate conductor layer structure with a word-line gate conductor layer WL1 and a plate-line gate conductor layer PL shown in Figure 3, the positions of the channel semiconductor layers 10a1 to 10b2 of the word-line gate conductor layer WL1 and the plate-line gate conductor layer PL in the stretching direction may be reversed.

[0065] (Fourth embodiment) Figure 4 shows a structural diagram of a 2-row, 2-stage dynamic flash memory according to the fourth embodiment of the present invention.

[0066] As shown in Figure 4, in the direction in which the channel semiconductor layers 10a1 to 10b2 are stretched, in a plan view, both ends of the back gate conductor layers BG1b and BG2b are formed so as to be at the ends of the plate wire gate conductor layer PL. In a vertical cross-section, the back gate conductor layers BG1b and BG2b overlap the plate wire gate conductor layer PL. This allows the back gate conductor layers BG1b and BG2b to be connected to the voltage-varying source lines SL1 and SL2. + N is connected to regions 11aa~11da and bit lines BL1 and BL2. + This allows us to separate the region 11ab~11db from N. +Capacitive coupling between regions 11aa and 11da is reduced. This contributes to the stable operation of the dynamic flash memory. Note that a similar effect can be obtained even if the back gate conductor layers BG1b and BG2b overlap the first word line gate conductor layer WL1 or the second word line gate conductor layer WL2. In particular, in a memory cell consisting of the first word line gate conductor layer WL1 and the plate line gate conductor layer PL, the positions of the back gate conductor layers BG1b and BG2b change depending on which conductor layer the signal charge is stored on.

[0067] (Fifth embodiment) Figure 5 shows a structural diagram of a 2-row, 2-stage dynamic flash memory according to the 5th embodiment of the present invention.

[0068] As shown in Figure 5, in the stretched direction of the channel semiconductor layers 10a1 to 10b2, in a plan view, the ends 103d1, 103d2, 103e1, and 103e2 of the back gate conductor layers BG1ba and BG2ba are formed to be inward from the positions of the outer ends 103f1 and 103f2 of the word line gate conductor layers WL1 and WL2. This allows for a larger number of holes in the signal charge group accumulated in the channel semiconductor layers 10a1 to 10b2 compared to the dynamic flash memory described in Figure 4. Furthermore, compared to the dynamic flash memory shown in Figure 1, N +Capacitive coupling between regions 11aa~11da and back gate conductor layers BG1b and BG2b can be reduced, enabling stable operation of the dynamic flash memory. Note that in a plan view, the same effect can be obtained even if one end of the back gate conductor layers BG1ba and BG2ba coincides with one end of the plate line gate conductor layer PL. While Figure 5 shows a structure consisting of three gate conductor layers (word line gate conductor layers WL1 and WL2, and plate line gate conductor layer PL), the same can be applied to the two-gate conductor layer structure (word line gate conductor layer WL1 and plate line gate conductor layer PL) shown in Figure 3. In this case, in a plan view, both ends 102a1, 102a2, 102b1, and 102b2 of the back gate conductor layers BG1d and BG2d coincide with one end of the word line gate conductor layer WL1. + From one end 102c1 on the region 11aa~11da side, the N of the plate wire gate conductor layer PL + This extends to one end 102c2 on the region 11ab-11db side.

[0069] (Sixth Embodiment) Using Figures 6A and 6B, the data writing and reading operations of a memory cell according to the sixth embodiment of the present invention will be explained.

[0070] Figure 6A is similar to the one shown in Figure 1A, N + A memory cell unit 104a including regions 11aa and 11ba, and N + A memory cell unit group 104 in which memory cell units 104b containing regions 11ca and 11da are arranged in two stages is provided with N + Memory cell unit 105a including regions 11ea and 11fa, and N + This shows a configuration in which a group of memory cell units 105, including a memory cell unit 105b containing regions 11ga and 11ha, are arranged adjacently in the horizontal direction (X direction). + Memory cell unit 104a containing regions 11aa and 11ba, and memory cell unit 105a containing regions 11ea and 11fa, + Channel semiconductor layer containing region 11aa and N +The elements are arranged to be aligned with substantially the same shape in a view perpendicular to the stretching direction of the channel semiconductor layer including region 11ba and the direction perpendicular to the substrate 1. + Memory cell unit 104b containing regions 11ca and 11da, and memory cell unit 105b containing regions 11ga and 11ha, are N + Channel semiconductor layer containing region 11ca and N + In the channel semiconductor layer containing region 11da, the elements are arranged to be aligned with substantially the same shape when viewed in a direction perpendicular to the stretching direction and the direction perpendicular to the substrate 1. + BL1 connected to regions 11ab and 11bb is N + N at one end of the channel semiconductor layer (not shown) connected to regions 11ea and 11fa + It connects to a region (not shown) and extends horizontally (X direction) relative to the substrate 1. And, in Figure 1A, N + BL2 connected to regions 11cb and 11db is N + N at one end of the channel semiconductor layer (not shown) connected to regions 11ga and 11ha + It connects to a region (not shown) and extends horizontally (X direction) relative to the substrate 1. In Figure 1C of the first embodiment, N + Source line SL1 connected to region 11aa, and N + Source wire SL2 connected to region 11ba is separated from other source wires and extends upward perpendicularly (Z direction) relative to the substrate 1, and is independently extracted. Furthermore, each source wire SL1 and SL2 is accessed independently of other source wires. In contrast, in this embodiment, N + Source line SL1 connected to regions 11aa and 11ca, and N + Source line SL3, connected to regions 11ea and 11ga, is connected to coupled source line SLO above. And N + Source line SL2 connected to regions 11ba and 11da, and N +Source line SL4, connected to regions 11fa and 11ha, is connected to the coupled source line SLE in the vertical direction (Z direction) upwards. That is, there is a source line group 106a consisting of alternating odd-numbered source lines SL1 and SL3, and a source line group 106b consisting of alternating even-numbered source lines SL2 and SL4. Source lines SL1 and SL3, which make up source line group 106a, extend in the same direction, i.e., vertically (Z direction) upwards, and are connected to the coupled source line SLO. Also, source lines SL2 and SL4, which make up source line group 106b, extend in the same direction, i.e., vertically (Z direction) upwards, and are connected to the coupled source line SLE. In this embodiment, each source wire SL1 to SL4 is extended perpendicular to the substrate 1 (Z direction) and extracted independently, but at the upper end of the extracted wires, source wire group 106a (source wires SL1, SL3) is connected to coupled source wire SLO, and source wire group 106b (SL2, SL4) is connected to coupled source wire SLE, which is independent of coupled source wire SLO.

[0071] Figure 6B shows the N in the memory cell shown in Figure 6A. +This section describes data writing and data reading operations in memory cells connected to regions 11aa and 11ba. In these data writing and data reading operations, as shown in Figure 6B(a), for example, a voltage Vs is applied to the coupled source line SLO connected to the odd-numbered memory cells, and a positive voltage V1 is applied to the coupled source line SLE connected to the even-numbered memory cells. As a result, the memory cells of the channel semiconductor layer 10a1 are accessed, and at the same time, the memory cells connected to the other coupled source lines SLO are also accessed. In this case, since no on-voltage is applied to the first and second word line gate conductor layers and plate line gate conductor layers of the other memory cells, current flows only to the memory cells of the first channel semiconductor layer, and a logic "1" is written or read. Alternatively, if a voltage V1 is applied to the coupled source line SLO and a voltage Vs is applied to the coupled source line SLE, current flows only to the memory cells of the second channel semiconductor layer 10a2, and a logic "1" is written or read. In the memory cell shown in Figure 1C, the number of coupling source lines extracted externally is equal to the number of source lines aligned in the direction of extension of the bit line BL1 in a plan view. In contrast, in this embodiment, the number of source lines extracted externally is limited to only two, coupling source lines SLO and SLE, connected to the odd-numbered and even-numbered memory cells. This simplifies external circuit connections.

[0072] Note that the coupled source lines SLO and SLE are connected to N + The memory cells containing regions 11aa, 11ba, 11ca, 11da, 11ea, 11fa, 11ga, and 11ha may be positioned vertically above (in the Z direction) or vertically below (in the Z direction). In Figure 6A, the coupling source lines SLO and SLE are formed on the same substrate-parallel plane (parallel to the XY plane) vertically above (in the Z direction), but the coupling source lines SLO and SLE may be formed separately in the vertical direction (Z direction). In this case, the coupling source lines SLO and SLE can be formed overlapping in a plan view (view in a direction perpendicular to the XY plane), thereby increasing the memory cell integration density.

[0073] Furthermore, in Figures 6A and 6B, source lines SL1 and SL3 connected to odd-numbered memory cells among the memory cells arranged in parallel with the substrate are connected to the coupled source line SLO, and source lines SL2 and SL4 connected to even-numbered memory cells are connected to the coupled source line SLE. Thus, in this embodiment, an example was described in which a group of source lines consisting of alternating source lines is connected to an independent source line. Alternatively, a group of source lines consisting of three or four or more alternating source lines may be configured to be connected to multiple independent coupled source lines corresponding to each of the source line groups. This reduces the load capacity of a single coupled source line, thereby achieving lower power consumption.

[0074] (Other embodiments) In Figure 1A, the materials of the first and second word wire gate conductor layers WL1 and WL2, the plate wire gate conductor layer PL, and the first and second back gate conductor layers BG1 and BG2 may be the same or different. This is also true in other embodiments.

[0075] Furthermore, the explanations in Figures 1A and 1C describe the case where the first to fourth channel semiconductor layers 10a1, 10a2, 10b1, and 10b2 use P-type conductivity to accumulate a group of holes as signal charges. Furthermore, the first to fourth channel semiconductor layers 10a1, 10a2, 10b1, and 10b2 may use N-type conductivity to accumulate electron groups as signal charges. In this case, N + Region 11ab~11db is P + A region is used. This is the same in other embodiments as well.

[0076] Furthermore, the present invention can be implemented in various forms and modified without departing from the broad spirit and scope of the invention. The embodiments described above are for illustrating one example of the present invention and do not limit the scope of the invention. The above embodiments and modifications can be combined arbitrarily. Moreover, the invention remains within the scope of the technical concept even if some of the constituent elements of the above embodiments are omitted as needed. [Industrial applicability]

[0077] According to the memory device using semiconductor elements according to the present invention, a high-density and high-performance memory device can be obtained. [Explanation of Symbols]

[0078] 1 circuit board 10a1, 10a2, 10b1, 10b2, 10a3, 10a4 channel semiconductor layers 11aa, 11ab, 11ba, 11bb, 11ca, 11cb, 11ca, 11da, 11cb, 11db N + region WL1, WL1a First word line gate conductor layer WL2, WL2a Second word line gate conductor layer PL, PLa plate wire gate conductor layer BG1, BG2, BG1a, BG2a, BG1b, BG2a, BG2b, BG2c, BG1d, BG2d, BG3 Back gate conductor layer 13aa, 13ab, 13ba, 13bb gate insulation layer 12a1, 12a2, 12a3, 12b1, 12b2, 12b3 Insulating layer 100 Dynamic Flash Memory 101a, 101b, 102a, 102b memory cells 102a1, 102a2, 102b1, 102b2, 102c1, 102c2, 103d1, 103d2, 103e1, 103e2, 103f1, 103f2 (both ends) 104a, 104b, 105a, 105b memory cell units 104, 105 Memory cell group SL1, SL1a First source line SL2, SL2a Second source line SLO, SLE combined source line SL3 Third Source Line SL4 4th source line BL1 First bit line BL2 Second bit line Vs, V1, V2, Vb voltages

Claims

1. In a memory device having a first channel semiconductor layer and a second channel semiconductor layer that are separated perpendicularly to the substrate and extended parallel to the horizontal, A first impurity region and a second impurity region are in contact with both ends of the first channel semiconductor layer, A third impurity region and a fourth impurity region are in contact with both ends of the second channel semiconductor layer, A first gate insulating layer located on the opposite side of the second channel semiconductor layer and in contact with the vertical side surface of the first channel semiconductor layer, A second gate insulating layer located on the second channel semiconductor layer side, in contact with the vertical side surface of the first channel semiconductor layer, A third gate insulating layer located on the first channel semiconductor layer side, in contact with the vertical side surface of the second channel semiconductor layer, A fourth gate insulating layer located opposite the first channel semiconductor layer and in contact with the vertical side surface of the second channel semiconductor layer, A first gate conductor layer that is in contact with the second gate insulating layer and the third gate insulating layer and has one or more conductor layer portions aligned in the stretching direction of the first channel semiconductor layer and the second channel semiconductor layer, A second gate conductor layer having one or more conductor layer portions aligned in the stretching direction and in contact with the first gate insulating layer, A third gate conductor layer having one or more conductor layer portions aligned in the stretching direction, in contact with the fourth gate insulating layer. It has, The first channel semiconductor layer and the second channel semiconductor layer are arranged to be aligned in substantially the same shape when viewed in a direction perpendicular to the stretching direction of the first channel semiconductor layer and the direction perpendicular to the substrate. The first memory cell includes the first channel semiconductor layer, the first impurity region, the second impurity region, the first gate insulating layer, the second gate insulating layer, the first gate conductor layer, and the second gate conductor layer. The second memory cell includes the second channel semiconductor layer, the third impurity region, the fourth impurity region, the third gate insulating layer, the fourth gate insulating layer, the second gate conductor layer, and the third gate conductor layer. The second gate conductor layer is shared by the first memory cell and the second memory cell. The first impurity region is connected to a first source line extending vertically, and the third impurity region is connected to a second source line extending vertically. The second and fourth impurity regions are connected to a first bit line that extends horizontally, During the data writing period and the data reading period, The memory device is configured to write or read logical "1" data in the memory cell of the first channel semiconductor layer by applying a first voltage to the first bit line, applying a second voltage to the first source line to allow an on-current to flow through the first channel semiconductor layer, and applying the same first voltage to the second source line as the first bit line, and then applying the same first voltage to the first bit line to allow an on-current to flow through the second channel semiconductor layer, and then writing or reading logical "1" data in the memory cell of the second channel semiconductor layer by applying a first voltage to the first bit line, and applying the same first voltage to the first source line as the first bit line. A memory device using semiconductor elements characterized by the following features.

2. The memory device is configured such that, when writing or reading the logic "1" data, a fixed voltage is maintained in the first gate conductor layer and the third gate conductor layer when a pulse voltage is applied to the second gate conductor layer, and when a pulse voltage is applied to the first gate conductor layer and the third gate conductor layer, a fixed voltage is maintained in the second gate conductor layer. A memory device using the semiconductor element described in feature 1.

3. The first gate conductor layer, the second gate conductor layer, and the third gate conductor layer consist of three conductor layer portions arranged to be substantially identical in shape when viewed in a direction perpendicular to the stretching direction of the first channel semiconductor layer and the second channel semiconductor layer and the direction perpendicular to the substrate, and the conductor layer portions at both ends in the stretching direction of each of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are wired together. A memory device using the semiconductor element described in feature 1.

4. In a plan view, in the stretching direction of the first and second channel semiconductor layers, the positions of both ends of the second gate conductor layer and the third gate conductor layer coincide with the positions of both ends of the first gate conductor layer. A memory device using the semiconductor element described in feature 1.

5. In a plan view, in the stretching direction of the first and second channel semiconductor layers, the positions of both ends of the second gate conductor layer and the third gate conductor layer coincide with the positions of both ends of any one of the multiple conductor layer portions of the first gate conductor layer. A memory device using the semiconductor element described in feature 1.

6. In a plan view, in the stretching direction of the first and second channel semiconductor layers, the positions of both ends of the second gate conductor layer and the third gate conductor layer are outside of at least one of the positions of both ends of the first gate conductor layer, and the positions of one or both ends of the second gate conductor layer and one or both ends of the third gate conductor layer are inside the positions of both ends of the conductor layer portion of the first gate conductor layer other than the at least one conductor layer portion. A memory device using the semiconductor element described in feature 1.

7. The memory device is configured such that, during the logical "1" data writing period and the logical "1" data reading period, if the signal charge is a group of holes, a voltage higher than the voltage applied to the first gate conductor layer is applied to the second and third gate conductor layers, and if the signal charge is a group of electrons, a voltage lower than the voltage applied to the first gate conductor layer is applied to the second and third gate conductor layers. A memory device using the semiconductor element described in feature 1.

8. During the logical "1" data writing period, the memory device accumulates a group of holes or electrons, which are signals generated by impact ionization or gate-induced drain current, in the first channel semiconductor layer or the second channel semiconductor layer, by a current flowing through either the first channel semiconductor layer connected to the first source line or the second channel semiconductor layer connected to the second source line. A memory device using the semiconductor element described in feature 1.

9. Multiple memory cell units, each comprising the first memory cell and the second memory cell, are arranged such that they are aligned in substantially the same shape when viewed in a direction perpendicular to the stretching direction of the first channel semiconductor layer and the second channel semiconductor layer and the direction perpendicular to the substrate. For each source line connected to each memory cell, there are multiple source line groups consisting of a predetermined number of source lines spaced apart. Each source wire constituting each source wire group extends in the same direction, and this same direction is either vertically upward or vertically downward. Each source line group is connected to a corresponding, mutually independent coupled source line. A memory device using the semiconductor element described in feature 1.

10. The coupling source line is positioned perpendicularly above or below the substrate from the first channel semiconductor layer and the second semiconductor layer. A memory device using the semiconductor element described in feature 9.

11. The independent coupling source lines are arranged on the same plane parallel to the substrate, vertically above the group of memory cells connected to the independent coupling source lines, or on the same plane vertically below the group of memory cells relative to the substrate. A memory device using the semiconductor element described in feature 9.

12. The independent coupling source lines are arranged on a plurality of planes parallel to the substrate and perpendicularly above the group of memory cells relative to the substrate, or on a plurality of planes parallel to the substrate and perpendicularly below the group of memory cells relative to the substrate. A memory device using the semiconductor element described in feature 9.

13. The memory device is configured such that, during the data erasure period, both the first channel semiconductor layer and the second channel semiconductor layer have a group of signal charges of holes or electrons indicating the logic "1" data, and in the operation to erase the logic "1" data from only one of them, the data erasure is performed on the group of signal charges of holes or electrons indicating the logic "1" data from both the first channel semiconductor layer and the second channel semiconductor layer, and then the logic "1" data is rewritten to either the first channel semiconductor layer or the second channel semiconductor layer that holds the logic "1" data. A memory device using the semiconductor element described in feature 1.

14. The memory device is configured such that, during the data erasure period, a plurality of memory cells including the first channel semiconductor layer and the second channel semiconductor layer are configured as a single block, and after block erasure in which the data of all the memory cells in the block is erased at once, the logical "1" data is written to a predetermined memory cell. A memory device using the semiconductor element described in feature 1.

15. The memory device is configured such that, during the data erasure period, the same voltage is applied to both the first bit line and the second source line, and if the signal charge group is a hole, a voltage lower than the voltage applied to the first bit line and the second source line is applied to the first source line, or if the signal charge group is an electron, a voltage higher than the voltage applied to the first bit line and the second source line is applied to the first source line. A memory device using the semiconductor element described in feature 1.

16. In a plan view, the second gate conductor layer and the third gate conductor layer are separated into two gate conductor layers in the central part in a direction perpendicular to the direction in which the first channel semiconductor layer and the second channel semiconductor layer are stretched. A memory device using the semiconductor element described in feature 1.

17. The memory device is configured such that, during the period in which a pulse voltage is applied to one of the two gate conductor layers separated in the central part, a fixed voltage that does not change over time is applied to the other gate conductor layer. A memory device using a semiconductor element as described in feature 16.

18. The memory device is configured such that, during the data retention period, if the signal charge is a group of holes, the voltage applied to the second and third gate conductor layers is the same as or lower than the voltage applied to the first gate conductor layer; and if the signal charge is a group of electrons, the voltage applied to the second and third gate conductor layers is the same as or higher than the voltage applied to the first gate conductor layer. A memory device using the semiconductor element described in feature 1.

19. The second gate conductor layer and the third gate conductor layer each have two separate conductor layer portions aligned in the stretching direction, and each of these two conductor layer portions is arranged to be substantially identical in shape when viewed in a direction perpendicular to the stretching direction and the direction perpendicular to the substrate. The memory device is During the data retention period, in the second and third gate conductor layers, where the signal charge is a group of holes and is separated into two, a voltage lower than the voltage applied to the other gate conductor layer is applied to one gate conductor layer, and in the second and third gate conductor layers, where the signal charge is a group of electrons and is separated into two, a voltage higher than the voltage applied to the other gate conductor layer is applied to one gate conductor layer. A memory device using the semiconductor element described in feature 1.

20. The second gate conductor layer and the third gate conductor layer each have three separate conductor layer portions aligned in the stretching direction, and each of these three conductor layer portions is arranged to be substantially identical in shape when viewed in a direction perpendicular to the stretching direction of the first channel semiconductor layer and the second channel semiconductor layer and the direction perpendicular to the substrate. The memory device is During the data retention period, in the second and third gate conductor layers, where the signal charge is a group of holes and is separated into three parts, the central gate conductor layer is subjected to a voltage lower than the voltage applied to the gate conductor layers on either side. In the second and third gate conductor layers, where the signal charge is a group of electrons and is separated into three parts, the central gate conductor layer is subjected to a voltage higher than the voltage applied to the gate conductor layers on either side. A memory device using the semiconductor element described in feature 1.

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