Storage device and method for manufacturing the same

Abstract

We provide a storage device that enables high-stack stacking. [Solution] The memory device of the embodiment comprises a plurality of memory cells MC, bit lines BL, and word lines WL. The plurality of memory cells include a plurality of transistors CT stacked in the Z direction on a substrate 20, and a plurality of capacitors CC stacked in the Z direction on the substrate and connected to the plurality of transistors. The plurality of transistors include a semiconductor layer 21 extending in the Y direction parallel to the substrate, and a gate electrode layer 23 provided opposite the semiconductor layer 21. The bit lines BL are connected to the semiconductor layers of the plurality of transistors CT and extend in the Z direction. The word lines WL include the gate electrodes of the plurality of transistors CT and extend in the X direction parallel to the substrate and intersecting the Y direction. The semiconductor layer 21 and the bit lines BL contain a conductive oxide.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to a memory device and a method of manufacturing the same.

Background Art

[0002] A memory device including memory cells arranged three-dimensionally is known. Examples of memory devices include DRAM (Dynamic Random Access Memory).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a memory device capable of high stacking.

Means for Solving the Problems

[0005] The memory device according to the embodiment includes a plurality of memory cells including a plurality of transistors stacked in a first direction on a substrate and a plurality of capacitors stacked in the first direction on the substrate and connected to the plurality of transistors, a bit line connected to the plurality of memory cells, and a word line connected to the plurality of memory cells. The plurality of transistors include a semiconductor layer extending in a second direction parallel to the substrate and a gate electrode provided to face the semiconductor layer. The bit line is connected to the semiconductor layer of the plurality of transistors and extends in the first direction. The word line includes the gate electrodes of the plurality of transistors and extends in a third direction parallel to the substrate and intersecting the second direction. The semiconductor layer and the bit line include a conductive oxide.

[0006] The manufacturing method for a memory device of the embodiment is a manufacturing method for a memory device comprising a memory cell including a transistor and a capacitor, a word line, and a bit line, comprising the steps of: alternately stacking a first sacrificial layer and a second sacrificial layer; forming a first slit at one end of the first sacrificial layer and the second sacrificial layer; removing one end of the first sacrificial layer and a portion of one end of the second sacrificial layer to form a sacrificial semiconductor layer corresponding to the semiconductor layer of the transistor at one end of the second sacrificial layer; forming the word line that intersects with the sacrificial semiconductor layer; forming a sacrificial bit line corresponding to the bit line at one end of the sacrificial semiconductor layer; forming a second slit at the other end of the first sacrificial layer and the second sacrificial layer; removing the other end of the second sacrificial layer and forming the capacitor at the other end of the sacrificial semiconductor layer; and replacing a portion of the sacrificial semiconductor layer and the sacrificial bit line with a semiconductor material layer. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram showing the configuration of the storage device according to the embodiment. [Figure 2] This is a circuit diagram showing a partial configuration of a memory cell array according to the embodiment. [Figure 3] This is a circuit diagram showing the configuration of the memory cells in the memory cell array according to the embodiment. [Figure 4] This is a perspective view showing the structure of a memory cell array according to an embodiment. [Figure 5] This is a perspective view showing a method for manufacturing a memory cell array according to an embodiment. [Figure 6] This is a perspective view showing a method for manufacturing a memory cell array according to an embodiment. [Figure 7] This is a perspective view showing a method for manufacturing a memory cell array according to an embodiment. [Figure 8] This is a perspective view showing a method for manufacturing a memory cell array according to an embodiment. [Figure 9] This is a perspective view showing a method for manufacturing a memory cell array according to an embodiment. [Figure 10]It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 11] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 12] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 13] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 14] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 15] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 16] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 17] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 18] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 19] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 20] [[ID=3{]]It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 21] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 22] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 23] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 24] It is a cross-sectional view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 25] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 26] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 27] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 28] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 29] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 30] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 31] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 32] It is a perspective view showing a method of manufacturing a memory cell array according to an embodiment. [Figure 33] It is a perspective view showing a method of manufacturing a memory cell array according to Modification Example 1 of the embodiment. [Figure 34] It is a perspective view showing a method of manufacturing a memory cell array according to Modification Example 1 of the embodiment. [Figure 35] It is a perspective view showing a method of manufacturing a memory cell array according to Modification Example 1 of the embodiment. [Figure 36] It is a perspective view showing a method of manufacturing a memory cell array according to Modification Example 2 of the embodiment. [Figure 37] It is a perspective view showing a method of manufacturing a memory cell array according to Modification Example 2 of the embodiment. [Figure 38] It is a perspective view showing a method of manufacturing a memory cell array according to Modification Example 2 of the embodiment. [Figure 39] It is a cross-sectional view showing a method of manufacturing a memory cell array according to Modification Example 3 of the embodiment. [Figure 40] It is a cross-sectional view showing a method of manufacturing a memory cell array according to Modification Example 3 of the embodiment. [Figure 41] It is a cross-sectional view showing a method of manufacturing a memory cell array according to Modification Example 3 of the embodiment. [Figure 42] It is a cross-sectional view showing a method of manufacturing a memory cell array according to Modification Example 3 of the embodiment. [Figure 43] It is a cross-sectional view showing a method of manufacturing a memory cell array according to Modification Example 3 of the embodiment. [Figure 44] It is a cross-sectional view showing a method of manufacturing a memory cell array according to Modification Example 3 of the embodiment. [Figure 45] This is a perspective view showing a method for manufacturing a memory cell array using an NPOC stacked structure according to a modified example 3 of the embodiment. [Figure 46] This is a perspective view showing a method for manufacturing a memory cell array using an NPOC stacked structure according to a modified example 3 of the embodiment. [Figure 47] This is a perspective view showing a method for manufacturing a memory cell array using an NPOC stacked structure according to a modified example 3 of the embodiment. [Figure 48] This is a perspective view showing a method for manufacturing a memory cell array using an NPOC stacked structure according to a modified example 3 of the embodiment. [Figure 49] This is a cross-sectional view showing a first example of the layout of bit line selection transistors in a memory device according to the embodiment. [Figure 50] This is a cross-sectional view showing a second example of the layout of bit line selection transistors in a memory device according to the embodiment. [Figure 51] This is a cross-sectional view showing a third example of the layout of bit line selection transistors in a memory device according to the embodiment. [Modes for carrying out the invention]

[0008] In the following description, components having the same function and configuration will be denoted by the same reference numeral. Furthermore, the embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this embodiment, and do not specify the materials, shapes, structures, and arrangements of the components as described below.

[0009] The drawings are schematic or conceptual. The dimensions and proportions in each drawing do not necessarily correspond to reality. Some drawings showing structures use the XYZ Cartesian coordinate system. The X-axis extends in the X direction. The Y-axis extends in the Y direction. The Z-axis extends in the Z direction. The X and Y directions are orthogonal to each other. The Z direction is orthogonal to both the X and Y directions and corresponds to the vertical direction with respect to the surface of the semiconductor substrate. In addition, the side with a larger coordinate on the X-axis (X direction), Y-axis (Y direction), or Z-axis (Z direction) may be called the positive direction, and the side with a smaller coordinate may be called the negative direction. The positive direction of the Z-axis may be called the upper side, and the negative direction may be called the lower side. The positive direction of the X or Y axis may be called the right side, and the negative direction may be called the left side.

[0010] The following describes the storage device of the embodiment.

[0011] 1. Structure First, the configuration of the storage device of the embodiment will be described with reference to Figure 1. Figure 1 is a block diagram showing the configuration of the storage device of the embodiment. Storage device 1 is a device for storing data. Storage device 1 is connected to memory controller 2 and is configured to read and write data based on instructions from memory controller 2.

[0012] The storage device 1 comprises a memory cell array 11, an input / output circuit 12, a control circuit 13, a voltage generation circuit 14, a row selection circuit 15, a column selection circuit 16, a write circuit 17, a read circuit 18, and a sense amplifier 19.

[0013] The memory cell array 11 includes multiple memory cells MC, multiple word lines WL, and multiple bit lines BL. Each memory cell MC can store 1 bit of data. Each memory cell MC is connected to one bit line BL and one word line WL. The memory cell MC is connected between the bit line BL and a plate line (not shown). The word line WL is associated with a row. The bit line BL is associated with a column. One memory cell MC is identified by selecting one row and one column.

[0014] The input / output circuit 12 is a circuit that performs input and output of data and signals. The input / output circuit 12 receives control signals CNT, command signals CMD, address signals ADD, and data DAT from outside the storage device 1, for example from the memory controller 2. The input / output circuit 12 inputs and outputs data DAT. When data is written to the storage device 1, data DAT is the written data. When data is read from the storage device 1, data DAT is the read data.

[0015] The control circuit 13 is a circuit that controls the operation of the memory device 1. The control circuit 13 receives a command CMD and a control signal CNT from the input / output circuit 12. Based on the control instructed by the command CMD and the control signal CNT, the control circuit 13 controls the write circuit 17 and the read circuit 18.

[0016] The voltage generation circuit 14 is a circuit that generates various voltages used in the memory device 1. Based on the control of the control circuit 13, the voltage generation circuit 14 generates multiple voltages of different magnitudes. The voltage generation circuit 14 supplies the generated voltages to the memory cell array 11, the write circuit 17, the read circuit 18, and the sense amplifier 19.

[0017] The row selection circuit 15 is a circuit that selects a row of memory cell MC. The row selection circuit 15 receives an address signal ADD from the input / output circuit 12. The row selection circuit 15 uses the voltage received from the voltage generation circuit 14 to select a word line WL associated with the row identified by the address signal ADD.

[0018] The column selection circuit 16 is a circuit that selects a column of memory cells MC. The column selection circuit 16 receives an address signal ADD from the input / output circuit 12. The column selection circuit 16 uses the voltage received from the voltage generation circuit 14 to select the bit line BL associated with the column identified by the address signal ADD.

[0019] The writing circuit 17 is a circuit that controls the writing of data to the memory cell MC. The writing circuit 17 receives the writing data from the input / output circuit 12. Based on the control of the control circuit 13 and the writing data, the writing circuit 17 supplies the voltage received from the voltage generation circuit 14 to the column selection circuit 16.

[0020] The read circuit 18 is a circuit that controls the reading of data from the memory cell MC. Based on the control of the control circuit 13, the read circuit 18 supplies the voltage received from the voltage generation circuit 14 to the column selection circuit 16. The read circuit 18 supplies multiple control signals for data reading to the sense amplifier 19.

[0021] The sense amplifier 19 is a circuit for determining the data stored in the memory cell MC. The sense amplifier 19 includes multiple sense amplifier circuits. The sense amplifier 19 receives multiple voltages from the voltage generation circuit 14 and operates using the received voltages. During data reading, the sense amplifier 19 amplifies the potential on the bit line BL to determine the data stored in the memory cell MC from which the data is to be read. The determined data is supplied to the input / output circuit 12.

[0022] 1.1 Circuit configuration of memory cell array Next, with reference to Figure 2, the memory cell array 11 in the embodiment of the storage device 1 will be described. Figure 2 is a circuit diagram showing a part of the configuration of the memory cell array 11 in the embodiment of the storage device. Figure 3 is a circuit diagram showing the configuration of the memory cells MC in the memory cell array 11.

[0023] As shown in Figure 2, the memory cell array 11 includes multiple memory cells MC. The memory cell array 11 has M word lines WL_0 to WL_M-1, N bit lines BL_0 to BL_N-1, and a plate line PL. M and N are integers greater than or equal to 0.

[0024] As shown in Figure 3, each memory cell MC is connected to one word line WL and one bit line BL. Each memory cell MC is also connected to a plate line PL.

[0025] Each memory cell (MC) includes a cell transistor (CT) and a cell capacitor (or memory element) (CC). The cell transistor (CT) is, for example, an n-type MOS field-effect transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET). Hereinafter, one of the transistor's sources and drains may be referred to as one end of the transistor, and the other as the other end.

[0026] One end of the cell capacitor CC is connected to the plate line PL. The other end of the cell capacitor CC is connected to one end of the cell transistor CT. The node to which the cell capacitor CC and the cell transistor CT are connected is sometimes referred to as the storage node SN. The other end of the cell transistor CT is connected to one bit line BL. Furthermore, the gate of the cell transistor CT is connected to one word line WL.

[0027] The cell capacitor CC stores data using the charge accumulated in the storage node SN, which is connected to the cell transistor CT.

[0028] The state of whether a storage node SN is accumulating charge corresponds to the state in which a memory cell MC is storing "1" data or "0" data. For example, when the potential of the storage node SN is positive relative to the potential of the plate wire PL, the memory cell MC is treated as storing "1" data, and when the potential of the storage node SN is negative relative to the potential of the plate wire PL, the memory cell MC is treated as storing "0" data.

[0029] A semiconductor layer constituting part of a cell transistor (CT) provides at least a region in which a channel is formed (channel region). The material of the semiconductor layer includes or is substantially composed of a conductive oxide (or oxide semiconductor). In this specification and in the claims, “substantially composed” means that the “substantially composed” element is permitted to contain unintended impurities. A conductive oxide refers to an oxide having semiconductor (or conductor) properties. Examples of conductive oxides are oxides containing one or more of indium (In), gallium (Ga), aluminum (Al), zinc (Zn), and tin (Sn). In one example, the conductive oxide is composed of, for example, In, Ga, Zn, and O (oxygen). In another example, it is composed of In, Al, Zn, and O.

[0030] 1.2 Structure of a memory cell array Next, with reference to Figure 4, the structure of the memory cell array 11 in the embodiment of the storage device 1 will be described. Figure 4 is a perspective view showing the structure of the memory cell array 11 in the embodiment of the storage device. Figure 4 shows a structure in which two arrays, a lower array LA and an upper array UA, are stacked.

[0031] As shown in Figure 3, a lower array LA and an upper array UA are provided on the semiconductor substrate 20. The lower array LA is provided above the semiconductor substrate 20, and the upper array UA is provided on top of the lower array LA.

[0032] The lower array LA contains multiple memory cells MC arranged in three dimensions. These memory cells MC are arranged in the X and Y directions, and these X and Y-direction memory cells MC are stacked in the Z direction. Note that in Figure 4, the multiple memory cells MC arranged in the Y direction are omitted, and only one memory cell MC is shown. Similarly, the upper array UA also contains multiple memory cells MC arranged in three dimensions.

[0033] The memory cells MC included in the lower array LA and upper array UA are described below. As mentioned above, the memory cells MC include cell transistors CT and cell capacitors CC.

[0034] A cell transistor (CT) has a semiconductor layer (or channel layer) 21, a gate insulating layer 22, and a gate electrode layer 23. The semiconductor layer 21 is stretched in the Y direction. The semiconductor layer 21 contains, for example, a conductive oxide. The conductive oxide contains at least one of In, Ga, Zn, Sn, Ti, Mo, or W. The gate insulating layer 22 is provided on the lower surface, upper surface, and side surface of the semiconductor layer 21. The gate electrode layer 23 is provided on the lower surface, upper surface, and side surface of the gate insulating layer 22. That is, the gate insulating layer 22 is provided so as to cover the semiconductor layer 21. The gate electrode layer 23 is provided so as to cover the gate insulating layer 22. The gate electrode layer 23 is arranged on the lower surface, upper surface, and side surface of the semiconductor layer 21 via the gate insulating layer 22. The gate electrode layer 23 extends in the X direction and constitutes a word line WL.

[0035] The cell capacitor CC has a first electrode layer 31, a second electrode layer 33, and an insulating layer 32 between the first electrode layer 31 and the second electrode layer 33. The first electrode layer 31 is provided at one end of the semiconductor layer 21 via a conductive layer 34. That is, the first electrode layer 31 is connected to the semiconductor layer 21 via the conductive layer 34. The first electrode layer 31 includes a conductive layer such as a titanium nitride layer. The conductive layer 34 includes a conductive oxide such as ITO (indium tin oxide).

[0036] The second electrode layer 33 is provided facing the first electrode layer 31 via an insulating layer 32. The second electrode layer 33 is shared by the cell capacitors CC of multiple memory cells MC. The second electrode layer 33 is connected to a plate wire PL (not shown). The second electrode layer 33 includes a conductive layer, such as a titanium nitride layer.

[0037] The three conductive layers 21a, 35, and 36 are provided at the other end of the semiconductor layer 21. That is, the conductive layers 21a, 35, and 36 are connected to the semiconductor layer 21. The conductive layers 21a and 35 are provided in sheet form, and the conductive layer 36 is provided in linear form. The conductive layers 21a, 35, and 36 are stretched in the Z direction. The conductive layers 21a, 35, and 36 constitute the bit line BL. Note that the conductive layer 21a may be formed integrally with the semiconductor layer 21. For example, the semiconductor layer 21 and the conductive layer 21a may be formed from the same conductive oxide using the same manufacturing process.

[0038] In the lower array LA (or upper array UA), the number of stacked cell capacitors CC is less than or equal to the number of stacked cell transistors CT.

[0039] Here, we have shown an example where two arrays, a lower array LA and an upper array UA, are stacked, but the same structure is observed when three or more arrays are stacked.

[0040] 2. Manufacturing method Next, a method for manufacturing the memory cell array 11 in the embodiment of the storage device 1 will be described with reference to Figures 5 to 32. Figures 5 to 32 are perspective views showing a method for manufacturing the memory cell array 11 in the embodiment of the storage device.

[0041] First, as shown in Figure 5, a mold layer 40 is formed in which a first sacrificial layer (e.g., a silicon nitride layer) 41 and a second sacrificial layer (e.g., an amorphous or polycrystalline silicon layer) 42 are alternately stacked in the Z direction.

[0042] Specifically, a first sacrificial layer 41 is formed on a semiconductor substrate (not shown) using, for example, CVD (Chemical Vapor Deposition). Subsequently, a second sacrificial layer 42 is formed on the first sacrificial layer 41 using, for example, CVD. Furthermore, the first sacrificial layer 41 is formed on the second sacrificial layer 42, and the second sacrificial layer 42 is formed on the first sacrificial layer 41. Similarly, the formation of the first sacrificial layer 41 and the second sacrificial layer 42 is repeated alternately. This forms a mold layer 40 as shown in Figure 5.

[0043] Next, as shown in Figure 6, holes 43h are formed in the mold layer 40 to form an insulating layer that separates the active area of ​​the cell transistor CT.

[0044] Specifically, for example, RIE (Reactive Ion Etching) is used to form holes 43h in the mold layer 40 that extend in the Y and Z directions.

[0045] Next, as shown in Figure 7, an insulating layer (for example, a silicon oxide layer) 43 is formed on the mold layer 40 to separate the active area of ​​the cell transistor CT.

[0046] Specifically, an insulating layer 43 is embedded in the holes 43h formed in the mold layer 40, for example, using CVD or ALD (Atomic Layer Deposition). Subsequently, the excess insulating layer 43 is removed. As a result, an insulating layer 43 that separates the active area is formed in the mold layer 40, as shown in Figure 7.

[0047] Next, as shown in Figure 8, the stacked layers of the first sacrificial layer 41 and the second sacrificial layer 42 at one end of the mold layer 40 in the negative direction of the Y-axis are removed. Hereafter, in this process, the stacked surface of the first sacrificial layer 41 and the second sacrificial layer 42 from which one end portion has been removed will be referred to as the first slit surface.

[0048] Next, as shown in Figure 9, a portion of the first sacrificial layer 41 is removed from the first slit surface.

[0049] Specifically, a portion of the first sacrificial layer 41 is removed by etching from one end of the first sacrificial layer 41 in the negative direction of the Y-axis, thereby receding the first sacrificial layer 41. In this process, the first sacrificial layer 41 is removed up to just before the region where the cell capacitor CC is formed.

[0050] Next, as shown in Figure 10, the second sacrificial layer 42 exposed by the removal of the first sacrificial layer 41 is trimmed. Hereafter, the trimmed portion of the second sacrificial layer 42 will be referred to as the beam portion 42a.

[0051] Specifically, the second sacrificial layer 42, which is exposed due to the retreat of the first sacrificial layer 41, is trimmed to reduce the thickness of the beam portion 42a in the Z direction.

[0052] Next, as shown in Figure 11, an insulating layer (e.g., a silicon oxide layer) 44 is formed to cover the beam portion 42a of the trimmed second sacrificial layer 42.

[0053] Specifically, for example, CVD is used to fill the beam portion 42a of the trimmed second sacrificial layer 42 with an insulating layer 44. Subsequently, the excess insulating layer 44 is removed. This forms an insulating layer 44 on the beam portion 42a of the second sacrificial layer 42, as shown in Figure 11.

[0054] Next, as shown in Figure 12, a portion of the insulating layer 44 is removed to expose the beam portion 42a of the second sacrificial layer 42.

[0055] Specifically, a portion of the insulating layer 44 is removed by etching from one end of the insulating layer 44 in the negative direction of the Y-direction, thereby receding the insulating layer 44. This exposes the beam portion 42a of the second sacrificial layer 42, as shown in Figure 12.

[0056] Next, as shown in Figure 13, an insulating layer (for example, a silicon nitride layer) 45 is formed on the beam portion 42a of the exposed second sacrificial layer 42.

[0057] Specifically, an insulating layer 45 is formed on the upper, lower, and side surfaces of the beam portion 42a of the second sacrificial layer 42, for example, using CVD or ALD. In this process, the insulating layer 45 is also embedded between adjacent beam portions 42a in the X direction.

[0058] Next, as shown in Figure 14, an insulating layer (for example, a silicon oxide layer) 46 is formed in the space in the Z direction where the insulating layer 45 is not formed.

[0059] Specifically, for example, CVD is used to fill the space between the beam portions 42a of the second sacrificial layer 42 where the insulating layer 45 is not formed with insulating layer 46. Subsequently, the excess insulating layer 46 is removed. As a result, as shown in Figure 14, insulating layer 46 is formed in the space where the insulating layer 45 was not formed.

[0060] Next, as shown in Figure 15, a portion of the insulating layer 45 is removed, and a gate insulating layer (e.g., a silicon oxide layer) 22 is formed on the exposed beam portion 42a of the second sacrificial layer 42. The gate insulating layer 22 functions as the gate insulating layer of the cell transistor CT. The gate insulating layer 22 is formed to cover the beam portion 42a.

[0061] Specifically, a portion of the insulating layer 45 is removed by etching from one end of the insulating layer 45 in the negative direction of the Y-direction, exposing the beam portion 42a of the second sacrificial layer 42. Subsequently, the upper, lower, and side surfaces of the exposed beam portion 42a of the second sacrificial layer 42 are oxidized, for example, using a thermal oxidation method, to form the gate insulating layer 22. As a result, the beam portion 42a of the second sacrificial layer 42 is covered with the gate insulating layer 22, as shown in Figure 15.

[0062] Next, as shown in Figure 16, a gate electrode layer 23 is formed on the gate insulating layer 22 that covers the beam portion 42a of the second sacrificial layer 42. The gate electrode layer 23 functions as the gate electrode layer of the cell transistor CT. The gate electrode layer 23 is formed to cover the gate insulating layer 22 on the beam portion 42a. The gate electrode layer 23 includes a metal layer, such as tungsten.

[0063] Specifically, a gate electrode layer 23 is formed on a gate insulating layer 22 that covers the upper, lower, and side surfaces of the beam portion 42a of the second sacrificial layer 42. The gate electrode layer 23 extends in the X direction and constitutes a word line WL.

[0064] Next, as shown in Figure 17, an insulating layer (for example, a silicon nitride layer) 47 is formed on the beam portion 42a of the second sacrificial layer 42, where the gate electrode layer 23 is not formed. Furthermore, the ends of the beam portion 42a of the second sacrificial layer 42 are exposed.

[0065] Specifically, an insulating layer 47 is embedded on the beam portion 42a of the second sacrificial layer 42, for example, using CVD or ALD. Subsequently, one end portion of the beam portion 42a of the second sacrificial layer 42 and the insulating layer 47 in the negative direction of the Y direction is removed by etching, exposing the end portion of the beam portion 42a of the second sacrificial layer 42.

[0066] Next, as shown in Figure 18, a sacrificial layer (e.g., a polycrystalline silicon layer) 48 is formed on one end face of the mold layer 40 in the negative direction of the Y-axis.

[0067] Specifically, a sacrificial layer 48 is embedded in the exposed ends of the beam portion 42a and the insulating layer 47, for example, using CVD or ALD. Subsequently, the excess sacrificial layer 48 is removed.

[0068] Next, as shown in Figure 19, a sacrificial layer 48a is formed that extends linearly in the Z direction.

[0069] Specifically, for example, RIE is used to remove the sacrificial layer 48 in the Z direction, forming a linear sacrificial layer 48a that extends in the Z direction.

[0070] Next, as shown in Figure 20, an insulating layer (for example, a silicon oxide layer) 49 is formed in the groove between the sacrificial layers 48a.

[0071] Specifically, an insulating layer 49 is embedded in the groove between adjacent sacrificial layers 48a using, for example, CVD or ALD. Subsequently, the excess insulating layer 49 is removed. This forms an insulating layer 49 that extends in the Z direction, as shown in Figure 20.

[0072] Next, as shown in Figure 21, a mold layer 50 for forming the upper array UA is formed on the mold layer 40. Similar to the mold layer 40, the mold layer 50 has a first sacrificial layer 41 and a second sacrificial layer 42 that are alternately stacked in the Z direction.

[0073] Next, as shown in Figure 22, holes 53h are formed in the mold layer 50 to form an insulating layer that separates the active area of ​​the cell transistor CT.

[0074] Subsequently, similar to the mold layer 40, the mold layer 50 is subjected to the manufacturing process shown in Figures 7 to 20, forming a structure similar to the one shown in Figure 20, as shown in Figure 23.

[0075] Next, as shown in Figure 24, the stacked portions of the first sacrificial layer 41 and the second sacrificial layer 42 at the other ends of the mold layers 40 and 50 in the positive direction of the Y-axis are removed. Hereafter, in this process, the stacked surface of the first sacrificial layer 41 and the second sacrificial layer 42 from which the other end portions have been removed will be referred to as the second slit surface.

[0076] Next, as shown in Figure 25, the second sacrificial layer 42 in the region where the cell capacitor CC is formed is removed.

[0077] Specifically, a portion of the second sacrificial layer 42 is removed by etching from the second slit surface, that is, from the other end of the second sacrificial layer 42 in the positive direction of the Y, thereby receding the second sacrificial layer 42. In this process, the second sacrificial layer 42 is removed up to the area in front of where the cell transistor CT is formed, for example, up to the gate insulating layer 22.

[0078] Next, as shown in Figure 26, a conductive layer 34 is formed on the other end face of the second sacrificial layer 42 from which a portion has been removed, i.e., on the other end face of the beam portion 42a. The conductive layer 34 includes, for example, an ITO layer.

[0079] Next, as shown in Figure 27, the first electrode layer 31 of the cell capacitor CC is formed on the conductive layer 34 and the first sacrificial layer 41. Furthermore, a sacrificial layer (e.g., a silicon nitride layer) 51 is formed on the first electrode layer 31. The first electrode layer 31 includes, for example, a titanium nitride layer.

[0080] Specifically, for example, a first electrode layer 31 is formed on the inner surface of the space created by removing the second sacrificial layer 42 using CVD. Furthermore, a sacrificial layer 51 is embedded on the first electrode layer 31.

[0081] Next, as shown in Figure 28, an insulating layer 32 of the cell capacitor CC is formed on the first electrode layer 31, and then a high dielectric layer 52 is formed. The high dielectric layer 52 has a dielectric constant higher than that of the insulating layer 32.

[0082] Specifically, the sacrificial layer 51 is removed, and an insulating layer 32 is formed on the first electrode layer 31. Furthermore, a high dielectric layer 52 is formed on the insulating layer 32.

[0083] Next, as shown in Figure 29, a second electrode layer 33 of the cell capacitor CC is formed on the insulating layer 32 and the high dielectric layer 52. The second electrode layer 33 includes, for example, a titanium nitride layer.

[0084] Specifically, a second electrode layer 33 is formed on the insulating layer 32 and the high dielectric layer 52 so as to face the first electrode layer 31.

[0085] Next, as shown in Figure 30, the sacrificial layer 48a formed in the region where the bit line BL is provided is removed. Furthermore, the beam portion 42a of the second sacrificial layer 42 formed in the region where the semiconductor layer (or channel layer) of the cell transistor CT is provided is removed.

[0086] Specifically, the sacrificial layer 48a is removed to expose the surface of the beam portion 42a of the second sacrificial layer 42. Subsequently, the beam portion 42a is removed by etching from one end of the beam portion 42a in the negative direction of the Y-direction. This removes the beam portion 42a of the second sacrificial layer 42, as shown in Figure 30.

[0087] Next, as shown in Figure 31, a semiconductor layer 21 is formed in the region where the semiconductor layer of the cell transistor CT is provided. At the same time, a conductive layer 21a is formed in the region where the bit line BL is provided. The semiconductor layer 21 and the conductive layer 21a include, for example, a conductive oxide (or a semiconductor material layer). The conductive oxide includes, for example, In, Ga, Zn, and O.

[0088] Specifically, a semiconductor layer 21 is formed in the region where the semiconductor layer of the cell transistor CT is provided, after the beam portion 42a of the second sacrificial layer 42 has been removed. Along with the formation of this semiconductor layer 21, a conductive layer 21a is formed that extends in the Z direction so as to be connected to the semiconductor layer 21. In other words, the sacrificial layer 48a and the beam portion 42a are replaced by the semiconductor layer 21 and the conductive layer 21a. Here, the sacrificial layer 48a is not completely replaced by the semiconductor layer 21 and the conductive layer 21a, and a gap remains where the bit line BL is provided. Note that the conductive layer 21a may be formed separately from the semiconductor layer 21.

[0089] Next, as shown in Figure 32, conductive layers 35 and 36 are formed in the region where the bit line BL is provided.

[0090] Specifically, conductive layers 35 and 36 extending in the Z direction are sequentially formed on the side surface of the conductive layer 21a. The conductive layers 21a, 35, and 36 function as bit lines BL. With this, the manufacturing of the memory cell array 11 of the embodiment is completed.

[0091] 3. Variation 1 The following describes a method for manufacturing the memory cell array 11 in the storage device 1 of the modified embodiment 1. Figures 33 to 35 are perspective views showing the method for manufacturing the memory cell array 11 in the storage device of the modified embodiment 1.

[0092] As shown in Figure 33, an insulating layer (e.g., a silicon oxide layer) 61 and an insulating layer 62 that separates the active area of ​​the cell transistor CT are formed on the mold layer 40 shown in Figure 20.

[0093] Next, as shown in Figure 34, an insulating layer 63 is formed on the insulating layer 61. The insulating layer 63 acts as an etching stop layer to stop etching in the etching process of the layer formed above it. The etching stop layer contains a metal oxide, or a metal nitride, or a metal. The etching stop layer includes, for example, aluminum oxide, or titanium nitride, tungsten, or a laminate of titanium nitride and tungsten.

[0094] Subsequently, as shown in Figure 35, a mold layer 50 is formed in which a first sacrificial layer (e.g., a silicon nitride layer) 41 and a second sacrificial layer (e.g., a polycrystalline silicon layer) 42 are alternately stacked in the Z direction. Furthermore, holes 53h are formed in the mold layer 50 to form an insulating layer that separates the active area of ​​the cell transistor CT. The subsequent steps are the same as the manufacturing process described in Figures 7 to 32.

[0095] 4. Variation 2 The following describes a method for manufacturing the memory cell array 11 in the storage device 1 of the modified embodiment 2. Figures 36 to 38 are perspective views showing the method for manufacturing the memory cell array 11 in the storage device of the modified embodiment 2.

[0096] As shown in Figure 36, an insulating layer (e.g., a silicon oxide layer) 71 is formed on the mold layer 40 shown in Figure 20. Subsequently, as shown in Figure 37, a barrier layer (e.g., titanium nitride) 72 and a metal layer (e.g., tungsten) 73 are formed within the insulating layer 71. The metal layer 73 acts as an etching stop layer to stop etching in the etching process of the layer formed above it.

[0097] Subsequently, as shown in Figure 38, a mold layer 50 is formed in which a first sacrificial layer (e.g., a silicon nitride layer) 41 and a second sacrificial layer (e.g., a polycrystalline silicon layer) 42 are alternately stacked in the Z direction. Furthermore, holes 53h are formed in the mold layer 50 to form an insulating layer that separates the active area of ​​the cell transistor CT. The subsequent steps are the same as the manufacturing process described in Figures 7 to 32.

[0098] 5. Variation 3 Below, as a third modification of the embodiment, another method for manufacturing the memory cell array 11 will be described. In the embodiment, a silicon nitride layer is used as the first sacrificial layer 41 and an amorphous or polycrystalline silicon layer is used as the second sacrificial layer 42, and a stacked structure is formed in which the first sacrificial layer 41 and the second sacrificial layer 42 are stacked alternately to form a cell transistor CT and a cell capacitor CC as a memory cell MC. However, it is also possible to form a memory cell MC using other layers as the first and second sacrificial layers.

[0099] Figures 39 to 44 are cross-sectional views showing the manufacturing method of the memory cell array 11 in a modified embodiment 3 of the storage device. Figures 39 to 44 schematically show the formation process of the cell transistor CT and cell capacitor CC included in the memory cell MC.

[0100] (1) When using a laminated structure of amorphous or polycrystalline silicon layer / silicon nitride layer / amorphous or polycrystalline silicon layer / silicon nitride layer (hereinafter also referred to as an SNSN laminated structure) (same as the structure described in the embodiment).

[0101] First, as shown in Figure 39(a), silicon nitride layers 101 and amorphous or polycrystalline silicon layers 102 are alternately stacked.

[0102] Next, the silicon nitride layer 101 is etched away to expose the amorphous or polycrystalline silicon layer 102. As shown in Figure 39(b), the exposed amorphous or polycrystalline silicon layer 102 is trimmed to form the beam portion 102a of the amorphous or polycrystalline silicon layer 102.

[0103] As shown in Figure 39(c), silicon oxide layers 103 are formed on the upper and lower surfaces of the beam portion 102a of the amorphous or polycrystalline silicon layer 102.

[0104] Next, the silicon oxide layer 103 is etched away to expose the beam portion 102a of the amorphous or polycrystalline silicon layer 102. As shown in Figure 39(d), a silicon nitride layer 104 is formed on the upper and lower surfaces of the beam portion 102a of the amorphous or polycrystalline silicon layer 102.

[0105] Next, a silicon oxide layer 106 is formed on the silicon nitride layer 105. As shown in Figure 39(e), the silicon nitride layer 105 between the beam portion 102a of the amorphous or polycrystalline silicon layer 102 and the silicon oxide layer 106 is recessed by etching.

[0106] As shown in Figure 39(f), a gate insulating layer 22 is formed on the upper and lower surfaces of the beam portion 102a of the amorphous or polycrystalline silicon layer 102. A gate electrode layer 23 is formed on the gate insulating layer 22.

[0107] As shown in Figure 39(g), a silicon oxide layer 106 is formed on the plane of the gate electrode layer 23 in the negative direction of the Y direction. The amorphous or polycrystalline silicon layer 102, excluding the beam portion 102a, is removed by etching.

[0108] As shown in Figure 39(h), the beam portion 102a in the positive direction of the Y direction is recessed by etching. That is, the beam portion 102a on the side where the cell capacitor CC is formed is recessed by etching. An ITO layer 107 is formed in the recessed area of ​​the beam portion 102a. The first electrode layer (or cylinder layer) 31 of the cell capacitor CC is formed on the ITO layer 107.

[0109] Subsequently, although not shown in the diagram, an insulating layer (or dielectric layer) 32 is formed on the first electrode layer 31. Furthermore, a second electrode layer 33 of the cell capacitor CC is formed on the insulating layer 32. Subsequent steps are omitted from the description.

[0110] (2) When a laminated structure of silicon oxide layer / amorphous or polycrystalline silicon layer / silicon oxide layer / amorphous or polycrystalline silicon layer (hereinafter also referred to as OSOS laminated structure) is used.

[0111] First, as shown in Figure 40(a), silicon oxide layers 111 and amorphous or polycrystalline silicon layers 112 are alternately stacked.

[0112] Next, the silicon oxide layer 111 is etched away to expose the amorphous or polycrystalline silicon layer 112. As shown in Figure 40(b), the exposed amorphous or polycrystalline silicon layer 112 is trimmed to form the beam portion 112a of the amorphous or polycrystalline silicon layer 112.

[0113] As shown in Figure 40(c), silicon oxide layers 113 are formed on the upper and lower surfaces of the beam portion 112a of the amorphous or polycrystalline silicon layer 112.

[0114] Next, the silicon oxide layer 113 is etched away to expose the beam portion 112a of the amorphous or polycrystalline silicon layer 112. As shown in Figure 40(d), a silicon nitride layer 114 is formed on the upper and lower surfaces of the beam portion 112a of the amorphous or polycrystalline silicon layer 112.

[0115] Next, a silicon oxide layer 115 is formed on the silicon nitride layer 114. As shown in Figure 40(e), the silicon nitride layer 114 between the beam portion 112a of the amorphous or polycrystalline silicon layer 112 and the silicon oxide layer 115 is recessed by etching.

[0116] As shown in Figure 40(f), a gate insulating layer 22 is formed on the upper and lower surfaces of the beam portion 112a of the amorphous or polycrystalline silicon layer 112. A gate electrode layer 23 is formed on the gate insulating layer 22.

[0117] As shown in Figure 40(g), a silicon oxide layer 116 is formed on the plane of the gate electrode layer 23 in the negative direction of the Y direction. The amorphous or polycrystalline silicon layer 112, excluding the beam portion 112a, is removed by etching.

[0118] As shown in Figure 40(h), the beam portion 112a in the positive direction of the Y direction is recessed by etching. That is, the beam portion 112a on the side where the cell capacitor CC is formed is recessed by etching. An ITO layer 117 is formed in the recessed area of ​​the beam portion 112a. The first electrode layer 31 of the cell capacitor CC is formed on the ITO layer 117.

[0119] Subsequently, although not shown in the diagram, an insulating layer (or dielectric layer) 32 is formed on the first electrode layer 31. Furthermore, a second electrode layer 33 of the cell capacitor CC is formed on the insulating layer 32. Subsequent steps are omitted from the description.

[0120] (3) When using a laminated structure of silicon oxide layer / silicon nitride layer / silicon oxide layer / silicon nitride layer (hereinafter also referred to as ONON laminated structure).

[0121] First, as shown in Figure 41(a), silicon oxide layers 121 and silicon nitride layers 122 are stacked alternately.

[0122] Next, the silicon oxide layer 121 is etched away to expose the silicon nitride layer 122. As shown in Figure 41(b), the exposed silicon nitride layer 122 is trimmed to form the beam portion 122a of the silicon nitride layer 122.

[0123] As shown in Figure 41(c), a silicon oxide layer 123 is formed on the upper and lower surfaces of the beam portion 122a of the silicon nitride layer 122.

[0124] As shown in Figure 41(d), the beam portion 122a of the silicon nitride layer 122 is replaced with the beam portion 124a of the amorphous or polycrystalline silicon layer. That is, the beam portion 122a of the silicon nitride layer 122 is removed by etching, and the beam portion 124a of the amorphous or polycrystalline silicon layer is formed in the area where the beam portion 122a was removed. Then, the silicon oxide layer 123 is recessed by etching, exposing the beam portion 124a of the amorphous or polycrystalline silicon layer. A silicon nitride layer 125 is formed on the upper and lower surfaces of the beam portion 124a of the amorphous or polycrystalline silicon layer.

[0125] Next, a silicon oxide layer 126 is formed on the silicon nitride layer 125. As shown in Figure 41(e), the silicon nitride layer 125 between the beam portion 124a of the amorphous or polycrystalline silicon layer and the silicon oxide layer 126 is recessed by etching.

[0126] As shown in Figure 41(f), a gate insulating layer 22 is formed on the upper and lower surfaces of the beam portion 124a of the amorphous or polycrystalline silicon layer. A gate electrode layer 23 is formed on the gate insulating layer 22.

[0127] As shown in Figure 41(g), a silicon oxide layer 127 is formed on the plane of the gate electrode layer 23 in the negative direction of the Y direction. Furthermore, the silicon nitride layer 122 is removed by etching.

[0128] As shown in Figure 41(h), the beam portion 124a in the positive direction of the Y direction is recessed by etching. That is, the beam portion 124a on the side where the cell capacitor CC is formed is recessed by etching. An ITO layer 128 is formed in the recessed area of ​​the beam portion 124a. The first electrode layer 31 of the cell capacitor CC is formed on the ITO layer 128.

[0129] Subsequently, although not shown in the diagram, an insulating layer (or dielectric layer) 32 is formed on the first electrode layer 31. Furthermore, a second electrode layer 33 of the cell capacitor CC is formed on the insulating layer 32. Subsequent steps are omitted from the description.

[0130] (4) When a laminated structure of silicon oxide layer / silicon nitride layer / amorphous or polycrystalline silicon layer / silicon nitride layer (hereinafter also referred to as ONSN laminated structure) is used.

[0131] First, as shown in Figure 42(a), a silicon oxide layer 131, a silicon nitride layer 132, an amorphous or polycrystalline silicon layer 133, and a silicon nitride layer 134 are stacked in that order.

[0132] As shown in Figure 42(b), the silicon nitride layers 132 and 134 are etched away to expose the amorphous or polycrystalline silicon layer 133.

[0133] As shown in Figure 42(c), silicon oxide layers 135 are formed on the upper and lower surfaces of the exposed amorphous or polycrystalline silicon layer 133.

[0134] As shown in Figure 42(d), the silicon oxide layers 131 and 135 are etched away to expose the amorphous or polycrystalline silicon layer 133. A silicon nitride layer 136 is formed on the upper and lower surfaces of the amorphous or polycrystalline silicon layer 133.

[0135] Next, a silicon oxide layer 137 is formed on the silicon nitride layer 136. As shown in Figure 42(e), the silicon nitride layer 136 between the amorphous or polycrystalline silicon layer 133 and the silicon oxide layer 137 is recessed by etching.

[0136] As shown in Figure 42(f), a gate insulating layer 22 is formed on the upper and lower surfaces of the amorphous or polycrystalline silicon layer 133. A gate electrode layer 23 is formed on the gate insulating layer 22.

[0137] As shown in Figure 42(g), a silicon oxide layer 138 is formed on the plane of the gate electrode layer 23 in the negative direction of the Y-direction. The silicon nitride layers 132 and 134 in the positive direction of the Y-direction are removed by etching. Furthermore, the amorphous or polycrystalline silicon layer 133 in the positive direction of the Y-direction is recessed by etching.

[0138] As shown in Figure 42(h), the amorphous or polycrystalline silicon layer 133 in the positive direction of the Y direction is further recessed by etching. That is, the amorphous or polycrystalline silicon layer 133 on the side where the cell capacitor CC is formed is recessed by etching. An ITO layer 139 is formed in the recessed region of the amorphous or polycrystalline silicon layer 133. The first electrode layer 31 of the cell capacitor CC is formed on the ITO layer 139.

[0139] Subsequently, although not shown in the diagram, an insulating layer (or dielectric layer) 32 is formed on the first electrode layer 31. Furthermore, a second electrode layer 33 of the cell capacitor CC is formed on the insulating layer 32. Subsequent steps are omitted from the description.

[0140] (5) When a laminated structure of silicon oxycarbide layer / silicon oxide layer / amorphous or polycrystalline silicon layer / silicon nitride layer (hereinafter also referred to as NSOC laminated structure) is used.

[0141] First, as shown in Figure 43(a), a silicon oxycarbide (SiOC) layer 141, a silicon oxide layer 142, an amorphous or polycrystalline silicon layer 143, and a silicon nitride layer 144 are laminated in that order.

[0142] As shown in Figure 43(b), the silicon nitride layer 144 is etched away to expose the amorphous or polycrystalline silicon layer 143.

[0143] As shown in Figure 43(c), the silicon oxide layer 142 is trimmed.

[0144] As shown in Figure 43(d), a silicon nitride layer 145 is formed on the structure shown in Figure 43(c).

[0145] As shown in Figure 43(e), the silicon nitride layer 145 is etched away to expose the amorphous or polycrystalline silicon layer 143.

[0146] As shown in Figure 43(f), a gate insulating layer 22 is formed on the upper surface of the amorphous or polycrystalline silicon layer 143. A gate electrode layer 23 is formed on the gate insulating layer 22.

[0147] As shown in Figure 43(g), a silicon oxide layer 146 is formed on the surface of the gate electrode layer 23 in the negative direction of the Y-direction. Subsequently, the silicon nitride layer 144 in the positive direction of the Y-direction is etched away. Furthermore, the amorphous or polycrystalline silicon layer 143 in the positive direction of the Y-direction is etched away. That is, the silicon nitride layer 144 and the amorphous or polycrystalline silicon layer 143 on the side where the cell capacitor CC is formed are etched away.

[0148] As shown in Figure 43(h), an ITO layer 147 is formed in the recessed region of the amorphous or polycrystalline silicon layer 143. The first electrode layer 31 of the cell capacitor CC is formed on the ITO layer 147.

[0149] Subsequently, although not shown in the diagram, an insulating layer (or dielectric layer) 32 is formed on the first electrode layer 31. Furthermore, a second electrode layer 33 of the cell capacitor CC is formed on the insulating layer 32. Subsequent steps are omitted from the description. The manufacturing method of the memory cell using the above-described NSOC stacked structure will be described in detail later.

[0150] (6) When using a laminated structure of silicon oxide layer / polycrystalline silicon layer / silicon nitride layer / polycrystalline silicon layer (hereinafter also referred to as OPNP laminated structure).

[0151] First, as shown in Figure 44(a), a silicon oxide layer 151, a polycrystalline silicon layer 152, a silicon nitride layer 153, and a polycrystalline silicon layer 154 are stacked in that order.

[0152] As shown in Figure 44(b), the silicon nitride layer 153 is etched away to expose the polycrystalline silicon layers 152 and 154.

[0153] As shown in Figure 44(c), the silicon oxide layer 151 is trimmed.

[0154] As shown in Figure 44(d), a silicon nitride layer 155 is formed on the structure shown in Figure 44(c).

[0155] As shown in Figure 44(e), the silicon nitride layer 155 is etched away to expose the polycrystalline silicon layers 152 and 154.

[0156] As shown in Figure 44(f), a gate insulating layer 22 is formed on the upper surface of the polycrystalline silicon layer 152 and the lower surface of the polycrystalline silicon layer 154. A gate electrode layer 23 is formed on the gate insulating layer 22.

[0157] As shown in Figure 44(g), a silicon oxide layer 156 is formed on the plane of the gate electrode layer 23 in the negative direction of the Y-direction. The silicon nitride layer 153 in the positive direction of the Y-direction is etched away. Furthermore, the polycrystalline silicon layers 152 and 154 in the positive direction of the Y-direction are etched away. That is, the silicon nitride layer 153 and polycrystalline silicon layers 152 and 154 on the side where the cell capacitor CC is formed are etched away.

[0158] As shown in Figure 44(h), an ITO layer 157 is formed in the recessed polycrystalline silicon layers 152 and 154. The first electrode layer 31 of the cell capacitor CC is formed on the ITO layer 157.

[0159] Subsequently, although not shown in the diagram, an insulating layer (or dielectric layer) 32 is formed on the first electrode layer 31. Furthermore, a second electrode layer 33 of the cell capacitor CC is formed on the insulating layer 32. Subsequent steps are omitted from the description.

[0160] The method for manufacturing a memory cell using the NSOC stacked structure described in (5) above will be explained below with reference to the perspective views shown in Figures 45 to 48. Figures 45 to 48 are perspective views showing the method for manufacturing a memory cell array using the NSOC stacked structure in Modification 3.

[0161] First, as shown in Figure 45, a mold layer 80 is formed in which a silicon oxycarbide layer 141, a silicon oxide layer 142, an amorphous or polycrystalline silicon layer 143, and a silicon nitride layer 144 are stacked in the Z direction in sequence. Furthermore, holes 83h are formed in the mold layer 80 to form an insulating layer that separates the active area of ​​the cell transistor CT.

[0162] Next, as shown in Figure 46, a silicon oxide layer 83 is formed in the hole 83h formed in the mold layer 80, for example, using CVD. Furthermore, one end portion of the mold layer 80 in the negative direction of the Y direction is removed. Hereafter, in this process, the laminated surface of the mold layer 80 from which one end portion has been removed will be referred to as the slit surface.

[0163] Next, as shown in Figure 47, a portion of the silicon nitride layer 144 is removed from the slit surface. That is, a portion of the silicon nitride layer 144 is removed by etching from one end of the silicon nitride layer 144 in the negative direction of the Y direction, thereby receding the silicon nitride layer 144.

[0164] Next, as shown in Figure 48, the silicon oxide layer 83 is trimmed to form a region where the word line WL is to be placed. That is, the silicon oxide layer 83 is removed by etching from the region where the silicon nitride layer 144 has been removed, creating a space for placing the word line WL.

[0165] Subsequently, although not shown in the diagram, a gate insulating layer 22 is formed on the upper surface of the amorphous or polycrystalline silicon layer 143. Furthermore, a word line WL, which serves as the gate electrode layer 23, is formed on the gate insulating layer 22. Subsequent steps are omitted from the description.

[0166] 6. Bit line selection transistor Next, the layout of the bit-line selection transistor used in the memory device of the embodiment will be described with reference to Figures 49, 50, and 51. Figures 49, 50, and 51 are cross-sectional views showing the first, second, and third examples of the bit-line selection transistor layout, respectively. Note that in Figures 49, 50, and 51, details such as fillings and interlayer insulating layers in the cross-section of the layers are omitted.

[0167] Figure 49 is a cross-sectional view showing a first example of the layout of bit line selection transistors in a memory device according to an embodiment.

[0168] A peripheral circuit PEC is provided below the memory cell array 11 (i.e., in the negative Z direction). The peripheral circuit PEC includes, for example, a CMOS circuit. A bit line selection transistor STR for selecting the bit line BL is provided between the memory cell array 11 and the peripheral circuit PEC.

[0169] Furthermore, a global bit line GBL is provided above the memory cell array 11 (i.e., in the positive Z direction). Multiple bit lines BL within the memory cell array 11 are connected to the global bit line GBL via contact plugs VI.

[0170] In other words, peripheral circuits PEC are arranged on the semiconductor substrate 20. Bit line selection transistors STR are arranged above the peripheral circuits PEC. Memory cell arrays 11 are arranged above the bit line selection transistors STR. Furthermore, global bit lines GBL are arranged above the memory cell arrays 11.

[0171] As described above, the memory cell array 11 includes a plurality of memory cells MC. Each memory cell MC includes a cell transistor CT and a cell capacitor CC. One end of the cell transistor CT is connected to the cell capacitor CC. The other end of the cell transistor CT is connected to the bit line BL. One end of the bit line BL is connected to the peripheral circuit PEC via a bit line selection transistor STR. The other end of the bit line BL is connected to the global bit line GBL via a contact plug VI.

[0172] The bit line selection transistor STR includes, for example, single-crystal or polycrystalline silicon, or a conductive oxide, as the semiconductor layer (or channel layer).

[0173] The peripheral circuit PEC includes, for example, a sense amplifier 19, a column selection circuit 16, a write circuit 17, a read circuit 18, a row selection circuit 15, a voltage generation circuit 14, a control circuit 13, and an input / output circuit 12.

[0174] As described above, by placing the bit line selection transistor STR between the peripheral circuit PEC and the memory cell array 11, which are arranged in the Z direction, the area in the XY plane required to form the bit line selection transistor STR can be reduced.

[0175] Figure 50 is a cross-sectional view showing a second example of the layout of bit line selection transistors in the memory device of the embodiment.

[0176] A bit line selection transistor STR is provided above the semiconductor substrate 20 (i.e., in the positive Z direction). A memory cell array 11 is provided above the bit line selection transistor STR. In other words, the bit line selection transistor STR is provided between the semiconductor substrate 20 and the memory cell array 11.

[0177] Furthermore, a global bit line GBL is provided above the memory cell array 11. Multiple bit lines BL within the memory cell array 11 are connected to the global bit line GBL via contact plugs VI.

[0178] One end of the cell transistor CT is connected to the cell capacitor CC. The other end of the cell transistor CT is connected to the bit line BL. One end of the bit line BL is connected to the semiconductor substrate 20 via the bit line selection transistor STR. The other end of the bit line BL is connected to the global bit line GBL via the contact plug VI.

[0179] As described above, by placing the bit line selection transistor STR between the semiconductor substrate 20 and the memory cell array 11, which are arranged in the Z direction, the area in the XY plane required to form the bit line selection transistor STR can be reduced.

[0180] Figure 51 is a cross-sectional view showing a third example of the layout of bit line selection transistors in the memory device of the embodiment.

[0181] A memory cell array 11 is provided above the semiconductor substrate 20 (i.e., in the positive Z direction). A bit line selection transistor STR is provided above the memory cell array 11. A global bit line GBL is provided above the bit line selection transistor STR. That is, a bit line selection transistor STR is provided between the memory cell array 11 and the global bit line GBL. Multiple bit lines BL within the memory cell array 11 are connected to the global bit line GBL via a contact plug VI and the bit line selection transistor STR.

[0182] One end of the cell transistor CT is connected to the cell capacitor CC. The other end of the cell transistor CT is connected to the bit line BL. One end of the bit line BL is connected to the global bit line GBL via the contact plug VI and the bit line selection transistor STR.

[0183] As described above, by placing the bit line selection transistor STR between the memory cell array 11 arranged in the Z direction and the global bit line GBL, the area in the XY plane required to form the bit line selection transistor STR can be reduced.

[0184] 7. Effects according to the embodiment According to the embodiment, a storage device that can be highly stacked can be provided. This makes it possible to increase the storage capacity of the storage device. Alternatively, it makes it possible to highly integrate memory cells in the storage device.

[0185] Generally, when forming memory cells using an epitaxially grown Si / SiGe stacked structure and stacking these memory cells on a substrate, there are limitations to the epitaxial growth of Si / SiGe. Furthermore, once a Si / SiGe epitaxial stacked film is processed to form a DRAM cell structure, it becomes impossible to form another Si / SiGe epitaxial stacked film on top of it, making high-level stacking difficult in some cases.

[0186] Therefore, in this embodiment, memory cells (MCs) are formed using, for example, an amorphous or polycrystalline silicon / silicon nitride (hereinafter referred to as Si / SiN) stacked structure. The Si / SiN stacked structure can be formed by a film deposition apparatus such as CVD without using epitaxial growth. For this reason, there are no limitations on the formation of the stacked structure as there are when epitaxial growth is used, and it is possible to achieve high stacking of memory cells (MCs).

[0187] Furthermore, in this embodiment, the cell transistor CT is formed after the cell capacitor CC of the memory cell MC is formed. That is, after the cell capacitor CC is formed, the semiconductor layer (i.e., the channel layer) of the cell transistor CT is formed by replacing the sacrificial layer. Therefore, the cell transistor CT is not exposed to the thermal process during the formation of the cell capacitor CC, and degradation of the characteristics of the cell transistor CT can be prevented. In addition, since the semiconductor layer of the cell transistor CT is formed by replacing the sacrificial layer, a conductive oxide can be applied to the semiconductor layer of the cell transistor CT. Furthermore, the bit line BL can be formed along with the formation of the semiconductor layer of the cell transistor CT. That is, a part of the bit line BL can be formed using the process for forming the semiconductor layer of the cell transistor CT.

[0188] In the above-described embodiments, functional blocks can be implemented as hardware, computer software, or a combination of both. It is not necessary for functional blocks to be distinguished as in the following example. For example, some functions may be performed by functional blocks other than the exemplary functional block. Furthermore, the exemplary functional block may be further divided into more detailed functional subblocks.

[0189] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0190] 1...Memory device, 2...Memory controller, 11...Memory cell array, 12...Input / output circuit, 13...Control circuit, 14...Voltage generation circuit, 15...Row selection circuit, 16...Column selection circuit, 17...Write circuit, 18...Read circuit, 19...Sense amplifier, 20...Semiconductor substrate, 21...Semiconductor layer, 21a...Conductive layer, 22...Gate insulating layer, 23...Gate gate layer, 31...Electrode layer, 32...Insulating layer, 33...Electrode layer, 34...Conductive layer, 35...Conductive layer, 40...Mold layer, 41...Sacrificial layer (e.g., silicon nitride layer), 42...Sacrificial layer (e.g., amorphous or polycrystalline silicon layer) ), 42a...beam section, 43...insulating layer, 43h...hole, 44...insulating layer, 45...insulating layer, 46...insulating layer, 47...insulating layer, 48...sacrificial layer, 48a...sacrificial layer, 49...insulating layer, 50...molding layer, 51...sacrificial layer, 52...high dielectric layer, 53h...hole, 61...insulating layer, 62...insulating layer, 63...insulating layer, 71...insulating layer, 80...molding layer, 83...silicon oxide layer, 83h...hole, 101...silicon nitride layer, 102...amorphous or polycrystalline silicon layer, 102a...beam section, 103...silicon oxide layer, 104...silicon nitride layer, 105...silicon nitride layer, 106...silicon oxide layer 107...ITO layer, 111...Silicon oxide layer, 112...Amorphous or polycrystalline silicon layer, 112a...Beam section, 113...Silicon oxide layer, 114...Silicon nitride layer, 115...Silicon oxide layer, 116...Silicon oxide layer, 117...ITO layer, 121...Silicon oxide layer, 122...Silicon nitride layer, 122a...Beam section, 123...Silicon oxide layer, 124a...Beam section, 125...Silicon nitride layer, 126...Silicon oxide layer, 127...Silicon oxide layer, 128...ITO layer, 131...Silicon oxide layer, 132...Silicon nitride layer, 133...Amorphous or polycrystalline silicon 134...Silicon nitride layer, 135...Silicon oxide layer, 136...Silicon nitride layer, 137...Silicon oxide layer, 138...Silicon oxide layer, 139...ITO layer, 141...Silicon carbide layer, 142...Silicon oxide layer, 143...Amorphous or polycrystalline silicon layer, 144...Silicon nitride layer, 145...Silicon nitride layer, 146...Silicon oxide layer, 147...ITO layer, 151...Silicon oxide layer, 152...Polycrystalline silicon layer, 153...Silicon nitride layer, 154...Polycrystalline silicon layer, 155...Silicon nitride layer, 156...Silicon oxide layer, 157...ITO layer.

Claims

1. A plurality of memory cells, each including a plurality of transistors stacked on a substrate in a first direction, and a plurality of capacitors stacked on the substrate in the first direction and connected to the plurality of transistors, Bit lines connected to the plurality of memory cells, Word lines connected to the plurality of memory cells, Equipped with, Each of the plurality of transistors includes a semiconductor layer extending in a second direction parallel to the substrate and a gate electrode provided opposite to the semiconductor layer. The bit line is connected to the semiconductor layer of the plurality of transistors and extends in the first direction. The word line includes the gate electrodes of the plurality of transistors and extends in a third direction parallel to the substrate and intersecting the second direction. The semiconductor layer and the bit line include a conductive oxide. storage device.

2. The conductive oxide included in the bit line is provided integrally with the conductive oxide included in the semiconductor layer, The storage device according to claim 1.

3. The conductive oxide contained in the bit wire is provided in the form of a sheet extending in the first direction, The bit line further comprises a conductive layer provided along the sheet-like conductive oxide. The storage device according to claim 1.

4. The substrate further comprises plate electrodes connected to the plurality of capacitors stacked on the substrate, The storage device according to claim 1.

5. The number of stacked capacitors is less than or equal to the number of stacked transistors. The storage device according to claim 1.

6. The conductive oxide contains one of In, Ga, Zn, Sn, Ti, Mo, or W. The storage device according to claim 1.

7. The gate electrode of the transistor is provided so as to cover the semiconductor layer. The storage device according to claim 1.

8. The gate electrode of the transistor is provided on either the upper or lower surface of the semiconductor layer. The storage device according to claim 1.

9. The semiconductor layer of the transistor includes a first semiconductor layer and a second semiconductor layer. The gate electrode of the transistor is located between the first semiconductor layer and the second semiconductor layer. The storage device according to claim 1.

10. The system further comprises a transistor provided between the substrate and the plurality of memory cells and connected to the bit line. The storage device according to claim 1.

11. A first circuit provided between the substrate and the plurality of memory cells, A transistor is provided between the first circuit and the plurality of memory cells and is connected to the bit line, Furthermore, The storage device according to claim 1.

12. A global bit line provided above the plurality of memory cells, A transistor is provided between the plurality of memory cells and the global bit line, and is connected to the bit line and the global bit line, Furthermore, The storage device according to claim 1.

13. In a method for manufacturing a memory device comprising a memory cell including a transistor and a capacitor, a word line, and a bit line, A process of alternately stacking the first sacrificial layer and the second sacrificial layer, A step of forming a first slit at one end of the first sacrificial layer and the second sacrificial layer, A step of forming a sacrificial semiconductor layer corresponding to the semiconductor layer of the transistor on one end of the second sacrificial layer by removing one end of the first sacrificial layer and a portion of one end of the second sacrificial layer, A step of forming the word line that intersects the sacrificial semiconductor layer, A step of forming a sacrificial bit line corresponding to the bit line at one end of the sacrificial semiconductor layer, The process involves forming a second slit at the other end of the first sacrificial layer and the second sacrificial layer, The steps include removing the other end of the second sacrificial layer and forming the capacitor at the other end of the sacrificial semiconductor layer, A step of replacing the sacrificial semiconductor layer and the sacrificial bit line with a semiconductor material layer, A method for manufacturing a storage device equipped with the above.

14. Before forming the second slit, the process from laminating the first and second sacrificial layers to forming the sacrificial bit line is repeated multiple times. After the above repetition, the capacitor is formed, and the sacrificial semiconductor layer and the sacrificial bit lines are replaced with the semiconductor material layer. A method for manufacturing a storage device according to claim 13.

15. In forming the capacitor, the second sacrificial layer is removed from the second slit, and a layer containing a conductive oxide is formed at the other end of the sacrificial semiconductor layer. A method for manufacturing a storage device according to claim 13.

16. Before repeating the process from stacking the first sacrificial layer and the second sacrificial layer to forming the sacrificial bit line multiple times, an etching stop layer is formed above the second sacrificial layer. A method for manufacturing a storage device according to claim 14.

17. After replacing the sacrificial semiconductor layer and the sacrificial bit line with a semiconductor material layer, A conductive layer is formed on the semiconductor material layer in which a portion of the sacrificial bit lines has been replaced. A method for manufacturing a storage device according to claim 13.

18. The semiconductor material layer includes a conductive oxide. A method for manufacturing a storage device according to claim 13.

19. The conductive oxide contains one of In, Ga, Zn, Sn, Ti, Mo, or W. A method for manufacturing a storage device according to claim 18.

20. The first sacrificial layer comprises silicon nitride, and the second sacrificial layer comprises amorphous or polycrystalline silicon. A method for manufacturing a storage device according to claim 13.

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