Barrier layer for word line contacts in 3D NAND memory

Abstract

This invention provides a barrier layer for word line contacts in 3D NAND memory. [Solution] This disclosure provides a method for forming a three-dimensional memory device. The method includes arranging an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate, and forming a stepped structure and a partition wall within the alternating dielectric stack. The stepped structure and the partition wall extend in a second direction parallel to the substrate, and the partition wall is adjacent to the stepped structure. The method also includes sequentially forming a first barrier layer and a second barrier layer distinct from the first barrier layer on the stepped structure. The method further includes forming gate line slit (GLS) openings in the partition walls. The GLS openings penetrate the alternating dielectric stack in the first direction and are far from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction.

Description

[Technical Field]

[0001] This disclosure relates generally to the field of semiconductor technology, and more specifically to structures and manufacturing methods for forming barrier layers to provide etch stops to word line contacts in three-dimensional NAND flash memory. [Background technology]

[0002] As memory devices are reduced to smaller die sizes to lower manufacturing costs and increase storage density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address these density and performance limitations in planar memory cells.

[0003] In 3D NAND flash memory, many layers of memory cells can be stacked vertically, which can significantly increase the storage density per unit area. Vertically stacked memory cells are addressed through word lines and bit lines, with each word line controlling a memory cell on one layer. A stepped structure can be used to provide electrical connections to the vertically stacked word lines, forming a contact structure for each word line.

[0004] To further increase the storage density of 3D NAND flash memory, the number of vertically stacked word lines has been significantly increased. Therefore, the contact structures for the word lines have a wide range of depths, with the shortest being for the topmost word line and the longest for the bottommost word line. To simultaneously form the contact structures for the word lines, an etch-stop layer (e.g., silicon nitride) is placed on a stepped structure, thereby avoiding over-etching on the upper word lines. However, the etch-stop layer can be lost during various processes before the contact structures are manufactured. In addition, the etch-stop layer can introduce other problems. For example, a thick etch-stop layer can cause seams during tungsten refilling when forming word lines. Therefore, there is a need to provide an improved method for forming 3D NAND flash memory. [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Embodiments of improved structures and manufacturing methods for forming a barrier layer to provide etch stops for word line contacts in a three-dimensional (3D) memory device are described in this disclosure. [Means for solving the problem]

[0006] One aspect of the present disclosure provides a method for forming a three-dimensional memory device. The method includes arranging an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate, and forming a stepped structure and a partition wall within the alternating dielectric stack. The stepped structure and partition wall extend in a second direction parallel to the substrate, and the partition wall is adjacent to the stepped structure. The method also includes sequentially forming a first barrier layer and a second barrier layer distinct from the first barrier layer on the stepped structure. The method further includes forming gate line slit (GLS) openings in the partition walls. The GLS openings penetrate the alternating dielectric stack in the first direction and are far from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction.

[0007] In some embodiments, forming a first barrier layer on a stepped structure further includes arranging the first barrier layer to cover at least the side walls of the stepped steps of the stepped structure.

[0008] In some embodiments, forming a second barrier layer on a stepped structure includes arranging a dielectric material on the stepped structure and the dividing wall, and removing the first portion of the dielectric material arranged on the dividing wall.

[0009] In some embodiments, the method further includes removing a second portion of dielectric material disposed within a second region of a stepped structure adjacent to a dividing wall to form a second barrier layer within a first region of the stepped structure, wherein the first and second regions extend in a second direction, and the first region is at the center of the stepped structure.

[0010] In some embodiments, the method also includes arranging a block mask to expose the dividing wall and a second region of a stepped structure adjacent to the dividing wall.

[0011] In some embodiments, the method involves arranging a GLS filler inside a GLS opening to form a GLS, further comprising arranging a GLS filler that includes an insulating material to form a GLS.

[0012] In some embodiments, the method further includes removing a second dielectric layer from between first dielectric layers through a GLS opening to form a lateral tunnel, and arranging a first conductive material within the lateral tunnel to form a film stack comprising alternately stacked conductive layers and first dielectric layers.

[0013] In some embodiments, removing the second dielectric layer involves selectively etching the second dielectric layer with respect to the first dielectric layer and the first barrier layer.

[0014] In some embodiments, the method further includes arranging an insulating layer on a second barrier layer that rests on a stepped structure.

[0015] In some embodiments, the method further includes forming a contact structure that contacts one of the conductive layers in a film stack, which includes penetrating an insulating layer in a first direction to expose a portion of one of the conductive layers, and arranging a second conductive material within the contact opening to contact the exposed portion of one of the conductive layers.

[0016] In some embodiments, forming a contact opening includes selectively etching an insulating layer with respect to a second barrier layer and etching the second barrier layer and the first barrier layer to expose a portion of one of the conductive layers within the contact opening.

[0017] Another aspect of the present disclosure provides a three-dimensional (3D) memory device. The 3D memory device includes a film stack having alternatingly stacked conductive layers and a first dielectric layer on a substrate in a first direction perpendicular to the substrate. The 3D memory device also includes a stepped structure disposed within the film stack and extending in a second direction parallel to the substrate, and a partition wall extending in the second direction and disposed adjacent to the stepped structure. The 3D memory device further includes a gate line slit (GLS) disposed within the partition wall, the GLS penetrating the film stack in the first direction and extending in the second direction. The 3D memory device also includes a first barrier layer disposed on the stepped structure, and a second barrier layer disposed on the first barrier layer within a first region of the stepped structure, which is different from the first barrier layer, and the second barrier layer is farther from the GLS in a third direction parallel to the substrate and perpendicular to the second direction.

[0018] In some embodiments, the first barrier layer covers at least the side walls of the stepped steps of the stepped structure.

[0019] In some embodiments, the 3D memory device further comprises an insulating layer disposed on the second barrier layer so as to cover the top surface and sidewalls of the second barrier layer.

[0020] In some embodiments, the 3D memory device also includes a contact structure that penetrates the insulating layer, the second barrier layer, and the first barrier layer in a first direction, and the contact structure contacts one of the conductor layers of the film stack.

[0021] In some embodiments, the first region is at the center of the stepped structure and extends in a second direction.

[0022] In some embodiments, the stepped structure further includes a second region that extends in the second direction and is positioned between the partition wall and the first region.

[0023] In some embodiments, the first barrier layer contains silicon oxide and the second barrier layer contains silicon nitride.

[0024] In some embodiments, the first barrier layer has a thickness within the range of 10 nm to 100 nm.

[0025] In some embodiments, the second barrier layer has a thickness within the range of 50 nm to 500 nm.

[0026] In some embodiments, the GLS includes an insulating material and is configured to divide the storage unit into sub-storage units that independently perform read or program operations.

[0027] Yet another aspect of the present disclosure provides a memory storage system including a three-dimensional memory device and a memory controller. The 3D memory device includes the features described above. The memory controller is configured to control the operation of the three-dimensional memory device and is connected to the 3D memory device.

[0028] A further aspect of this disclosure provides a 3D memory die including a three-dimensional memory device and peripheral circuitry. The 3D memory device includes the features described above. The peripheral circuitry is coupled to the 3D memory device and configured to support the operation of the 3D memory device.

[0029] Other aspects of this disclosure can be understood by those skilled in the art in light of the description, claims, and drawings of this disclosure.

[0030] The accompanying drawings, incorporated herein and forming part thereof, illustrate embodiments of the present disclosure and, together with the description, further assist in explaining the principles of the present disclosure and enabling those skilled in the art to fabricate and use the present disclosure. [Brief explanation of the drawing]

[0031] [Figure 1] This is a schematic top-down diagram illustrating exemplary three-dimensional (3D) memory devices according to some embodiments of the present disclosure. [Figure 2] This is a schematic top-down diagram illustrating the regions of a 3D memory device according to some embodiments of the present disclosure. [Figure 3] This is a perspective view illustrating some exemplary 3D memory array structures according to several embodiments of the present disclosure. [Figure 4-1] This figure illustrates process flows for manufacturing 3D memory devices according to some embodiments of the present disclosure. [Figure 4-2] This figure illustrates process flows for manufacturing 3D memory devices according to some embodiments of the present disclosure. [Figure 5] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 6] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 7]This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 8] This is a top-down diagram illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure. [Figure 9] This is a perspective view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 10] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 11] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 12] This is a top-down diagram illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure. [Figure 13A] This is a top-down diagram illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure. [Figure 13B] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 13C] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 13D] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 14A] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 14B]This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 14C] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 15A] This is a top-down diagram illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure. [Figure 15B] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 16A] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 16B] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 16C] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 17A] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 17B] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 17C] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 18A] This is a top-down diagram illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure. [Figure 18B]This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 19A] This is a top-down diagram illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure. [Figure 19B] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 20A] This is a top-down diagram illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure. [Figure 20B] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 20C] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 20D] This is a cross-sectional view illustrating an exemplary structure of a 3D memory device in a particular process step according to some embodiments of the present disclosure. [Figure 21A] This is a cross-sectional view illustrating another exemplary structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 21B] This is a cross-sectional view illustrating another exemplary structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 21C] This is a cross-sectional view illustrating another exemplary structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 22] This figure illustrates a storage system having one or more memory chips according to some embodiments of the present disclosure. [Figure 23A] This figure illustrates a storage system having one or more memory chips according to some embodiments of the present disclosure. [Figure 23B]This figure illustrates a storage system having one or more memory chips according to some embodiments of the present disclosure. [Figure 24] This is a schematic diagram illustrating three-dimensional (3D) memory dies according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0032] The features and advantages of the present invention will become more apparent when read in conjunction with the drawings, which use similar reference letters to identify corresponding elements throughout the detailed description provided below. In the drawings, similar reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit of the corresponding reference number.

[0033] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0034] While specific configurations and arrangements are described, it will be understood that these are described for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure may be adopted in a variety of other applications.

[0035] References in the specification such as "one embodiment," "embodiment," "an exemplary embodiment," and "several embodiments" should be noted to indicate that the embodiments described may have certain features, structures, or characteristics, but not all embodiments may necessarily include those features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when certain features, structures, or characteristics are described in relation to one embodiment, it will be within the knowledge of those skilled in the art that such features, structures, or characteristics may be affected in relation to other embodiments, whether or not they are explicitly described.

[0036] The terms “first,” “second,” or similar terms may be used here to describe various elements, but these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiment, the first element may also be called the second element, and similarly, the second element may also be called the first element. As used herein, the phrase “and / or” includes any combination of the one or more items listed in relation to the relevant item.

[0037] In general, terms can be understood, at least in part, from their usage in context. For example, at least in part, depending on the context, the phrase “one or multiple” as used herein may be used to describe a feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, here again, articles such as “a,” “an,” or “the” in the English original may be understood, at least in part, depending on the context, as to indicate singular or plural use. In addition, the phrase “based on” can be understood not necessarily intended to convey an exclusive set of elements, but instead, at least in part, depending on the context, may allow for the presence of additional elements that are not necessarily explicitly described.

[0038] It should be readily understood that the meanings of “on,” “above,” and “over” in the original English text of this disclosure should be interpreted in the broadest sense, with “on” not only meaning “directly on top of” something, but also including the meaning of “on top of” something with an intermediate feature or layer in between. Furthermore, “above” or “over” in the original English text can also mean “above” or “on” something without an intermediate feature or layer in between (i.e., directly on top of something), not only meaning “above” something or “on top of” something that is overlapping something, but also “on top of” something or overlapping something without an intermediate feature or layer in between.

[0039] Spatial relative terms in the original English text, such as "beneath," "below," "lower," "above," "upper," and similar words, may be used herein to facilitate description when describing the relationship between one element or feature and another, as illustrated in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or process stages, in addition to the orientation shown in the figures. The device may be oriented in any other way (rotated 90 degrees or in other directions), and the spatial relative descriptors used herein may be interpreted accordingly.

[0040] As used herein, the term “substrate” refers to the material to which subsequent material layers are added. A substrate comprises a “top” surface and a “bottom” surface. The top surface of the substrate is typically where the semiconductor device is formed, and therefore, unless otherwise specified, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. Patterns can be formed on the substrate itself. Materials added on the substrate can be patterned or left unpatterned. Furthermore, substrates can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, substrates can be made from electrically nonconductive materials, such as glass, plastic, or sapphire wafers.

[0041] As used herein, the term “layer” refers to a portion of a material that includes a region having thickness. A layer has a top and a bottom, with the bottom of the layer being relatively close to the substrate and the top being relatively far from the substrate. A layer may extend across an entire structure below or above, or may have a smaller extent than the extent of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom of a continuous structure, or between any pair of horizontal planes at the top and bottom. A layer may extend along horizontal, vertical, and / or tapered surfaces. The substrate may be a layer, may contain one or more layers, and / or have one or more layers above, above, and / or below it. A layer may also contain multiple layers. For example, the interconnection layer may include one or more conductive layers and contact layers (on which contacts, interconnection lines, and / or vertical interconnection accesses (VIAs) are formed) and one or more dielectric layers.

[0042] In this disclosure, for the sake of ease of explanation, the term "tier" is used to refer to elements of substantially the same height along the vertical direction. For example, a word line and the gate dielectric layer beneath it may be referred to as a "tier," a word line and the insulating layer beneath it may be referred to collectively as a "tier," and word lines of substantially the same height may be referred to as a "word line tier" or similar, and so on.

[0043] As used herein, the phrase “nominal” refers to a desired or target value of a characteristic or parameter for a component or process stage, set at the design stage of the product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or manufacturing tolerances. As used herein, the word “approximately” indicates a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of the subject. Based on a particular technology node, the word “approximately” may indicate a value of a given quantity that varies, for example, within 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0044] In this disclosure, the terms “horizontal / horizontally / lateral / outer / lateral” mean nominally parallel to the outer surface of the substrate, and the phrase “perpendicular / perpendicular” means nominally perpendicular to the outer surface of the substrate. Similarly, the terms “parallel” or “perpendicular” also mean nominally parallel or perpendicular.

[0045] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND strings) on a transversely oriented substrate such that the memory strings extend perpendicularly with respect to the substrate.

[0046] Figure 1 illustrates a schematic top-down view of an exemplary three-dimensional (3D) memory device 100 according to several embodiments of the present disclosure. The 3D memory device 100, such as 3D NAND flash memory, can be a memory chip (package), a memory die, or any part of a memory die, and can include one or more memory planes 101, each of which can include a memory block 103. The same concurrent operations can be performed in each memory plane 101. A memory block 103, which can have a size in megabytes (MB), is the smallest size for performing an erase operation. As shown in Figure 1, the exemplary 3D memory device 100 comprises four memory planes 101, and each memory plane 101 comprises six memory blocks 103. Each memory block 103 can include memory cells, each memory cell can be addressed through interconnections such as bit lines and word lines. The bit lines and word lines can be arranged vertically (for example, in rows and columns, respectively) to form an array of metal wires. In Figure 1, the directions in which the bit lines and word lines extend are labeled "BL" and "WL," and are also referred to as the WL direction and the BL direction. In this disclosure, memory block 103 is also referred to as a "memory array" or "array." A memory array is a core region within a memory device that performs storage functions.

[0047] The 3D memory device 100 also includes a peripheral region 105, which is the region surrounding the memory plane 101. The peripheral region 105 includes many digital, analog, and / or mixed-signal circuits to support the functions of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuits use active and / or passive semiconductor devices, such as transistors, diodes, capacitors, and resistors, as will be obvious to those skilled in the art.

[0048] Please note that the arrangement configuration of the memory planes 101 within the 3D memory device 100 and the arrangement configuration of the memory blocks 103 within each memory plane 101, as illustrated in Figure 1, are for illustrative purposes only and do not limit the scope of this disclosure.

[0049] Referring to Figure 2, an enlarged top-down view of a region 108 of the memory block 103 in Figure 1 is illustrated according to several embodiments of the present disclosure. Region 108 of the 3D memory device 100 may include a stepped region 210 and a channel structure region 211. The channel structure region 211 may include an array of memory strings 212, each containing a stacked memory cell. The stepped region 210 may include a stepped structure and an array of contact structures 214 formed on the stepped structure. In some embodiments, slit structures (also referred to as gate line slits) 216 extending in the WL direction across the channel structure region 211 and the stepped region 210 can divide the memory block into a plurality of memory fingers 218. At least some of the slit structures 216 can function as common source contacts (e.g., to an array common source) for the array of memory strings 212 within the channel structure region 211. A top select gate cut 220, for example, is located in the middle of each memory finger 218 to divide the top select gate (TSG) of the memory finger 218 into two parts, thereby dividing the memory finger into two memory slices 224, where memory cells in the memory slices 224 sharing the same word line form a programmable (read / write) memory page. Erase operations of 3D NAND memory can be performed at the memory block level, while read and write operations can be performed at the memory page level. Memory pages can have a size in kilobytes (KB). In some embodiments, region 108 also includes a dummy memory string 222 for process variation control during manufacturing and / or for additional mechanical support.

[0050] Figure 3 illustrates a partial perspective view of an exemplary three-dimensional (3D) memory array structure 300 according to several embodiments of the present disclosure. The memory array structure 300 comprises a substrate 330, an insulating film 331 covering the substrate 330, tiers of bottom select gates (BSGs) 332 covering the insulating film 331, and tiers of control gates 333, also referred to as "word lines (WLs)," which are stacked on the BSGs 332 to form a film stack 335 of alternating conductors and dielectric layers. Dielectric layers adjacent to the control gate tiers are not shown in Figure 3 for clarity.

[0051] The control gates of each tier are separated by slit structures 216-1 and 216-2 that penetrate the film stack 335. The memory array structure 300 also includes tiers of top select gates (TSGs) 334 that cover the stack of control gates 333. The stacks of TSGs 334, control gates 333, and BSGs 332 are also referred to as "gate electrodes". The memory array structure 300 further comprises memory strings 212 and doped source line regions 344 in portions of the substrate 330 between adjacent BSGs 332. Each memory string 212 includes channel holes 336 that penetrate the insulating film 331 and the film stack 335 of alternating conductors and dielectric layers. The memory string 212 also includes a memory film 337 disposed on the sidewalls of the channel holes 336, a channel layer 338 disposed on the sidewalls of the memory film 337, and a core filler 339 surrounded by the channel layer 338. Memory cells 340 (e.g., 340-1, 340-2, 340-3) may be formed at the intersections of control gates 333 (e.g., 333-1, 333-2, 333-3) and memory strings 212. A portion of the channel layer 338 responds to each control gate and is also referred to as the memory cell channel 338. The memory array structure 300 further comprises bit lines (BLs) 341 connected to the memory strings 212, the BLs 341 being positioned above the TSG 334. The memory array structure 300 also comprises metal interconnect lines 343 connected together with the gate electrodes through a contact structure 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connections to each tier of the gate electrodes.

[0052] In Figure 3, for illustrative purposes, three tiers of control gates 333-1, 333-2, and 333-3 are illustrated together with one tier of TSG 334 and one tier of BSG 332. In this example, each memory string 212 may contain three memory cells 340-1, 340-2, and 340-3, corresponding to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and memory cells can be greater than three to increase storage capacity. The memory array structure 300 may also include other structures, such as TSG cuts, common source contacts (i.e., array common sources), and dummy memory strings. These structures are not shown in Figure 3 for simplicity.

[0053] To further increase the storage density of 3D NAND memory, the number of vertically stacked word lines 333 has been continuously increased. Therefore, the contact structures 214 for the word lines 333 have a wide range of depths, with the shortest being for the topmost word line and the longest for the bottommost word line. To form contact structures 214 for all word lines 333 simultaneously, an etch stop layer is placed on a stepped structure, thereby avoiding over-etching on the upper word lines. However, the etch stop layer can be lost in various processes before the contact structures are manufactured. For example, as shown in Figure 21A, the etch stop layer for forming the contact structures 214 (also referred to as the second barrier layer 1166 in the detailed description below) and the sacrificial layer used to form the word lines 333 (also referred to as the second dielectric layer 454 in the detailed description below) are usually made from the same material, such as silicon nitride. During the substitution process to form the word lines 333, the etch stop layer 1166 can be removed simultaneously with the sacrificial layer 454 through the gate line slit (GLS) opening 1582. Lateral tunnels 1684 and 2184 can be formed as shown in Figure 21B. An additional conductive layer 2186 can be formed simultaneously as a conductive layer 1786 that can function as a word line 333. As such, parasitic leakage paths may arise due to the additional conductive layer 2186. In addition, the thick etch stop layer 1166 creates seams in the additional conductive layer 2186, which can weaken the mechanical strength of the 3D memory structure. Therefore, there is a need to provide an improved method for forming 3D NAND memory.

[0054] Figure 4 illustrates a method 400 for forming a three-dimensional (3D) memory device according to several embodiments of the present disclosure. It should be understood that the process steps shown in method 400 are not exhaustive, and other steps may be performed before, after, or between any of the illustrated steps. In some embodiments, some steps of method 400 may include other steps that are omitted or not described herein for simplicity. In some embodiments, the steps of method 400 may be performed in a different order and / or vary.

[0055] Figures 5-12, 13A-13D, 14A-14C, 15A-15B, 16A-16C, 17A-17C, 18A-18B, 19A-19B, and 20A-20D illustrate exemplary structures of a 3D memory device in a specific process step according to Method 400.

[0056] Referring to Figure 4, it can be seen that in process step S405, an alternating dielectric stack may be arranged on a substrate plate, and the alternating dielectric stack includes a first dielectric layer and a second dielectric layer alternately stacked on the substrate. A cross-sectional view of an exemplary 3D memory structure 500 after process step S405 is shown in Figure 5.

[0057] As shown in Figure 5, the 3D memory structure 500 includes an alternating dielectric stack 450 disposed on a substrate 330.

[0058] The substrate 330 can provide a platform for forming subsequent structures. In some embodiments, the substrate 330 may be any suitable semiconductor substrate having any suitable semiconductor material such as single crystal, polycrystalline, or single-crystal semiconductor. For example, the substrate 330 may include silicon, silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, the substrate 330 may include a layer of semiconductor material formed on a handle wafer, for example, glass, plastic, or another semiconductor substrate.

[0059] The front surface 330f of the substrate 330 is also referred to herein as the “main surface” or “top surface” of the substrate. Layers of material may be disposed on the front surface 330f of the substrate 330. The “top” or “upper” layer is the layer furthest or further away from the front surface 330f of the substrate. The “bottom” or “lower” layer is the layer closest or closer to the front surface 330f of the substrate.

[0060] The alternating dielectric stack 450 includes pairs of dielectric layers stacked alternately along a vertical direction (i.e., the z-direction or a first direction) perpendicular to the front surface 330f of the substrate 330, and each pair of dielectric layers includes a first dielectric layer 452 (also referred to as the “dielectric layer”) and a second dielectric layer 454 (also referred to as the “sacrificial layer”) that is different from the first dielectric layer 452. The alternating dielectric stack 450 extends in a transverse direction (e.g., the WL direction or a second direction) parallel to the front surface 330f of the substrate 330.

[0061] In the alternating dielectric stack 450, the first dielectric layer 452 and the second dielectric layer 454 are arranged alternately in a vertical direction perpendicular to the substrate 330. In other words, each second dielectric layer 454 is sandwiched between two first dielectric layers 452, and each first dielectric layer 452 may be sandwiched between two second dielectric layers 454 (excluding the bottom and top layers).

[0062] The formation of the alternating dielectric stack 450 may include arranging the first dielectric layers 452 such that each has the same thickness or different thicknesses. An exemplary thickness of the first dielectric layers 452 may be in the range of 10 nm to 500 nm, preferably about 25 nm. Similarly, the second dielectric layers 454 may each have the same thickness or different thicknesses. An exemplary thickness of the second dielectric layers 454 may be in the range of 10 nm to 500 nm, preferably about 35 nm. The number of dielectric layer pairs in Figure 5 is for illustrative purposes only, and it should be understood that any suitable number of layers may be included in the alternating dielectric stack 450.

[0063] In some embodiments, the first dielectric layer 452 includes any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide incorporating F-, C-, N-, and / or H-. The first dielectric layer 452 may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide film. In some embodiments, the first dielectric layer 452 may be any combination of the above materials.

[0064] The formation of the first dielectric layer 452 on the substrate 330 may include any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted CVD (PECVD), rapid thermochemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density plasma CVD (HDP-CVD), sputtering, vapor deposition, thermal oxidation, nitride formation, other suitable deposition methods, and / or combinations thereof.

[0065] In some embodiments, the second dielectric layer 454, unlike the first dielectric layer 452, includes any suitable material that can be selectively removed with respect to the first dielectric layer 452. For example, the second dielectric layer 454 may include silicon oxide, silicon oxynitride, silicon nitride, TEOS, polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, and any combination thereof. In some embodiments, the second dielectric layer 454 may also include amorphous semiconductor materials such as amorphous silicon or amorphous germanium. The second dielectric layer 454 may be disposed using techniques similar to those used for the first dielectric layer 452, such as CVD, PVD, ALD, sputtering, vapor deposition, thermal oxidation or nitriding, or any combination thereof.

[0066] In some embodiments, the first dielectric layer 452 may be silicon oxide, and the second dielectric layer 454 may be silicon nitride.

[0067] In some embodiments, the alternating dielectric stack 450 may include layers added to the first dielectric layer 452 and the second dielectric layer 454, which may be made of different materials and / or of different thicknesses.

[0068] Referring to Figure 4, it can be seen that a first stepped structure can be formed within the alternating dielectric stack in process step S410. A cross-sectional view of an exemplary 3D memory structure 600 formed in process step S410 is shown in Figure 6.

[0069] As shown in Figure 6, the 3D memory structure 600 includes a first stepped structure 656 in which a first stepped step 658 is formed within the alternating dielectric stack 450. The first stepped step 658, or “stepped layer,” refers to a stack of layers having the same lateral dimension on a surface parallel to the substrate surface 330f. Each of the first stepped steps terminates with a lateral dimension “a” as shown in Figure 6, shorter than the first stepped step below it. In some embodiments, the first stepped structure 656 has first stepped steps 658 facing the WL direction, and each of the first stepped steps 658 includes a lateral dimension “a” along the WL direction. In this example, the first stepped structure 656 extends in the WL direction (or a second direction) parallel to the substrate.

[0070] In some embodiments, each of the first stepped steps 658 includes one pair of a first dielectric layer 452 and a second dielectric layer 454. In some embodiments, each of the first stepped steps 658 may include two or more pairs of the first dielectric layer 452 and the second dielectric layer 454. As shown in Figure 6, each of the first stepped steps 658 includes one pair of a first dielectric layer 452 and a second dielectric layer 454, with the first dielectric layer 452 resting on the second dielectric layer 454. Each of the first stepped steps 658 exposes a portion of the first dielectric layer 452.

[0071] The first stepped structure 656 can be formed by applying an iterative etch-trim process on the alternating dielectric stack 450. The etch-trim process includes an etching process and a trimming process. In the etching process, a portion of the first stepped step 658 with an exposed surface can be removed. The remaining portion of the first stepped step 658 is either covered by the upper level of the stepped step or by a patterning mask and is not etched. The etching depth is the thickness of the first stepped step 658. In some embodiments, the thickness of the first stepped step 658 is the thickness of one pair of first dielectric layers 452 and second dielectric layers 454. The etching process on the first dielectric layer 452 can have high selectivity on the second dielectric layer 454, and / or vice versa. Thus, the underlying dielectric layer pair can act as an etch-stop layer. By switching the etching process for each layer, the first stepped step 658 can be etched in a single etching cycle. As a result, one of the first stepped steps 658 may be formed between each etching trim cycle.

[0072] In some embodiments, the first stepped step 658 may be etched using anisotropic etching, such as reactive ion etching (RIE) or other dry etching processes. In some embodiments, the first dielectric layer 452 is silicon oxide. In this example, etching of silicon oxide may include RIE using a fluorinated gas, such as carbon-fluorine (CF4), hexafluoroethane (C2F6), CHF3, or C3F6 and / or any other suitable gas. In some embodiments, the silicon oxide layer may be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etching approach may be used. In some embodiments, the second dielectric layer 454 is silicon nitride. In this example, etching of silicon nitride may include RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and / or combinations thereof. Methods and etchants for removing monolayer stacks should not be limited by embodiments of this disclosure.

[0073] The trimming process involves applying an appropriate etching process (e.g., isotropic dry etching or wet etching) to the patterning mask so that the patterning mask can be pulled back laterally. The lateral pullback dimension determines the lateral dimension "a" of each step of the first stepped structure 656. After trimming the patterning mask, a portion of the uppermost first stepped step 658 is exposed, while the rest of the uppermost first stepped step 658 remains covered by the patterning mask. The next cycle of the etch trimming process restarts from the etching process. In some embodiments, the patterning mask trimming process may include dry etching such as RIE using O2, Ar, N2, etc.

[0074] Referring to Figure 4, it can be seen that in process step S415, the second stepped structure can be formed by removing the exposed portion of the first dielectric layer 452. Cross-sectional, top-down, and perspective views of an exemplary 3D memory structure 700 formed by process step S415 are shown in Figures 7 to 9, respectively.

[0075] As shown in Figure 7, the 3D memory structure 700 includes a second stepped structure 760 (also referred to as a stepped structure) in which a second stepped step 762 (also referred to as a stepped step) is formed within the alternating dielectric stack 450. The second stepped structure 760 can be formed by removing the exposed portion of the first dielectric layer 452 within the 3D memory structure 600 (Figure 6). Similar to the first stepped structure 656, the second stepped step 762 also faces the WL direction, and the second stepped step 762 has a lateral dimension "a" in the WL direction. In this example, the second stepped structure 760 extends in the WL direction (or second direction) parallel to the substrate.

[0076] The first dielectric layer 452 can be etched using anisotropic etching, such as reactive ion etching (RIE) or other dry etching processes. In some embodiments, the first dielectric layer 452 is silicon oxide. In this example, etching of silicon oxide may include RIE using a fluorinated gas, such as carbon-fluorine (CF4), hexafluoroethane (C2F6), CHF3, or C3F6 and / or any other suitable gas. In some embodiments, the silicon oxide layer may be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etching approach may be used. The etching process for the first dielectric layer 452 may have high selectivity on the second dielectric layer 454. Thus, the second dielectric layer 454 can function as an etch stop layer.

[0077] In some embodiments, each of the second stepped steps 762 also includes one pair of the first dielectric layer 452 and the second dielectric layer 454, where the second dielectric layer 454 lies on top of the first dielectric layer 452. Each of the second stepped steps 762 exposes a portion of the second dielectric layer 454. In some embodiments, each of the second stepped steps 762 may also include two or more pairs of the first dielectric layer 452 and the second dielectric layer 454.

[0078] Figure 7 illustrates a cross-sectional view along line CC' in Figure 8. As shown in Figures 8 and 9, the stepped region 210 extends along the WL direction and may include one or more second stepped structures 760 extending along the WL direction. Each of the second stepped structures 760 includes a second stepped step 762 that steps up or down along the WL direction with a lateral dimension "a". As an example, Figure 8 depicts two second stepped structures 760, and Figure 9 depicts more dielectric layer pairs of the first dielectric layer 452 and the second dielectric layer 454. Note that the number of stepped structures and dielectric layer pairs in the 3D memory structure 700 is not limited to the examples herein.

[0079] As shown in Figures 8 and 9, the 3D memory structure 700 also includes a plurality of partitioned regions 863 that separate the second stepped structure 760. A portion of the alternating dielectric stack 450 within the partitioned regions 863 is not etched during the iterative etch-trim process to form the first stepped structure 656, which forms the partition wall 865 (in Figure 6). The partitioned regions 863 are positioned adjacent to the second stepped structure 760. As such, the partition wall 865 formed within the alternating dielectric stack 450 is positioned adjacent to the second stepped structure 760 and extends in the WL direction, similar to the second stepped structure 760.

[0080] Referring to Figure 4, it can be seen that in process step S420, the first barrier layer may be disposed on the second stepped structure and dividing wall of the alternating dielectric stack. A cross-sectional view of an exemplary 3D memory structure 1000 after process step S420 is shown in Figure 10.

[0081] As shown in Figure 10, the 3D memory structure 1000 includes a first barrier layer 1064 disposed on the 3D memory structure 700 (in Figures 7-9). The first barrier layer 1064 covers the second stepped structure 760 and dividing wall 865 of the alternating dielectric stack 450 on both the outer surface and the vertical sidewalls (as shown in Figures 8-9). The first barrier layer 1064 on the outer surface and the vertical sidewalls may have the same thickness or different thicknesses. In some embodiments, the first barrier layer 1064 is equiangled, and the thickness of the first barrier layer 1064 on the outer surface and the vertical sidewalls is approximately the same. The first barrier layer 1064 may have a thickness in the range of 10 nm to 100 nm. The portion of the first barrier layer 1064 formed on the outer surface of the stepped structure may function as an etch stop layer for etching processes in the z-direction (first direction) perpendicular to the substrate 330. The portion of the first barrier layer 1064 formed on the side wall of the stepped structure 760 can function, for example, as an etch stop layer for an etching process in the WL direction (or a second direction) parallel to the front surface 330f of the substrate 330.

[0082] In some embodiments, the first barrier layer 1064 may be any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, high-k dielectric materials (Al2O3, HfO2, Ta2O3, ZrO2, La2O3, etc.), or any combination thereof. The first barrier layer 1064 may be deposited by any suitable thin-film deposition technique such as CVD (e.g., PECVD, LPCVD, RTCVD, HDP-CVD, MOCVD, etc.), ALD, PVD, sputtering, or vapor deposition. In some embodiments, the first barrier layer 1064 may be silicon oxide.

[0083] Referring to Figure 4, it can be seen that in process step S425, a second barrier layer, different from the first barrier layer, can be disposed on the first barrier layer on the second stepped structure and dividing wall of the alternating dielectric stack. A cross-sectional view of an exemplary 3D memory structure 1100 after process step S425 is shown in Figure 11.

[0084] As shown in Figure 11, the 3D memory structure 1100 includes a second barrier layer 1166 disposed on top of the 3D memory structure 1000, on top of the first barrier layer 1064. The second barrier layer 1166 covers the first barrier layer 1064 on the outer surface. In some embodiments, the second barrier layer 1166 also covers the first barrier layer 1064 on the vertical sidewalls. The second barrier layer 1166 on the outer surface and on the vertical sidewalls may have the same thickness or different thicknesses. In some embodiments, the second barrier layer 1166 is non-equal-angled, and the thickness of the second barrier layer 1166 on the vertical sidewalls is thinner than that on the outer surface. As described below, the second barrier layer 1166 may be used as an etch-stop layer to form a contact structure on stepped steps. Therefore, a second barrier layer 1166 with a greater thickness on the outer surface of the stepped steps is preferred. In some embodiments, the second barrier layer 1166 and the first barrier layer 1064 can cover the outer surface and vertical sidewalls of the second stepped structure 760 and the dividing walls 865 of the alternating dielectric stack 450 (as shown in Figures 8-9).

[0085] In some embodiments, the second barrier layer 1166 may include any suitable dielectric material different from the first barrier layer 1064. The second barrier layer 1166 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS, high-k dielectric materials (such as Al2O3, HfO2, Ta2O3, ZrO2, La2O3), or any combination thereof. The second barrier layer 1166 may be deposited by any suitable thin-film deposition technique such as CVD (e.g., PECVD, LPCVD, RTCVD, HDP-CVD, MOCVD), ALD, PVD, sputtering, or vapor deposition. In some embodiments, the second barrier layer 1166 may be silicon nitride, the first barrier layer 1064 may be silicon oxide, the first dielectric layer 452 may be silicon oxide, and the second dielectric layer 454 may be silicon nitride. In this example, the first barrier layer 1064 and the first dielectric layer 452 can be used as etch-stop layers when removing the second dielectric layer 454. When the first barrier layer 1064 is positioned between the second dielectric layer 454 and the second barrier layer 1166 on the outer surface and vertical sidewall, the first barrier layer 1064 can protect the second barrier layer 1166 from etching when removing the second dielectric layer 454.

[0086] Referring to Figure 4, it can be seen that in process step S430, the block mask may be positioned to cover the first central region of the second stepped structure. A top-down view of an exemplary 3D memory structure 1200 after process step S430 is shown in Figure 12.

[0087] As shown in Figure 12, the 3D memory structure 1200 includes a block mask 1270 disposed on the 3D memory structure 1100 (in Figure 11). The block mask 1270 is configured to expose a portion of the alternating dielectric stack 450 adjacent to the second stepped structure 760. For example, the block mask 1270 exposes a partition wall 865 of a partition region 863 located adjacent to the second stepped structure 760. In some embodiments, the block mask 1270 also exposes a portion of the second stepped structure 760 adjacent to the partition region 863 and the partition wall 865. In other words, the block mask 1270 covers a first central region 1272 of the second stepped structure 760. The first region 1272 extends in the WL direction. The second stepped structure 760 may include a first region 1272 covered by the block mask 1270 and a second region 1274 exposed by the block mask 1270. In some embodiments, the second region 1274 does not include the second barrier layer 1166. The second region 1274 also extends in the WL direction and is positioned between the dividing wall 865 and the first region 1272. The exposed portion of the second stepped structure 760 in the second region 1274 and the exposed dividing wall 865 are collectively referred to as the exposed structure 1276. The block mask may be used in a subsequent process to remove a portion of the second barrier layer 1166 disposed on the exposed structure 1276.

[0088] The block mask 1270 may include any suitable photoresist. In some embodiments, the block mask 1270 may also include hard masks, such as silicon oxide, silicon nitride, TEOS, amorphous or polycrystalline silicon, spin-on glass, or any combination thereof. In some embodiments, the block mask 1270 may also include carbon-based polymer materials, silicon-containing anti-reflective coatings (SiARC), etc. The block mask 1270 may be formed through lithography, and the pattern may be transferred from the reticle to the block mask 1270. In some embodiments, forming the block mask 1270 may also include dry etching (e.g., reactive ion etching), wet etching, or a combination thereof.

[0089] Please note that the second barrier layer 1166 and the first barrier layer 1064 are omitted in the top-down view of Figure 12 for clarity.

[0090] Referring to Figure 4, it can be seen that in process step S435, the second barrier layer can be removed from the structure exposed by the block mask. A top-down view and various cross-sectional views of an exemplary 3D memory structure 1300 after process step S435 are shown in Figures 13A to 13D.

[0091] Figure 13B illustrates a cross-sectional view along line BB' in Figure 13A, within the second region 1274 of the second stepped structure 760. Figure 13C illustrates a cross-sectional view along line CC' in Figure 13A, within the first region 1272 of the second stepped structure 760. As previously described, the block mask 1270 covers the first region 1272 of the second stepped structure 760. The block mask exposes the exposed structure 1276, including the second region 1274 of the second stepped structure 760 and the dividing wall 865 of the dividing region 863. Thus, the second barrier layer 1166 can be removed from the exposed structure 1276, for example, within the second region 1274 of the second stepped structure 760. Similarly, the second barrier layer 1166 can also be removed from the dividing wall 865 of the dividing region 863. That is, a first portion of the second barrier layer 1166 (or dielectric material) can be removed from the dividing wall 865. Then, a second portion of the second barrier layer 1166 can be removed from the second region 1274 of the second stepped structure 760. In this manner, the second barrier layer 1166 can be formed within the first region of the stepped structure.

[0092] In some embodiments, the second barrier layer 1166 can be selectively removed with respect to the first barrier layer 1064. For example, the second barrier layer 1166 can be etched at a rate considerably faster than the etching rate of the first barrier layer 1064. The second barrier layer 1166 can be removed by using any preferred etching process, such as dry etching, wet etching, or a combination thereof. In some embodiments, the second barrier layer 1166 can be etched by RIE.

[0093] Figure 13D illustrates a cross-sectional view along line AA' in Figure 13A, traversing the exposed structure 1276 and the first region 1272 of the second stepped structure 760. Due to the topology between the dividing wall 865 and the second stepped step 762, in some embodiments, the second barrier layer 1166 and the first barrier layer 1064 can cover the sidewall of the dividing wall 865. See also Figure 9. In some embodiments, in process step S435, the second barrier layer 1166 on the sidewall of the dividing wall 865 can also be removed and stopped on the first barrier layer 1064 beneath it. In this example, the removal of the second barrier layer 1166 from the sidewall of the dividing wall 865 may be performed by an isotropic etching process (e.g., isotropic RIE, wet etching, etc.), and the second barrier layer 1166 may be etched laterally in addition to vertically.

[0094] As the storage capacity of the 3D NAND memory increases, the number of the first dielectric layers 452 and the second dielectric layers 454 also increases. As a result, the topology between the partition wall 865 and the second stepped structure 760 also increases. By using the block mask 1270, the second barrier layer 1166 is etched isotropically (i.e., in the vertical and transverse directions), which can significantly reduce etching time and greatly decrease the risk of over-etching on the outer surface.

[0095] After removing the second barrier layer 1166 from the exposed structure 1276, the block mask 1270 (in Figure 12) can be peeled off. As shown in Figures 13A to 13D, after completing process step S435, the second barrier layer 1166 covers the first region 1272 of the second stepped structure 760, and the second barrier layer 1166 can be removed from the other regions.

[0096] Referring to Figure 4, it can be seen that in process step S440, the insulating layer may be disposed on the second stepped structure and dividing wall of the alternating dielectric stack. Exemplary cross-sectional views of the 3D memory structure 1400 along lines AA', BB', and CC' (see Figure 13A) by process step S440 are shown in Figures 14A to 14C, respectively.

[0097] As shown in Figures 14A to 14C, the 3D memory structure 1400 includes a second barrier layer 1166 on the second stepped structure 760 and dividing wall 865 of the alternating dielectric stack 450, and an insulating layer 1480 disposed on the first barrier layer 1064. The insulating layer 1480 covers at least the top surface (the surface furthest from the substrate 330) and side walls of the second barrier layer 1166. The insulating layer 1480 can protect the second barrier layer 1166 from etching in subsequent processes when the second dielectric layer 454 is removed.

[0098] The insulating layer 1480 may include any suitable insulating material, such as low-k dielectric materials like silicon oxide, silicon oxynitride, silicon nitride, TEOS, spin-on glass, carbon-doped oxide (CDO or SiOC or SiOC:H), or fluorine-doped oxide (SiOF). The insulating layer 1480 may be disposed by CVD, PVD, ALD, sputtering, vapor deposition, etc. In some embodiments, the insulating layer 1480 may have a planar top surface on the second stepped structure 760 and dividing wall 865 of the alternating dielectric stack 450. The insulating layer 1480 may be planarized using CMP.

[0099] Referring to Figure 4, it can be seen that in process step S445, a gate line slit (GLS) opening may be formed within the split wall, and the GLS opening penetrates the alternating dielectric stack vertically. A top-down view and a cross-sectional view of an exemplary 3D memory structure 1500 by process step S445 are shown in Figures 15A and 15B.

[0100] As shown in Figure 15A, the 3D memory structure 1500 includes a GLS opening 1582 that extends laterally along the WL direction, parallel to the second stepped structure 760. In some embodiments, the GLS opening 1582 may be formed within a dividing wall 865 of the alternating dielectric stack 450.

[0101] Figure 15B illustrates a cross-sectional view along line AA' in Figure 15A. The GLS opening 1582 penetrates the insulating layer 1480 and the dividing wall 865 of the alternating dielectric stack 450 in the z-direction perpendicular to the substrate 330. In some embodiments, the GLS opening 1582 penetrates further into the substrate 330. The GLS opening 1582 can be formed by a lithography process and an etching process. The etching process may include any preferred dry etching, wet etching, or a combination thereof.

[0102] As previously described, the second barrier layer 1166 may be removed from the exposed structure 1276 in process step S435. Thus, the GLS opening 1582 is far from (or away from) the second barrier layer 1166 in the BL direction (parallel to the substrate 330 and also referred to as the WL direction or a third direction perpendicular to the second direction), and the second barrier layer 1166 is located in the first region 1272 on the second stepped step 762. As a result, the second barrier layer 1166 may be covered from the top and sides by the insulating layer 1480 and not exposed by the GLS opening 1582.

[0103] Referring to Figure 4, it can be seen that in process step S450, the second dielectric layer (including the dividing wall and the second stepped structure) in the alternating dielectric stack can be removed through the GLS opening. Exemplary cross-sectional views of the 3D memory structure 1600 along lines AA', BB', and CC' (see Figure 15A) after process step S450 are shown in Figures 16A to 16C, respectively.

[0104] As shown in Figures 16A to 16C, the 3D memory structure 1600 includes a lateral tunnel, and the second dielectric layer 454 of the alternating dielectric stack 450 can be selectively removed with respect to the first dielectric layer 452 and the first barrier layer 1064. The lateral tunnel 1684 can extend laterally between adjacent first dielectric layers 452. Note that the terms “lateral / lateral / outer” as used herein refer to a plane parallel to the top surface 330f of the substrate 330.

[0105] As previously described, the second dielectric layer 454 in the alternating dielectric stack 450 (see Figure 15B), also referred to as the sacrificial layer, can be selectively removed from between the first dielectric layers 452. In other words, the etching process of the second dielectric layer 454 can be stopped on the first dielectric layer 452. The second dielectric layer 454 can be removed by isotropic dry etching and / or wet etching. The plasma and / or chemicals used in dry / wet etching can move vertically and laterally from the GLS opening 1582. For example, the plasma and / or chemicals can move along the WL direction and / or BL direction from the GLS opening 1582 toward the second stepped structure 760 (see also Figure 15A). In some embodiments, the second dielectric layer 454 may be silicon nitride and the first dielectric layer 452 may be silicon oxide. In this example, the second dielectric layer 454 can be removed by RIE using one or more etchants such as CF4, CHF3, C4F8, C4F6, and CH2F2. In some embodiments, the second dielectric layer 454 can be removed using wet etching such as phosphoric acid.

[0106] When the etching process used to remove the second dielectric layer 454 (e.g., silicon nitride) is selective for the first barrier layer 1064 (e.g., silicon oxide), the first barrier layer 1064 disposed on the second stepped structure 760 can also function as an etch stop layer in addition to the first dielectric layer 452 (e.g., silicon oxide). For example, when both the second barrier layer 1166 and the second dielectric layer 454 can be removed in process step S450 (i.e., both containing silicon nitride), the first barrier layer 1064 covering the top surface (i.e., outer surface) and vertical surface (i.e., sidewall) of the second stepped step 762 can protect the second barrier layer 1166 from being etched from the lateral tunnel 1684 beneath it (see Figure 16C). The portion of the first barrier layer 1064 formed on the outer surface of the stepped structure can function as an etch stop layer for etching processes in the z-direction perpendicular to the substrate 330. The portion of the first barrier layer 1064 formed on the vertical sidewall of the stepped structure 760 can function as an etch stop layer for etching processes in the WL and BL directions parallel to the front surface 330f of the substrate 330.

[0107] As previously described, by using the block mask 1270 in process steps S430 and S435, the second barrier layer 1166 can be removed from the exposed structure 1276, thereby moving away from or away from the GLS opening 1582. The second barrier layer 1166 can be covered and protected by the insulating layer 1480 near the split wall 865. Thus, etching chemical reactions traveling through the GLS opening 1582 do not attack the second barrier layer 1166 (see Figure 16A) and do not form extra lateral tunnels on top of the first barrier layer 1064.

[0108] Referring to Figure 4, it can be seen that in process step S455, the first conductive material is disposed inside the lateral tunnel passing through the GLS opening, and a conductive layer can be formed between the first dielectric layers. Cross-sectional views of exemplary 3D memory structures 1700 along lines AA', BB', and CC' (see Figure 15A) following process step S455 are shown in Figures 17A to 17C, respectively.

[0109] As shown in Figures 17A to 17C, the 3D memory structure 1700 includes a conductive layer 1786 disposed inside the lateral tunnel 1684 (in Figures 16A to 16C) through the GLS opening 1582. The conductive layer 1786 may be disposed between adjacent first dielectric layers 452, and the conductive layer 1786 and the first dielectric layers 452 can form a film stack 335 in which conductive and dielectric layers are arranged alternately (as in Figure 3).

[0110] In some embodiments, the conductive layer 1786 may be formed by filling a lateral tunnel with a first conductive material. The first conductive material of the conductive layer 1786 may include metals or metallic alloys such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. In some embodiments, the first conductive material of the conductive layer 1786 may also include polycrystalline semiconductors such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, and any other suitable materials, and / or combinations thereof. In some embodiments, the polycrystalline material may be incorporated with any suitable type of dopant, such as boron, phosphorus, arsenic, or any combination thereof. In some embodiments, the first conductive material may also be an amorphous semiconductor such as amorphous silicon. In some embodiments, the first conductive material may be deposited using a preferred deposition method such as chemical vapor deposition (CVD) (e.g., LPCVD, PECVD, MOCVD, RTCVD, etc.), physical vapor deposition (PVD), sputtering, vapor deposition, atomic layer deposition (ALD), or any combination thereof. In some embodiments, the conductive layer 1786 (or the first conductive material) comprises tungsten (W) deposited by CVD.

[0111] In some embodiments, the gate dielectric layer 1785 may be disposed inside the lateral tunnel 1684 (in Figures 16A to 16C) before the conductive layer 1786 is disposed. In some embodiments, the gate dielectric layer 1785 surrounds the conductive layer 1786. For example, in the z direction, the gate dielectric layer 1785 is disposed between the first dielectric layer 452 and the conductive layer 1786. In the WL or BL direction, the gate dielectric layer 1785 is disposed between the conductive layer 1786 and the first barrier layer 1064. The gate dielectric layer 1785 may include any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, and / or any suitable combination thereof. The gate dielectric layer 1785 may also include high-k dielectric materials, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The gate dielectric layer 1785 may be deposited by one or more preferred deposition processes such as CVD, PVD, and / or ALD.

[0112] In some embodiments, etching and cleaning processes may be used to remove excess first conductive material on the sidewalls of the GLS opening 1582. As such, each conductive layer 1786 of the film stack 335 may be electrically insulated from one another. In some embodiments, excess first conductive material on the insulating layer 1480 may also be removed, for example, by CMP.

[0113] After completing process step S455, the second dielectric layer 454 may be replaced with a conductive layer 1786, and the alternating conductive stack 450 becomes a film stack 335 of layers in which conductive layers and dielectric layers are arranged alternately. Thus, the second stepped structure 760 becomes the third stepped structure 1760, and the second stepped step 762 becomes the third stepped step 1762.

[0114] However, if the block mask 1270 is not used and the second barrier layer 1166 is not removed near the GLS opening 1582 (see FIGS. 21A-21C), and if the second barrier layer 1166 and the second dielectric layer 454 are made of the same material, such as silicon nitride, the second barrier layer 1166 can be removed together with the second dielectric layer 454 in process step S450. An additional tunnel 2184 can be formed under the insulating layer 1480. In process step S455, an additional conductor layer 2186 can also be formed under the insulating layer 1480. The additional conductor layer 2186 can cause a circuit shot and / or increase leakage. Further, in order to completely fill the additional tunnel 2184, the thickness "t" of the additional conductor layer 2186 needs to be at least the thickness of the second barrier layer 1166. However, if the width of the GLS opening 1582 is not wide enough, for example, having a width w < t, the GLS opening 1582 can be filled and pitch-off can occur before the additional tunnel 2184 can be filled. The resulting seam of the additional conductor layer 2186 can cause structural problems (such as a decrease in mechanical strength, attraction of defects and chemicals, etc.), thereby reducing the product yield. Therefore, removing the second barrier layer 1166 by using the block mask 1270 can improve the manufacturing process for 3D NAND flash memory.

[0115] Referring to FIG. 4, it can be seen that in process step S460, a GLS filler can be disposed inside the GLS opening to form the GLS. Exemplary top-down views and cross-sectional views of the 3D memory structure 1800 according to process step S460 are shown in FIGS. 18A-18B.

[0116] As shown in Figures 18A and 18B (along line AA'), the 3D memory structure 1800 includes a gate line slit (GLS) 216 (similar to the slit structure 216 in Figures 2 and 3) between adjacent third stepped structures 1760. The GLS 216 may be formed within the partition wall 865 of the partition region 863. The GLS 216 extends laterally along the WL direction.

[0117] The GLS216 penetrates the insulating layer 1480, the first barrier layer 1064, and the film stack 335 in which conductive and dielectric layers are alternately arranged in the z direction. In some embodiments, the GLS216 can further penetrate into the substrate 330.

[0118] GLS216 includes a GLS filler 1888 disposed within a GLS opening 1582 (in Figure 17A). The GLS filler 1888 may include any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, boron or phosphorus-doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine-doped oxide (SiOF), or any combination thereof. The GLS filler 1888 may be deposited, for example, by ALD, CVD (e.g., PECVD, RTCVD, LPCVD, etc.), PVD, sputtering, vapor deposition, or any other suitable film deposition technique.

[0119] In some embodiments, the GLS filler 1888 outside the GLS opening 1582 can be removed by etching (e.g., RIE) or CMP. As such, the GLS 216 may be coplanar with the insulating layer 1480.

[0120] As illustrated with respect to Figures 2 and 3, the GLS216 can divide a storage unit (e.g., memory block 103) into sub-storage units (e.g., memory finger 218), and the sub-storage units can perform read and / or program operations independently. As such, read and program speeds can be improved compared to 3D NAND memory.

[0121] Referring to Figure 4, it can be seen that in process step S465, a contact opening is formed, and a portion of one of the conductive layers of the third stepped structure can be exposed. A top-down view and a cross-sectional view of an exemplary 3D memory structure 1900 after process step S465 are shown in Figures 19A and 19B.

[0122] As shown in Figure 19A, the 3D memory structure 1900 includes contact openings 1990 within a first region 1272 of a third stepped structure 1760. As shown in the cross-sectional view along line CC' in Figure 19B, the contact openings 1990 penetrate the insulating layer 1480, the second barrier layer 1166, and the first barrier layer 1064 in the z direction, exposing a portion of the conductive layer 1786. In some embodiments, each contact opening 1990 exposes a portion of one of the conductive layers 1786 of the third stepped structure 1760.

[0123] In some embodiments, forming the contact opening 1990 involves selectively etching the insulating layer 1480 with respect to a second barrier layer 1166, which can function as an etch stop. The second barrier layer 1166 and the first barrier layer 1064 are then etched to expose a portion of the conductive layer 1786 inside the contact opening 1990.

[0124] In some embodiments, a photoresist or polymer material may be used as a mask layer for etching the contact openings 1990. Due to the topology of the stepped structure, the depth of the contact openings 1990 depends on the arrangement of the stepped steps. Contact openings 1990 relative to lower stepped steps may be considerably deeper than contact openings 1990 relative to upper stepped steps. Therefore, contact openings 1990 relative to third stepped steps 1762, which are closer to the substrate 330, require a longer etching time than contact openings 1990 that are further away from the substrate 330. A selective etching process may be used so that the etching rate of the insulating layer 1480 is considerably higher than that of the second barrier layer 1166. In other words, in the etching process for the contact openings 1990, the second barrier layer 1166 acts as an etch-stop layer, protecting the underlying structure until all contact openings 1990 are formed on the second barrier layer 1166 relative to the third stepped structure 1760. Next, a portion of the second barrier layer 1166 and the first barrier layer 1064 inside the contact opening 1990 may be removed.

[0125] In some embodiments, when the gate dielectric layer is disposed before the conductive layer 1786 is disposed, etching also includes removing the gate dielectric layer inside the contact opening 1990.

[0126] The etching process for the contact opening 1990 may include dry etching, wet etching, and / or a combination thereof. When the insulating layer 1480 is silicon oxide and the second barrier layer 1166 is silicon nitride, anisotropic RIE can be used to etch the silicon oxide with chemical etchants, such as CF4, CHF3, C2F6, C3F6, and / or any combination thereof, and when etching the silicon nitride, RIE can be used with chemical etchants, such as O2, N2, CF4, NF3, Cl2, HBr, BCl3, and / or combinations thereof. The etching processes and chemical reactions listed herein are merely examples and should not be considered limiting.

[0127] The second barrier layer 1166 can function as an etch stop during the etching process against the contact opening 1990, so the second barrier layer 1166 can have a thickness sufficient to protect the underlying structure. For example, the second barrier layer 1166 can have a thickness in the range of 10 nm to 500 nm, more specifically 50 nm to 500 nm. As previously described with respect to Figures 16A-16C, 17A-17C, and 21A-21B, the second barrier layer 1166 can be pulled back from the GLS opening 1582 by using the block mask 1270. The second barrier layer 1166 can be surrounded by the insulating layer 1480 and the first barrier layer 1064 during the removal of the second dielectric layer 454 and the formation of the lateral tunnel 1684. Thereafter, the additional tunnel 2184 and the additional conductive layer 2186 can be avoided. Therefore, the thickness of the second barrier layer 1166 can be optimized for the etching process of the contact opening 1990 without being limited by the additional tunnel 2184 and / or additional conductive layer 2186. That is, the thickness of the second barrier layer 1166 can be increased to provide sufficient etch-stopping function when forming the contact opening 1990 on the third stepped structure 1760.

[0128] Referring to Figure 4, it can be seen that in process step S470, the second conductive material is placed inside the contact opening, forming a contact structure for the third stepped structure. A top-down view of an exemplary 3D memory structure 2000 by process step S470 is shown in Figure 20A. Figures 20B to 20D show cross-sectional views of the 3D memory structure 2000 along lines CC', AA', and BB' in Figure 20A.

[0129] As shown in Figures 20A and 20B, the 3D memory structure 2000 includes a contact structure 214 within a first region 1272 of a third stepped structure 1760. The contact structure 214 (similar to that shown in Figures 2 and 3) includes a second conductive material 1992 disposed inside a contact opening 1990 (in Figures 19A and 19B). The contact structure 214 penetrates the insulating layer 1480, the second barrier layer 1166, and the first barrier layer 1064 in the z direction. The contact structure 214 can contact one of the conductive layers 1786 of the film stack 335 through the third stepped structure 1760. In some embodiments, when the gate dielectric layer 1785 is disposed before the conductive layer 1786 is disposed, the contact structure 214 also penetrates the gate dielectric layer 1785.

[0130] In some embodiments, the second conductive material 1992 inside the contact opening 1990 can be in direct contact with the conductive layer 1072. The second conductive material 1992 may include any suitable conductive material, such as metals or metallic compounds, for example, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and / or any combination thereof. The metal or metallic compound may be deposited by using a suitable deposition method such as CVD, PVD, ALD, sputtering, or vapor deposition. The second conductive material 1992 is WSi x CoSi x NiSi x , or AlSi xThe material may also be a metal silicide containing such materials. The metal silicide material may be formed by directly distributing a metal layer on a polycrystalline silicon layer inside the contact opening 1990, then passing it through a thermal annealing process, and subsequently removing any unreacted metal. In some embodiments, the second conductive material 1992 includes a TiN / W / TiN combination deposited by CVD.

[0131] The formation of the contact structure 214 may also include a planarization process, such as CMP, to remove excess second conductive material 1992 on the insulating layer 1480. As shown in Figure 20B, the contact structure 214 may be coplanar with the insulating layer 1480.

[0132] This disclosure also provides a 3D memory device manufactured using the method described above.

[0133] Referring to Figures 20A to 20D, the 3D memory structure 2000 comprises a film stack 335 in which conductive layers and dielectric layers are arranged alternately. The film stack 335 comprises conductive layers 1786 and a first dielectric layer 452 alternately arranged on a substrate 330, which are stacked in the z direction perpendicular to the substrate 330. In some embodiments, the first dielectric layer 452 contains silicon oxide and the conductive layers contain tungsten.

[0134] A third stepped structure 1760 (also referred to as a stepped structure) may be provided in the film stack 335 within the stepped region 210. The third stepped structure 1760 comprises third stepped steps 1762 (also referred to as stepped steps) that extend in the WL direction and move up and down along the WL direction (i.e., facing the WL direction). The third stepped steps 1762, or “staired layer”, refer to a layer stack having the same lateral dimensions on a surface parallel to the substrate surface 330f. Each of the third stepped steps terminates with a length shorter than the third stepped step below it.

[0135] The film stack 335 may include a dividing wall 865 within the dividing region 863. The dividing wall 865 extends parallel to the third stepped structure 1760 in the WL direction. The dividing wall 865 is adjacent to the third stepped structure 1760.

[0136] The 3D memory structure 2000 also includes a first barrier layer 1064 and a second barrier layer 1166. The first barrier layer 1064 is disposed on the third stepped structure 1760 and can cover the top surface and side walls of the third stepped step 1762. Different from the first barrier layer 1064, the second barrier layer 1166 may be disposed on the first barrier layer 1064 in a first region 1272 of the third stepped structure 1760, which is located in the center of the third stepped structure 1760. The first region 1272 extends along the WL direction. In other words, the second barrier layer 1166 is located in the center of the third stepped structure 1760 and can cover the central portion of the third stepped step 1762. The second barrier layer 1166 can be removed from the second region 1274 of the third stepped structure 1760. The second region 1274, extending along the WL direction, is adjacent to the dividing wall 865. In some embodiments, the second region 1274 is located on each side of the first region 1272. In some embodiments, the first barrier layer contains silicon oxide and the second barrier layer contains silicon nitride. In some embodiments, the first barrier layer 1064 has a thickness in the range of 10 nm to 100 nm and the second barrier layer 1166 has a thickness in the range of 50 nm to 500 nm.

[0137] The 3D memory structure 2000 also includes a GLS 216 that penetrates the film stack 335 perpendicularly in the z direction. In some embodiments, the GLS 216 further penetrates into the substrate 330. The GLS 216 extends parallel to the WL direction and parallel to the third stepped structure 1760. The GLS 216 extends parallel to the first region 1272 and the second region 1274 of the third stepped structure 1760. In some embodiments, the second barrier layer 1166 is far from the GLS 216 in the BL direction. The GLS 216 may include a GLS filler 1888, which may include any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc.

[0138] The 3D memory structure 2000 also includes a third stepped structure 1760 and an insulating layer 1480 disposed on a first barrier layer 1064 and a second barrier layer 1166 on a dividing wall 865 of the film stack 335. In some embodiments, the GLS 216 may be coplanar with the insulating layer 1480. The GLS 216 is configured to divide the memory block into sub-storage units (e.g., memory fingers).

[0139] The 3D memory structure 2000 also includes a contact structure 214 formed on a third stepped step 1762 of a third stepped structure 1760, which can provide an electrical connection to a conductive layer 1786 of a film stack 335 in which conductive layers and dielectric layers are arranged alternately. In some embodiments, the contact structure 214 may be located within a first region 1272 of the stepped structure. The contact structure 214 penetrates perpendicularly through the insulating layer, the second dielectric layer, and the first dielectric layer to contact a portion of one of the conductive layers 1786 of the film stack 335.

[0140] In some embodiments, the conductive layer 1786 can be electrically connected to the bottom select gate 332 (in Figure 3), control gate or word line 333, or top select gate 334 of the 3D memory device. In some embodiments, the 3D memory device may include a memory string 212 (see Figures 2-3) that penetrates the film stack 335 perpendicularly in the z direction, and the intersection between the control gate 333 and the memory string 212 can form a memory cell 340 as shown in Figures 2-3.

[0141] Figure 22 illustrates a block diagram of an exemplary system S1 having a storage system 10 according to some embodiments of the present disclosure. System S1 could be a mobile phone, desktop computer, laptop computer, tablet, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage in it. The storage system 10 (also referred to as a NAND storage system) may comprise a memory controller 20 and one or more semiconductor memory chips 25-1, 25-2, 25-3, ..., 25-n. Each semiconductor memory chip 25 (hereinafter simply referred to as a “memory chip”) may be a NAND chip (i.e., “flash”, “NAND flash”, or “NAND”). The storage system 10 can communicate with the host computer 15 through the memory controller 20, which may be connected to one or more memory chips 25-1, 25-2, 25-3, ..., 25-n via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n. In some embodiments, each memory chip 25 may be managed by the memory controller 20 via the memory channel 30.

[0142] In some embodiments, the host computer 15 may include a processor of an electronic device such as a central processing unit (CPU), or a system-on-a-chip (SoC) such as an application processor (AP). The host computer 15 transmits data to be stored in the NAND storage system or storage system 10, or retrieves data by reading from the storage system 10.

[0143] The memory controller 20 can process I / O requests received from the host computer 15, ensure data integrity and efficient storage, and manage the memory chip 25. To perform these tasks, the controller runs firmware 21, which may be executed by one or more processors 22 (e.g., a microcontroller unit, CPU) within the controller 20. For example, the controller 20 runs firmware 21 to map logical addresses (i.e., addresses used by the host associated with host data) to physical addresses within the memory chip 25 (i.e., the actual locations where the data is stored). The controller 20 also runs firmware 21 to manage defective memory blocks within the memory chip 25, which can remap logical addresses to different physical addresses, i.e., move data to different physical addresses. The controller 20 may also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.) which may be used to store various metadata used by the firmware 21. In some embodiments, the memory controller 20 can also perform error recovery through an error correction code (ECC) engine 29. ECC can be used to detect and correct raw bit errors occurring within each memory chip 25.

[0144] The memory channel 30 can provide data and control communication between the memory controller 20 and each memory chip 25 via a data bus. The memory controller 20 can select one of the memory chips 25 according to the chip enable signal.

[0145] In some embodiments, each memory chip 25 in Figure 22 may include one or more memory dies 2201, each memory die 2201 may include a 3D NAND memory 100 as shown in Figures 1-3. In some embodiments, each of the one or more memory dies 2201 may include a 3D memory device 2000 as shown in Figures 20A-20D, which can be manufactured using the method 400 of Figure 4. In some embodiments, a memory controller 20 may be configured to control the operation of the 3D memory device (e.g., the 3D NAND memory 100), and the controller is connected to the 3D memory device.

[0146] The memory controller 20 and one or more memory chips 25 can be integrated into various types of storage devices and included in the same package, for example, a Universal Flash Storage (UFS) package or an eMMC package. That is, the storage system 10 can be implemented and packaged in different types of final electronic products. In one example, as shown in Figure 23A, the memory controller 20 and a single memory chip 25 can be integrated into a memory card 26. The memory card 26 can include PC cards (PCMCIA, International Association of PC Memory Cards), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 may further include a memory card connector 24 that connects the memory card 26 to a host (for example, a host computer 15 in Figure 22). In another example, as shown in Figure 23B, the memory controller 20 and multiple memory chips 25 can be integrated into a solid-state drive (SSD) 27. The SSD27 may further include an SSD connector 28 for connecting the SSD27 to a host (for example, the host computer 15 in Figure 22).

[0147] Figure 24 illustrates schematic diagrams of memory die 2201 according to several embodiments of the present disclosure. In one example, the memory die 2201 may include a 3D memory device 100 in Figure 1 having a 3D memory array structure 300 shown in Figure 3. In this example, the memory die 2201 may further include a 3D memory structure 2000 shown in Figures 20A to 20D. In some embodiments, the memory die 2201 includes one or more memory blocks 103 (e.g., 103-1, 103-2). Each memory block 103 includes a memory string 212. Each memory string 212 includes a memory cell 340. Memory cells 340 sharing the same word line form a memory page 432. The memory string 212 may also include at least one field-effect transistor (e.g., MOSFET) at each end, which are controlled by a bottom select gate (BSG) 332 and a top select gate (TSG) 334, respectively. The drain terminal of the top select transistor 334-T is connected to the bit line 341, and the source terminal of the bottom select transistor 332-T may be connected to the array common source (ACS) 430. The ACS 430 may be shared by the memory string 212 within the entire memory block and is also referred to as the common source line.

[0148] The memory die 2201 may also include peripheral circuits 2402, which include numerous digital, analog, and / or mixed-signal circuits supporting the functionality of the memory block 103, such as a page buffer / sense amplifier 50, a row decoder / word line driver 40, a column decoder / bit line driver 52, a control circuit 70, a voltage generator 65, and an input / output buffer 55. These circuits may include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, and resistors, as will be obvious to those skilled in the art.

[0149] The memory block 103 can be coupled to the row decoder / word line driver 40 via a word line ("WL") 333, a bottom select gate ("BSG") 332, and a top select gate ("TSG") 334. The memory block 103 can also be coupled to the page buffer / sense amplifier 50 via a bit line ("BL") 341. The row decoder / word line driver 40 can select one of the memory blocks 103 on the memory die 2201 in response to an X-path control signal supplied by the control circuit 70. The row decoder / word line driver 40 can transfer the voltage supplied from the voltage generator 65 to the word line in response to the X-path control signal. During readout and program operation, the row decoder / word line driver 40 reads the voltage V according to the X-path control signal received from the control circuit 70. read and program voltage V pgm Transfer the selected word line and pass voltage V pass It can be transferred to a non-selected word line.

[0150] The column decoder / bit line driver 52 controls the inhibit voltage V according to the Y path control signal received from the control circuit 70. inhibitThe bit can be transferred to the unselected bit line and the selected bit line connected to ground. In other words, the column decoder / bit line driver 52 may be configured to select or deselect one or more memory strings 212 according to the Y path control signal from the control circuit 70. The page buffer / sense amplifier 50 may be configured to read and program (write) data to and from the memory block 103 according to the Y path control signal from the control circuit 70. For example, the page buffer / sense amplifier 50 may store one page's worth of data to be programmed in one memory page 432. In another example, the page buffer / sense amplifier 50 may perform a verify operation to ensure that the data has been properly programmed into each memory cell 340. In yet another example, during a read operation, the page buffer / sense amplifier 50 may sense the current flowing through the bit line 341 that reflects the logical state (i.e., data) of the memory cell 340 and amplify the small signal to a measurable magnification.

[0151] The input / output buffer 55 can transfer I / O data to and from the page buffer / sense amplifier 50, and further, addresses ADDR or commands CMD to the control circuit 70. In some embodiments, the input / output buffer 55 can function as an interface between the memory controller 20 (Figure 1) and the memory die 2201 on the memory chip 25.

[0152] The control circuit 70 can control the page buffer / sense amplifier 50 and the row decoder / word line driver 40 in response to the command CMD transferred by the input / output buffer 55. During the program operation, the control circuit 70 can control the row decoder / word line driver 40 and the page buffer / sense amplifier 50 to program the selected memory cell. During the read operation, the control circuit 70 can control the row decoder / word line driver 40 and the page buffer / sense amplifier 50 to read the selected memory cell. The X-path control signal and the Y-path control signal include the row address X-ADDR and the column address Y-ADDR that can be used to identify the selected memory cell in the memory block 103. The row address X-ADDR can include a page index, a block index, and a plane index for identifying the memory page 432, the memory block 103, and the memory plane 101 (in the case of FIG. 1), respectively. The column address Y-ADDR can identify a byte or a word in the data of the memory page 432.

[0153] The voltage generator 65 can generate the voltages to be supplied to the word lines and the bit lines under the control of the control circuit 70. The voltages generated by the voltage generator 65 include the read voltage V read , the program voltage V pgm , the pass voltage V pass , the inhibit voltage V inhibit and so on.

[0154] In summary, the present disclosure provides a method for forming a three-dimensional memory device. The method includes arranging an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate, and forming a stepped structure and divider walls within the alternating dielectric stack. The stepped structure and divider walls extend in a second direction parallel to the substrate, with the divider walls adjacent to the stepped structure. The method also includes sequentially forming a first barrier layer and a second barrier layer distinct from the first barrier layer on the stepped structure. The method further includes forming gate line slit (GLS) openings in the divider walls. The GLS openings penetrate the alternating dielectric stack in the first direction and are farther from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction.

[0155] This disclosure also provides a three-dimensional (3D) memory device. The 3D memory device includes a film stack having conductive layers and a first dielectric layer alternately stacked on a substrate in a first direction perpendicular to the substrate. The 3D memory device also includes a stepped structure disposed within the film stack and extending in a second direction parallel to the substrate, and a dividing wall extending in the second direction and disposed adjacent to the stepped structure. The 3D memory device further includes a gate line slit (GLS) disposed within the dividing wall, the GLS penetrating the film stack in the first direction and extending in the second direction. The 3D memory device also includes a first barrier layer disposed on the stepped structure, and a second barrier layer disposed on the first barrier layer within a first region of the stepped structure, which is different from the first barrier layer, and the second barrier layer is farther from the GLS in a third direction parallel to the substrate and perpendicular to the second direction.

[0156] This disclosure further provides a memory storage system including a 3D memory device. The 3D memory device includes the features described above.

[0157] In this disclosure, a second barrier layer (e.g., silicon nitride) may be used as an etch stop layer to form contact openings for a stepped structure. By using a block mask, a portion of the second barrier layer positioned around the gate line slit can be removed before removing the second dielectric layer (e.g., silicon nitride) in the alternating dielectric stack. After pulling back the second barrier layer from the gate line slit, the second barrier layer is not replaced by the conductive layer, thereby avoiding potential conductive paths. The thickness of the second barrier layer is not limited by the replacement process either. Thus, the performance and reliability of the 3D memory device can be improved.

[0158] This disclosure also provides a three-dimensional (3D) memory die including a 3D memory device and peripheral circuits. The 3D memory device comprises a film stack having alternatingly stacked conductive layers and a first dielectric layer on a substrate in a first direction perpendicular to the substrate; a stepped structure disposed within the film stack and extending in a second direction parallel to the substrate; and a dividing wall extending in the second direction and disposed adjacent to the stepped structure. The 3D memory device also comprises a gate line slit (GLS) disposed within the dividing wall, the GLS penetrating the film stack in a first direction and extending in a second direction; a first barrier layer disposed on the stepped structure; and a second barrier layer disposed on the first barrier layer within a first region of the stepped structure. The second barrier layer, distinct from the first barrier layer, is far from the GLS in a third direction parallel to the substrate and perpendicular to the second direction. The peripheral circuitry is coupled to the 3D memory device and configured to support the operation of the 3D memory device. For example, the peripheral circuitry may include functional devices such as a page buffer / sense amplifier 50, a column decoder / bit line driver 52, an I / O buffer 55, a voltage generator 65, a control circuit 70, and a row decoder 40.

[0159] The above-mentioned descriptions of specific embodiments will fully illustrate the general nature of this disclosure so that, by applying knowledge within the scope of the art, such specific embodiments can be easily modified and / or adapted to various uses without departing from the general concepts of this disclosure and without conducting unnecessary experiments. Accordingly, such adaptations and modifications are intended to fall within the meaning and scope of the equivalent embodiments of the disclosed embodiments, based on the disclosures and guidance presented herein. It will be understood that the language or terminology herein is for illustrative purposes only and not restrictive, and therefore should be interpreted by those skilled in the art in light of the disclosures and guidance.

[0160] Embodiments of the present disclosure have been described above with the help of functional configuration blocks illustrating implementations of specified functions and their relationships. The boundaries of these functional configuration blocks are arbitrarily defined herein for the sake of clarity. Alternative boundaries may be defined insofar as the specified functions and their relationships are adequately performed.

[0161] The sections describing the invention and abstract may specify one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and are therefore not intended to limit the present disclosure and the accompanying claims in any way.

[0162] The extent and scope of this disclosure should be defined solely by the claims and their equivalents, and not by the exemplary embodiments described above.

[0163] [1] A method for forming a three-dimensional memory device, A step of arranging an alternating dielectric stack, wherein the alternating dielectric stack includes a first dielectric layer and a second dielectric layer alternately stacked on a substrate in a first direction perpendicular to the substrate, A step of forming a stepped structure and a dividing wall within the alternating dielectric stack, wherein the stepped structure and the dividing wall extend in a second direction parallel to the substrate, and the dividing wall is adjacent to the stepped structure, The steps include sequentially forming a first barrier layer and a second barrier layer different from the first barrier layer on the aforementioned stepped structure, A step of forming a gate line slit (GLS) opening in the dividing wall, wherein the GLS opening penetrates the alternating dielectric stack in the first direction and is far from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction. Methods that include... [2] The method according to [1], wherein the step of forming the first barrier layer on the stepped structure further includes the step of arranging the first barrier layer so as to cover at least the side walls of the stepped steps of the stepped structure. [3] The step of forming the second barrier layer on the stepped structure is: The steps include: arranging a dielectric material on the stepped structure and the divided wall; The method according to [1], comprising the step of removing a first portion of the dielectric material disposed on the dividing wall. [4] A step of removing the second portion of the dielectric material disposed in the second region of the stepped structure adjacent to the dividing wall to form the second barrier layer in the first region of the stepped structure, wherein the first region and the second region extend in the second direction, and the first region is at the center of the stepped structure. The method described in [3], further including the method described in [3]. [5] A step of arranging a block mask to expose the dividing wall and the second region of the stepped structure adjacent to the dividing wall. The method described in [4], further including the method described in [4]. [6] A step of forming a GLS by arranging a GLS filler inside the GLS opening, wherein the GLS filler includes an insulating material. The method described in [1], further including the method described in [1]. [7] The step of removing the second dielectric layer from between the first dielectric layers through the GLS opening to form a lateral tunnel, The steps include: arranging a first conductive material inside the lateral tunnel to form a film stack including alternately stacked conductive layers and the first dielectric layer; The method described in [1], further including the method described in [1]. [8] The method according to [7], wherein the step of removing the second dielectric layer comprises the step of selectively etching the second dielectric layer with respect to the first dielectric layer and the first barrier layer. [9] Step of placing the insulating layer on the second barrier layer on the stepped structure. The method described in [7], further including the method described in [7].

[10] A step of forming a contact structure for contacting one of the conductive layers in the film stack. The method described in [9], further including the method described in [9].

[11] The method according to

[10] , wherein the step of forming the contact structure includes the step of forming a contact opening that penetrates the insulating layer in the first direction to expose one portion of the conductive layer.

[12] The method according to

[11] , wherein the step of forming the contact structure further includes the step of arranging a second conductive material inside the contact opening and bringing it into contact with the one exposed portion of the conductive layer.

[13] The method according to

[11] , wherein the step of forming the contact opening comprises the step of selectively etching the insulating layer with respect to the second barrier layer.

[14] A memory device, It is a film stack, A conductive layer and a first dielectric layer are alternately stacked on a substrate in a first direction perpendicular to the substrate, A stepped structure extending in a second direction parallel to the substrate, A film stack comprising a dividing wall extending in the second direction and positioned adjacent to the stepped structure, A gate line slit (GLS) is provided in the dividing wall, wherein the GLS penetrates the film stack in the first direction and extends in the second direction, A first barrier layer is provided on the aforementioned stepped structure, A second barrier layer disposed on the first barrier layer within the first region of the stepped structure, the second barrier layer being different from the first barrier layer, and the second barrier layer being further from the GLS in a third direction parallel to the substrate and perpendicular to the second direction. A memory device comprising the above features.

[15] The memory device according to

[14] , wherein the first barrier layer covers at least the side walls of the stepped steps of the stepped structure.

[16] An insulating layer disposed on the second barrier layer so as to cover the top surface and side walls of the second barrier layer. The memory device described in

[14] further comprises the following:

[17] A contact structure that penetrates the insulating layer, the second barrier layer, and the first barrier layer in the first direction, wherein the contact structure is in contact with one of the conductive layers of the film stack. The memory device described in

[16] further comprises the following:

[18] The memory device according to

[14] , wherein the first region is located at the center of the stepped structure and extends in the second direction.

[19] The memory device according to

[18] , wherein the stepped structure further comprises a second region, the second region of the stepped structure extending in the second direction and positioned between the dividing wall and the first region.

[20] The memory device according to

[14] , wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride.

[21] The memory device according to

[14] , wherein the first barrier layer has a thickness in the range of 10 nm to 100 nm.

[22] The memory device according to

[14] , wherein the second barrier layer has a thickness in the range of 50 nm to 500 nm.

[23] The memory device according to

[14] , wherein the GLS includes an insulating material and is configured to divide the storage unit into sub-storage units which independently perform read operations or program operations.

[24] A memory storage system, A 3D memory device, It is a film stack, A conductive layer and a first dielectric layer are alternately stacked on a substrate in a first direction perpendicular to the substrate, A stepped structure extending in a second direction parallel to the substrate, A film stack comprising a dividing wall extending in the second direction and positioned adjacent to the stepped structure, A gate line slit (GLS) is provided in the dividing wall, wherein the GLS penetrates the film stack in the first direction and extends in the second direction, A first barrier layer is provided on the aforementioned stepped structure, A three-dimensional memory device comprising a second barrier layer disposed on the first barrier layer within the first region of the stepped structure, the second barrier layer being different from the first barrier layer, and the second barrier layer being farther from the GLS in a third direction parallel to the substrate and perpendicular to the second direction, A memory controller configured to control the operation of the three-dimensional memory device, wherein the controller is connected to the three-dimensional memory device, and A memory storage system equipped with the following features.

[25] The memory storage system according to

[24] , wherein the first barrier layer covers at least the side walls of the stepped steps of the stepped structure.

[26] An insulating layer disposed on the second barrier layer so as to cover the top surface and side walls of the second barrier layer. The memory storage system described in

[24] further comprises the following:

[27] A contact structure that penetrates the insulating layer, the second barrier layer, and the first barrier layer in the first direction, wherein the contact structure is in contact with one of the conductive layers of the film stack. The memory storage system described in

[26] further comprises the following:

[28] The memory storage system according to

[24] , wherein the first region is located at the center of the stepped structure and extends in the second direction.

[29] The memory storage system according to

[28] , wherein the stepped structure further comprises a second region, the second region of the stepped structure extending in the second direction and positioned between the dividing wall and the first region.

[30] The memory storage system according to

[24] , wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride.

[31] The memory storage system according to

[24] , wherein the first barrier layer has a thickness in the range of 10 nm to 100 nm.

[32] The memory storage system according to

[24] , wherein the second barrier layer has a thickness in the range of 50 nm to 500 nm.

[33] The memory storage system according to

[24] , wherein the GLS includes an insulating material and is configured to divide the storage unit into sub-storage units which independently perform read operations or program operations.

[34] A three-dimensional (3D) memory die, A 3D memory device, It is a film stack, A conductive layer and a first dielectric layer are alternately stacked on a substrate in a first direction perpendicular to the substrate, A stepped structure extending in a second direction parallel to the substrate, A film stack comprising a dividing wall extending in the second direction and positioned adjacent to the stepped structure, A gate line slit (GLS) is provided in the dividing wall, wherein the GLS penetrates the film stack in the first direction and extends in the second direction, A first barrier layer is provided on the aforementioned stepped structure, A 3D memory device comprising a second barrier layer disposed on the first barrier layer within the first region of the stepped structure, the second barrier layer being different from the first barrier layer, and the second barrier layer being farther from the GLS in a third direction parallel to the substrate and perpendicular to the second direction, A peripheral circuit is coupled to the 3D memory device and configured to support the operation of the 3D memory device. A 3D memory die equipped with [a specific feature].

[35] The 3D memory die according to

[34] , wherein the first barrier layer covers at least the side walls of the stepped steps of the stepped structure.

[36] An insulating layer disposed on the second barrier layer so as to cover the top surface and side walls of the second barrier layer. A 3D memory die described in

[34] further comprising the above.

[37] A contact structure that penetrates the insulating layer, the second barrier layer, and the first barrier layer in the first direction, wherein the contact structure is in contact with one of the conductive layers of the film stack. A 3D memory die described in

[36] further comprising the above.

[38] The 3D memory die according to

[34] , wherein the first region is located at the center of the stepped structure and extends in the second direction.

[39] The 3D memory die according to

[38] , wherein the stepped structure further comprises a second region, the second region of the stepped structure extending in the second direction and positioned between the dividing wall and the first region.

[40] The 3D memory die according to

[34] , wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride.

[41] The 3D memory die according to

[34] , wherein the first barrier layer has a thickness in the range of 10 nm to 100 nm.

[42] The 3D memory die according to

[34] , wherein the second barrier layer has a thickness in the range of 50 nm to 500 nm.

[43] The 3D memory die according to

[34] , wherein the GLS includes an insulating material and is configured to divide the storage unit into sub-storage units which independently perform read operations or program operations. [Explanation of symbols]

[0164] S1 System 10 Storage Systems 15 Host computer 20 Memory Controllers 21 Firmware 22 processors 23 memory 24 Memory card connectors 25 memory chips 25-1, 25-2, 25-3, ..., 25-n semiconductor memory chips 26 memory cards 27 SSD 28 SSD connectors 30 memory channels 30-1, 30-2, 30-3, ..., 30-n memory channels 40 Row Decoder / Word Line Driver 50-page buffer / sense amplifier 52-column decoder / bit line driver 55 Input / Output Buffers, I / O Buffers 65 Voltage Generator 70 Control circuits 100 3D memory devices, 3D NAND memory 101 memory plane 103 memory blocks 105 Peripheral area 108 areas 210 Stepped area 211 Channel structure region 212 memory string 214 Contact structure 216 Slit structure (also called gate wire slit) 216-1 and 216-2 Slit Structure 218 Memory Fingers 222 Dummy memory string 224 memory slices 300 memory array structure 330 circuit boards 330f front 331 Insulating film 332 Bottom Select Gate (BSG) 332-T Bottom Select Transistor 333 Control Gate 333 Word lines 333-1, 333-2, 333-3 control gates 334 Top Select Gate (TSG) 334-T Top Select Transistor 335 Film Stack 336 Channel Hole 337 Memory Film 338 channel layers 339 Core-filled film 340 memory cells 340-1, 340-2, and 340-3 memory cells 341-bit line (BL) 343 Metal interconnecting wires 344 Doped source line region 400 ways 432 memory pages 450 Alternating Dielectric Stack 452 First dielectric layer 454 Second dielectric layer 500 3D memory structure 600 3D memory structure 656 First stepped structure 658 First stepped step 700 3D memory structure 760 Second stepped structure 762 Second stepped step 863 Split area 865 dividing wall 1000 3D memory structure 1064 First barrier layer 1072 Conductive layer 1100 3D memory structure 1166 Second barrier layer 1200 3D memory structure 1270 Block Mask 1272 First Domain 1274 Second Region 1276 Exposed structure 1300 3D memory structure 1400 3D memory structure 1480 Insulating layer 1500 3D memory structure 1582 Gate wire slit (GLS) opening 1600 3D memory structure 1684 and 2184 Side Tunnels 1700 3D memory structure 1760 Third stepped structure 1762 Third stepped step 1785 Gate Dielectric Layer 1786 Conductive layer 1800 3D memory structure 1888 GLS Filler 1900 3D memory structure 1990 Contact opening 1992 Second conductive material 2000 3D memory structure 2184 Tunnel 2186 Conductive layer 2201 Memory Die

Claims

1. A memory device, It is a film stack, A conductive layer and a dielectric layer are alternately stacked in a first direction, A stepped structure extending in a second direction perpendicular to the first direction, A film stack comprising a wall structure extending in the second direction and positioned adjacent to the stepped structure, A gate line slit (GLS) is provided in the wall structure, wherein the GLS penetrates the film stack in the first direction and extends in the second direction, A first barrier layer is provided on the aforementioned stepped structure, A second barrier layer disposed on the first barrier layer, wherein the second barrier layer is different from the first barrier layer, A substrate, wherein the second barrier layer is located in a third direction parallel to the substrate and perpendicular to the second direction, and is farther from the GLS, and A memory device comprising the above features.

2. A contact structure that penetrates the second barrier layer and the first barrier layer in the first direction, wherein the contact structure is in contact with one of the conductive layers of the film stack. The memory device according to claim 1, further comprising:

3. An insulating layer disposed on the second barrier layer so as to cover the top surface of the second barrier layer, wherein the contact structure penetrates the insulating layer in the first direction, The memory device according to claim 2, further comprising:

4. The memory device according to claim 1, wherein the first barrier layer and the second barrier layer cover at least the side walls of the stepped steps of the stepped structure.

5. The memory device according to claim 1, wherein the first barrier layer has a thickness in the range of 10 nm to 100 nm.

6. The memory device according to claim 1, wherein the second barrier layer has a thickness in the range of 50 nm to 500 nm.

7. The memory device according to claim 1, wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride.

8. The memory device according to claim 1, wherein the wall structure, which is part of the film stack, comprises a portion of the conductive layer and a portion of the dielectric layer that are alternately stacked in the first direction.

9. The memory device according to claim 1, wherein the first barrier layer is disposed on the side wall of the wall structure.

10. The memory device according to claim 1, wherein the wall structure extends along the entire length of the stepped structure in the second direction.

11. A memory device, It is a film stack, A conductive layer and a dielectric layer are alternately stacked in a first direction, A stepped structure extending in a second direction perpendicular to the first direction, A film stack comprising a wall structure extending in the second direction and positioned adjacent to the stepped structure, A gate line slit (GLS) is provided in the wall structure, wherein the GLS penetrates the film stack in the first direction and extends in the second direction, The first barrier layer, The first part is arranged on the aforementioned stepped structure, A first barrier layer comprising a second portion disposed on the side wall of the wall structure, A second barrier layer disposed on the first barrier layer, wherein the second barrier layer is different from the first barrier layer, A substrate, wherein the second barrier layer is located in a third direction parallel to the substrate and perpendicular to the second direction, and is farther from the GLS, and A memory device comprising the above features.

12. The memory device according to claim 11, wherein the second barrier layer is disposed on the first portion of the first barrier layer.

13. A contact structure that penetrates the second barrier layer and the first barrier layer in the first direction, wherein the contact structure is in contact with one of the conductive layers of the film stack. The memory device according to claim 11, further comprising:

14. An insulating layer disposed on the second barrier layer so as to cover the top surface of the second barrier layer, wherein the contact structure penetrates the insulating layer in the first direction, The memory device according to claim 13, further comprising:

15. The memory device according to claim 11, wherein the first barrier layer and the second barrier layer cover at least the side walls of the stepped steps of the stepped structure.

16. The memory device according to claim 11, wherein the first barrier layer has a thickness in the range of 10 nm to 100 nm.

17. The memory device according to claim 11, wherein the second barrier layer has a thickness in the range of 50 nm to 500 nm.

18. The memory device according to claim 11, wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride.

19. The memory device according to claim 11, wherein the wall structure, which is part of the film stack, comprises a portion of the conductive layers and a portion of the dielectric layers that are alternately stacked in the first direction.

20. The memory device according to claim 11, wherein the wall structure extends along the entire length of the stepped structure in the second direction.

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