Dynamic random access memory system including single-ended sense amplifier and method of operating same

Abstract

A DRAM system includes a first array of DRAM cells, each column of DRAM cells connected to a corresponding bit line, and a plurality of single-ended sense amplifiers, each connected to a corresponding bit line, each single-ended sense amplifier including a kick capacitor connected to the corresponding bit line, a latch circuit having a first internal node for storing a data bit, and an isolation transistor connecting the corresponding bit line to the first internal node of the latch circuit, the corresponding bit line being configured to be the only bit line in the first array of DRAM cells connected to the latch circuit.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Non-provisional Patent Application No. 18 / 399,579, filed December 28, 2023, by Richard S. Roy, entitled "Dynamic Random Access Memory System Including Single-Ended Sense Amplifiers and Method of Operating the Same," and U.S. Provisional Patent Application No. 63 / 477,942, filed December 30, 2022, by Richard S. Roy, entitled "DRAM Architecture with Decoded Sub-Word Line (SWL) Configuration and Related Methods."

[0002] The present invention relates to dynamic random access memory (DRAM) systems, and more particularly to DRAM systems including single-ended sense amplifiers. [Background technology]

[0003] DRAM has been used in many system configurations to provide data storage for applications such as machine learning. As these applications become more complex, it has become increasingly difficult to provide DRAM systems that can address all of these applications' access requirements (e.g., random access bandwidth, latency, power consumption, random access capability, memory capacity and density, and refresh). JEDEC Standard No. 238A describes specifications for high-bandwidth memory (HBM3) DRAMs that connect to a host computer die via a distributed interface. HBM3 DRAMs employ a wide interface architecture for high-speed, low-power operation. Meanwhile, improved DRAM systems are needed to achieve increased random access bandwidth, reduced access latency, reduced operating and standby power, improved random access performance, larger memory capacity, higher density, and improved refresh schemes. Current HBM architectures primarily focus on extending the traditional paradigm by increasing data bandwidth for large-block access, which entails significant power consumption increases due to the analog circuitry required to achieve data rates approaching 10 Gb / sec / pin. However, they are largely inadequate for high-speed random (or quasi-random) addressing. Summary of the Invention [Means for solving the problem]

[0004] Therefore, the present invention focuses on increasing the number of sustained independent transactions per second (SIT / s), which requires applying nearly independent addresses at very high rates to a stack of DRAM chips connected by through-silicon-via (TSV) structures, while also requiring significant improvements in power efficiency per transaction. Additional features include significant improvements in power, latency, and data bandwidth per transaction, with little or no impact on area overhead.

[0005] According to one embodiment of the present invention, a dynamic random access memory (DRAM) system is provided, comprising: a first array of DRAM cells arranged in a plurality of rows and columns, each column of DRAM cells connected to a corresponding bit line; and a plurality of single-ended sense amplifiers each connected to a corresponding bit line of the first array of DRAM cells, each single-ended sense amplifier including a kick capacitor connected to the corresponding bit line, a latch circuit having a first internal node for storing a data value, and an isolation transistor connecting the corresponding bit line to the first internal node of the latch circuit, the corresponding bit line being the only bit line in the first array of DRAM cells connected to that latch circuit.

[0006] In one embodiment, the latch circuit includes a first p-channel transistor (P1) having a source connected to a first control node (PCOM), a gate connected to a first internal node (INT0), and a drain connected to a second internal node (INT0#); a first n-channel transistor (N1) having a source connected to a second control node (NCOM), a gate connected to the first internal node, and a drain connected to the second internal node; a second p-channel transistor (P2) having a source connected to the first control node, a gate connected to the second internal node, and a drain connected to the first internal node; and a second n-channel transistor (N2) having a source connected to the second control node, a gate connected to the second internal node, and a drain connected to the first internal node.

[0007] In one embodiment, a precharge circuit is connected to the latch circuit, and the precharge circuit includes a first precharge transistor selectively connecting the first internal node to a ground voltage supply source and a second precharge transistor selectively connecting the second internal node to the ground voltage supply source.

[0008] In one embodiment, the latch circuit further includes means for varying a voltage applied to the first control node (PCOM) between ground potential and a positive power supply voltage, and means for varying a voltage applied to the second control node (NCOM) between ground potential and a negative power supply voltage.

[0009] In a particular embodiment, each single-ended sense amplifier further includes a refresh control transistor having a gate connected to a second internal node, a drain connected to a corresponding bit line, and a source connected to receive a bit line refresh control signal.

[0010] In some embodiments, means are provided for varying the voltage applied to the kick capacitor during a read access.

[0011] According to another embodiment of the present invention, a method for operating a DRAM system is provided. The method includes precharging a bit line connected to a DRAM cell to a ground potential, precharging a first internal node and a second internal node of a sense amplifier latch to a ground potential, and disabling the sense amplifier latch by driving a first power supply voltage terminal and a second power supply terminal of the sense amplifier latch to a ground potential. Activating a word line connected to the DRAM cell causes the DRAM cell to generate a read voltage on the bit line. Activating a kick capacitor then lowers the read voltage generated on the bit line. Connecting the bit line to the first internal node of the sense amplifier latch causes the read voltage generated on the bit line to be applied to the first internal node of the sense amplifier latch. The sense amplifier latch is then enabled by disconnecting the bit line from the first internal node of the sense amplifier latch and driving the first power supply voltage terminal of the sense amplifier latch to a positive power supply voltage and the second power supply terminal of the sense amplifier latch to a negative power supply voltage. The DRAM cell is then refreshed by connecting the bit line to the first internal node of the sense amplifier latch. In one embodiment, the word line is first activated by applying a positive voltage to it, and then this positive voltage is boosted.

[0012] According to another embodiment, the present invention provides a DRAM system including a first integrated circuit chip including a plurality of processors, a second integrated circuit chip including a plurality of independent DRAM arrays connected to correspond to each of the plurality of processors on the first integrated circuit chip, and a refresh control circuit disposed on the first integrated circuit chip. The refresh control circuit initiates refresh operations on the plurality of DRAM arrays on the second integrated circuit chip. In a specific embodiment, an interconnect structure connects each of the plurality of processors on the first integrated circuit chip to each other. In another embodiment, a first plurality of through-silicon-via (TSV) structures connect the first integrated circuit chip and the second integrated circuit chip to each other.

[0013] In another embodiment, the DRAM system further includes a third integrated circuit chip including a plurality of DRAM arrays, each of the plurality of DRAM arrays of the third integrated circuit chip connected to a corresponding one of the plurality of processors in the first integrated circuit chip. In this embodiment, a second plurality of through-silicon-via (TSV) structures connect the first integrated circuit chip and the third integrated circuit chip to each other, the second plurality of TSV structures extending through the first integrated circuit chip. According to another embodiment, a power management integrated circuit is connected to the first integrated circuit chip and the second integrated circuit chip, and the power management integrated circuit provides a first plurality of power supply voltages to the first integrated circuit chip and the second integrated circuit chip and a second plurality of power supply voltages only to the second integrated circuit chip.

[0014] According to another embodiment, the present invention provides a DRAM system including: a first integrated circuit chip including a plurality of DRAM banks, each having a plurality of DRAM banks, extending in a parallel direction along the width of the first integrated circuit chip; and a plurality of through-silicon-via (TSV) regions, each including a plurality of TSV interconnect structures, extending in a parallel direction along the width of the integrated circuit chip, each of the plurality of TSV regions being disposed between and connected to a corresponding pair of the plurality of DRAM blocks.

[0015] In one embodiment, the DRAM blocks and TSV regions are configured to form independent DRAM sectors, each DRAM sector including a set of DRAM banks and a set of TSV interconnect structures.

[0016] In another embodiment, the DRAM system includes a second integrated circuit chip including multiple processors, each processor connected to a corresponding DRAM sector via a set of multiple TSV interconnect structures included in the corresponding independent DRAM sector. In yet another embodiment, all of the processors are connected to each other by interconnect structures on the second integrated circuit chip.

[0017] According to another embodiment, the present invention includes a DRAM system including a first integrated circuit chip including a plurality of processors; a second integrated circuit chip including a first plurality of independent DRAM sectors, each of the first plurality of independent DRAM sectors connected to a corresponding processor in the first integrated circuit chip via a first plurality of through-silicon-via (TSV) interconnect structures; and a third integrated circuit chip including a second plurality of independent DRAM sectors, each of the second plurality of independent DRAM sectors connected to a corresponding processor in the first integrated circuit chip via a second plurality of TSV interconnect structures extending through the first integrated circuit chip.

[0018] According to another embodiment, the present invention includes a DRAM system including a first integrated circuit chip including a plurality of processors, a plurality of DRAM integrated circuit chips each including a plurality of independent DRAM sectors, and a plurality of sets of through-silicon-via (TSV) interconnect structures, each set of TSV interconnect structures connecting a corresponding processor in the first integrated circuit chip to a corresponding DRAM sector in each of the plurality of DRAM integrated circuit chips.

[0019] According to another embodiment, the present invention includes a DRAM unit cell disposed in an integrated circuit chip, the DRAM unit cell including a plurality of through silicon vias (TSVs) extending through the integrated circuit chip, a first plurality of DRAM banks arranged along a first axis, and a second plurality of DRAM banks arranged along the first axis, the plurality of TSVs disposed along the first axis between the first DRAM banks and the second DRAM banks, the plurality of TSVs transmitting address and control signals for accessing the first DRAM banks and the second DRAM banks, and subsequently transmitting read data and write data to the first DRAM banks and the second DRAM banks.

[0020] In a particular embodiment, each of the first plurality of DRAM banks and the second plurality of DRAM banks includes a plurality of strips, each strip including a plurality of corresponding DRAM bit cell rows in the DRAM bank, a first primary sense amplifier circuit disposed adjacent to a first row of the plurality of corresponding DRAM bit cell rows and connected to a first subset of the DRAM bit cells, and a second primary sense amplifier circuit disposed adjacent to a last row of the plurality of corresponding DRAM bit cell rows and connected to a second subset of the DRAM bit cells.

[0021] According to another embodiment, the present invention includes a DRAM unit cell having a first memory bank and a second memory bank. The first memory bank includes DRAM cells having a plurality of rows and columns, the plurality of rows being divided into N DRAM strips, where N is an integer greater than 1, each DRAM strip including a plurality of consecutive rows of DRAM cells of the first memory bank. The first memory bank also includes N+1 primary sense amplifier circuits, each DRAM strip of the first memory bank being connected to a corresponding pair of primary sense amplifier circuits of the first memory bank. The second memory bank includes DRAM cells having a plurality of rows and columns, the plurality of rows of the second memory bank being divided into N DRAM strips, each DRAM strip of the second memory bank including a plurality of consecutive rows of DRAM cells of the second memory bank. The second memory bank also includes N+1 primary sense amplifier circuits, each DRAM strip of the second memory bank being connected to a corresponding pair of primary sense amplifier circuits of the second memory bank. Furthermore, a secondary sense amplifier circuit is disposed between the first memory bank and the second memory bank, and this secondary sense amplifier circuit is connected to each of the primary sense amplifier circuits of the first memory bank and the second memory bank.

[0022] In one embodiment, half of a first column of DRAM cells in one of the N DRAM strips of a first memory bank are connected to a first primary sense amplifier circuit of the first memory bank, and half of a second column of DRAM cells in the remaining first column are connected to a second primary sense amplifier circuit of the first memory bank.

[0023] In another embodiment, each of the N DRAM strips of the first memory bank includes a plurality of main word lines and a plurality of virtual sub-word lines, each main word line connected to a corresponding plurality of virtual sub-word lines, and each virtual sub-word line connected to a row of DRAM cells of the first memory bank.

[0024] In another embodiment, each virtual sub-word line includes multiple independent sub-word line segments, each sub-word line segment connected to multiple consecutive DRAM cells in a row of DRAM cells of the first memory bank.

[0025] In another embodiment, a DRAM unit cell includes multiple sub-word line drivers, each connected to a corresponding one of the sub-word line segments.

[0026] In another embodiment, each sub-word line driver is connected to receive a main word line signal transmitted from a corresponding one of the plurality of main word lines and a sub-word line segment select signal for selecting the sub-word line segment connected to the sub-word line driver.

[0027] According to another embodiment, the present invention provides a DRAM system including: a first set of DRAM cells arranged in a plurality of rows and four columns, each of the four columns of the DRAM cells of the first set connected to a respective bit line of a first group of four bit lines; a second set of DRAM cells arranged in a plurality of rows and four columns, each of the four columns of the DRAM cells of the second set connected to a respective bit line of a second group of four bit lines; and a first pair of single-ended sense amplifiers disposed between the DRAM cells of the first set and the DRAM cells of the second set. The first single-ended sense amplifier pair includes a first single-ended sense amplifier, a second single-ended sense amplifier, a first transistor that selectively connects or disconnects the first single-ended sense amplifier to a first bit line in a first group of bit lines, a second transistor that selectively connects or disconnects the first single-ended sense amplifier to a first bit line in a second group of bit lines, a third transistor that selectively connects or disconnects the second single-ended sense amplifier to a second bit line in the first group of bit lines, and a fourth transistor that selectively connects or disconnects the second single-ended sense amplifier to a second bit line in the second group of bit lines, wherein the first transistor and the second transistor are controlled so that the first single-ended sense amplifier is connected to at most one bit line at a time, and the third transistor and the fourth transistor are controlled so that the second single-ended sense amplifier is connected to at most one bit line at a time.

[0028] In one embodiment, the width of the first single-ended sense amplifier pair is configured to be equal to or less than four times the pitch between adjacent bit lines.

[0029] In another embodiment, the DRAM system further includes a second single-ended sense amplifier pair disposed adjacent to the first set of DRAM cells, the second single-ended sense amplifier pair including a third single-ended sense amplifier, a fourth single-ended sense amplifier, a fifth transistor selectively connecting and disconnecting the third single-ended sense amplifier to a third bit line in the first group of bit lines, and a sixth transistor selectively connecting and disconnecting the fourth single-ended sense amplifier to a fourth bit line in the first group of bit lines.

[0030] In another embodiment, the DRAM system further includes a global bit line, the global bit line connected to the first single-ended sense amplifier and the second single-ended sense amplifier of the first single-ended sense amplifier pair and the third single-ended sense amplifier and the fourth single-ended sense amplifier of the second single-ended sense amplifier pair.

[0031] The present invention will be more fully understood with reference to the following description and drawings. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is a side view of a multi-threaded dynamic random access memory (MTDRAM) system including multiple MTDRAM chips and an ASIC controller, according to one embodiment of the present invention. [Figure 2] 2 is a side view of a power management integrated circuit (IC) connected to the MTDRAM system of FIG. 1, according to one embodiment of the present invention. [Figure 3] 1 is a top view of an MTDRAM chip according to an embodiment of the present invention; [Figure 4] FIG. 4 is a top view of the MTDRAM chip of FIG. 3, showing the locations of the sixteen 2 GB MTDRAM sectors. [Figure 5]4 is a top view of the ASIC controller of FIG. 1 showing the schematic placement of multiple processors and the placement of corresponding TSV sections for interfacing with the MTDRAM chip of FIG. 3. [Figure 6A] FIG. 2 is a side view illustrating how a processor in an ASIC controller is connected to corresponding MTDRAM sectors in multiple MTDRAM chips, in accordance with one embodiment of the present invention. [Figure 6B] FIG. 10 is a side view illustrating how a processor in an ASIC controller is connected to corresponding MTDRAM sectors in multiple MTDRAM chips, according to another embodiment of the present invention. [Figure 6C] FIG. 10 is a side view illustrating how a processor in an ASIC controller is connected to corresponding MTDRAM sectors on multiple MTDRAM chips, according to yet another embodiment of the present invention. [Figure 7] 1 is a top view of a set of four MTDRAM unit cells included in a 2 Gb sector of an MTDRAM chip according to one embodiment of the present invention. [Figure 8] 1 is a plan view of an MTDRAM bank included in an MTDRAM unit cell according to one embodiment of the present invention, the MTDRAM bank including multiple MTDRAM strips each having multiple subarrays. [Figure 9] FIG. 1 is a circuit diagram illustrating a portion of an MTDRAM strip according to one embodiment of the present invention, including a main wordline driver, a main wordline, multiple virtual sub-wordlines (each having multiple sub-wordline segments), multiple sub-wordline drivers, and multiple primary sense amplifier circuits. [Figure 10] FIG. 1 illustrates read / write access instructions to an MTDRAM unit cell according to one embodiment of the present invention. [Figure 11] FIG. 11 is a block diagram illustrating a first access pattern implemented in an MTDRAM unit cell according to the read / write access instructions of FIG. 10. [Figure 12]FIG. 11 is a block diagram illustrating a second access pattern implemented in an MTDRAM unit cell according to the read and write access instructions of FIG. 10. [Figure 13] FIG. 10 is a circuit diagram illustrating a sub-word line driver of the MTDRAM strip of FIG. 9 in accordance with one embodiment of the present invention. [Figure 14] FIG. 14 is a waveform diagram illustrating the operation of the sub-word line driver of FIG. 13 in accordance with one embodiment of the present invention. [Figure 15A] FIG. 1 is a circuit diagram illustrating a circuit implemented by an ASIC controller that generates pre-decoded sub-word line segment address signals for accessing a sub-array of MTDRAM unit cells, in accordance with one embodiment of the present invention. [Figure 15B] FIG. 15B is a waveform diagram illustrating the generation of sub-word line segment address signals by the circuit of FIG. 15A in accordance with one embodiment of the present invention. [Figure 16] FIG. 15B is a block diagram illustrating how the sub-word line segment access signals generated by the circuitry of FIG. 15A control the sub-word line driver circuits in a portion of a sub-array of MTDRAM unit cells, in accordance with one embodiment of the present invention. [Figure 17] FIG. 10 is a block diagram illustrating primary sense amplifiers and bit lines associated with a sub-array of the MTDRAM strip of FIG. 9, in accordance with one embodiment of the present invention. [Figure 18] FIG. 18 is a circuit diagram of a pair of single-ended primary sense amplifiers shown in FIG. 17, in accordance with one embodiment of the present invention. [Figure 19] FIG. 19 is a waveform diagram illustrating a read operation on a bit cell connected to the single-ended primary sense amplifier shown in FIG. 18, the bit cell storing a logic “1” data value, in accordance with one embodiment of the present invention. [Figure 20] FIG. 19 is a waveform diagram illustrating a read operation to a bit cell connected to the single-ended primary sense amplifier of FIG. 18, the bit cell storing a logic “0” data value, in one embodiment of the present invention. [Figure 21] FIG. 18 is a circuit diagram of a pair of single-ended primary sense amplifiers of FIG. 17 in accordance with another embodiment of the present invention. [Figure 22] FIG. 22 is a waveform diagram illustrating a read operation to a bit cell connected to the single-ended primary sense amplifier of FIG. 21, the bit cell storing a logic “1” data value, in one embodiment of the present invention. [Figure 23] FIG. 22 is a waveform diagram illustrating a read operation to a bit cell connected to the single-ended primary sense amplifier of FIG. 21, the bit cell storing a data value of logic “0,” in accordance with one embodiment of the present invention. [Figure 24] FIG. 10 is a block diagram illustrating how data is routed from a 512-bit section of a primary sense amplifier circuit associated with a sub-word line segment to a corresponding 64-bit section of a secondary sense amplifier circuit using 64 global bit lines, in accordance with one embodiment of the present invention. [Figure 25] FIG. 8 is a block diagram of a unit cell according to FIG. 7 , outlining the global bit line routing from the primary sense amplifier to the secondary sense amplifier, the global input / output (GIO) line routing from the secondary sense amplifier to the tertiary sense amplifier, and the TSV input / output (TIO) line routing from the tertiary sense amplifier to the TSV, in one embodiment of the present invention. [Figure 26] FIG. 10 is a block diagram illustrating the layout of a 32 Gb MTDRAM chip according to another embodiment of the present invention. [Figure 27] FIG. 27 is a block diagram of a unit cell of the MTDRAM chip of FIG. 26, which includes 16 memory banks, four secondary sense amplifier circuits, two tertiary sense amplifier circuits, and a set of TSV structures that define two independent data channels, in accordance with one embodiment of the present invention. [Figure 28] FIG. 28 is a block diagram showing how a set of TSV structures of the unit cells of FIG. 27 are connected to a corresponding processor in an ASIC controller and to a corresponding set of TSV structures of unit cells located on other MTDRAM chips, according to another embodiment of the present invention. [Figure 29]FIG. 28 is a block diagram illustrating the highlighted region of the unit cell of FIG. 27 in which TSVs, secondary sense amplifier control circuits, and secondary sense amplifier repeater circuits are located in the regions between the main word line drivers and between the sub-word line drivers, in accordance with another embodiment of the present invention. [Figure 30] FIG. 28 is a circuit diagram illustrating multiplexer circuitry for routing data between the secondary and tertiary sense amplifier circuits in the unit cell of FIG. 27 via global input / output lines, in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] The present invention includes a multi-threaded DRAM (MTDRAM) architecture that implements through-silicon via (TSV) structures to connect multiple MTDRAM chips to a dedicated controller chip. The system is optimized for power, including reduced standby refresh power consumption (IDD6) and reduced power consumption per read / write transaction. The MTDRAM system also significantly improves random address access speeds (both near-random and fully random) compared to conventional DRAM systems. Furthermore, the MTDRAM system does not require significant additional costs in terms of area overhead, design, materials, or manufacturing.

[0034] In one embodiment, a significant reduction in power required per transaction compared to conventional DRAM systems is achieved through the following: Up to a 2x improvement in mismatch due to the use of primary sense amplifiers with highly matched threshold voltage transistors (due to the use of an MST process for these sense amplifier transistors); Up to a 10x reduction in refresh power due to the use of small-signal single-ended primary sense amplifiers (operated using ground as the reference voltage) resulting in longer refresh intervals; Up to a 5x power reduction due to the use of small signals (i.e., signals with voltage swings much smaller than Vdd) in the on-chip data path from the primary sense amplifier to the I / O TSV structures, as well as in the address and control paths leading to the final decoder (although the final decoder still needs to increase its voltage swing to Vdd to operate conventional NAND or NOR logic); Up to an 8x power reduction due to the use of decoded sub-word line segments; and Up to a 1.5x reduction in power wastage in long lines due to the use of small unit cells. Additionally, all chip connection paths are provided on the ASIC controller, which significantly improves power efficiency and allows for complex connections.

[0035] Furthermore, the random address access speed of the MTDRAM architecture significantly exceeds that of conventional HBM DDR5 systems, resulting in an order of magnitude improvement in SIT / s (Thread Executions per Second) due to the newly defined "near-random" address access rate.

[0036] As explained in more detail below, the MTDRAM architecture is optimized for future TSV manufacturing and test flow evolution: it can easily scale as the minimum TSV pitch shrinks. Furthermore, it can easily be overlaid with standard logic interfaces for legacy systems.

[0037] FIG. 1 is a side view of a multi-threaded dynamic random access memory (MTDRAM) system 100 according to one embodiment of the present invention. In the illustrated embodiment, the MTDRAM system 100 includes an application-specific integrated circuit (ASIC) controller 110 fabricated using an advanced logic process, which includes multiple distributed processors 111-114 and refresh control circuitry 115. While only four distributed processors 111-114 are shown in FIG. 1, it will be understood that, as described below, the ASIC controller 110 typically includes four or more processors. The MTDRAM system 100 further includes multiple MTDRAM integrated circuit chips 101-104, each containing a DRAM memory structure (described in more detail below) accessed by the processor in the ASIC controller 110. The controller 110 and the MTDRAM chips 101-104 are connected in a stacked configuration using multiple through-silicon-via (TSV) interconnect structures. The TSV connection structures 121-124 are shown schematically in Figure 1 by vertical lines, and each TSV connection structure 121-124 includes a TSV that penetrates the MTDRAM chips 101-104 (e.g., TSVs 131-134 of the TSV connection structure 121) and interconnects that connect the TSVs between the MTDRAM chips 101-104 and the controller 110 (e.g., interconnects 141-144 of the TSV connection structure 121). While Figure 1 shows only four TSV connection structures 121-124, it should be understood that the MTDRAM system 100 includes many more TSV connection structures. As described in more detail below, the TSV connection structures 121-124 are used to route address signals, input / output signals, and power supply voltages to each element of the MTDRAM system 100.

[0038] 2 is a side view illustrating a power management integrated circuit (IC) connected to the MTDRAM chips 101-104 and the ASIC controller 110 in one embodiment. The power management IC (PMIC) 150 receives multiple power supply voltages (e.g., Vddp=1.8V, Vddturbo=0.8-1.2V, Vdd=0.4-0.6V, GND=0V) and, in response, generates multiple control / power supply voltages used by the MTDRAM chips 101-104 and the ASIC controller 110. TSV connection structures 151-159 are used to provide the various voltages from the power management IC 150 to the MTDRAM chips 101-104 and the ASIC controller 110, as shown. It should be noted that some voltages (e.g., Vneg=-200mV, GND, Vrefglobal=100-150mV, Vdd=0.4-0.6V, Vnwell=0.6-1.0V, Vddturbo, and Vddgate=0.8-1.2V) are supplied to both the MTDRAM chips 101-104 and the ASIC controller 110, while other voltages (e.g., VK=50mV and Vddp=1.8V) are supplied only to the MTDRAM chips 101-104 (i.e., they pass through the ASIC controller 110 without any connections). How these voltages are used within the MTDRAM chips 101-104 will be described in more detail below.

[0039] In the illustrated embodiment, MTDRAM system 100 includes four MTDRAM chips 101-104, each having 32 gigabits (Gb) of DRAM storage capacity. However, it should be understood that in other embodiments, MTDRAM system 100 can be modified to include a different number of MTDRAM chips 101-104 or MTDRAM chips having different DRAM capacities. In the described embodiment, ASIC controller 110 includes refresh control circuitry 115 necessary to refresh the DRAM cells in MTDRAM chips 101-104. As explained in more detail below, the refresh interval for the DRAM cells in MTDRAM chips 101-104 is advantageously extended, thereby advantageously reducing the number of refresh operations that must be performed within a given period of time. As a result, significant power savings are realized.

[0040] FIG. 3 is a top view of an MTDRAM chip 101 according to one embodiment. Note that the MTDRAM chips 102-104 are designed with a similar layout to the MTDRAM chip 101 to facilitate interconnection of the stack of four MTDRAM chips, as shown in FIGS. 1 and 2. As shown in FIG. 3, the MTDRAM chip includes four TSV regions 201-204, and the TSVs of the MTDRAM chip 101 are arranged in these regions 201-204. As shown, the TSV regions 201-204 extend horizontally across the MTDRAM chip 101. Eight 4 Gb MTDRAM memory blocks 211-212, 221-222, 231-232, and 241-242 also extend horizontally across the MTDRAM chip 101, with the TSV regions 201-204 interleaved with these 4 Gb MTDRAM memory blocks. More specifically, TSV region 201 is disposed between MTDRAM memory blocks 211 and 212, and TSV region 201 includes TSVs that transmit address, data, and control signals used in the operation of MTDRAM memory blocks 211-212. Similarly, TSV regions 202, 203, and 204 are disposed between MTDRAM memory block pairs 221-222, 231-232, and 241-242, respectively (these TSV regions include TSVs that transmit address, data, and control signals used in the operation of these memory blocks). While the described embodiment includes four TSV regions 201-204 and corresponding eight memory blocks, it should be understood that other embodiments may use a different number of TSV regions (and corresponding memory blocks).

[0041] Each of the MTDRAM memory blocks 211-212, 221-222, 231-232, and 241-242 includes 64 MTDRAM memory banks along the horizontal direction of FIG. 3 and 4 MTDRAM memory banks along the vertical direction of FIG. 2. In the described embodiment, each MTDRAM memory bank has a storage capacity of 16 Mb (e.g., a 4k by 4k MTDRAM bit cell array). In other embodiments, the MTDRAM memory blocks may include a different number of memory banks, and each memory bank may have a different storage capacity.

[0042] TSV regions 201-204 and MTDRAM memory blocks 211-212, 221-222, 231-232, and 241-242 are divided into 16 independently accessible 2 Gb MTDRAM sectors. The 2 Gb sector 300 shown in Figure 3 includes the following components: 64 (16 x 4) MTDRAM memory banks in MTDRAM memory block 211, 64 (16 x 4) MTDRAM memory banks in MTDRAM memory block 212, and a portion of TSV region 201 located between these memory banks, which portion of TSV region 201 is labeled "TSV section 300TSV" in Figure 3.

[0043] The MTDRAM chip 101 includes a total of sixteen 2 Gb MTDRAM sectors (each identical to sector 300). FIG. 4 is a top view of the MTDRAM chip 101 showing the locations of the sixteen 2 Gb MTDRAM sectors 300-315. The sixteen MTDRAM sectors 300-315 in the MTDRAM chip 101 operate independently (i.e., the sixteen MTDRAM sectors 300-315 do not communicate with each other in the MTDRAM chip 101). According to one embodiment, each of the sixteen MTDRAM sectors 300-315 is accessed by a corresponding processor located in the ASIC controller 110. In other embodiments, the capacity of the MTDRAM sectors may be other than 2 Gb, and the number of MTDRAM sectors present in the MTDRAM chip 101 may be greater than or less than sixteen.

[0044] FIG. 5 is a top view of the ASIC controller 110, showing the general layout of the processors 400-415 and the corresponding TSV section 400. TSV ~415 TSV In the illustrated embodiment, the processors 400-415 are connected to access the MTDRAM sectors 300-315, respectively, in the MTDRAM chip 101. More specifically, the TSV section 400 of the controller 110 TSV ~415 TSV The TSVs in the MTDRAM chip 101 are TSV sections 300 TSV ~315 TSV Each processor 400-415 is connected to a corresponding TSV in the MTDRAM chip 101. In the described embodiment, the number of processors 400-415 corresponds to the number of independent MTDRAM sectors 300-315, but it should be understood that other configurations are possible. For example, a single processor in the controller 110 may be configured to access multiple MTDRAM sectors 300-315 in parallel. Note that in this embodiment, multiple MTDRAM sectors in the chip 101 accessed by a single processor in the controller 110 continue to operate independently (i.e., these MTDRAM sectors do not communicate with each other in the MTDRAM chip 101). It should also be understood that each of the processors 400-415 may implement one or more multi-core processors. In other embodiments, multiple processors in the ASIC controller 110 are configured to independently access corresponding groups of memory banks (i.e., unit cells) in a single MTDRAM sector.

[0045] In the described embodiment, MTDRAM chips 102-104 are identical to MTDRAM chip 101. Thus, MTDRAM chips 102-104 are stacked on MTDRAM chip 101 (as shown in FIG. 1), and vertically aligned 2 Gb MTDRAM sectors in chips 101-104 are connected to corresponding processors in ASIC controller 110 via corresponding TSV regions.

[0046] 6A is a side view showing processor 400 connected to corresponding 2 Gb MTDRAM sectors in chips 101-104. In this embodiment, processor block 400 is connected to 2 Gb MTDRAM sectors 300 in MTDRAM chip 101 via bus B, which includes TSV section 400. TSV One-quarter of the TSVs in the TSV Similarly, processor 400 is independently connected to corresponding 2 Gb MTDRAM sectors 300', 300'', and 300''' in MTDRAM chips 102, 103, and 104 via buses B', B'', and B''', respectively. Each of these buses connects to TSV section 400 TSV and one-fourth of the TSVs in the MTDRAM chips 102, 103, and 104, respectively. TSV , 300´´ TSV , 300´´´ TSV 6A is advantageous in that it allows all stacked MTDRAM chips 101-104 to have the same TSV pattern (even if only one-quarter of the TSVs are used to access the MTDRAM memory in any MTDRAM chip). The bus configuration of FIG. 6A allows the TSV sections 300 to be separated in the manner shown. TSV , 300´ TSV , 300´´ TSV , and 300´´´ TSVThis is easily achieved by selectively connecting (or disconnecting) the TSVs in the MTDRAM chips 101-104. When using the configuration of FIG. 6A, each of the MTDRAM chips 101-104 includes a TSV selection circuit that selectively couples the appropriate quarter of the TSVs in the TSV section to access the MTDRAM memory within the chip. This TSV selection circuit may be controlled according to JTAG or other similar means. In one embodiment, the processor 400 controls the TSV selection circuits in the MTDRAM chips to perform this configuration based on the known interconnection pattern of the TSVs between the MTDRAM chips (i.e., the processor 400 specifies that the TSV selection circuits of the MTDRAM chips 101, 102, 103, and 104 select buses B, B', B'', and B''' respectively). In this manner, each of the four 2 Gb sectors 300, 300', 300'', and 300''' stacked in the MTDRAM chips 101-104 has a different and independent address and data bus.

[0047] FIG. 6B is a side view illustrating how processor 400 is connected to 2 Gb MTDRAM sectors corresponding to each of chips 101-104, according to another embodiment. In this embodiment, all MTDRAM chips 101-104 share the same address and data bus B. This requires a means of individually addressing each of the MTDRAM chips 101-104 (e.g., a 2-bit address may be used to select one of the four MTDRAM chips 101-104 for any given access). In one embodiment, the necessary identification values ​​are pre-loaded into each MTDRAM chip 101-104 and processor 400 via JTAG. In this embodiment, processor 400 can read (or write) data from only one MTDRAM chip sub-array at a time.

[0048] FIG. 6C is a side view illustrating a processor 400 connecting to 2 Gb MTDRAM sectors corresponding to each of the chips 101-104, according to another embodiment. In this embodiment, the stacks of four 2 Gb sectors in the MTDRAM chips 101-104 share a common address bus AB, but each has its own data bus including DB, DB', DB", and DB'". In this case, a means of individually addressing the MTDRAM chips 101-104 is required (e.g., using a 4-bit address for any access allows any combination of the four MTDRAM chips 101-104 to be selected). In this embodiment, data can be read (or written) in parallel from the same address in any combination of the MTDRAM chips 101-104. In one embodiment, the necessary identification values ​​are preloaded into each MTDRAM chip 101-104 and the processor 400 via JTAG. The above embodiment illustrates how the number of required TSVs (through silicon vias) can be adjusted by changing the operational capabilities of the MTDRAM system.

[0049] While MTDRAM sectors 300-315 in MTDRAM chip 101 are individually accessible, processors 400-415 in ASIC controller 110 are all interconnected. Conventional logic processes used to fabricate ASIC controller 110 typically include 10-15 metal layers, which may be used to interconnect processors 400-415. In one embodiment, these connections allow processors 400-415 to communicate with each other, allowing data retrieved from any MTDRAM sector in MTDRAM chips 101-104 to be shared among any processors in ASIC controller 110.

[0050] Returning again to the configuration of the MTDRAM chip 101, the 2 Gb MTDRAM sectors 300-315 are further subdivided into 16 independent unit cells. Each unit cell contains eight MTDRAM banks and the corresponding TSVs required to access these eight MTDRAM banks. Thus, the MTDRAM chip 101 has a total of 256 unit cells. Each of these unit cells can be independently accessed by a corresponding processor on the ASIC controller 110 using any of the TSV configurations shown in Figures 6A, 6B, and 6C.

[0051] FIG. 7 illustrates a top view of a set 500 of four unit cells 501-504 in a 2 Gb sector 300 (FIG. 3) according to one embodiment. The boundaries of the four unit cells 501-504 are indicated by dashed lines. Unit cells 501, 502, 503, and 504 include MTDRAM banks (MBs) 0-7, 10-17, 20-27, and 30-37, respectively. Each unit cell includes eight corresponding MTDRAM banks arranged in one column and eight rows, as shown. In the embodiment of FIG. 7, each unit cell includes eight banks, but it should be understood that in other embodiments, each unit cell may include a different number of banks (e.g., 2, 4, or 16 banks). Furthermore, while the banks of unit cells in FIG. 7 are arranged in one column and eight rows, it should be understood that in other embodiments, the unit cells may include a different number of rows and columns (e.g., 4 rows and 2 columns). A word line driver circuit (WL) typically extends vertically through each unit cell. Each MTDRAM bank includes a corresponding number of primary sense amplifier (PSA) circuits (not shown in FIG. 7). Each MTDRAM bank also shares a secondary sense amplifier circuit (commonly referred to as SSA) with its vertically adjacent MTDRAM bank. For example, vertically adjacent MTDRAM banks 10 and 11 in unit cell 502 share a secondary sense amplifier circuit SSA0. The mechanism by which data is transferred between the primary sense amplifier circuit and the secondary sense amplifier circuit SSA0 of MTDRAM banks 10 and 11 is described in detail below. Similarly, the primary sense amplifier circuits of vertically adjacent pairs of MTDRAM banks 12-13, 14-15, and 16-17 are configured to share corresponding secondary sense amplifier circuits SSA1, SSA2, and SSA3, respectively. Furthermore, each set of four vertically adjacent MTDRAM banks also shares a tertiary sense amplifier circuit (commonly referred to as TSA). More specifically, in the unit cell 502, the vertically adjacent MTDRAM banks 10 to 13 share the tertiary sense amplifier circuit TSA0, and the MTDRAM banks 14 to 17 share the tertiary sense amplifier circuit TSA1.Data is transferred between the secondary sense amplifier circuits SSA0-SSA1 and SSA2-SSA3 and the tertiary sense amplifier circuits TSA0 and TSA1, respectively.

[0052] Each of the unit cells 501 to 504 is a TSV region 300 TSV 7, unit cells 501, 502, 503, and 504 each include a set of TSVs 501, 502, 503, and 504, respectively. TSV , 502 TSV , 503 TSV , and 504 TSV Each unit cell is independently accessed through its corresponding set of TSVs. More specifically, each set of TSVs includes a TSV structure (shown as a circle in FIG. 7) for transmitting instructions (including addresses) from the processor 400 in the corresponding ASIC controller 110 to the corresponding unit cell, and a TSV structure for transmitting input / output signals (e.g., data) between the processor 400 and the corresponding unit cell. Each set of TSV structures may include voltages and control voltages supplied from the power management IC 150 to the corresponding unit cell. Furthermore, each set of TSVs also includes the TSV structures necessary for the corresponding processor 400 in the ASIC controller 110 to communicate with the corresponding unit cells in the stacked MTDRAM chips 102, 103, and 104 (as shown in FIGS. 6A-6C). Note that FIG. 7 is not drawn to scale, and that each set of TSVs 501 TSV , 502 TSV , 503 TSV , and 504 TSV It should be understood that includes many more TSVs than shown in FIG. 7. The number of TSV structures required for each unit cell can be calculated based on the description provided herein. It should be noted that the minimum pitch of the TSVs defines various elements in the layout of the MTDRAM chip. As TSV processes improve, a smaller minimum TSV pitch will advantageously improve area efficiency in the design of the MTDRAM chip 101.

[0053] In the embodiment shown in FIG. 7, unit cells 501-504 are physically divided into two halves, an upper half including memory banks 10-13, and a lower half including memory banks 14-17. Then, a set of TSVs (e.g., TSV set 502) is divided into two halves. TSV ) are located between the two halves. As a result, the set of TSVs corresponding to each unit cell are located in the common TSV area 201 of the MTDRAM chip 101.

[0054] Although only four unit cells 501 to 504 are shown in FIG. 7, it should be understood that these unit cells are replicated horizontally and vertically based on the configurations of FIGS. 3 and 4 to form the entire layout of the MTDRAM chip 101.

[0055] FIG. 8 illustrates a top view of an MTDRAM bank 11 (and a portion of an adjacent MTDRAM bank 10) within a unit cell 502, according to one embodiment. The main word line driver circuitry is generally designated MWD, and the sub-word line driver circuitry is generally designated SWD. The primary sense amplifier circuitry is generally designated PSA, and the primary sense amplifier circuits of the MTDRAM bank 11 are designated PSA0-PSA8. The Y-decoder driver circuitry associated with the primary sense amplifier circuits is generally designated Y-DEC, and the bit cell array is generally designated BC. Each bit cell array (BC) consists of 512 rows and 256 columns of MTDRAM bit cells, resulting in a 4096 x 4096 MTDRAM bit cell array (16 Mb) for the entire MTDRAM bank 11. In this embodiment, each unit cell has a capacity of 128 Mb (8 x 16 Mb).

[0056] Each MTDRAM bank is divided into multiple strips, and each strip includes 512 corresponding rows (and corresponding MWD circuits, SWD circuits, primary sense amplifiers, and Y-DEC driver circuits) in that MTDRAM bank. For example, MTDRAM bank 11 includes eight MTDRAM strips S0 to S7, each of which constitutes 512 consecutive rows in MTDRAM bank 11.

[0057] Each MTDRAM strip is further divided to include multiple MTDRAM subarrays. In the embodiment of Figure 8, each MTDRAM strip includes eight MTDRAM subarrays. For example, MTDRAM strip S0 includes MTDRAM subarrays A0-A7. As described in more detail below, each subarray includes a pair of horizontally adjacent bit cell (BC) arrays (forming a 512x512 bit cell subarray), sub-word line driver (SWD) circuits disposed between adjacent bit cell arrays, and primary sense amplifiers disposed vertically adjacent above and below the bit cell arrays.

[0058] Each MTDRAM bank includes 1024 main word lines (MWLs) and 4096 virtual sub-word lines (SWLs), with each main word line connected to four corresponding virtual sub-word lines. Thus, each MTDRAM strip includes 128 main word lines and 512 virtual sub-word lines. As described in more detail below, each virtual sub-word line is subdivided into eight independently addressable sub-word line segments, with each sub-word line segment located in a corresponding sub-array within the corresponding strip.

[0059] For example, each virtual sub-word line of MTDRAM strip S0 is divided into eight sub-word line segments, and these eight sub-word line segments are arranged in a corresponding one of the eight MTDRAM sub-arrays A0-A7 of strip S0. Because each sub-word line segment is independently controlled by a corresponding sub-word line driver, access to strip S0 can access data from any combination of MTDRAM sub-arrays A0-A7 of MTDRAM bank 11. As will be described in more detail below, this configuration advantageously increases the access flexibility of MTDRAM strip S0 and can also reduce power consumption when accessing MTDRAM bank 11.

[0060] Although the MTDRAM bank 11 is described based on a particular bank size (16 Mb), a particular bit cell array size (512 rows by 256 columns), a particular strip size (512 rows), a particular number of strips (8), a particular number of subarrays per strip (8), and a particular number of virtual sub-word lines per main word line (4), it should be understood that these parameters may be varied to implement an MTDRAM bank according to other embodiments of the present invention.

[0061] FIG. 9 is a circuit diagram illustrating the first main word line / signal MWL0 (and first main word line driver MWD0) of MTDRAM strip S0 and the four first virtual sub-word lines SWL0-SWL3 of strip S0 that are driven in response to the main word line signal MWL0. As previously mentioned, each virtual sub-word line SWL0-SWL3 includes eight sub-word line segments. These virtual sub-word lines SWL0-SWL3 are referred to as "virtual" because the eight sub-word line segments that make up each sub-word line are not contiguous (although each virtual sub-word line accesses a corresponding row of DRAM bit cells in strip S0). FIG. 9 illustrates the two first sub-word line segments of each virtual sub-word line SWL0-SWL3. More specifically, the sub-word line segment SWL of virtual sub-word line SWL0 0,0 and SWL 0,1, the sub-word line segment SWL of the virtual sub-word line SWL1 1,0 and SWL 1,1 , the sub-word line segment SWL of the virtual sub-word line SWL2 2,0 and SWL 2,1 , and the sub-word line segment SWL of the virtual sub-word line SWL3 3,0 and SWL 3,1 9. The pattern in FIG. 9 is repeated in the horizontal direction, and the remaining six sub-word line segments of each virtual sub-word line SWL0 to SWL3 (i.e., the sub-word line segment SWL 0,2 ~SWL 0,7 , SWL1 sub-word line segment SWL 1,2 ~SWL 1,7 , SWL2 sub-word line segments SWL 2,2 ~SWL 2,7 , SWL3 sub-word line segments SWL 3,2 ~SWL 3,7 ) of each virtual sub-word line. 0,0 , S.W.L. 1,0 , S.W.L. 2,0 and SWL 3,0 ) corresponds to the first subarray A0 of strip S0, and the second sub-word line segment (e.g., SWL 0,1 , S.W.L. 1,1 , S.W.L. 2,1 and SWL 3,1 ) corresponds to the second subarray A1 of strip S0.

[0062] Although FIG. 9 shows only the first main word line MWL0 and its corresponding four virtual sub-word lines SWL0-SWL3, this pattern is repeated vertically to form the remaining main word lines and virtual sub-word lines (i.e., main word lines MWL1-MWL3) of the MTDRAM strip S0. 127 and virtual sub-word lines SWL4 to SWL 511 ) is implemented.

[0063] 9, each sub-word line segment is connected to a corresponding sub-word line driver. More specifically, the sub-word line segment SWL 0,0 , S.W.L. 1,0 , S.W.L. 2,0 , and SWL 3,0 are the sub-word line drivers SWD 0,0 , S.W.D. 1,0 , S.W.D. 2,0 , and SWD 3,0 Similarly, the sub-word line segment SWL 0,1 , S.W.L. 1,1 , S.W.L. 2,1 , and SWL 3,1 are the sub-word line drivers SWD 0,1 , S.W.D. 1,1 , S.W.D. 2,1 , and SWD 3,1 These sub-word line drivers are controlled to drive the sub-word line segments in a manner described in more detail below.

[0064] Each sub-word line segment is connected to 512 corresponding DRAM bit cells, with 256 bit cells located to the left and right of the corresponding sub-word line driver. As shown in detail in Figure 9, the sub-word line segments SWL 0,0 , S.W.L. 1,0 , S.W.L. 2,0 and SWL 3,0 The leftmost bit cell of 0,0 Similarly, these sub-word line segments SWL 0,0 , S.W.L. 1,0 , S.W.L. 2,0 and SWL 3,0 The rightmost bit cell of the 0,5119, it is understood that each column of bit cells in MTDRAM strip S0 is connected to a corresponding bit line (there are a total of 4096 bit lines in strip S0), and each bit line in MTDRAM strip S0 is connected to a primary sense amplifier circuit. In one embodiment, bit cells in "even" numbered columns are connected to "even" numbered bit lines (e.g., bl 0,0 ), and these even-numbered bit lines are connected to a primary sense amplifier circuit PSA0 at the top of the MTDRAM strip S0. More specifically, the 2048 even-numbered bit lines of the MTDRAM strip S0 are each connected to one of the 2048 primary single-ended sense amplifiers in the primary sense amplifier circuit PSA0.

[0065] Similarly, bit cells in "odd" numbered columns connect to odd numbered bit lines (e.g., bl 0,511 ), and these odd-numbered bit lines are connected to a primary sense amplifier circuit PSA1 located at the bottom of the MTDRAM strip S0. More specifically, the 2048 odd-numbered bit lines of the MTDRAM strip S0 are each connected to one of the 2048 primary single-ended sense amplifiers in the primary sense amplifier circuit PSA1.

[0066] Primary sense amplifier circuit PSA other than the edge n (n is 1 to 7) is the adjacent MTDRAM strip S (n-1) and S nFor example, the primary sense amplifier circuit PSA1 is shared by adjacent MTDRAM strips S0 and S1, and the primary sense amplifier circuit PSA4 is shared by adjacent strips S3 and S4. As described above, when accessing MTDRAM strip S0, the odd-numbered bit lines of strip S0 are accessed using the 2048 sense amplifiers of the primary sense amplifier circuit PSA1. On the other hand, when accessing MTDRAM strip S1 in a different access, the odd-numbered bit lines of strip S1 are also accessed using the 2048 sense amplifiers of the primary sense amplifier circuit PSA1 (and the even-numbered bit lines of strip S1 are accessed using the 2048 sense amplifiers of the primary sense amplifier circuit PSA2).

[0067] This primary sense amplifier sharing configuration allows for an efficient layout of the required primary sense amplifier circuits and global I / O lines in the MTDRAM bank 11. The configuration and operation of the primary sense amplifier circuits is described in further detail below.

[0068] Each of the primary sense amplifier circuits PSA0-PSA8 of the MTDRAM bank 11 is connected to the secondary sense amplifier circuit SSA0, and data read from and written to the MTDRAM bank 11 is routed between the primary sense amplifier circuits PSA0-PSA8 and the secondary sense amplifier circuit SSA0. Similarly, each of the primary sense amplifier circuits of the adjacent MTDRAM bank 10 is also connected to the secondary sense amplifier circuit SSA0. Therefore, the MTDRAM banks 10 and 11 share the secondary sense amplifier circuit SSA0.

[0069] MTDRAM banks 12 and 13 of unit cell 502 have the same configuration as MTDRAM banks 10 and 11, with the primary sense amplifier circuits of MTDRAM banks 12 and 13 connected to secondary sense amplifier circuit SSA1 (i.e., MTDRAM banks 12 and 13 share secondary sense amplifier circuit SSA1). Secondary sense amplifier circuits SSA0 and SSA1 are connected to tertiary sense amplifier circuit TSA0. MTDRAM banks 14-17 have the same configuration as MTDRAM banks 10-14, with the primary sense amplifier circuits of MTDRAM banks 14 and 15 connected to secondary sense amplifier circuit SSA2, and the primary sense amplifier circuits of MTDRAM banks 16 and 17 connected to secondary sense amplifier circuit SSA3. Furthermore, as shown in FIG. 7, secondary sense amplifier circuits SSA2 and SSA3 are connected to tertiary sense amplifier circuit TSA1.

[0070] The DRAM bit cell shown in Figure 9 (e.g., DRAM bit cell bc 0,0In the example shown, the pass-gate transistor G0 of each DRAM bit cell is an n-channel transistor with its gate connected to one of the corresponding sub-word line segments. In one embodiment, this n-channel transistor G0 is fabricated using the modulation-doped semiconductor technology (MST) layers / techniques described in commonly owned U.S. Patents 10,109,342 and 10,107,854, which are incorporated herein by reference in their entireties. This MST technique allows the n-channel pass-gate transistor G0 to be effectively overdriven during write or refresh operations. To access a particular sub-word line segment, the sub-word line driver corresponding to that sub-word line segment is activated, applying a high read / write control voltage to the corresponding sub-word line segment (i.e., the pass-gate transistors of the bit cells connected to that segment). As will be described in more detail below, this sub-word line driver is activated in response to the following signals: A main word line address signal for identifying the main word line (MWL) to be accessed, a sub-word line segment address signal for identifying the sub-word line segment to be accessed, and a reset signal for the sub-word line segment. For example, the first sub-word line segment SWL of bank 11 0,0 When accessing the bank 11, a bank address signal specifying the bank 11, a main word line address signal specifying the main word line MWL0, and a sub-word line segment SWL 0,0 The access is performed in response to a sub-word line segment address signal specifying the sub-array A0 and a sub-word line segment reset signal associated with the sub-array A0 (details will be described later). 0,0 indicates the corresponding sub-word line segment SWL 0,0 is driven from a low voltage (e.g., -200 mV) to a high voltage (e.g., 1.8 V or higher), thereby driving the sub-word line segment SWL 0,0The 512 bit cells connected to the sub-word line segments are read and written via the primary sense amplifier circuits PSA0 and PSA1 and the corresponding bit lines. The Y-decoder circuit performs 8-to-1 multiplexing / demultiplexing between the primary and secondary sense amplifier circuits, and multiplexes the 512 bits of input / output data from the sub-word line segments onto the corresponding 64 global bit lines.

[0071] The ability to access individual sub-word line segments independently provides significant power savings within a memory bank. For example, if the other seven sub-word line segments (SWL0, SWL1, SWL2) belonging to virtual sub-word line SWL0 are accessed, 0,1 , S.W.L. 0,2 , S.W.L. 0,3 , S.W.L. 0,4 , S.W.L. 0,5 , S.W.L. 0,6 , S.W.L. 0,7 ) without activating the sub-word line segment SWL 0,0 The data values ​​can be read from the TSVs. Furthermore, the use of relatively short bit lines (i.e., the bit line length corresponds to 512 bit cell rows) and the relatively small size of the unit cells contribute to power reduction. This allows data transmission between the unit cells and the corresponding TSVs using relatively short I / O lines.

[0072] Addressing of the MTDRAM chips 101-104 will now be described in more detail. Each unit cell in the MTDRAM chip 101 is individually addressed using a corresponding set of TSVs (e.g., MTDRAM unit cell 502 is addressed using a corresponding set of TSVs 502 in FIG. 7). TSV Address and control signals (i.e., instructions) are sent from the processor 400 in the ASIC controller 110 to the set of TSVs 502. TSV104)。 In the described embodiment, these address and control signals are transmitted to the MTDRAM unit cell 502 in the MTDRAM chip 101 (and the corresponding MTDRAM unit cells on the MTDRAM chips 102, 103, and 104) in a pre-decoded state. This reduces or eliminates the need for decoder circuitry in the MTDRAM chips 101-104. Furthermore, the use of pre-decoded signals reduces the number of active signals transmitted from the processor 400 to the MTDRAM chips 101-104 (because the TSV structures have a relatively high capacitance), which provides the advantage of reduced power consumption. In other embodiments, these address and control signals are transmitted in an undecoded state, and these signals are decoded locally on the MTDRAM chips 101-104. In other embodiments, a combination of pre-decoded and undecoded signals may be transmitted from the ASIC controller 110 to the MTDRAM chips 101-104.

[0073] TSV Set 502 TSV A specific example will be used to explain how to access an MTDRAM unit cell 502 using the TSV set 502. In this example, it is assumed that the processor 400 sends information to the MTDRAM chip 101 in a pre-decoded format. All MTDRAM unit cells in the system 100 can be accessed simultaneously and in parallel in a similar manner, with each unit cell being accessed at a completely independent address location. TSV Some of the TSVs are used to transmit read / write (R / W) access commands from the processor 400 to the MTDRAM unit cells 502.

[0074] 10 illustrates an R / W access instruction 1000 used to access an MTDRAM unit cell 502 in one embodiment. In this embodiment, the set of TSVs 502 TSVcontains 64 TSVs and transmits 64-bit input / output (I / O) values ​​between the unit cell 502 and the processor 400.

[0075] The access command 1000 includes a 2-bit burst length value BURST[1:0] that indicates the burst length of the access. More specifically, the values ​​of BURST[1:0] "00," "01," "10," and "11" specify data values ​​with burst lengths of 1, 2, 4, and 8, respectively. The access command 1000 also includes a 1-bit read / write value (RW) that indicates whether the operation is a read or write operation.

[0076] The access instruction 1000 also includes an 8-bit bank address value BANK[7:0]. Each bit of this BANK[7:0] is used to individually select or deselect a corresponding bank among the eight MTDRAM banks 10 to 17 in the unit cell 502. For example, if the bank address value BANK[7:0] is "0000 0001," bank 10 is selected for access, and banks 11 to 17 are not selected. Similarly, if BANK[7:0] is "0000 0010," bank 11 is selected for access, and banks 10 and 12 to 17 are not selected.

[0077] The access instruction 1000 also includes a 24-bit decoded main word line address value MWL[23:0]. This MWL[23:0] is used to select one of the 1024 main word lines (MWL) in the selected bank for access. In one embodiment, the main word line (MWL) selection is performed using 1024 four-input NAND gates. The first input of each NAND gate receives one of the eight MWL bits MWL[23:16] (identifying one of the eight strips S0-S7), the second input receives one of the MWL[15:8] bits, the third input receives one of the MWL[7:4] bits, and the fourth input receives one of the MWL[3:0] bits. Only one bit from each of these bit groups is activated during an access (such an arrangement is well known to those skilled in the art). In other embodiments, other decoding techniques may be used to select the main word lines. If one of 1024 MWLs is simply selected, 10-bit addressing is sufficient when decoding is performed within the unit cell 502.

[0078] The access instruction 1000 includes a pre-decoded 4-bit sub-word line segment address value for individually addressing each of the eight sub-arrays in the selected bank. More specifically, the access instruction 1000 includes a SWS address value for specifying sub-word line segments in sub-arrays A0, A1, A2, A3, A4, A5, A6, and A7. A0 [3:0], SWS A1 [3:0], SWS A2 [3:0], SWS A3 [3:0], SWS A4 [3:0], SWS A5 [3:0], SWS A6 [3:0] and SWS A7Each subarray includes a 4-bit decoded sub-word line segment address value MWL[23:0]. More specifically, each 4-bit decoded sub-word line segment address value is used to select one of the four sub-word line segments associated with the selected main word line within the corresponding subarray. Only one of these 4 bits is activated in each access. For example, if the main word line address value MWL[23:0] selects the main word line MWL0 (see FIG. 9), then the sub-word line segment address value SWS for subarray A0 is A0 When [3:0] has a value of "0001", the corresponding sub-word line segment SWL 0,0 Similarly, the sub-word line segment address value SWS A1 When [3:0] has a value of "0100", in the subarray A1, the sub-word line segment SWL shown in FIG. 2,1 It should be noted that the sub-word line segment address is associated with the selected main word line, i.e., SWS A0 [0], SWS A0 [1], SWS A0 [2] and SWS A0 [3] is a sub-array A0 selects first, second, third and fourth sub-word line segments corresponding to the selected main word line in the row.

[0079] Therefore, as shown in FIG. 9, the sub-word line segment address bit SWS A0 [0], SWS A0 [1], SWS A0 [2] and SWS A0 [3] indicates the corresponding sub-word line driver circuit SWD 0,0 , S.W.D. 1,0 , S.W.D. 2,0 and SWD 3,0 Similarly, the sub-word line segment address bits SWS A1 [0], SWS A1 [1], SWSA1 [2] and SWS A1 [3] is the corresponding sub-word line driver circuit SWD 0,1 , S.W.D. 1,1 , S.W.D. 2,1 and SWD 3,1 This pattern is repeated for the remaining sub-word line driver circuits in unit cell 502.

[0080] The access instruction 1000 also includes a decoded 8-bit sub-word line segment reset value SRS[7:0], which is used to reset the sub-word line driver circuits in each of the sub-arrays A0-A7. More specifically, the sub-word line segment reset bits SRS[0], SRS[1], SRS[2], SRS[3], SRS[4], SRS[5], SRS[6], and SRS[7] are used to reset the sub-word line driver circuits in the sub-arrays A0, A1, A2, A3, A4, A5, A6, and A7, respectively. Thus, as shown in FIG. 9, the sub-word line segment reset bit SRS[0] resets the sub-word line driver circuit SWD in the sub-array A0. 0,0 , S.W.D. 1,0 , S.W.D. 2,0 and SWD 3,0 The sub-word line segment reset bit SRS[1] is supplied to the sub-word line driver circuit SWD in the sub-array A1. 0,1 , S.W.D. 1,1 , S.W.D. 2,1 and SWD 3,1 This pattern is repeated for the remaining sub-word line driver circuits in unit cell 502.

[0081] The access instruction 1000 also includes an 8-bit decoded Y-address value Y-DEC[7:0] that specifies the 8-to-1 decoding process used to couple the 512 primary sense amplifiers corresponding to each sub-word line segment being accessed to the 64 secondary sense amplifiers in the corresponding secondary sense amplifier circuit.

[0082] The addressing scheme described above allows the unit cells to be accessed flexibly. Below are some example access patterns:

[0083] Figure 11 is a block diagram illustrating an example read access using the addressing scheme of Figure 10. Referring to Figure 9, this access is performed using sub-word line segment SWL of sub-array A1 in strip S1 of memory bank 10. 1,1 (BANK[7:0]="0000 0001" specifies bank 10, RW="1" indicates a read operation, MWL[23:0] specifies the main word line MWL0 in strip S1 of bank 10, BURST[1:0]="00" indicates no burst operation, and SWS A1 [3:0]="0010" is the sub-word line segment SWL in sub-array A1 of bank 10 1,1 This access specifies the sub-word line segment SWL of the sub-array A1 in the strip S1 of the memory bank 10. 1,1 Data is read from the selected sub-word line segment SWL. 1,1 provides 512 bits of read data to the corresponding primary sense amplifier circuits PSA0 and PSA1 in memory bank 10. A Y address value (Y-DEC[7:0]) selects one 64-bit word from the 512 bits of read data. This 64-bit word is transferred from the primary sense amplifier circuits PSA0 and PSA1 to the corresponding secondary sense amplifier circuit SSA0 as shown. In the illustrated embodiment, the secondary sense amplifier circuit SSA0 includes 512 secondary sense amplifiers SS0 (i.e., 64 bits for each of the eight sub-word line segments of the corresponding memory banks 10-11) and an 8-to-1 multiplexer circuit MUX0. The 64-bit word stored in the secondary sense amplifier SS0 is transferred to the sub-word line segment address SWS as shown. A1The 64-bit word is routed to the tertiary sense amplifier circuit TSA0 via the 8-to-1 multiplexer circuit MUX0 according to the activated bits of TSV set 502 [3:0]. TSV The tertiary sense amplifier circuit SSA1 transmits the data to the ASIC controller 110 using a 64-bit TSV structure. Note that in this embodiment, the tertiary sense amplifier circuit TSA0 has a width of 64 bits, and data is routed from the multiplexer circuit MUX0 to the tertiary sense amplifier circuit TSA0 via 64 global input / output (GIO) lines. Note that the secondary sense amplifier circuit SSA1 also has the same configuration as the secondary sense amplifier circuit SSA0, and both SSA0 and SSA1 share the same 64 GIO lines.

[0084] It should also be noted that the secondary sense amplifier circuits SSA2 and SSA3 and the tertiary sense amplifier circuit TSA1 have the same configuration as the secondary sense amplifier circuits SSA0 and SSA1 and the tertiary sense amplifier circuit TSA0, respectively. The secondary sense amplifier circuits SSA2 and SSA3 share a second set of 64 GIO lines, which are used to send and receive data to and from the tertiary sense amplifier circuit TSA1. In one embodiment, the tertiary sense amplifier circuits TSA0 and TSA1 share the set of TSVs 502. TSV In another embodiment (described in more detail below), the tertiary sense amplifier circuits TSA0 and TSA1 share the same 64 TSV structure contained in the set of TSVs 502. TSV The pair of 64 TSV structures included in

[0085] 12 is a block diagram illustrating a series of six pre-specified read accesses (RW=1) to memory bank 12 (BANK[7:0]="0000 0100") of unit cell 502. More specifically, consecutive read accesses are performed to three different sub-word line segments SWS[0], SWS[4], and SWS[6] of memory bank 12 (SWS[7:0]="0101 0001") in the specified main word line and virtual sub-word line (specified by MWL[23:0] / SWL[3:0]), and each sub-word line segment is accessed with a burst length of 2 (BURST[1:0]="01").

[0086] In this access, the sub-word line segments SWL in the sub-arrays A0, A4, and A6 belonging to the strip S6 of the memory bank 12 are 0,0 , S.W.L. 0,4 and SWL 0,6 (BANK[7:0]="0000 0100" specifies bank 12, RW="1" specifies a read operation, MWL[23:0] specifies the main word line MWL0 in strip S6 of bank 12, BURST[1:0]="01" specifies a burst length of 2, and SWSA0[3:0]="0001" specifies the sub-word line segment SWL in sub-array A0 of bank 12.) 0,0 and SWSA4[3:0]="0001" specifies the sub-word line segment SWL 0,4 Specify SWS A6 [3:0]="0001" indicates the sub-word line segment SWL in the sub-array A6 of the bank 12. 0,6 (Specify the

[0087] In the illustrated example, the designated main word line and sub-word line segments are arranged in strip S6 of memory bank 12. The selected three sub-word line segments SWL 0,0 , S.W.L. 0,4 and SWL 0,6respectively supply 512 bits of read data to the corresponding primary sense amplifier circuits in the memory bank 12. The Y address value (e.g., Y-DEC[7:0]="0000 0001") is assigned to each sub-word line segment SWL 0,0 , S.W.L. 0,4 and SWL 0,6 First, one 64-bit word is selected from the three 64-bit words. These three 64-bit words are transferred from the primary sense amplifier circuit to the corresponding secondary sense amplifier circuit SSA1 as shown in the figure. The secondary sense amplifier circuit SSA1 includes 512 secondary sense amplifiers SS1 (i.e., 64 bits for each sub-word line segment of the corresponding memory banks 12 and 13) and an 8-to-1 multiplexer circuit MUX1.

[0088] The multiplexer circuit MUX1 is connected to the sub-word line segment SWL 0,0 The Y-address value is then incremented (e.g., Y-DEC[7:0]="0000 0010"), and the second 64-bit word of the burst operation is transferred from the sub-word line segment SWL0,0 to the secondary sense amplifier SS1. The multiplexer circuit MUX1 routes the second 64-bit word of the burst operation from the secondary sense amplifier SS1 to the tertiary sense amplifier TSA0.

[0089] Then, the Y-address value is reset (e.g., Y-DEC[7:0]="0000 0001") and the corresponding 64-bit word is assigned to the sub-word line segment SWL 0,4 The multiplexer circuit MUX1 routes the sub-word line segments SWL 0,4The Y-address value is then incremented (e.g., Y-DEC[7:0]="0000 0010") so that the fourth 64-bit word of the burst operation is routed to the tertiary sense amplifier TSA0. 0,4 The fourth 64-bit word of this burst operation is transferred from the secondary sense amplifier SS1 to the tertiary sense amplifier TSA0. The multiplexer circuit MUX1 routes the fourth 64-bit word of this burst operation from the secondary sense amplifier SS1 to the tertiary sense amplifier TSA0.

[0090] The Y-address value is reset again (e.g., Y-DEC[7:0]="0000 0001"), and the corresponding 64-bit word is sent to the sub-word line segment SWL 0,6 The multiplexer circuit MUX1 routes the sub-word line segment SWL 0,6 , is routed to the tertiary sense amplifier TSA0 as the fifth 64-bit word of the burst operation. The Y address value is then incremented (e.g., Y-DEC[7:0]="0000 0010"), and the sixth 64-bit word of the burst operation is routed to the sub-word line segment SWL 0,6 The sixth 64-bit word is transferred from the secondary sense amplifier SS1 to the tertiary sense amplifier TSA0. The multiplexer circuit MUX1 routes this sixth 64-bit word from the secondary sense amplifier SS1 to the tertiary sense amplifier TSA0.

[0091] Specific examples are shown in FIGS. 11 and 12, and it should be understood from these examples that this embodiment enables a variety of access patterns.

[0092] In one embodiment, the cycle time of the primary sense amplifier circuit is 32 nanoseconds, and the cycle time for accessing a unit cell is 4 nanoseconds. Therefore, once a strip within a memory bank is accessed, that strip is unavailable for other accesses for 32 nanoseconds. Furthermore, because each strip shares a primary sense amplifier with adjacent strips (above or below, if provided), these adjacent strips are also unavailable for access for 32 nanoseconds. For example, in the example of FIG. 11 , a read access to strip S1 of memory bank 10 makes strip S1 and adjacent strips S0 and S2 unavailable for access for 32 nanoseconds. This strip unavailability prevents fully random access to all addresses within unit cell 502. However, each new access address for a 64-bit data value can address any location within unit cell 502, excluding the strip accessed during the previous 32 nanoseconds and its adjacent strips. The unit cell 502 has a total of 64 strips (8 strips in each of the memory banks 10 to 17). Access to one strip may exclude access to up to two adjacent strips, so the next access address can be set to 61 of the 64 strips. This means that the random address availability rate is 95%, which is referred to as "nearly random" in this specification. When the unit cell 502 is accessed in an "nearly random" manner and data is transferred in the TSV at a speed of 2 GHz, the bandwidth of the "nearly random" address is 2×10 9 The "near-random" address bandwidth across the 256 unit cells of MTDRAM chip 101 is 2.048 × 10 12 On the other hand, the rate of completely random access to any strip of unit cells 502 is 32 nanoseconds, or 31.25 MHz, so the bandwidth of completely random addressing in 256 unit cells on MTDRAM chip 101 is 8×10 9The bandwidth of the completely random address across the 1024 unit cells of MTDRAM chips 101-104 is 3.2 × 10 10 All of these implementations achieve the same random access bandwidth as conventional DDR5 (approximately 1×10 7 This provides a significant improvement over the previous 1000 times per second (1000 times per second).

[0093] In light of the above discussion, different addressing schemes may be implemented to meet the particular requirements of memory system 100, taking into account the limitations imposed by the number of available TSVs.

[0094] The sub-word line driver circuit will now be described in more detail below. Figure 13 shows the sub-word line driver SWD of Figure 9 according to one embodiment. 0,0 All the sub-word line drivers in the MTDRAM chip 101 are sub-word line drivers SWD 0,0 It should be understood that the sub-word line driver SWD is the same as the sub-word line driver SWD. 0,0 includes PMOS transistors 1601-1602, NMOS transistors 1611-1612, and capacitor 1621 connected as shown. Capacitor 1622 represents a parasitic capacitance at node 1625.

[0095] The main word line decoder circuit 1610 decodes the selected signal of the main word line address MWL[23:0] (and the bank address signal BANK[1]) to determine whether the current access specifies the main word line MWL0 of bank 11. If the main word line address MWL[23:0] and the bank address signal BANK[1] specify the main word line MWL0 of bank 11, the main word line decoder circuit 1610 activates the corresponding main word line activation signal MWL[0].

[0096] As will be explained in more detail below, the sub-word line segments SWL 0,0 During access to the sub-word line driver SWD 0,0is the MWL[0] signal, the sub-word line segment address signal SWS A0 [0] and the sub-word line segment reset signal SRS[0], the sub-word line segment SWL 0,0 is activated to drive the to a high voltage (1.8 to 2.0 V).

[0097] FIG. 14 shows a sub-word line driver SWD in one embodiment. 0,0 1 is a waveform diagram showing the operation of the A In this case, the MWL[0] signal is deactivated to low (0V), and the sub-word line segment address signal SWS A0 [0] is maintained at a logic high voltage of 1.8V, and the sub-word line segment reset signal SRS[0] is maintained at a logic high voltage of 1V. Under this condition, the main word line driver MWD0 supplies a voltage of GND (0V) to the main word line MWL0. A0 The SRS[0] and SRS[0] signals turn on NMOS transistors 1611 and 1612, respectively, thereby connecting the sub-word line segment SWL 0,0 The voltage at this sub-word line segment SWL is reduced to -200 mV. 0,0 Note that a negative voltage applied to reduces charge leakage from the DRAM bitcells connected to it.

[0098] Time T B , the sub-word line segment reset signal SRS[0] is deactivated to a logic low state (GND), thereby turning off the NMOS transistor 1612 and resetting the sub-word line segment SWL 0,0 will no longer be actively pulled down to -200mV.

[0099] Time T C , the main word line driver MWD0 drives the voltage of the main word line MWL0 to a high voltage of 1.8V (in response to the MWL[0] signal being activated).

[0100] Time TD In the sub-word line segment address signal SWS A0 [0] is driven to a logic low state (-200 mV), which turns off NMOS transistor 1611 and turns on PMOS transistors 1601 and 1602. The turned-on PMOS transistor 1601 couples the main word line MWL0 to the sub-word line segment SWL 0,0 , which connects the sub-word line segment SWL 0,0 1625. Under this condition, a voltage of 1.8V is applied across capacitor 1621, causing capacitor 1621 to charge. PMOS transistor 1602, which is turned on, connects main word line MWL0 to parasitic capacitor 1622, thereby driving node 1625 toward 1.8V. Under this condition, parasitic capacitor 1622 charges.

[0101] Time T E , the capacitors 1621 and 1622 are fully charged, and the sub-word line segment SWL 0,0 After the voltage is fully raised to 1.8V, the sub-word line segment address signal SWS A0 [0] is raised from −200 mV to 1.8 V, which turns on NMOS transistor 1611 and turns off PMOS transistors 1601 and 1602. At time T F In this state, the main word line driver MWD0 drives the voltage of the main word line MWL0 to GND (0 V). 0,0 The voltage is maintained at 1.8V.

[0102] Time T G In the sub-word line segment address signal SWS A0 [0] is driven to a slightly higher voltage, a boost voltage of about 2.0 V. Under this condition, the capacitor 1621 drives the sub-word line segment SWL 0,0 The voltage of the sub-word line segment SWL is further boosted to a boost voltage of about 2.0 V. 0,0The pass gate transistor of a DRAM bit cell connected to 0,0 ~bc 0,511 pass gate transistor, G o ) to overdrive the corresponding bit line (e.g., bit line bl 0,0 When a high voltage (1.4V) is applied to the bit cell, the maximum bit cell voltage (Vbc 0,0 =1.4V) is the bit cell (e.g., bit cell bc 0,0 ) is written to the sub-word line segment address signal SWS in the above manner. A0 Note that [0] is not boosted. In this case, the maximum voltage of the bitcell only reaches 1.8V, which is the threshold voltage of the pass-gate transistor G0 (i.e., 1.8V - 0.6V = 1.2V), and does not reach a high voltage such as 2.0V - 0.6V = 1.4V. In this way, the maximum voltage in the bitcell is reduced, shortening the required refresh interval. Therefore, by using the pass-gate transistor G0 with MST technology, it is possible to reduce the IDD6 power consumption during standby by extending the refresh interval.

[0103] Time T H , the sub-word line segment reset signal SRS[0] is driven to a logic high state (1V), and the sub-word line segment address signal SWS A0 [0] is driven to 1.8 V. Under this condition, the sub-word line segment SWL 0,0 is pulled down to -200 mV via the NMOS transistors 1611 and 1612 that are turned on, in preparation for the next access.

[0104] In one embodiment, the sub-word line segment address signal SWS A0The sub-word line segment reset signal SRS[0] and the sub-word line segment reset signal SRS[0] are generated by the processor 400 in the ASIC controller 110 and are transmitted to the sub-word line drivers SWD through two corresponding TSV structures. 0,0 With this configuration, the sub-word line driver SWD 0,0 This is advantageous because it eliminates the need for a decoding circuit.

[0105] FIG. 15A shows the sub-word line segment address signal SWS in the processor 400 of the ASIC controller 110. A0 [0] (and the sub-word line segment address signal SWS supplied to the sub-array A0 as shown in FIGS. 9 and 16) A0 [1], SWS A0 [2], SWS A0 14 is a circuit diagram showing a circuit 1500 for generating the sub-word line segment reset signal SRS[0] at time T B and T H Since this is a simple signal that switches between 0V and 1V at 1500, the generation of this signal in processor 400 is not shown here. Circuit 1500 includes p-channel transistors 1501-1509, n-channel transistors 1511-1515, capacitor 1520, and inverter 1521 connected as shown.

[0106] FIG. 15B shows the sub-word line segment address signal SWS using circuit 1500. A0 15 is a waveform diagram 1550 showing the generation of [0]. A0 [1], SWS A0 [2] and SWS A0 It should be understood that [3] is generated in a similar manner.

[0107] Time T D Previously (see Figure 14), V PUP The signal is low (0V), which turns on p-channel transistor 1509, causing a voltage V PLUS is 1.8V.KICKN The signal is high (1V), and the output of inverter 1521 is 0V. Under this condition, capacitor 1520 is charged to 1.8V. Sub-word line control signals SWL[0], SWL[1], SWL[2], and SWL[3] are initially low (0V), which turns n-channel transistors 1511-1514 off and p-channel transistors 1501, 1503, 1505, and 1507 on. Also, the SWS signal is initially low (0V), which turns n-channel transistor 1515 off and p-channel transistors 1502, 1504, 1506, and 1508 on. Under these conditions, the 1.8V signal on node 1510 is transmitted to sub-word line decoder SWD via the corresponding TSV structures, as shown in FIG. 9. 0,0 , S.W.D. 1,0 , S.W.D. 2,0 and SWD 3,0 to SWL respectively. A0 [0], SWL A0 [1], S.W.L. A0 [2], S.W.L. A0 [3] is transmitted as a signal.

[0108] Time T D Just before time T, the SWS signal and the SWL[0] signal are driven high (1.8V), turning off p-channel transistors 1501, 1502, 1504, 1506, and 1508, and turning on n-channel transistors 1511 and 1515. D In the sub-word line segment address signal SWS A0 [0] is pulled down to -200 mV via the n-channel transistors 1511 and 1515 in the ON state. A0 [1], SWS A0 [2] and SWS A0 [3] is the time T D It remains at 1.8V even at

[0109] Time T EAt time T, the SWS signal and the SWL[0] signal are driven low (-200 mV), turning on p-channel transistors 1501, 1502, 1504, 1506, and 1508, and turning off n-channel transistors 1511 and 1515. E In the sub-word line segment address signal SWS A0 [0] is pulled up to 1.8V through p-channel transistors 1501 and 1502 which are on.

[0110] Time T G In V PUP The signal transitions to a logic high voltage (1.8V), which turns off p-channel transistor 1509. Then, V KICKN The signal transitions to a logic low voltage (0V), and the output of inverter 1521 provides a 1V signal to the lower plate of capacitor 1520. This reduces the capacitance of kick capacitor 1520 and the capacitance of sub-word line segment SWL 0,0 Based on the ratio of the capacitances of PLUS =2V) is driven at time T G At this boosted voltage V PLUS is transmitted through the p-channel transistors 1501 and 1502 in the ON state, and the boosted sub-word line segment address signal SWS A0 [0] (2.0V) is supplied.

[0111] Time T H Just before, V KICKN The signal transitions to a logic high voltage (1V), which causes inverter 1521 to drive a low voltage of 0V onto the bottom plate of capacitor 1520, increasing the voltage at node 1510 (V PLUS ) to a low voltage (V PLUS <2.0V). Then, V PUP The signal transitions to a logic low voltage (0V), turning on p-channel transistor 1509 and pulling the voltage at node 1510 down to 1.8V (V PLUS =1.8V). Time T H In the sub-word line segment address signal SWS A0The voltage at [0] is also V PLUS This causes the sub-word line segment address signal SWS A0 The generation of [0] is complete.

[0112] As shown in FIG. 15A, the circuit 1500 generates SWCs according to SWL[1], SWL[2], and SWL[3] and SWS. 1,0 , S.W.C. 2,0 , and SWC 3,0 On the other hand, as described above, the sub-word line segment address signal SWS A0 [0], SWS A0 [1], SWS A0 [2] and SWS A0 Only one of [3] is active at any given time.

[0113] FIG. 16 illustrates the use of SWS 11 to control the sub-wordline driver circuits of the portion of sub-array A0 associated with the first main wordline MWL0 and the second main wordline MWL1 of bank 11, in accordance with one embodiment of the present invention. A0 [0], SWS A0 [1], SWS A0 [2], SWS A0 1 is a block diagram showing how the SRS[3] signal and the SRS[0] signal are used. 0,0 , S.W.D. 1,0 , S.W.D. 2,0 and SWD 3,0 are the sub-word line segment address signals SWS A0 [0], SWS A0 [1], SWS A0 [2] and SWS A0 [3]. The sub-word line driver circuit SWD associated with the main word line MWL1. 4,0 , S.W.D. 5,0 , S.W.D. 6,0 and SWD 7,0 , and the sub-word line segment address signal SWS A0 [0], SWSA0 [1], SWS A0 [2] and SWS A0 [3]. This pattern is repeated for the remaining sub-word line drivers in sub-array A0. Each sub-word line driver in sub-array A0 is connected to receive sub-word line segment reset signal SRS[0].

[0114] Sub-word line segment address signal SWS A1 [0], SWS A1 [1], SWS A1 [2] and SWS A1 [3], and the sub-word line segment reset signal SRS[1] are similarly transmitted to the sub-word line driver circuits SWD in the portion of sub-array A1 associated with the first and second main word lines MWL0 and MWL1 of bank 11. 0,1 , S.W.D. 1,1 , S.W.D. 2,1 , S.W.D. 3,1 , S.W.D. 4,1 , S.W.D. 5,1 , S.W.D. 6,1 , S.W.D. 7,1 is used to control

[0115] Single-Ended Sense Amplifier Operation

[0116] The configuration of the primary sense amplifier and how the bit cells are accessed are described below. As will become apparent from the following description, the primary sense amplifier operates as a single-ended sense amplifier, i.e., each DRAM bit cell is accessed by sensing the voltage on a single corresponding bit line (as opposed to the prior art, which requires sensing the voltage difference on a pair of bit lines, one of which is a dummy line capacitively held to an equalization reference voltage of Vbit / 2).

[0117] FIG. 17 illustrates, in one embodiment, individual primary sense amplifiers SA0-SA associated with a first subarray A0 in a strip S0 of a memory bank 11. 511 and bit line bl0,1 ~bl 0,511 The primary sense amplifier circuit PSA0 is disposed adjacent to the upper end of the sub-array A0, and SA0 to SA 511 Similarly, the primary sense amplifier circuit PSA1 is disposed adjacent to the bottom end of the subarray A0, and the primary sense amplifiers SA0 to SA7 are arranged adjacent to the bottom end of the subarray A0. 511 , including the even-numbered primary sense amplifiers (e.g., SA0, SA2, SA4, SA6, etc.). 0,1 ~bl 0,511 odd numbered bit lines (e.g., bl 0,1 , bl 0,3 , bl 0,5 ) are connected to the corresponding odd-numbered primary sense amplifiers in PSA0, and the even-numbered bit lines (e.g., bl 0,0 , bl 0,2 , bl 0,4 ) are connected to the corresponding even-numbered primary sense amplifiers in PSA1.

[0118] The primary sense amplifier circuit PSA1 is shared with the first subarray in strip S1 of memory bank 11, which is connected to bit line bl as shown. 1,1 ~bl 1,511 Contains. 1,1 ~bl 1,511 The even numbered bit lines (e.g., bl 1,0 , bl 1,2 , bl 1,4 , bl 1,6 ) are connected to the corresponding even-numbered primary sense amplifiers in PSA1.

[0119] FIG. 17 also shows the first sub-word line segment SWL of the sub-array A0. 0,0 , and the corresponding sub-word line driver circuit SWD 0,0 (See FIG. 16) and the corresponding DRAM bit cell (bc). Specifically, FIG. 17 shows the bit line bl 0,0 and BL 0,2 Bit cells bc connected to 0,0and bc 0,2 17 shows the sense amplifiers SA0 and SA2 corresponding to the bit line bl in the first subarray of the strip S1. 1,0 and BL 1,2 , and two bit cells bc connected to sense amplifiers SA0 and SA2, respectively. 1,0 and bc 1,2 Also shown.

[0120] In the embodiment of FIG. 17, sense amplifiers SA0 to SA 511 are grouped in pairs (e.g., sense amplifiers SA0 and SA2 are grouped as sense amplifier pair 1700, and sense amplifiers SA4 and SA6 are grouped as sense amplifier pair 1701). Advantageously, the configuration of primary sense amplifiers PSA0 and PSA1 allows each sense amplifier pair to have a width corresponding to the pitch of four bit lines (e.g., the width of sense amplifier pair 1701 is 1 / 4 the pitch of bit lines bl 0,3 and BL 0,7 This configuration makes it easy to arrange single-ended sense amplifiers in the limited space in memory bank 11.

[0121] Here, the first sub-word line segment SWL of the strip S0 0,0 The operation of sense amplifiers SA0 and SA2 will now be described in relation to a read operation on the data line.

[0122] FIG. 18 is a circuit diagram of a primary sense amplifier pair 1700 in one embodiment. Primary sense amplifier pair 1700 includes sense amplifiers SA0 and SA2. Sense amplifier SA0 includes p-channel transistors P1 and P2 and n-channel transistors N1 and N2, which are configured as a cross-coupled inverter between the PCOM and NCOM terminals as shown. The gates of transistors P1 and N1 are commonly connected to an internal sense amplifier node INT0, and the gates of transistors P2 and N2 are commonly connected to an internal sense amplifier node INT0#. N-channel transistor N11 is connected between the internal sense amplifier node INT0 and ground. N-channel transistor N12 is connected between the internal sense amplifier node INT0# and ground. The gates of transistors N11 and N12 are connected to receive precharge control signals PRE0 and PRE1, respectively.

[0123] Sense amplifier SA2 includes p-channel transistors P3 and P4 and n-channel transistors N3, N4, N13, and N14, which are configured similarly to those described above for p-channel transistors P1-P2 and n-channel transistors N1-N2, N11-N12 in sense amplifier SA0. The gates of transistors P3 and N3 are commonly connected to an internal sense amplifier node INT2, and the gates of transistors P4 and N4 are commonly connected to an internal sense amplifier node INT2#. N-channel transistors N13 and N14 are connected between the internal sense amplifier nodes INT2 and INT2#, respectively, and ground. The gates of transistors N13 and N14 are connected to receive precharge control signals PRE0 and PRE1, respectively.

[0124] According to one embodiment, the transistors N1-N4 and P1-P4 that make up the cross-coupled inverters of sense amplifiers SA0 and SA2 are constructed using MST transistors, thereby advantageously minimizing the mismatch in threshold voltages of these transistors.

[0125] Primary sense amplifier pair 1700 also includes high voltage thick oxide NMOS transistors 1001-1004, PMOS transistors 1011-1014, bit line voltage kick capacitors 1021-1024, and n-channel output select transistors N20 and N22.

[0126] NMOS transistors 1001 and 1003 respectively connect the internal sense amplifier node INT0 to the bit line bl 0,0 and BL 1,0 NMOS transistors 1002 and 1004 are configured to connect / isolate the internal sense amplifier node INT2 to the bit line bl 0,2 and BL 1,2 The gates of NMOS isolation transistors 1001 and 1002 are connected to an isolation signal ISO corresponding to strip S0. S0 and the gates of NMOS isolation transistors 1003 and 1004 are connected to receive an isolation signal ISO corresponding to strip S1. S1 is connected to receive

[0127] PMOS transistors 1011 and 1012 respectively transmit the bit line refresh control signal BREC associated with strip S0. S0 and bit line bl 0,0 and BL 0,2 Similarly, PMOS transistors 1013 and 1014 are configured to connect / disconnect the bit line refresh control signal BREC associated with strip S1, respectively. S1 and bit line bl 1,0 and BL 1,2 The gates of the PMOS transistors 1011 and 1013 are connected to the internal sense amplifier node INT0#, and the gates of the PMOS transistors 1012 and 1014 are connected to the internal sense amplifier node INT2#.

[0128] The bit line voltage kick capacitors 1021, 1022, 1023 and 1024 are connected to the bit lines bl 0,0 , bl 1,0 , bl 1,0 and BL 1,2 Each of these kick capacitors 1021-1024 is further connected to receive a kick control signal Vk as shown.

[0129] Output select transistors N20 and N22 selectively connect internal sense amplifier nodes INT0 and INT2, respectively, to global bit line GBL0 in response to the decoded y-address values ​​Y-DEC[0] and Y-DEC[2].

[0130] FIG. 18 shows the bit line bl of the adjacent strip S1. 1,0 and BL 1,2 Also shown are the primary sense amplifier pair 1700. x,0 and bc x,2 (The corresponding sub-word line segment SWL X,0 ) are connected to the bit line bl 1,0 and BL 1,2 The strip S0 (for example, the sub-word line segment SWL 0,0 During a read access to the S1 becomes inactive (low), and the bit line bl of strip S1 1,0 and BL 1,2 (and bitcell bl 1,0 and BL 1,2 ) from the sense amplifiers SA0 and SA2.

[0131] In the example below, the bit cell bc 0,0 stores a logic "1" value (see Figure 19), and bit cell bc 0,2stores a logic "0" value (see FIG. 20). In this example, the pass gate transistors of the bit cell are fabricated using MST technology, and these pass gate transistors are designed to be overdriven (i.e., capable of boosting the voltage applied to the gate of the pass gate transistor), allowing a high bit cell voltage to be applied to the bit cell capacitor. In the following, the sub-word line segment SWL 0,0 19 and 20 show the read operation of the bit cell bc , focusing on the operation of the primary sense amplifier pair 1700. 0,0 and bc 0,2 10 is a waveform diagram showing a read access to a sub-word line segment SWL coupled to an even-numbered bit line. 0,0 The bit cell of is referred to as bit cell bc in the following. 0,0 and bc 0,2 It will be understood that the sub-word line segments SWL coupled to the odd-numbered bit lines are read out to the primary sense amplifier circuit PSA1 in a manner similar to that described for the odd-numbered bit lines. 0,0 It should also be understood that the bit cells of are similarly read into the primary sense amplifier circuit PSA0 in a manner similar to that described below.

[0132] Before time T1

[0133] Before time T1 (FIGS. 19 and 20), precharge signals PRE0 and PRE1 are activated high at 1V, turning on n-channel transistors N11-N14. Under these conditions, internal sense amplifier nodes INT0, INT0#, INT2, and INT2# are pulled to GND. Before time T1, the power supply voltages PCOM and NCOM for the sense amplifiers are also held at GND. Additionally, the p-well regions of n-channel transistors N1-N4 and N11-N14 are biased to 0V, and the n-well regions of p-channel transistors P1-P4 are biased to 1V.

[0134] BREC S0 and BREC S1The voltage of ISO is held at GND. In this state, the PMOS transistors 1011 to 1014 are turned off. S0 and ISO S1 The control voltage of the NMOS isolation transistors 1001 to 1004 is also held at GND, and in this state, the NMOS isolation transistors 1001 to 1004 are turned off. The transistors 1001 to 1004 in the off state connect the primary sense amplifiers SA0 and SA2 to the bit line bl 0,0 , bl 0,2 , bl 1,0 and BL 1,2 Electrically insulate from

[0135] Also, before time T1, the bit line bl 0,0 , bl 0,2 , bl 1,0 and BL 1,2 are precharged to GND. The kick control voltage Vk applied to the kick capacitors 1021-1024 is held at a positive voltage to produce a 40 mV swing on the bit line when Vk transitions to a logic low voltage (e.g., 0 V). The actual value of the kick control voltage Vk depends on the relative capacitance values ​​of the bit line and the kick capacitor.

[0136] Sub-word line segment SWL 0,0 and SWL X,0 is held at a negative supply voltage of -200 mV, which causes the bitcell bc 0,0 , bc 0,2 , bc X,0 and bc X,2 3. This configuration advantageously reduces leakage current while these bitcells are not being accessed.

[0137] In this example, the bit cell bc 0,0 The storage capacitor C0 is connected to the bitcell voltage V of approximately 1V. bc0,0 where the bitcell voltage V bc0,0Note that the initial program voltage is set to 1.4V, and this initial program voltage will decrease over time. In one embodiment, refresh is not required until the bitcell voltage drops to approximately 800mV. That is, as long as the bitcell voltage is 800mV or higher, the bitcell can be read successfully.

[0138] In this example, the bit cell bc 0,2 The storage capacitor of the bit cell voltage Vbc is approximately -200mV. 0,2 holds.

[0139] At time T1

[0140] At time T1, the precharge control voltage PRE0 is driven to GND, which turns off n-channel transistors N11 and N13, so that the internal sense amplifier nodes INT0 and INT2 are no longer actively pulled to GND through transistors N11 and N13.

[0141] At time T2

[0142] At time T2, the selected sub-word line segment SWL 0,0 is driven from -200 mV to 1.8 V Vddp power supply voltage. This allows the bitcell bc 0,0 and bc 0,2 The pass gate transistors of the bit cells are turned on, and the respective bit cell voltages V bc0,0 and V bc0,2 corresponds to the bit line bl 0,0 and BL 0,2 The selected word line segment SWL0,0 is connected to the corresponding 512 bit cells bc as shown in FIG. 0,0 ~bc 0,511 The unselected sub-word line SWL is connected to X,0 continues to be held at -200mV.

[0143] In this state, the bit cell bc0,0 The charge stored in the bit line bl 0,0 The bit line bl 0,0 The voltage of the bit cell bc rises from GND. 0,2 The charge stored in the bit line bl 0,2 Discharge the bit line bl 0,2 The voltage at is below GND.

[0144] At time T3

[0145] At time T3, bit cell bc 0,0 and bc 0,2 The corresponding bit lines are 0,0 and BL 0,2 After partially charging / discharging the bit line bl, the kick control voltage Vk transitions to GND (0V). 0,0 and BL 0,2 The voltages at the GND and GND terminals are reduced by approximately 40mV each, ensuring adequate read margin for bitcells holding a logic low voltage (-200mV).

[0146] At time T4

[0147] At time T4, ISO S0 The signal is driven high to 1V, which turns on NMOS transistors 1001 and 1002. Under this condition, the bit line bl 0,0 and BL 0,2 are connected to the corresponding primary sense amplifiers SA0 and SA2, respectively. S1 Since the signal is held at GND, the corresponding NMOS transistors 1003 and 1004 remain off, and the bit line bl X,1 and BL X,2 are electrically isolated from the primary sense amplifiers SA0 and SA2.

[0148] Bit line bl 0,0

[0149] Bit line bl 0,0The voltage at the INT0 node also rises in response to the voltage rise at the bit line bl 0,0 Since the capacitance is much smaller than that of the INT0 node and the bit line bl 0,0 The charge sharing between the INT0 node and the bit line bl0,0 only slightly reduces the positive signal that appears on the INT0 node and the bit line bl0,0. The voltage on the INT0 node must rise to a voltage sufficiently greater than GND (i.e., INT0#) so that the primary sense amplifier SA0 can accurately detect a high level under the full range of process, voltage, and temperature (PVT) operating conditions. In the illustrated example, the INT0 node and the bit line bl 0,0 By time T5, the voltage at the INT0 node is 41 mV due to charge sharing between the accessed bit cell bc0,0 and the accessed bit cell voltage V bc0,0 decreases to 41 mV by time T5. The voltage on INT0# remains pulled down to GND through n-channel transistor N12 until time T5.

[0150] Bit line bl 0,2

[0151] The voltage of the INT2 node is 0,2 The voltage at the INT2 node must drop to a voltage sufficiently lower than GND (i.e., INT2#) so that the primary sense amplifier SA2 can accurately detect a low level under all PVT and variations. In the example shown, INT2 and bl 0,2 The voltage at INT2# drops to −41 mV by time T5. The voltage at INT2# remains pulled down to GND through on-state n-channel transistor N14 until time T5.

[0152] At time T5

[0153] At time T5, ISO S0 The voltage is driven to GND, which turns off NMOS transistors 1001 and 1002, and the bit line bl 0,0 and BL 0,2are electrically isolated from the primary sense amplifiers SA0 and SA2. Additionally, the precharge control voltage PRE1 is driven to GND, turning off n-channel precharge transistors N12 and N14, which prevent these precharge transistors N12 and N14 from actively pulling the voltages of INT0# and INT2# down to GND.

[0154] Also, at time T5, the PCOM voltage is driven from GND to approximately 1V (or less to conserve power) and the NCOM voltage is driven from GND to -200mV to latch the primary sense amplifiers SA0 and SA2. Because the initial voltage levels of INT0# and INT2# are low (i.e., GND), the NCOM voltage must be driven below GND to ensure headroom for sensing by the cross-coupled n-channel transistors N1-N2 and N3-N4. Note that these cross-coupled elements have very low threshold voltages near 0V.

[0155] Primary Sense Amplifier SA0

[0156] In primary sense amplifier SA0, the relatively "high" voltage (41mV) on INT0 (relative to the NCOM voltage of 0 to -200mV) turns on n-channel transistor N1, which quickly pulls INT0# down from 0mV to -200mV.

[0157] As the voltage at INT0# decreases (from GND to -200mV) and the PCOM voltage simultaneously increases (from GND to 1V), p-channel transistor P2 turns on, thereby pulling the voltage at INT0 from 41mV up to the PCOM voltage of 1V by time T6.

[0158] Bit line bl 0,0 and the corresponding bit cell voltage Vbc 0,0 is the bit line bl 0,0 is electrically isolated from the primary sense amplifier SA0, it remains at about 41 mV from time T5 to time T6.

[0159] Primary Sense Amplifier SA2

[0160] In primary sense amplifier SA2, the relatively "low" voltage (-41mV) on INT2 (relative to the increasing PCOM voltage) turns on p-channel transistor P3, which pulls the voltage on INT2# from GND to 1V by time T5.

[0161] The voltage at INT2# rising (from GND to 1V) and the simultaneous falling of the NCOM voltage (from GND to -200mV) turn on n-channel transistor N4, which pulls the voltage at INT2 down from -41mV to -200mV by time T6.

[0162] The voltages of the bit lines bl0,2 and the corresponding bit cell voltages V bc0,2 is the bit line bl 0,2 remains at approximately -41 mV from time T5 to time T6 because it is electrically isolated from the primary sense amplifier SA2.

[0163] At time T6

[0164] At time T6, the ISOS0 signal is driven to 1V, which turns on NMOS transistors 1001 and 1002, connecting bit line bl 0,0 and BL 0,2 Under these conditions, the bit lines bl 0,0 The voltage of the bit line bl is raised from -41 mV to the INT0 voltage (1 V) of the sense amplifier SA0 through the NMOS transistor 1001. 0,2 The voltage at this point is pulled down from -41 mV to the INT2 voltage (-200 mV) of the sense amplifier SA2 via the NMOS transistor 1002. Note that when the INT0 voltage reaches 1 V or -200 mV, the Y-DEC[0] (or Y-DEC[2]) signal becomes active.

[0165] Also, at time T6 (or immediately thereafter), the BREC applied to the sources of the PMOS transistors 1011 and 1012 S0 The voltage is driven from 0V to 1.4V.

[0166] The sense amplifier SA0 applies a low voltage (INT0#=-200mV) to the gate of the PMOS transistor 1011, thereby turning it on. As a result, the bit line bl 0,0 and the corresponding bitcell voltage V bc0,0 is pulled up to the BRECS0 voltage of 1.4 V. At this point, the voltage at INT0 does not exceed 1.0 V due to the high threshold voltage of NMOS isolation transistor 1001.

[0167] The sense amplifier SA2 applies a high voltage (INT2#=1V) to the gate of the PMOS transistor 1012, thereby turning it off. As a result, the corresponding bit line bl 0,2 BREC S0 The voltage of 1.4V is not applied.

[0168] PMOS transistors 1011-1014 and NMOS transistors 1001-1004 allow primary sense amplifiers SA0 and SA2 to operate at higher performance (e.g., be able to charge the bit lines to higher voltages). Transistors P1-P4 and N1-N4 have low threshold voltages (thin gate oxides) and advantageously operate at levels below 1V.

[0169] At time T7

[0170] If the pass gate transistor of the bit cell is manufactured by MST technology, at time T7, the sub-word line driver SWD 0,0 is the selected sub-word line segment (SWL 0,0 ) to a voltage above 1.8V (e.g., 2V). This allows the bitcell bc 0,0 and bc 0,2Under this condition, the gate of the pass transistor of the bit cell bc 0,0 The bit cell voltage Vbc maintained by 0,0 is the bit line bl 0,0 The voltage applied to the S0 =1.4V). 0,0 The operation of has been described above in connection with FIGS.

[0171] If the pass gate transistors of the bit cell are not manufactured by MST technology, this operation is omitted. 0,0 ) remains at 1.8V and is not boosted. This results in a logic "1" being written back to the bitcell at a 200mV lower voltage, reducing the time to trigger a refresh operation (compared to implementing MST technology). However, the time to trigger a refresh operation is still significantly longer than in a conventional DRAM system using Vdd / 2 sensing.

[0172] At time T8

[0173] At time T8, the sub-word line driver SWD 0,0 is deactivated (from either a 1.8V or 2.0V state), and the sub-word line segment SWL 0,0 The voltage of the sub-word line segment SWL drops to about -200 mV by time T9. 0,0 The pass gate transistors of the bit cells connected to bl are turned off, isolating the bit cell voltage from the bit line voltage. At this point, the bit line bl 0,0 Bitcell bc connected to 0,0 is the bit cell voltage Vbc 0,0 is refreshed to 1.4V, and the bit line bl 0,2 Bitcell bc connected to 0,2 is the bitcell voltage V bc0,2 has been updated to -200mV.

[0174] At time T9

[0175] At time T9, BREC S0 The voltage is driven from 1.4V to GND, and the bit line bl 0,0 The PMOS transistor 1011 connected to the bit line bl is effectively turned off. 0,0 The upper voltage begins to drop towards the INT0 voltage (1V).

[0176] Time T 10 In

[0177] Time T 10 From this, the NCOM and PCOM voltages are driven to GND. As a result, the INT0# voltage rises from -200 mV to GND through the on-state of transistor N1. Furthermore, the INT0 voltage begins to drop from 1 V towards GND through the on-state of transistor P2. At this point, the INT0 node is connected to the bit line bl through NMOS transistor 1001. 0,0 is still connected to the bit line bl 0,0 The voltages on PCOM, NCOM, INT0, INT0# and bl also drop towards GND. 0,0 Each voltage of 11 All reach GND before

[0178] In the primary sense amplifier SA2, the INT2 voltage begins to rise from -200 mV to GND through the on-state transistor N4. Additionally, the INT2# voltage begins to fall from 1 V towards GND through the on-state transistor P3. At this point, the INT2 node is connected to the bit line bl through the NMOS transistor 1002. 0,2 is still connected to the bit line bl 0,2 The voltage of INT2, INT2# and bl also rises from -200mV towards GND. 0,2 All of the voltages reach GND before time T11.

[0179] Time T11 In

[0180] At time T11, ISO S0 The voltage is driven from 1V to GND, NMOS transistors 1001 and 1002 are turned off, and primary sense amplifiers SA0 and SA2 are connected to bit line bl 0,0 and BL 0,2 is separated from

[0181] Time T 12 In

[0182] Time T 12 At time T1, the precharge control voltages PRE0 and PRE1 are driven from GND to 1V, and sense amplifiers SA0 and SA2 are precharged (as described before time T1). At this time, INT0, INT0#, INT2, and INT2# are actively pulled to GND by transistors N11, N12, N13, and N14, respectively.

[0183] Also, at time T 12 At this time, the kick control voltage Vk also returns to a high level, and the capacitors 1021 to 1024 are ready to be charged in preparation for the next access.

[0184] As described above, the primary sense amplifiers SA0 and SA2 operate as single-ended sense amplifiers, and the corresponding bit cells bc 0,0 and bc 0,2 That is, each primary sense amplifier SA0 and SA2 accesses a corresponding single bit line bl 0,0 and BL 0,2 This configuration advantageously achieves high density bit cell arrays and reduced power requirements during access.

[0185] Furthermore, the vertically aligned configuration of sense amplifiers SA0 and SA2 shown in FIG. 18 advantageously allows sense amplifier SA0 / SA2 pairs to be formed at a 4 bit line pitch within MTDRAM bank 502, as shown in FIG. 17.

[0186] 21 is a circuit diagram illustrating a sense amplifier pair 2100 including primary sense amplifiers S0 and S2 according to another embodiment of the present invention. Sense amplifier pair 2100 is similar to sense amplifier pair 1700 (FIG. 18), and therefore like elements in FIG. 21 and FIG. 18 are given like reference numerals. According to the alternative embodiment of FIG. 21, DRAM bit cell bc 0,0 , bc 0,2 , bc X,0 and bc X,2 The bit cell pass gate transistors are fabricated using conventional process technology (i.e., not using MST technology). In this embodiment, when a DRAM bit cell is accessed, the gates of the bit cell pass gate transistors are not overdriven to 2V. Therefore, as shown in FIGS. 19 and 20 (time T7 to time T8), the sub-word line segment SWL 0,0 Therefore, there is no need for a sub-word line driver to supply a boost voltage to the sub-word line.

[0187] Furthermore, because the bit cell voltage representing a logic high state is reduced, PMOS transistors 1011-1014, which were used in sense amplifier pair 1700 to drive the bit line voltage to 1.4V, are not needed in sense amplifier pair 2100, thereby reducing the number of transistors required for sense amplifier pair 2100. In this embodiment, the high voltage on PCOM is raised to 1.1V, and the voltages on internal sense amplifier nodes INT0 and INT2 are used to drive the corresponding bit lines bl 0,0 and BL 0,2 The gates of NMOS isolation transistors 1001-1004 are driven with a high voltage of 1.8V, which causes the full voltage of internal sense amplifier nodes INT0 and INT2 to be applied to the corresponding bit lines bl 0,0 and BL 0,2 In this embodiment, the isolation transistors 1001 to 1004 are manufactured using a thick gate oxide film that can withstand this high gate voltage.

[0188] 22 and 23 show bit cells bc and0,0 and bc 0,2 1 shows a waveform diagram of a read access to the bit cell bc using the sense amplifier pair 2100. 0,0 holds the bit cell voltage at logic high, and bit cell bc 0,2 (The waveforms in Figures 22 and 23 are similar to those in Figures 17 and 18, so only the differences between these waveforms will be discussed here.)

[0189] As shown in FIGS. 22 and 23, the sub-word line voltage SWL 0,0 is not boosted between times T6 and T8. Additionally, the PCOM voltage rises to 1.1V and the internal sense amplifier nodes INT0 and INT2# are driven to 1.1V by time T6. Also, the high ISO S0 The voltage is raised to 1.8V. Therefore, at time T6, the ISO S0 When the voltage goes high, the entire 1.1V on the internal sense amplifier node INT0 is pulled high to the corresponding bit line bl 0,0 As a result, the bit line bl 0,0 and the corresponding bit cell voltage bc 0,0 is raised to 1.1V by time T8. Thus, in the embodiment of FIGS. 21-23, the high bitcell voltage bc 0,0 is reduced to 1.1 V (instead of 1.4 V in the embodiment of FIGS. 18 to 20).

[0190] As discussed above in connection with Figures 18 to 23, the GND voltage is effectively used as a reference voltage for read access by the single-ended sense amplifiers S0 and S2. 0,0 (or bit line bl 0,2 ) is compared with the GND voltage, and the bit cell bc 0,0 (or bitcell bc 0,2) to determine the logic "1" or logic "0" value stored in the DRAM. This eliminates the need to generate a separate reference voltage for this purpose, completely eliminating noise caused by the reference voltage (Vref). It also eliminates the need to rely on dummy bit lines to provide the reference voltage for read access, as required by conventional DDR5 DRAM.

[0191] The ability to perform a reliable read operation on a DRAM cell depends on the bitcell voltage (V CORE ), bit line precharge voltage (V BLP ), bit line capacitance (C B ) and bit cell capacitance (C S ) and the capacitive coupling between bit lines when adjacent bit lines read opposite data values.

[0192] Bitcell voltage V CORE A DRAM cell having a precharge voltage V BLP The change in bit line voltage (ΔV) caused by reading from the bit line set to B ) and bit cell capacitance (C S ) is C B / C S In a DRAM array where

[0193]

number

[0194] In conventional DRAM arrays (e.g., DDR5), a read operation is performed by precharging both the bit line to be read and the dummy bit line to a voltage equal to Vdd / 2. Thus, in a DRAM array with Vdd=1.1V (i.e., a logic high voltage initially written to the DRAM bit cell is 1.1V), the bit line is precharged to 0.55V (V BLP=0.55V). If the bitcell voltage is 1.0V (i.e., V CORE =1.0V), and the ratio of the bit line capacitance to the bit cell capacitance (C B / C S ) is 4, the ΔV across this DRAM array will be 90mV (i.e., (1.0-0.55) / (1+4)). Furthermore, assuming a worst-case bitline coupling (capacitive coupling due to surrounding bitlines having the opposite read voltage) of 20%, the voltage on the bitline being read will change by 20%, resulting in a ΔV across the DRAM bitcell of 72mV (i.e., 90mV x 0.8).

[0195] In addition, C B / C S Note that as the ratio increases (e.g., longer bitlines or smaller bitcell capacitance), ΔV decreases in an undesirable way. For example, in the conventional DRAM array described above, B / C S For a ratio of 9, the ΔV is 45mV (i.e., (1.0 - 0.55) / (1 + 9)). In the worst case, with 20% bitline coupling, the ΔV drops to 36mV (i.e., 45mV x 0.8). With such a small ΔV, it becomes difficult to reliably read the data. Note that in conventional DRAM arrays, this problem occurs symmetrically for both logic "0" and logic "1" reads.

[0196] For comparison, consider the single-ended sense amplifier described in the above embodiment. When the bit cell voltage is −200 mV (i.e., VCORE=−200 mV) at the end of the refresh period, the ratio of the bit line capacitance to the bit cell capacitance (C B / C S) is 4, the ΔV for this DRAM array will be -40mV (i.e., (-200mV-0) / (1+4)). Assuming a worst-case bitline-to-bitline coupling of 20%, the ΔV will be -32mV (i.e., -40mV x 0.8). Now, by capacitively reducing the bitline voltage by an additional 40mV, the ΔV becomes -72mV. In this example, the ΔV for the conventional DRAM array and the single-ended sense amplifier are the same.

[0197] To maintain symmetry, the ΔV at the high level of the bit line must be 72mV + 40mV + 8mV, or 120mV. Therefore, the bit cell voltage (V CORE ) should be 600mV or more (V CORE =120mV × (1 + 4)), which is the V required for a conventional DRAM bitcell. CORE Therefore, the refresh interval of the DRAM bit cell of the present invention is significantly lower than the V CORE The refresh interval is extended by the time it takes for the bitcell voltage to drop further from 1V to 600mV, which is the threshold voltage. This means that the refresh interval can be extended by 5 to 10 times, depending on the linearity of the bitcell leakage current. Note that if the high voltage written to the bitcell is 1.4V, as shown in Figures 18 and 19, the refresh interval will be extended even further.

[0198] In a single-ended sense amplifier embodiment of the present invention, at the end of the refresh period, the bitcell voltage is −200 mV (i.e., V CORE =-200mV), and C B / C SIf the ratio of C to C is 9, then the ΔV across this DRAM bit cell will be -20mV (i.e., (200mV-0) / (1+9)). Assuming a worst-case bit line coupling of 20%, the ΔV across this DRAM array will be -16mV (i.e., 20mV x 0.8). Now, if we capacitively kick down the bit line voltage by 30mV (instead of 40mV), then the ΔV will be -46mV. In this example, the ΔV (-46mV) of the single-ended sense amplifier will be B / C S This is better than the ΔV (36mV) of a conventional DRAM array with a ratio of 9.

[0199] To maintain symmetry, the ΔV relative to the high level of the bit line must be 46mV + 30mV + 4mV, or 80mV. Therefore, the bit cell voltage at the end of the refresh period (V CORE ) is 800mV(V CORE =80mV×(1+9)) or more. The refresh interval of the DRAM bit cell according to the present invention is V CORE The time it takes for the voltage to drop further from 1V to 800mV is extended, which means the refresh interval can be increased by about 5 times, depending on the linearity of the bitcell leakage characteristics.

[0200] In other embodiments, the logic low voltage written to the bit cells connected to the single-ended sense amplifier may be increased from −200 mV to −100 mV. B / C S If the ratio of is 4, the ΔV for this DRAM array will be -20mV (i.e., (-100mV-0) / (1+4)). Assuming a worst-case bitline coupling of 20% due to bitline coupling, the ΔV for this DRAM array will be -16mV (i.e., -20mV x 0.8). By further capacitively pulling the bitline voltage down by 30mV, the ΔV will be -46mV.

[0201] To maintain symmetry, the ΔV when the bit line is high must be 46mV + 30mV + 4mV, or 80mV. Therefore, the bit cell voltage at the end of the refresh period (V CORE ) must be greater than 400mV (V CORE =80mV×(1+4)). According to the present invention, the refresh interval of a DRAM bit cell is 100mV (V of a conventional DRAM bit cell). CORE The refresh interval is extended by the time it takes for the voltage to drop further from 1V to 400mV (which is the time it takes for the voltage to drop further). This means a significant extension of the refresh interval, depending on the linearity of the bitcell leakage characteristics.

[0202] In another embodiment, the logic low voltage written to the bit cell connected to the single-ended sense amplifier is −100 mV, and C B / C S If the ratio of C to C is 9, then the ΔV for this DRAM array will be -10mV (i.e., (-100mV-0) / (1+9)). Assuming a worst case bitline coupling of 20%, the ΔV for this DRAM array will be -8mV (i.e., -10mV x 0.8). By capacitively dropping the bitlines by 30mV, the ΔV for the DRAM bitcell (-38mV) in this example will be B / C S This is superior to the ΔV (36mV) of a conventional DRAM bit cell with a ratio of 9.

[0203] To maintain symmetry, the ΔV (voltage difference) relative to the high level of the bit line must be 38mV + 30mV + 2mV, or 70mV. Therefore, the bit cell voltage at the end of the refresh period (V CORE ) is 700mV or more (V CORE =70mV×(1+9)). In accordance with the present invention, the refresh interval of a DRAM bit cell must be 100mV (V COREThe refresh interval is extended by the time it takes for the voltage to drop further from 1V to 700mV (which is the linearity of the bitcell leakage characteristics). This means a significant extension of the refresh interval.

[0204] In view of the above example, the circuit designer must determine the logic low DRAM bit cell voltage, the capacitive kick-down voltage, and the C B / C S The ratio can be easily adjusted (eg, by controlling the bit line length and DRAM bit cell capacitance) to achieve the desired tradeoff between sensing margin and refresh interval.

[0205] FIG. 24 shows the sub-word line segment SWL 0,0 1 is a block diagram illustrating how data is routed from portions of the primary sense amplifier circuits PSA0 and PSA1 associated with a corresponding secondary sense amplifier circuit SSA0, according to one embodiment.

[0206] Each sub-word line segment can read and write data from and to its corresponding 512 bit cells. In the above example, the primary sense amplifier circuits PSA0 and PSA1 combine to form the sub-word line segment SWL 0,0 512 bit cells associated with bc 0,0 ~bc 0,511 and loads data into the corresponding primary sense amplifiers SA0-SA511. Each primary sense amplifier pair provides a one-bit data value to a corresponding global bit line. In the above example, any primary sense amplifier S0-S7 belonging to the primary sense amplifier pairs SA0 / SA2, SA1 / SA3, SA4 / SA6, and SA5 / SA7 may provide the read data value on the global bit line GBL0. More specifically, the primary sense amplifiers SA nA read data value stored in (n=0, 1, 2, 3, 4, 5, 6 or 7) is routed to global bit line GBL0 when the y column address signal Y-DEC[n] is "1" and all other y column address signals are "0".

[0207] The above circuit configuration is repeated for each of four successive primary sense amplifier pairs. 504 / SA 506 ), (SA 505 / SA 507 ), (SA 508 / SA 510 ), and (SA 509 / SA 511 ) is connected to the global bit line GBL as shown in the figure. 63 The primary sense amplifier SA (504+n) The read data value stored in the y-column address signal Y-DEC[n] (n=0, 1, 2, 3, 4, 5, 6 or 7) is transmitted to the global bit line GBL when the y-column address signal Y-DEC[n] is "1" and all other y-column address signals are "0". 63 is routed to

[0208] In this way, 64-bit data values ​​are transmitted from the primary sense amplifiers PSA0 to PSA1 to the global bit lines GBL0 to GBL 63 to the secondary sense amplifier SSA0 via . To perform a burst read operation, the y column address value is changed in successive cycles to read consecutive 64-bit data values ​​from the contents already present in the primary sense amplifier circuits PSA0-PSA1 (for example, four consecutive read accesses in a burst to the contents of the primary sense amplifier circuits PSA0-PSA1 can be achieved by changing the y column address value in the following order: "0000 0001", "0000 0010", "0000 0100", "0000 1000").

[0209] FIG. 24 shows a single sub-word line segment SWL 0,0Although the access circuitry for the corresponding strip S0 is shown, it should be understood that up to eight sub-word line segments of the corresponding strip S0 can be accessed in parallel (i.e., up to eight 64-bit words can be read in parallel from the corresponding strip S0). In this embodiment, the width of the secondary sense amplifier SSA0 is 512 bits.

[0210] In embodiments where only one 64-bit data value is read from a memory bank in any given read access (i.e., the embodiment of FIGS. 12-13), the output data values ​​from all eight sub-word line segments of strip S0 are transmitted across 64 global bit lines GBL0-GBL1. 63 , and the width of the secondary sense amplifier SSA0 is 64 bits.

[0211] In one embodiment, the secondary sense amplifier circuit receives data values ​​from the primary sense amplifier circuit (which has a signal swing of approximately 0.4V) and responsively provides output data values ​​with a signal swing of approximately 0.4V to the tertiary sense amplifier circuit, which then provides output signals with a signal swing of approximately 0.4V to the TSVs.

[0212] 25 is a block diagram of a unit cell 502, and schematically illustrates global bit line (GBL) paths from the primary sense amplifier circuits to the secondary sense amplifier circuits SSA0-SSA3, global I / O (GIO) path paths from the secondary sense amplifier circuits SSA0-SSA3 to the tertiary sense amplifier circuits TSA0-TSA1, and tertiary I / O (TIO) path paths from the tertiary sense amplifier circuits TSA0 and TSA1 to the TSV structures. In the embodiment shown in FIG. 25, the GBL, GIO, and TIO lines are all formed in the same metal layer of the MTDRAM chip 101, and the GIO lines run parallel to and between adjacent GBL lines.

[0213] In one embodiment, the cycle time of the primary sense amplifier circuit is 32 nanoseconds (i.e., a read access to a strip can be initiated every 32 nanoseconds). However, it should be understood that burst read accesses can also be performed, in which two, four, or eight data values ​​stored in the primary sense amplifier circuit are read consecutively from the unit cells during a read access without requiring a 32 nanosecond wait time. In one embodiment, such burst read data can be read from the memory bank at a frequency of 2 GHz.

[0214] In one embodiment, each MTDRAM bank has an access cycle time of 4 nanoseconds. That is, data can be read from an address within a particular MTDRAM bank every 4 nanoseconds, unless a prior access to the bank prevents access to that address. In an embodiment in which the primary sense amplifier circuit has a cycle time of 32 nanoseconds, once a read access is initiated to a strip within a particular unit cell, subsequent read accesses to the same strip (or adjacent strips) are inhibited for 32 nanoseconds.

[0215] While the present invention is described using a specific embodiment in which the unit cells operate with a 64-bit data word width, it should be understood that in other embodiments, some unit cells are designed to have a 64-bit data word width and other unit cells are designed to have one or more different data word widths. For example, other unit cells may be designed to have a 72-bit or 80-bit data word width. In these embodiments, the height (i.e., the number of rows) within each unit cell is fixed (e.g., 4096 rows in the above-described embodiment) to allow unit cells having different data word widths to be placed adjacent to each other.

[0216] Furthermore, while the present invention is described based on a configuration having MTDRAM chips 101-104 with a certain number of TSV regions (e.g., four TSV regions 201-204), memory banks with a specific number of MTDRAM strips (e.g., each memory bank 10-17 has eight corresponding MTDRAM strips S0-S7), and one input / output data channel per unit cell, it should be understood that the above-described MTDRAM chips may have different configurations in other embodiments.

[0217] For example, Figure 26 illustrates the layout of a 32 Gb MTDRAM chip 2750 according to another embodiment of the present invention. The MTDRAM chip 2750 includes sixteen independent 2 Gb sectors 2700-2715 arranged as shown. More specifically, the MTDRAM chip 2750 has two main TSV strips 2721 and 2722 and four 8 Gb MTDRAM memory blocks 2731-2734 extending horizontally across the MTDRAM chip 2750 as shown. The TSV strips 2721 and 2722 are arranged within the TSV regions 2700 that correspond to and service the MTDRAM sectors 2700-2715, respectively. TSV ~2715 TSV Each MTDRAM sector 2700-2715 has eight memory banks in the width direction and 16 memory banks in the depth direction (the memory bank configuration is as described above). Also, Figure 26 shows unit cell UC1 as an example, and the MTDRAM chip 2750 includes a total of 128 unit cells identical to UC1.

[0218] FIG. 27 is a block diagram of the unit cell UC1, which has 16 memory banks MB0 to MB 15 Each of these memory banks has the same configuration as the memory bank 11 described above with reference to FIGS. 7 and 8. Therefore, each of the memory banks MB0 to MB 158 and 9 in that each has eight MTDRAM strips, and each strip is composed of eight subarrays. The main word line decoder / driver is generally indicated as MWLD in FIG. 27, and the sub word line decoder / driver is generally indicated as SWLD. The unit cell UC1 has 16 memory banks MB0 to MB 15 7 and 8 include eight memory banks 10-17, each of which has four secondary sense amplifier circuits. Thus, unit cell UC1 includes secondary sense amplifier circuits SSC0-SSC3, each of which is configured to receive data from a primary sense amplifier circuit belonging to a corresponding set of four memory banks. More specifically, secondary sense amplifier circuits SSC0, SSC1, SSC2, and SSC3 receive data from memory banks MB0-MB3, MB4-MB7, MB8-MB9, and MB9-MB10, respectively. 11 and MB 12 ~MB 15 In each read operation, the primary sense amplifier circuit is connected to the memory bank MB0 to MB10, and is configured to receive data from the primary sense amplifier circuit. 15 18 to 24, in which a 64-bit data word is accessed from a corresponding 512-bit sub-word line segment located in one of the primary sense amplifier circuits PSA0 to PSA1. Such a read operation is as described above in relation to FIGS. 18 to 24, in which a 64-bit data word is accessed from 512 primary sense amplifiers belonging to the primary sense amplifier circuits PSA0 to PSA1 through 64 global bit lines GBL0 to GBL 63 The signals are transferred to the secondary sense amplifier circuit SSA0 via the secondary sense amplifier circuits SSC0, SSC1, SSC2, and SSC3. Since each memory bank has eight 512-bit sub-word line segments, each secondary sense amplifier circuit SSC0 to SSC3 includes a total of 512 (64 x 8) secondary sense amplifiers. More specifically, the secondary sense amplifier circuits SSC0, SSC1, SSC2, and SSC3 include secondary sense amplifier sets SS0, SS1, SS2, and SS3, respectively, and each of these secondary sense amplifier sets SS0 to SS3 is composed of 512 secondary sense amplifiers.

[0219] Each secondary sense amplifier circuit SSC0-SSC3 includes an 8-to-1 multiplexer circuit that routes one 64-bit data word from a corresponding set of secondary sense amplifiers SS0-SS3 to a corresponding tertiary sense amplifier circuit via 64 global input / output (GIO) lines. More specifically, secondary sense amplifier circuit SSC0 includes an 8-to-1 multiplexer circuit MUX0 that routes data from 64 of the 512 secondary sense amplifiers in secondary sense amplifier set SS0 to a first set of 64 GIO lines (e.g., GIO1[63:0]) that are connected to the 64 tertiary sense amplifiers that make up tertiary sense amplifier circuit TSC0. Secondary sense amplifier circuit SSC1 also includes an 8-to-1 multiplexer circuit MUX1 that routes data from 64 of the 512 secondary sense amplifiers in secondary sense amplifier set SS1 to a first set of 64 GIO lines (GIO1[63:0]) that are connected to the 64 tertiary sense amplifiers that make up tertiary sense amplifier circuit TSC0. Note that at any given time, only one of secondary sense amplifier circuits SSC0 or SSC1 provides a 64-bit data value to tertiary sense amplifier circuit TSC0.

[0220] In the lower half of unit cell UC1, secondary sense amplifier circuit SSC2 includes an 8-to-1 multiplexer circuit MUX2 that routes data from 64 of the 512 secondary sense amplifiers in secondary sense amplifier set SS2 to a second set of 64 GIO lines (e.g., GIO2[63:0]) that are connected to the 64 tertiary sense amplifiers that make up tertiary sense amplifier circuit TSC1. Secondary sense amplifier circuit SSC3 also includes an 8-to-1 multiplexer circuit MUX3 that routes data from 64 of the 512 secondary sense amplifiers in secondary sense amplifier set SS3 to a second set of 64 GIO lines (GIO2[63:0]) that are connected to the 64 tertiary sense amplifiers that make up tertiary sense amplifier circuit TSC1. Note that at any given time, only one of secondary sense amplifier circuits SSC2 and SSC3 provides a 64-bit data value to tertiary sense amplifier circuit TSC1.

[0221] As shown in FIG. 27, the unit cell UC1 includes a set of TSVs 2750 located in the center between the tertiary sense amplifier circuits TSC0 and TSC1. TSV Although omitted in FIG. 27 for clarity, in addition to the various control / address TSV structures described above, a TSV set 2750 TSV are 128 TSV structures TSV0 to TSV1 connected to both the tertiary sense amplifier circuits TSC0 and TSC1. 127 More specifically, each of the 64 bits of data stored in the tertiary sense amplifier circuits TSC0 and TSC1 is connected to two TSV structures. For example, the first data bit stored in each of the tertiary sense amplifier circuits TSC0 and TSC1 is connected to both TSV0 and TSV1, and similarly, the last data bit is connected to both TSV1 and TSV2 as shown in the figure. 125 and TSV 127 Even-numbered TSV structures (TSV0, TSV2, ..., TSV 126) defines the first 64-bit data channel (CH1), and the odd-numbered TSV structures (TSV1, TSV3, ..., TSV 127 ) define a second 64-bit data channel (CH2). In one embodiment, two accesses can be performed in parallel in unit cell UC1. In this embodiment, a first 64-bit data value is transferred between the first tertiary sense amplifier circuit TSC0 and either 64-bit data channel CH1 or CH2, while a second 64-bit data value is transferred between the second tertiary sense amplifier circuit TSC1 and the remaining channel CH1 or CH2. In one embodiment, the TSV structures TSV0-TSV1 that make up the 64-bit channels CH1 and CH2 127 are connected only to a corresponding processor (e.g., processor 400) on ASIC controller 110 (in the manner shown in FIG. 6A or 6C). In another embodiment, TSV structures TSV0-TSV127 constituting 64-bit channels CH1 and CH2 are connected to corresponding tertiary sense amplifier circuits on other stacked MTDRAM chips 102-104 in addition to a corresponding processor (e.g., processor 400) on ASIC controller 110 (in the manner shown in FIG. 6B).

[0222] FIG. 28 shows a configuration in which the TSV structures TSV0 and TSV1 included in the unit cell UC1 in the MTDRAM chip 101 are connected to the processor 400 in the ASIC controller 110, as well as the corresponding TSV structures included in the corresponding unit cells in the MTDRAM chips 102, 103, and 104, i.e., TSV 0´ and TSV 1´ , TSV 0´´ and TSV 1´´ , TSV 0´´´ and TSV 1´´´1 is a block diagram showing the connection between the TSV structures TSV0 and TSV1 and the tertiary sense amplifier circuit TSC0. The TSV structures TSV0 and TSV1 are connected to a first tertiary sense amplifier circuit TSC0 via switching transistors T0 and T1, respectively, and are also connected to a second tertiary sense amplifier circuit TSC1 via switching transistors T2 and T3. The transistors T0 and T1 selectively connect the tertiary sense amplifier TSC0 to TSV0 (channel CH1) and TSV1 (channel CH2), respectively. Similarly, the transistors T2 and T3 selectively connect the tertiary sense amplifier TSC1 to TSV0 (channel CH1) and TSV1 (channel CH2), respectively.

[0223] Similarly, transistor T 10 ~T 13 indicates the tertiary sense amplifier circuit TSC in the MTDRAM chip 102. 10 and TSC 11 TSV 0´ (Channel CH1) and TSV 1´ (channel CH2). Transistor T 20 ~T 23 indicates a tertiary sense amplifier circuit TSC on the MTDRAM chip 103. 20 and TSC 21 TSV 0´´ (Channel CH1) and TSV 1´´ (channel CH2). Transistor T 31 ~T 33 indicates a tertiary sense amplifier circuit TSC on the MTDRAM chip 104. 30 and TSC 31 TSV 0´´´ (Channel CH1) and TSV 1´´´ (channel CH2). The remaining TSV structures TSV2 to TSV 127 It should be understood that the TSV structures TSV0-TSV1 are also connected to corresponding TSV structures on the processor 400 and MTDRAM chips 102-104 in a manner similar to the TSV structures TSV0-TSV1.

[0224] The configuration of FIG. 28 includes tertiary sense amplifier circuits TSC0 to TSC1, TSC 10 ~TSC11 , T.S.C. 20 ~TSC 21 and TSC 30 ~TSC 31 Advantageously, this allows for a wide range of connections between the processor 400 and the tertiary sense amplifier circuits TSC0-TSC1, TSC2 in the first channel CH1. 10 ~TSC 11 , T.S.C. 20 ~TSC 21 and TSC 30 ~TSC 31 , while a second 64-bit data value can be simultaneously transmitted between the processor 400 and the tertiary sense amplifier circuits TSC0-TSC1, TSC2 in the second channel CH1. 10 ~TSC 11 , T.S.C. 20 ~TSC 21 and TSC 30 ~TSC 31 Similarly, the first 64-bit data value can be transmitted between any one of the tertiary sense amplifier circuits TSC0-TSC1, TSC 10 ~TSC 11 , T.S.C. 20 ~TSC 21 and TSC 30 ~TSC 31 while a second 64-bit data value is transmitted between any two of the tertiary sense amplifier circuits TSC0-TSC1, TSC2 in the second channel CH2. 10 ~TSC 11 , T.S.C. 20 ~TSC 21 and TSC 30 ~TSC 31 It is possible to transmit simultaneously between any two of the above.

[0225] FIG. 29 is a block diagram illustrating the highlighted region 3000 of FIG. 27 in accordance with one embodiment of the present invention. A first open region 3001 exists between adjacent main word line decoder / driver circuits (MWLDs). In one embodiment, the first open region 3001 includes a secondary sense amplifier control circuit 3010 (i.e., circuitry for enabling an addressed secondary sense amplifier SS1 in the secondary sense amplifier circuit SSC1 and circuitry for controlling the multiplexer circuit MUX1 in SSC1) and a plurality of TSV structures 3011. In one embodiment, the TSV structures 3011 are used to transmit main word line address signals used by the main word line decoder / driver to select / activate the main word lines. Advantageously, the placement of the secondary sense amplifier control circuit 3010 and the TSV structures 3011 as described above effectively utilizes layout area that might otherwise be wasted. Additionally, the placement of the TSV structures 3011 provides an additional benefit of providing a low-latency signal path to the main word line decoder / driver circuits.

[0226] The second open region 3002 is located between adjacent sub-word line decoder / driver circuits (SWLDs). In one embodiment, the second open region 3002 includes a secondary sense amplifier control repeater circuit 3020 (i.e., a circuit for relaying control signals provided from the secondary sense amplifier control circuit 3010) and a plurality of TSV structures 3021. In one embodiment, the TSV structures 3021 are used to transmit sub-word line address / control signals used by the sub-word line decoder / driver to select / activate the sub-word lines. Advantageously, the placement of the repeater circuit 3020 and the TSV structures 3021 as described above effectively utilizes otherwise wasted layout area. Furthermore, the location of the TSV structures 3021 advantageously provides a low-latency signal path to the sub-word line decoder / driver circuits. It should be understood that although TSV sets 3011 and 3021 are each illustrated with a specific number of TSV structures, the actual number of TSV structures included in TSV sets 3011 and 3021 is selected based on the operational requirements of unit cell UC1.

[0227] 30 shows a circuit diagram of secondary sense amplifier circuits SSC0 and SSC1, including secondary sense amplifiers SS0 and SS1, multiplexer circuits MUX0 and MUX1, global I / O lines GIO[0:63], and tertiary sense amplifier circuit TSC0, according to one embodiment of the present invention. 00 ~SW 07 are controlled to selectively couple up to one 64-bit data value stored in the secondary sense amplifier SS0 to the global I / O lines GIO[0:63] as shown in the figure. Similarly, eight 64-bit switches SW 10 ~SW 17 are controlled to selectively couple up to one 64-bit data value stored in the secondary sense amplifier SS1 to the global I / O lines GIO[0:63] as shown. At any given time, only sixteen of these 64-bit switches (SW00 ~SW 07 and SW 10 ~SW 17 ) is one (or zero) of the switches SW 00 ~SW 07 and SW 10 ~SW 17 is controlled according to the bank address and the sub-word line segment address. 00 is enabled when the first sub-word line segment in any of the memory banks MB0 to MB3 of the unit cell UC1 is accessed, and the switch SW 17 becomes valid when accessing the last sub-word line segment in any of the memory banks MB4 to MB7.

[0228] In the illustrated embodiment, multiplexer circuits MUX0 and MUX1 each include a corresponding set of 64 parallel wires, shown as 3110 and 3111 in FIG. 30. Each of the 64 parallel wires in set 3110 (and each of the 64 parallel wires in set 3111) is connected to a corresponding one of the 64 global I / O lines GIO[0:63], and thereby to a corresponding tertiary sense amplifier in 64-bit tertiary sense amplifier circuit TSC0. These connections are indicated by solid black circles in FIG. 30. Additionally, 64-bit switch SW 00 ~SW 07 Each of the 64 switches SW couples a corresponding set of 64 amplifiers of the secondary sense amplifiers SS0 to 64 parallel wires of the set 3110. Similarly, the 64-bit switch SW 10 ~SW 17 Each switch in couples a corresponding set of 64 amplifiers of secondary sense amplifiers SS1 to 64 parallel wires of set of wires 3111.

[0229] It should be understood that the secondary sense amplifier circuits SSC2 and SSC3 (including the secondary sense amplifiers SS2 and SS3 and the multiplexer circuits MUX2 and MUX3), and the tertiary sense amplifier circuit TSC1 (together with a corresponding set of 64 global I / O lines) are also configured similarly to the configuration shown in FIG.

[0230] The above-described configuration of MUX0 and MUX1 has the advantageous effect of reducing the number of global I / O lines (64 lines) that need to be formed on the unit cell UC1.

[0231] While the present invention has been described in connection with several embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications apparent to those skilled in the art. Accordingly, the present invention is limited only by the scope of the following claims.

Claims

1. 1. A dynamic random access memory (DRAM) system comprising: a first array of DRAM cells arranged in a plurality of rows and columns, the columns connected to corresponding bit lines; a plurality of single-ended sense amplifiers each connected to a corresponding bit line of the first array of DRAM cells; Each single-ended sense amplifier is a kick capacitor connected to the corresponding bit line; a latch circuit having a first internal node for storing a data value; an isolation transistor connecting the corresponding bit line to the first internal node of the latch circuit; A DRAM system wherein the corresponding bit line is the only bit line connected to the latch circuit of the first array of DRAM cells.

2. The latch circuit a first p-channel transistor having a source connected to a first control node, a gate connected to the first internal node, and a drain connected to a second internal node; a first n-channel transistor having a source connected to a second control node, a gate connected to the first internal node, and a drain connected to the second internal node; a second p-channel transistor having a source connected to the first control node, a gate connected to the second internal node, and a drain connected to the first internal node; a second n-channel transistor having a source connected to said second control node, a gate connected to said second internal node, and a drain connected to said first internal node.

3. a first precharge transistor (N11) selectively coupling the first internal node to a ground voltage source; 3. The DRAM system of claim 2, further comprising: a second precharge transistor (N12) selectively coupling said second internal node to said ground voltage source.

4. means for varying the voltage applied to the first control node (PCOM) between ground potential and a positive power supply voltage; 3. The DRAM system of claim 2, further comprising: means for varying a voltage applied to said second control node (NCOM) between a ground potential and a negative power supply voltage.

5. 3. The DRAM system of claim 2, wherein each single-ended sense amplifier further includes a p-channel transistor having a gate connected to the second internal node, a drain coupled to the corresponding bit line, and a source coupled to receive a bit line refresh control signal.

6. 2. The DRAM system of claim 1, further comprising: means for varying a voltage applied to said kick capacitor during a read access.

7. 1. A method of operating a dynamic random access memory (DRAM) system, comprising: precharging the bit lines connected to the DRAM cells to ground potential; precharging a first internal node and a second internal node of the sense amplifier latch to a ground potential; driving a first power supply voltage terminal and a second power supply voltage terminal of the sense amplifier latch to a ground potential; activating a word line connected to a DRAM cell to generate a read voltage on the bit line of the DRAM cell; activating a kick capacitor to drop the read voltage developed on the bit line; connecting the bit line to a first internal node of the sense amplifier latch for applying the read voltage generated on the bit line to the first internal node of the sense amplifier latch; isolating the bit line from the first internal node of the sense amplifier latch; driving the first power supply voltage terminal of the sense amplifier latch to a first power supply voltage higher than ground potential and driving the second power supply voltage terminal of the sense amplifier latch to a second power supply voltage; connecting the bit line to the first internal node of the sense amplifier latch.

8. 8. The method of claim 7, wherein activating the word line comprises first applying a positive voltage to the word line and then boosting the positive voltage.

9. 1. A dynamic random access memory (DRAM) system comprising: a first integrated circuit chip including a plurality of processors; a second integrated circuit chip having a first plurality of independent DRAM arrays, each of the first plurality of independent DRAM arrays connected to a corresponding one of the plurality of processors on the first integrated circuit chip; a refresh control circuit disposed on the first integrated circuit chip and configured to initiate refresh operations for the first plurality of DRAM arrays on the second integrated circuit chip.

10. 10. The DRAM system of claim 9, wherein said first integrated circuit chip comprises an interconnect structure connecting each of said plurality of processors to one another.

11. 10. The DRAM system of claim 9, further comprising a plurality of through silicon via (TSV) structures connecting the first integrated circuit chip and the second integrated circuit chip to one another.

12. 10. The DRAM system of claim 9, further comprising a third integrated circuit chip including a plurality of DRAM arrays, each of the plurality of DRAM arrays of the third integrated circuit chip connected to a corresponding one of the plurality of processors in the first integrated circuit chip.

13. a first set of through-silicon-via (TSV) structures connecting the first integrated circuit chip and the second integrated circuit chip to one another; a second set of TSV structures connecting the first integrated circuit chip and the third integrated circuit chip to each other; 13. The DRAM system of claim 12, wherein the second set of TSV structures extends through the first integrated circuit chip.

14. further comprising a power management integrated circuit coupled to the first integrated circuit chip and the second integrated circuit chip; 10. The DRAM system of claim 9, wherein the power management integrated circuit supplies a first plurality of power supply voltages to the first integrated circuit chip and the second integrated circuit chip, and a second plurality of power supply voltages to only the second integrated circuit chip.

15. 1. A dynamic random access memory (DRAM) system including a first integrated circuit chip, The first integrated circuit chip comprises: a plurality of DRAM blocks each including a plurality of DRAM banks and extending in parallel along the width direction of the first integrated circuit chip; a plurality of through-silicon-via (TSV) regions, each of which comprises a plurality of TSV interconnect structures and each of which extends in parallel across the width of the integrated circuit chip; A DRAM system, wherein each TSV region is disposed between a corresponding pair of the plurality of DRAM blocks and is connected to the corresponding pair.

16. 16. The DRAM system of claim 15, wherein the plurality of DRAM blocks and the plurality of TSV regions are configured to form a plurality of independent DRAM sectors, each DRAM sector including a set of the plurality of DRAM banks and a set of the plurality of TSV interconnect structures.

17. further comprising a second integrated circuit chip including a plurality of processors; 17. The DRAM system of claim 16, wherein each processor is connected to a corresponding independent DRAM sector via a set of the plurality of TSV interconnect structures included in the corresponding independent DRAM sector.

18. 20. The DRAM system of claim 17, wherein said second integrated circuit chip includes an interconnect structure connecting all of said plurality of processors to one another.

19. 1. A dynamic random access memory (DRAM) system comprising: a first integrated circuit chip including a plurality of processors; a second integrated circuit chip having a first plurality of independent DRAM sectors, each of the first plurality of independent DRAM sectors connected to a corresponding processor in the first integrated circuit chip via a first plurality of through silicon via (TSV) interconnect structures; a third integrated circuit chip including a second plurality of independent DRAM sectors, each of the second plurality of independent DRAM sectors connected to a corresponding processor in the first integrated circuit chip via a second plurality of TSV interconnect structures extending through the first integrated circuit chip.

20. 1. A dynamic random access memory (DRAM) system comprising: a first integrated circuit chip including a plurality of processors; a plurality of DRAM integrated circuit chips each containing a plurality of independent DRAM sectors; a set of a plurality of through-silicon-via (TSV) interconnect structures configured to connect corresponding processors in the first integrated circuit chip to corresponding DRAM sectors in each of the plurality of DRAM integrated circuit chips.

21. A dynamic random access memory (DRAM) unit cell disposed on an integrated circuit chip, comprising: a plurality of through-silicon vias (TSVs) extending through the integrated circuit chip; a first plurality of DRAM banks arranged along a first axis; a second plurality of DRAM banks arranged along the first axis; the plurality of TSVs are disposed along the first axis between the first plurality of DRAM banks and the second plurality of DRAM banks; the plurality of TSVs are configured to transmit address and control signals for accessing the first plurality of DRAM banks and the second plurality of DRAM banks, and then transmit read data and write data for the first plurality of DRAM banks and the second plurality of DRAM banks.

22. Each of the first plurality of DRAM banks and the second plurality of DRAM banks includes a plurality of strips, the plurality of strips comprising: a plurality of corresponding rows of DRAM bit cells in the DRAM bank; a first primary sense amplifier circuit disposed adjacent a first row of the plurality of corresponding DRAM bit cell rows and connected to a first subset of the DRAM bit cells; a second primary sense amplifier circuit disposed adjacent a last row of the plurality of corresponding DRAM bit cell rows and connected to a second subset of the DRAM bit cells.

23. 1. A dynamic random access memory (DRAM) unit cell comprising: a first memory bank; a second memory bank; and a secondary sense amplifier circuit disposed between the first memory bank and the second memory bank; the first memory bank includes a plurality of rows and columns of DRAM cells; a plurality of N+1 primary sense amplifier circuits; the plurality of rows of the first memory bank are divided into N DRAM strips, where N is an integer greater than 1, and the N DRAM strips of the first memory bank each include a plurality of contiguous rows of the DRAM cells of each DRAM strip of the first memory bank; In the plurality of N+1 primary sense amplifier circuits, each of the N DRAM strips of the first memory bank is connected to a corresponding pair of the primary sense amplifier circuits of the first memory bank; the second memory bank includes a plurality of rows and columns of DRAM cells; a plurality of N+1 primary sense amplifier circuits of the second memory bank; the plurality of rows of the second memory bank are divided into N DRAM strips, each of the N DRAM strips of the second memory bank including a plurality of consecutive rows of the DRAM cells of each DRAM strip of the second memory bank; In the plurality of N+1 primary sense amplifier circuits of the second memory bank, each of the N DRAM strips of the second memory bank is connected to a corresponding pair of the primary sense amplifier circuits of the second memory bank; The secondary sense amplifier circuit is connected to each of the primary sense amplifier circuits of the first memory bank and the second memory bank.

24. a first half of a column of the DRAM cells in one of the N DRAM strips of the first memory bank is connected to a first primary sense amplifier circuit of the first memory bank; 24. The DRAM unit cell of claim 23, wherein a second half of the column of DRAM cells in one of the N DRAM strips of the first memory bank is connected to a second primary sense amplifier circuit of the first memory bank.

25. Each of the N DRAM strips of the first memory bank a plurality of main word lines; a plurality of virtual sub-word lines; 24. The DRAM unit cell of claim 23, wherein each main word line is connected to a corresponding one of said plurality of virtual sub-word lines, and each virtual sub-word line is connected to a row of said DRAM cells in said first memory bank.

26. each virtual sub-word line includes a plurality of independent sub-word line segments; 26. The DRAM unit cell of claim 25, wherein each sub-word line segment is connected to a plurality of consecutive DRAM cells in the row of DRAM cells of the first memory bank.

27. further comprising a plurality of sub-word line drivers; 27. The DRAM unit cell of claim 26, wherein each sub-word line driver is connected to a corresponding one of the sub-word line segments.

28. 28. The DRAM unit cell of claim 27, wherein each sub-word line driver is connected to receive a main word line signal transmitted from a corresponding one of the plurality of main word lines, and a sub-word line segment select signal for selecting the sub-word line segment connected to the sub-word line driver.

29. further comprising instructions specifying access to the first memory bank of the DRAM unit cells, the instructions comprising: a bank address for selecting the first memory bank; a main word line address for selecting one of the plurality of main word lines of the first memory bank; and a sub-word line address for selecting one of said sub-word line segments of a plurality of virtual sub-word lines connected to a selected one of said plurality of main word lines.

30. The instruction: a column select address for selecting a word in the selected sub-word line segment; a burst value indicating the burst length of the access; 30. The DRAM unit cell of claim 29 further comprising: a read / write value indicating whether the access is a read access or a write access.

31. 1. A dynamic random access memory (DRAM) system comprising: a first set of DRAM cells arranged in a plurality of rows and four columns, each of the four columns of DRAM cells in the first set connected to a corresponding bit line of a first group of four bit lines; a second set of DRAM cells arranged in a plurality of rows and four columns, each of the four columns of DRAM cells in the second set connected to a corresponding bit line of a second group of four bit lines; a first single-ended sense amplifier pair disposed between the first set of DRAM cells and the second set of DRAM cells; The first single-ended sense amplifier pair a first single-ended sense amplifier; a second single-ended sense amplifier; a first transistor selectively connecting or disconnecting the first single-ended sense amplifier to a first bit line in the first group of bit lines; a second transistor selectively connecting or disconnecting the first single-ended sense amplifier to a first bit line in the second group of bit lines; a third transistor selectively connecting or disconnecting the second single-ended sense amplifier to a second bit line in the first group of bit lines; and a fourth transistor selectively connecting or disconnecting the second single-ended sense amplifier to a second bit line in the second group of bit lines; the first transistor and the second transistor are controlled so that the first single-ended sense amplifier is simultaneously connected to a maximum of one bit line, The third transistor and the fourth transistor are controlled so that the second single-ended sense amplifier is simultaneously connected to a maximum of one bit line.

32. 32. The DRAM system of claim 31, wherein the first single-ended sense amplifier pair is configured to have a width equal to or less than four times the pitch between adjacent bit lines.

33. and a second pair of single-ended sense amplifiers disposed adjacent to the first set of DRAM cells, the second pair of single-ended sense amplifiers comprising: a third single-ended sense amplifier; and a fourth single-ended sense amplifier; and a fifth transistor selectively connecting or disconnecting the third single-ended sense amplifier to a third bit line in the first group of bit lines; and a sixth transistor selectively connecting or disconnecting said fourth single-ended sense amplifier to a fourth bit line in said first group of said bit lines.

34. 34. The DRAM system of claim 33, further comprising a global bit line connected to the first single-ended sense amplifier and the second single-ended sense amplifier of the first single-ended sense amplifier pair, and the third single-ended sense amplifier and the fourth single-ended sense amplifier of the second single-ended sense amplifier pair.

35. and a third single-ended sense amplifier pair disposed adjacent to the second set of DRAM cells, the third single-ended sense amplifier pair comprising: a fifth single-ended sense amplifier; and a sixth single-ended sense amplifier; and a seventh transistor selectively connecting or disconnecting the fifth single-ended sense amplifier to a third bit line in the second group of bit lines; and an eighth transistor selectively connecting or disconnecting said sixth single-ended sense amplifier to a fourth bit line in said second group of said bit lines.

36. 36. The DRAM system of claim 35, further comprising a global bit line connected to the first single-ended sense amplifier and the second single-ended sense amplifier of the first single-ended sense amplifier pair, the third single-ended sense amplifier and the fourth single-ended sense amplifier of the second single-ended sense amplifier pair, and the fifth single-ended sense amplifier and the sixth single-ended sense amplifier of the third single-ended sense amplifier pair.

37. 34. The DRAM system of claim 33 further comprising a global bit line connected to the first single-ended sense amplifier and the second single-ended sense amplifier of the first single-ended sense amplifier pair.

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