Layer-molded direct contact and dielectric structure and method of manufacture thereof

Abstract

A method for manufacturing a semiconductor assembly may include providing a semiconductor component disposed within a first encapsulant, the encapsulant being disposed around at least four sides of the semiconductor component, contacting the at least four sides, and disposed on a front surface of the semiconductor component. A first layered structure may be formed on the encapsulant and the semiconductor component as a build-up interconnect structure. The first layered structure may include a first conductive layer formed on the first encapsulant, a first dielectric formed on the first conductive layer, and a second encapsulant disposed on the first conductive layer and the first dielectric. The top surface of the second encapsulant may be planarized to form a flat surface for forming a second layered structure or additional structures, such as package interconnects.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent No. 63 / 480,094, entitled "Stacked Molded Direct Contact and Dielectric Structure and Method for Making the Same," filed January 16, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] Incorporation by Reference The following disclosures are incorporated by reference herein in their entireties: U.S. Provisional Patent No. 63 / 347,516, entitled "Molded Direct Contact Interconnect Build-Up Structure Without Capture Pads," filed May 31, 2022; U.S. Provisional Patent No. 63,391,694, entitled "Molded Direct Contact Interconnect Substrate," filed July 22, 2022; and U.S. Utility Patent No. 17 / 957,683, entitled "Quad Flat No-Lead (QFN) Package Without Leadframe and Direct Contact Interconnect Build-Up Structure and Method for Making the Same," filed September 30, 2022.

[0003] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of apparatus and methods for forming electronic or semiconductor assemblies that include laminated direct contact and dielectric structures, such as build-up interconnect structures and methods for their manufacture. [Background technology]

[0004] Semiconductor devices, packages, substrates, and interposers are commonly found in modern electronic products. The fabrication of semiconductor devices involves a multi-stage buildup of components. Traditional interconnect structures consist of alternating dielectric and conductive layers. To allow connectivity from one layer to another, openings or via holes may be formed in the dielectric. On conductive layers, capture pads are used in the vias to correct for manufacturing mismatches.

[0005] 1A-1E show cross-sectional side views of assemblies or packages 550, providing various examples from the prior art. In conventional build-up interconnect structures 500, deformations 510 (e.g., dimples, waves, or undulations) result from following contours from underlying layers, including dielectric layer 502 and conductive layer 504. Deformations 510 can make manufacturing difficult and often increase manufacturing costs. Also shown are features of chips or components 514, UBM pads, POP land pads, SMD land pads, or LGA pads 520, package interconnects, solder bumps, electrodes, LGA or BGA arrays 522, encapsulant 530, and vertical conductive interconnects 533.

[0006] More specifically, Figure 1C shows an enlarged view in which conductive layer 504 includes deformations 510, which are highlighted by their locus or centerline 512. Deformations 510 are depicted as depressions, waves, or undulations. Summary of the Invention [Means for solving the problem]

[0007] In some aspects, the present disclosure relates to a method of manufacturing a semiconductor assembly, the method including providing a semiconductor component including a conductive stud formed on and bonded to a front surface of the semiconductor component. A first encapsulant is disposed around and in contact with at least four sides of the semiconductor component, disposed on the front surface of the semiconductor component, and disposed in contact with at least a portion of a side of the conductive stud. A first layered structure is formed on the encapsulant and on the semiconductor component as a build-up interconnect structure. Forming the first layered structure includes forming a first conductive layer, the first conductive layer including a redistribution layer (RDL), the redistribution layer disposed on the first encapsulant and coupled to the conductive studs, forming a first dielectric layer on the first conductive layer, forming a conductive stamp coupled to the first conductive layer and exposed to the first dielectric layer, disposing a second encapsulant on the first conductive layer, the first dielectric layer, and the conductive stamp, and planarizing a top surface of the second encapsulant to expose the conductive stamp and form a flat top surface for forming additional structures. A second layered structure is formed on the first layered structure and the flat top surface as a build-up interconnect structure to improve the planarization of the second layered structure. Forming the second layered structure includes forming a second conductive layer on the first layered structure, forming a second dielectric layer disposed on the second conductive layer, and forming a third encapsulant, the third encapsulant including a planarized upper surface disposed on the second conductive layer and the second dielectric layer. A portion of the second encapsulant forms a multilayer encapsulant body that passes through or around one or more of the first conductive layer and at least a portion of the first dielectric layer for direct contact with the first encapsulant, and the second conductive layer and at least a portion of the second dielectric layer for direct contact with the third encapsulant. The second encapsulant and the third encapsulant are formed without a semiconductor chip disposed therein.

[0008] In some cases, an interstitial dielectric layer is disposed between the first encapsulant and the first conductive layer. One or more of the first dielectric layer, the second dielectric layer, and the interstitial dielectric layer include polyimide. A first conductive layer is formed directly on the first encapsulant without the interstitial dielectric layer. Package interconnects are formed on the second layered structure and the planarized top surface, the package interconnects including one or more of solder bumps, pins, land grid arrays (LGAs), or ball grid arrays (BGAs). One or more additional conductive layers are formed on the first dielectric layer, the second dielectric layer, or both the first and second dielectric layers, and one or more of the second encapsulant and the third encapsulant are formed on and in direct contact with the one or more additional conductive layers. A portion of the second encapsulant may form a multilayer encapsulant body that passes through or around one or more of the first conductive layer and at least a portion of the first dielectric layer for direct contact with the first encapsulant, and the second conductive layer and at least a portion of the second dielectric layer for direct contact with the third encapsulant. The first dielectric layer may be formed such that a portion of the first dielectric layer contacts a lower portion of the sidewall of the conductive stamp. The second encapsulant layer may be positioned such that a portion of the second encapsulant layer contacts an upper portion of the sidewall of the conductive stamp. A backside layered structure may be formed on the backside of the semiconductor component.

[0009] In another aspect, the present disclosure relates to a method for manufacturing a semiconductor assembly, the method including providing a semiconductor component disposed within a first encapsulant, the encapsulant being disposed around at least four sides of the semiconductor component, contacting the at least four sides, and disposed on a front surface of the semiconductor component. A first layered structure can be formed on the encapsulant and the semiconductor component as a build-up interconnect structure. The first layered structure can be formed by forming a first conductive layer, including a RDL, the RDL being disposed on the first encapsulant and bonded to the semiconductor component; forming a first dielectric on the first conductive layer; forming a conductive stamp bonded to the first conductive layer; disposing a second encapsulant on the first conductive layer, the first dielectric, and the conductive stamp; and planarizing a top surface of the second encapsulant to expose the conductive stamp and form a flat top surface for forming additional structures. A second layered structure may be formed on the first layered structure and on the planar upper surface as a build-up interconnect structure, and forming the second layered structure includes forming a second conductive layer on the first layered structure, forming a second dielectric disposed on the second conductive layer, and forming a third encapsulant, the third encapsulant including a planarized upper surface disposed on the second conductive layer and the second dielectric.

[0010] In some cases, a portion of the second encapsulant forms a multilayer encapsulant body through or around one or more of the first conductive layer and at least a portion of the first dielectric for direct contact with the first encapsulant, and the second conductive layer and at least a portion of the second dielectric for direct contact with the third encapsulant. The semiconductor component may include a chip, which may include a conductive stud, which may be formed on and bonded to the front surface of the semiconductor component, and the encapsulant may contact a side of the conductive stud. An interstitial dielectric may be disposed between the first encapsulant and the first conductive layer. The first conductive layer may be formed directly on the first encapsulant without the interstitial dielectric. The first layered structure and the second layered structure may each include a RDL. One or more additional conductive layers may be disposed on the first dielectric layer, the second dielectric layer, or both the first and second dielectric layers, and one or more of the second encapsulant and the third encapsulant may be disposed on and in direct contact with the one or more additional conductive layers. The second encapsulant and the third encapsulant may be formed without a semiconductor chip disposed therein. The first dielectric may be disposed such that a portion of the first dielectric contacts the lower portion of the sidewall of the conductive stamp. The second encapsulant layer may be disposed such that a portion of the second encapsulant layer contacts the upper portion of the sidewall of the conductive stamp. A backside layer structure may be formed on the backside of the semiconductor component. The lower surface of the second encapsulant may be formed to include an undulating contour that follows the deformation of the first conductive layer, and the flat upper surface of the second encapsulant may be formed to include no undulating contour and not follow the deformation of the first conductive layer.

[0011] In yet another aspect, the present disclosure relates to a method for manufacturing a semiconductor assembly. The method includes providing a semiconductor component disposed within a first encapsulant, the encapsulant being disposed around at least four sides of the semiconductor component, contacting the at least four sides, and disposed on a front surface of the semiconductor component. A first layered structure may be formed on the encapsulant and the semiconductor component as a build-up interconnect structure. The first layered structure may include a first conductive layer formed on the first encapsulant, a first dielectric formed on the first conductive layer, a second encapsulant disposed on the first conductive layer and the first dielectric, and a top surface of the second encapsulant planarized to form a flat surface for forming additional structures.

[0012] In some cases, a gap dielectric may be disposed between the first encapsulant and the first conductive layer. The first conductive layer may be formed directly on the first encapsulant without a gap dielectric. A second layered structure may be formed on the first layered structure and the flat surface as a build-up interconnect structure to improve the flatness of the second layered structure. The first layered structure and the second layered structure may each include a RDL. A package interconnect may be formed on the first layered structure and the flat surface. The package interconnect may include one or more of solder bumps, pins, LGAs, or BGAs. The second layered structure may include either a second conductive layer disposed on the first layered structure, a second dielectric disposed on the second conductive layer, and a third encapsulant having a planarized top surface disposed on the second conductive layer and the second dielectric, or a third dielectric including vias disposed on the second conductive layer and the second dielectric such that the second layered structure does not include the encapsulant. The second conductive layer may be formed on the first dielectric, and the second encapsulant layer may be formed on and in direct contact with the second conductive layer. The second encapsulant and the third encapsulant may be formed without a semiconductor chip disposed therein. A portion of the second encapsulant may form a multilayer encapsulant body through or around one or more of: at least a portion of the first conductive layer and the first dielectric to directly contact the first encapsulant; and at least a portion of the second conductive layer and the second dielectric to directly contact the third encapsulant. A conductive stamp coupled to the first conductive layer can be formed, a first dielectric can be formed such that a portion of the first dielectric contacts a lower portion of a sidewall of the conductive stamp, and a second encapsulant layer can be positioned such that a portion of the second encapsulant layer contacts an upper portion of the sidewall of the conductive stamp.

[0013] These and other aspects, features, uses, and advantages will be apparent to those skilled in the art from the specification, drawings, and claims. Unless otherwise indicated, it is intended that the terms and phrases in this specification and claims be given their plain, ordinary, and accustomed meanings to those of ordinary skill in the applicable technical field. The inventors fully recognize that they can act as term definers if they wish. As their term definers, the inventors expressly choose to use only the plain and ordinary meanings of terms in this specification and claims, unless otherwise indicated, and further expressly state "special" definitions of those terms and explain how they differ from the plain and ordinary meanings. It is the inventors' intent and desire that the plain, plain, and ordinary meanings of terms be applied in interpreting this specification and claims, unless there is an explicit intention to apply such "special" definitions.

[0014] The inventors are also aware of the normal rules of English grammar. Accordingly, where a noun, term, or phrase is intended to further characterize, identify, or narrow in any way, such noun, term, or phrase will expressly include additional adjectives, descriptive terms, or other modifiers in accordance with the normal rules of English grammar. In the absence of the use of such adjectives, descriptive terms, or modifiers, such noun, term, or phrase is intended to be given its plain, ordinary English meaning, as set forth above, to one of ordinary skill in the applicable art.

[0015] Furthermore, the inventors are fully informed of the standards and application of the special provisions of 35 U.S.C. 112(f). Accordingly, the use of the words "function," "means," or "step" in the detailed description, drawing descriptions, or claims is not intended to indicate in any way an intention to invoke the special provisions of 35 U.S.C. 112(f) to define the invention. Conversely, if an attempt is made to invoke the provisions of 35 U.S.C. 112(f) to define an invention, the claims would specifically and explicitly recite the precise phrase "means for" or "step for," and would also recite the phrase "function" (i.e., "means for performing the function of [insert function]"), but such phrase would not recite any structure, material, or act that supports the function. Thus, it is the inventors' express intent not to invoke 35 U.S.C. 112(f) when a claim recites "means for performing the function of ..." or "steps for performing the function of ..." if the claim also recites any structure, material, or act that supports the means or step or performs the recited function. Furthermore, when 35 U.S.C. 112(f) is invoked to define claimed aspects, these aspects are not limited to the specific structure, materials, or acts described in the preferred embodiment, but are further intended to include any structure, material, or act that performs the claimed function, or any equivalent structure, material, or act known now or later developed for performing the claimed function, as described in alternative embodiments or forms of the present disclosure. [Brief explanation of the drawings]

[0016] [Figure 1A] 1A-1D illustrate various assemblies, such as semiconductor packages, that include build-up interconnect structures known in the prior art. [Figure 1B] 1A-1D illustrate various assemblies, such as semiconductor packages, that include build-up interconnect structures known in the prior art. [Figure 1C]1A-1D illustrate various assemblies, such as semiconductor packages, that include build-up interconnect structures known in the prior art. [Figure 1D] 1A-1D illustrate various assemblies, such as semiconductor packages, that include build-up interconnect structures known in the prior art. [Figure 1E] 1A-1D illustrate various assemblies, such as semiconductor packages, that include build-up interconnect structures known in the prior art. [Figure 2A] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices. [Figure 2B] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices. [Figure 2C] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices. [Figure 2D] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices. [Figure 3A] 1A-1C illustrate the formation of a reconstructed wafer or panel including components disposed within an encapsulant. [Figure 3B] 1A-1C illustrate the formation of a reconstructed wafer or panel including components disposed within an encapsulant. [Figure 3C] 1A-1C illustrate the formation of a reconstructed wafer or panel including components disposed within an encapsulant. [Figure 3D] 1A-1C illustrate the formation of a reconstructed wafer or panel including components disposed within an encapsulant. [Figure 3E] 1A-1C illustrate the formation of a reconstructed wafer or panel including components disposed within an encapsulant. [Figure 3F] 1A-1C illustrate the formation of a reconstructed wafer or panel including components disposed within an encapsulant. [Figure 4A] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices having heterogeneous laminate molded direct contact and dielectric structures formed thereon. [Figure 4B]1A-1C illustrate components such as semiconductor dies, chips, and embedded devices having heterogeneous laminate molded direct contact and dielectric structures formed thereon. [Figure 4C] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices having heterogeneous laminate molded direct contact and dielectric structures formed thereon. [Figure 4D] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices having heterogeneous laminate molded direct contact and dielectric structures formed thereon. [Figure 4E] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices having heterogeneous laminate molded direct contact and dielectric structures formed thereon. [Figure 4F] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices having heterogeneous laminate molded direct contact and dielectric structures formed thereon. [Figure 4G] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices having heterogeneous laminate molded direct contact and dielectric structures formed thereon. [Figure 4H] 1A-1C illustrate components such as semiconductor dies, chips, and embedded devices having heterogeneous laminate molded direct contact and dielectric structures formed thereon. [Figure 5A] FIG. 1 illustrates a heterogeneous laminate molded direct contact structure and a dielectric structure formed on one or more components. [Figure 5B] FIG. 1 illustrates a heterogeneous laminate molded direct contact structure and a dielectric structure formed on one or more components. [Figure 6A] FIG. 10 illustrates further features of the layered structure, including a conductive stamp in contact with the encapsulant and dielectric, and both front and back layered structures. [Figure 6B] FIG. 10 illustrates further features of the layered structure, including a conductive stamp in contact with the encapsulant and dielectric, and both front and back layered structures. [Figure 7] 1A and 1B show further details of a semiconductor assembly including a layered structure and deformation of a conductive layer therein. [Figure 8A]FIG. 1 shows a flow chart or wireframe view of a method for forming a semiconductor assembly including a layered structure. [Figure 8B] FIG. 1 shows a flow chart or wireframe view of a method for forming a semiconductor assembly including a layered structure. DETAILED DESCRIPTION OF THE INVENTION

[0017] The present disclosure relates to shaped direct contact and dielectric interconnect structures, such as those for use with semiconductor structures, devices, and packages. The shaped direct contact and dielectric interconnect structures may be (or may include) conductive layers formed as part of an additive or build-up process. Additionally, the interconnect structures may be (or may include) conductive layers formed by etch-back as part of an etching or removal process. In this process, a conductive layer is deposited (possibly including vias to an underlying conductive layer, and occasionally using independently deposited via "plugs" between layers). Photoresist is then applied and patterned on the conductive layer, followed by an etching process (either wet or dry) to remove unwanted conductive material. This results in the desired conductive pattern and layered structure. If necessary, the process used to form the conductive layer may be structurally sensitive, since etched-back conductors will have more sloped sidewalls than built-up conductors (usually due to a somewhat isotropic etch). In either case, it is important to ensure that either built-up or etched-back conductive layers are considered. For convenience and uniformity, the term "build-up" will be used throughout this application, but as will be appreciated by those skilled in the art (POSA), for purposes of this disclosure, it also includes etched-back interconnect structures.

[0018] In some cases, the molded direct contact and dielectric interconnect build-up structures can include wiring for semiconductor devices with different pitches (e.g., high density and ultra-high density, as described more fully herein). The molded direct contact and dielectric interconnect build-up structures (and methods for making and using them) can include or provide a unique layered structure including a dielectric with patterned via holes and one or more conductive wiring layers, followed by a non-photodefined molding or encapsulant structure, whereby the structure can be planarized (by molding or grinding) to provide a flat or planar surface for subsequent dielectric and one or more wiring layers in an iterative process. The dielectric can be a photosensitive material, and photopatterning is used to define the via holes, or the dielectric can be non-photosensitive, and the via holes are formed using a photoresist pattern followed by a wet or dry etching process. The dielectric material has different properties than the encapsulant, and in some cases has a low dielectric constant or other properties that allow the dielectric to improve the electrical performance of the interconnect structure, the conductive layer, or both, measured against what can be achieved using the encapsulant alone. In some cases, the different properties of the dielectric material allow for improved thermal performance or improved reliability performance compared to what can be achieved using encapsulant alone. Traditionally, build-up layers have been limited to 4-6 layers in wafer-level or panel-level build-up manufacturing processes. However, with the shaped direct contact and dielectric interconnect build-up structure of the present invention, any desired number of layers (e.g., even 20-30 build-up layers) is now possible for wafer-level or panel-level build-up manufacturing processes.

[0019] Thus, advantages of molded direct contact and dielectric interconnect build-up structures include one or more of the following: (i) planar encapsulant or mold compound interleaved or interspersed (vertically offset) from dielectric layers within a layered structure, (ii) improved electrical and signal performance for conductive layers (e.g., signal or clock lines) formed above, below, within, or simultaneously with dielectric materials (e.g., polyimide (PI)) within a larger structure that includes the encapsulant layers, (iii) improved number of vertical build-up layers, (iv) improved thermal performance, and (v) improved reliability performance.

[0020] At least some of the above advantages are at least partially available using unit-specific patterning (e.g., patterning (custom lithography) and build-up interconnect structures, e.g., front-side build-up interconnect structures (also known under the trademark "Adaptive Patterning™"). Unit-specific patterning enables scaling to ultra-high density pitch, which can often be used with higher speed chip attach equipment for semiconductor dies. Unit-specific patterning (including Adaptive Patterning™ and AP™) ensures alignment for high density interconnects with shaped direct contact and dielectric interconnect build-up structures. Unit-specific patterning may also be used in the processes disclosed herein for manufacturing packages, including the ability to make large-area connections precisely aligned to chip bond pads for very low contact resistance.

[0021] The structure and method of the present invention provide advantages over the prior art, which involves using dielectric materials (e.g., polymers and polyimides) without a molding compound. By adding a layer of encapsulant or molding compound, topographical planarity is achieved and improved.

[0022] Detailed aspects and applications of the present disclosure are described below in the following figures and detailed description of the technology. Unless otherwise indicated, it is intended that the words and phrases in the specification and claims be given their plain, ordinary, and accustomed meanings to those of ordinary skill in the applicable technical field.

[0023] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various aspects of the present disclosure. However, those skilled in the relevant art will understand that embodiments of the technology disclosed herein may be practiced without these specific details. It should be noted that there are many different alternative configurations, devices, and technologies to which the disclosed technology may be applied. The full scope of the technology disclosed herein is not limited to the examples described below.

[0024] The singular forms "a," "an," and "the" include plural referents unless the context clearly indicates otherwise. Thus, for example, a reference to "a step" includes a reference to one or more of such steps.

[0025] The present disclosure, its aspects and embodiments, are not limited to the specific package types, material types, or other system component examples or methods disclosed herein. Many additional components, manufacturing, and assembly procedures known in the art consistent with semiconductor wafer fabrication, manufacturing, and packaging are contemplated for use with particular embodiments from this disclosure. Thus, for example, while particular embodiments are disclosed, such embodiments and implementations may include any parts, models, types, materials, versions, quantities, etc., as known in the art for such systems and implementations consistent with the intended operation.

[0026] The terms "exemplary" and "example," or various forms thereof, are used herein to mean serving as an example, illustration, or illustration. Any aspect or design described herein as "exemplary" or "example" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Furthermore, examples are provided merely for clarity and understanding and are not intended to limit or restrict in any way the disclosed subject matter or relevant portions of this disclosure. It should be understood that countless additional or alternative examples of various scopes could have been provided but have been omitted for brevity. As used herein, "substantially" or "about" means the recited amount plus or minus (+ or -) 50% or less, 40% or less, 30% or less, 20% or less, 10% or less, 5% or less, or 1% or less.

[0027] Where the following examples, embodiments, and implementations refer to examples, those skilled in the art will understand that other manufacturing devices and examples can be mixed or substituted for those provided. Where the description refers to specific embodiments, it will be readily apparent that many changes can be made without departing from the spirit thereof, and that these embodiments and implementations can be applied to other technologies. Accordingly, the disclosed subject matter is intended to encompass all such changes, modifications, and variations that are within the spirit and scope of this disclosure and the knowledge of those skilled in the art.

[0028] FIG. 2A shows a plan or top view of a substrate 8. The substrate 8 may include a semiconductor wafer or native wafer 10 having a base substrate material 12 (e.g., without limitation, silicon, germanium, gallium arsenide, indium phosphide, gallium nitride, or silicon carbide) for structural support. Multiple chips, semiconductor dies, or components 14 may be formed on the wafer 10, separated by inactive inter-die wafer areas or saw streets 16. As used herein, components 14 include active elements, passive elements, or both. Components 14 include semiconductor components, chips, and semiconductor dies. Components 14 also include non-semiconductor components (e.g., inactive components, passive components, or components formed without transistors). Components 14 include sensors and microelectromechanical systems (MEMS), which do not rely on semiconductor materials to create transistors. Components 14 may also include discrete passive elements (e.g., resistors or capacitors) or groups of passive elements (e.g., integrated passive devices (IPDs)), other semiconductor dies, ICs, bridge dies, wafer-level chip-scale packages (WLCSPs), MEMs, optical components (e.g., image sensors, transmitters, receivers, and light-emitting diodes (LEDs)), and any other suitable components. For illustrative purposes, non-limiting examples of components 14 that are chips or semiconductor dies are set forth in FIGS. 2A-2D . Thus, saw streets 16 may provide a cutting area for separating semiconductor wafer 10 into individual components or chips 14 that become embedded devices, which may be formed on substrates 8 formed of glass, ceramic, or other suitable materials to provide structural support for subsequent processing.

[0029] Each component 14 may include one or more active elements, passive elements, or both active and passive elements. In some cases, components 14 may be formed without active and passive elements and may be used for transmission or wiring, for example, by including TSVs for vertical interconnections. For example, components 14 may be formed as bridge chips having only electrical wiring, with copper studs of a semiconductor chip electrically connected or coupled to wiring, routing, or RDLs. Components 14 may also be merely dummy substrates with no electrical function, or rather function as structural elements, which may or may not include copper studs.

[0030] The component 14 may include a semiconductor chip or die including a backside or rear surface 18 and a frontside or front surface including an active layer 20 opposite the backside or rear surface 18. The active layer includes one or more analog or digital circuits implemented as active devices, conductive layers, and dielectric layers formed within or on the chip and electrically interconnected according to the electrical design and function of the semiconductor chip. In some cases, passive devices may also be incorporated as part of the semiconductor chip or die. The circuitry included in the component 14 may include one or more transistors, diodes, and other circuit elements formed within the active layer to implement analog or digital circuits (e.g., DSP, ASIC, memory, or other circuits). The circuitry may include RF circuits, LEDs, LCOS, CIS, transistors, optoelectronics, MEMS, etc. The component 14 may also include IPDs (e.g., inductors, capacitors, and resistors) for RF signal processing, digital power line control, or other functions. The component 14 may be formed on a native wafer 10. In some cases, wafer-level processes may be used to simultaneously form multiple packages on wafer 10. In other cases, packages may be formed as part of a reconstituted wafer and may include multiple components or chips molded together.

[0031] Figure 2B shows a cross-sectional view of a portion of semiconductor wafer 10 taken along section line 2B in Figure 2A. Each component 14 is shown to include a backside or rear surface 18 and an active layer 20 facing the backside.

[0032] An electrically conductive layer or contact pad 22 is formed on the active layer 20 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process. The conductive layer 22 can be one or more layers of aluminum (Al), titanium (Ti), copper (Cu), tin (Sn), nickel (Ni), gold (Au), palladium (Pd), silver (Ag), cobalt (Co), platinum (Pt), tantalum (Ta), or other suitable electrically conductive material. The conductive layer 22 functions as a contact pad or bond pad electrically coupled or connected to the circuitry on the active layer 20. The conductive layer 22 can be formed as side-by-side contact pads spaced a first distance from an edge 24 of the component 14, as shown in FIG. 2B . Alternatively, the conductive layer 22 can be formed as multiple rows of staggered contact pads, with a first row of contact pads located a first distance from the edge 24 of the component 14 and a second row of contact pads, alternating with the first row, located a second distance from the edge 24 of the component 14. In other cases, the component 14 can include a digital, analog, or RF chip (or other chip) with more than two rows of bond pads and can further include 22 bond pads across the surface of the chip that do not follow a complete grid pattern. Other components 14 can have an array of bond pads across the surface of the chip.

[0033] FIG. 2B also shows that the semiconductor substrate 10 and the component 14 may be subjected to an optional operation (e.g., grinding with a grinder 29, wet etching, plasma etching, polishing, or other suitable process) to reduce the thickness of the semiconductor substrate 10 and the component 14.

[0034] FIG. 2B further illustrates that one or more optional insulating, passivating, or dielectric layers 26 may be conformally applied over the active layer 20 and the conductive layer 22. The insulating layer 26 may include one or more layers applied using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable processes. The insulating layer 26 may include, without limitation, one or more layers of silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), carbon-doped silicon oxide (CDO), tantalum pentoxide (TaO), aluminum oxide (AlO), polymer, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or other materials with suitable insulating and structural properties. While the foregoing list includes some precise chemical formulas for some materials, in some cases, the insulating materials may be non-stoichiometric, depending on the deposition process. Alternatively, the component 14 may be packaged without the insulating layer 26. In another embodiment, insulating layer 26 comprises a passivation layer formed on active layer 20 without being disposed on conductive layer 22. If insulating layer 26 is present and formed on conductive layer 22, an opening is formed completely through insulating layer 26 to expose at least a portion of conductive layer 22 for subsequent mechanical and electrical interconnection. Alternatively, if insulating layer 26 is omitted, no opening is formed, exposing conductive layer 22 for subsequent electrical interconnection.

[0035] FIG. 2B illustrates that conductive studs or electrical interconnect structures 125 can be formed as bumps, thick pads, columns, pillars, posts, or conductive studs to be disposed on and coupled or connected to contact pads 22. Conductive studs 125 can be formed directly on contact pads 22 using a patterning and metal deposition process (e.g., printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, evaporation, or other suitable metal deposition process). Alternatively, conductive studs 125 can be formed in a non-vertical position on pads 22 and connected by RDLs. Conductive studs 125 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, palladium (Pd), or other suitable electrically conductive material and can include one or more under-bump metallization (UBM) layers. In one embodiment, a photoresist layer can be deposited on component 14 and contact pads 22. Portions of the photoresist layer can be exposed to light and removed by development or other suitable process. Electrically conductive studs 125 may further be formed as pillars or other structures, as previously described, within the removed portions of the photoresist and on the contact pads 22 using a plating process. In some embodiments, copper may be used in the plating process. The photoresist layer and other suitable layers (e.g., a seed layer deposited prior to depositing the photoresist) may be removed, leaving behind the conductive studs 125. The conductive studs 125 provide subsequent mechanical and electrical interconnection and standoff for the active layer 20 and the insulating layer 26 (if present). In some cases, the conductive studs 125 include a height H1 in the range of 10 to 100 micrometers (μm), 5 to 50 μm, or approximately 25 μm.

[0036] A conductive stud is a conductive interconnect structure that has generally vertical sides, is wider than it is tall, and can be built up on a substrate (e.g., on the active surface of a chip, polyimide, or mold compound). Conductive studs are typically formed of the same material as pillars or posts, but can be different from the pillars or posts (each of which can have a height greater than its width). Conductive studs are typically formed in a cylindrical shape, but can be formed with cross-sectional areas that are circular, oval, octagonal, or any polygonal or other shape and size. Another application for conductive studs is as a thermally conductive stud that is not electrically coupled to an active electrical circuit but instead thermally coupled to a heat source of an active device and conducts or dissipates heat to another structure (e.g., a land pad (i.e., a dummy conductive stud) on the surface of a PCB). The generally vertical, straight sides of the conductive stud 125 differ from the side shapes present for solder balls with generally rounded sides or solder balls that are compressed or deformed outward. The substantially vertical nature of conductive stud 125 results from its formation within a previously developed or etched structure, such as an opening in a photoresist layer, which also has substantially vertical, straight walls, but may include imperfections or irregularities in the shape due to the development or etching process, the photoresist material, or other materials and processes used. For example, development or etching typically does not completely or uniformly remove the photoresist within the opening, resulting in an imperfect, substantially vertical opening when depositing the conductive material for conductive stud 125. The term "substantially vertical," as used herein, includes perfectly vertical sides and imperfectly vertical sides. The conductive stud is not a wire bond or solder.

[0037] FIG. 2C further illustrates, by way of example, that one or more optional adhesives or die attach films (DAFs) 41 (possibly even conductive materials for heat transfer or other suitable purposes) may be attached to rear surface 18 of component 14, e.g., for subsequent mounting on a carrier. FIG. 2C also illustrates that wafer 10 may be separated into individual components 14 through saw streets 16 with a saw or wafer cutting tool 32 using a saw blade, laser cutting tool, plasma, or scribe-and-break process. In some cases, component 14 may have a thickness (shown vertically on the page, bottom to top) of about 15 μm to about 150 μm for thin polished wafers and about 100 μm to about 800 μm for thick polished wafers.

[0038] FIG. 2D shows a cross-sectional view of an embodiment in which component 14 is formed as an embedded component or embedded semiconductor device 44. The embedded component 44 can be disposed on a temporary carrier, a reusable carrier, a sacrificial carrier, a permanent carrier, or any suitable carrier 50 (formed of metal, glass, silicon, mold compound, or other suitable material, which may include a release layer). The carrier 50 can include a wafer (circular footprint), a panel (square or rectangular), or any suitable shaped form factor or footprint, and can include a diameter or width of 200 to 600 mm, e.g., 300 mm, or any other suitable size. The embedded component 44 can be separated by separating it through the gap or saw streets 40 into individual embedded components or embedded semiconductor devices 44 using a saw blade, a grinding wheel, a plasma cutting tool, a laser cutter, or other suitable tool 32. The individual embedded components or embedded semiconductor devices 44 may be used interchangeably with component 14 in any subsequent figures and descriptions. The embedded component 44 can further be used as part of a subsequently formed assembly or package, as described in more detail below. However, embedded components 44, including chips or semiconductor dies or other components 14, may be fully testable after the conductive studs 125 are applied and before the embedded components 44 are separated from the panel or assembled into another structure.

[0039] In some cases, the embedded semiconductor die 44 may be formed as described in U.S. Patent Application No. 13 / 632,062, now U.S. Patent No. 8,535,978, entitled "Die Up Fully Molded Fan-out Wafer Level Packaging," filed April 29, 2015, the entire disclosure of which is incorporated herein by reference.

[0040] 3A shows a plan or top view of temporary carrier 120. Temporary carrier 120 may include a wafer (circular or substantially circular footprint), a panel (square or rectangular), or any suitable shaped (e.g., generally circular with flat edges) form factor or footprint, and may include a diameter or width of 200-600 mm, e.g., 300 mm, or any other suitable size. Components 14 may be placed on temporary carrier 120 using a pick-and-place operation or in any other suitable manner.

[0041] Component 14 can be oriented either face-up, with active layer 20 facing away from carrier 120 on which component 14 is mounted, or face-down, with active layer 20 facing toward carrier 120 on which component 14 is mounted. Thus, adhesive 41 can be included or omitted from rear surface 18 of component 14, depending on the process used to encapsulate component 14 and form a panel or reconfigurable panel 134 (e.g., as shown in FIG. 3E ) that includes component 14 fully molded within encapsulant 130 (e.g., as shown in FIG. 3D ).

[0042] FIG. 3B shows a cross-sectional profile view of components 14 or 44 positioned face-up on a temporary carrier 120. Each component 14 includes a conductive stud 125 disposed on the front surface of the component. The component, if present, can be the active layer 18. In some cases, the temporary carrier 120 can be a metal carrier, a silicon carrier, a glass carrier, or a carrier made of other suitable material used in a molding or encapsulation process, and can then be removed after an encapsulant, such as a mold compound, a filled epoxy film, such as ABF, or another dielectric, such as polyimide, is deposited and cured, or both. As a result, the encapsulant provides structural support, and the temporary carrier is no longer necessary for processing. The components 14 can be positioned adjacent to each other or laterally offset (e.g., in a side-by-side arrangement). As a result, multiple components 14 can be arranged at the panel level within a reconstructed wafer 134 (e.g., as shown in FIG. 3E) and processed through various manufacturing steps before being separated into individual assemblies or packages (including QFN, DFN, or SON packages 300). Thus, multiple parts 14 may be processed together at the same time on a temporary carrier 120. This will be understood by the POSA even though a close-up view of only a portion of a part 14 is shown.

[0043] 3C shows a close-up view of component 14 taken along the cross-section marker of FIG. 3B, highlighting conductive studs 125 formed on surface or active layer 20 and aligned on component 14. While not required for all embodiments, the conductive studs 125 of the particular embodiment shown herein are shown around the periphery of component 14 for the particular implementation in which they are used. An optional interface layer 122 (e.g., double-sided tape, film, or deposition material) may be used underneath components 14 to temporarily hold them to temporary carrier 120 during processing.

[0044] 3B and 3C, illustrates the placement of encapsulant 130 face-up around component 14, on temporary carrier 120, around the four sides of component 14, on the front of component 14, and around conductive studs 125. As used herein, over, on, or around can mean in direct contact or in contact with another intervening layer (e.g., a polymer or polyimide layer disposed between chip 14 and encapsulant 130). Conductive studs 125 formed on the active layer of component 14 may be contacted, surrounded, partially surrounded, or encapsulated or molded in a single step with a single encapsulant, polyimide, or mold compound, with the same encapsulant, polyimide, or mold compound 130 disposed around the periphery of component 14, including at least four sides. The encapsulant 130 can be deposited around multiple components 14 using paste printing, compression molding, transfer molding, liquid encapsulation, dispensing, lamination, vacuum lamination, spin coating, slit or slot die coating, or other suitable application. The encapsulant 130 may be an organic material, mold compound, polyimide, or a composite material, such as a filled epoxy resin, such as a filled ABF or epoxy acrylate, suitable for planarization, such as chemical mechanical planarization (CMP) or grinding. Therefore, in some cases, the encapsulant 130 is not a polymeric material, such as unfilled polyimide. Unfilled polyimide may not perform well in grinding operations and may impair grinding wheel movement. Figure 3F shows a planar surface 132 with exposed conductive studs 125.

[0045] Continuing from FIG. 3D, FIG. 3E is a plan view of an entire reconstituted wafer or panel 134, with FIG. 3D being a cross-sectional side view of a portion of reconstituted wafer 134 taken along section line 3D. FIG. 3E shows a plan view of components 14 within panel 134, similar to the plan view of components 14 on carrier 120 shown in FIG. 3A. FIG. 3E differs from FIG. 3A by including encapsulant 130 disposed on, around, or both on and around components 14.

[0046] FIG. 3E shows that the encapsulant 130 can be deposited around multiple components 14 using paste printing, compression molding, transfer molding, liquid encapsulant molding, lamination, vacuum lamination, spin coating, or other suitable application methods. The encapsulant 130 can be a polymer composite, such as a filled epoxy resin (commonly referred to as electronic mold compound or EMC), a filled epoxy acrylate, ABF (Ajinomoto Build-Up Film®), or other polymers with appropriate fillers. The components 14 can be embedded together within the encapsulant 130 to form a panel, reconfigured panel, wafer, or reconfigured wafer 134, which allows multiple components 14 to be processed and packaged simultaneously to form multiple assemblies or packages (e.g., QFN, DFN, SON, or BGA packages). The panel 134 can be non-conductive, providing mechanical rigidity as well as environmental protection for the components 14 from external elements and contaminants.

[0047] The panel 134 can optionally undergo a curing process to harden the encapsulant 130. As shown in FIG. 3F, the surface of the encapsulant 130 can be substantially flush with the adhesive 41. Alternatively, the encapsulant 130 can be substantially flush with the back surface 18, with the encapsulant exposed by removal of the carrier and interface layers. The reconfigurable panel 134 can include a footprint or form factor of any shape and size (e.g., circular, rectangular, or square), for example, form factors ranging from 200 to 600 millimeters (mm), including the form factor of a semiconductor wafer including a circular footprint with a diameter of 300 mm. Any other desired size can also be formed.

[0048] Continuing from FIGS. 3D and 3E, FIG. 3F also illustrates that temporary carrier 120 may be removed after molding or placing encapsulant 130. In some cases, the backside or rear surface 18 of component 14 may be exposed from encapsulant 130 and other layers. Alternatively, in other cases, as shown in FIGS. 2C and 3F, a backside laminate, encapsulant, die attach film (DAF), or other material 41 may be placed on the backside of component 14. Thus, in some cases, the backside laminate (including polyimide or mold compound) may be more than temporary and may become part of the final product, or may be removed in a later processing step (e.g., a grinding or polishing step). Various processing steps may be included such that the backside of the semiconductor chip is exposed to or covered by the encapsulant or other material.

[0049] The encapsulant 130 on the front surface or active layer 20 may be planarized or ground to expose the conductive studs 125 before or after removing the temporary carrier 120. As previously mentioned, FIG. 3F shows a close-up view of a portion of component 14 after the encapsulant 130 on the front surface or active layer 20 of component 14 has been planarized to form a planar surface 132 that includes the exposed ends of the conductive studs 125 and further includes the planarized encapsulant surface. The planarization or grinding of the encapsulant produces a flatness in the range of approximately 0.5 to 2.0 micrometers (μm) and a peak-to-valley total roughness height of 5 nanometers (nm) to 2 μm measured over a characteristic measurement distance, which may include a distance or length of approximately 1 millimeter (mm). While conventional encapsulant grinding can be performed with lower flatness, greater precision and accuracy can be achieved by controlling the grinding using integrated sensors (e.g., laser, acoustic, or other non-contact methods), resulting in improved flatness. In some cases, first conductive stud 125 may be formed with a height of about 50 micrometers (μm) or less, or about 250 μm or less, and may be further ground down to a height less than its original height (e.g., in certain embodiments, about 4 μm or 1 μm or less). As used herein, "about" or "substantially" means a percent difference of 50%, 40%, 30%, 20%, 10%, or 5% or less.

[0050] 4A-4H, 5A-5B, 6A-6B, and 7 show various diagrams for forming layered structures 150, 200, 250, 350 (or any desired number of layered structures). Layered structures 150, 200, 250, 350 include encapsulants 180, 230, 280, 380, respectively, with separate dielectric layers 160, 210, 260, 360 and conductive layers 154, 204, 254, 354, respectively, formed above or below the encapsulant layers 180, 230, 280, 280 to form the layered structures. Multiple such layered structures 150, 200, 250, 350 may be used as part of the same semiconductor assembly or package 330 (including components 14) or substrate (not including components or chips 14). By forming the semiconductor assembly 330 with the layered structure 150, 200, 250, 350, many advantages are achieved, as will be described in more detail herein. As shown in Figure 4A (and other figures), vertically spaced encapsulant layers 180, 230, 280, 380 are formed as part of the layered structure 150, 200, 250, 350, and the encapsulant layers 180, 230, 280 are disposed between, sandwiched between, or interleaved with the following materials: Vertically stacked or spaced apart: (i) one or more layers of conductive layers 154, 204, 254, 354 (including RDLs 156, 206, 256 and traces 158, 208, 258); and (ii) dielectric layers 160, 166, 210, 216, 260, 266, and 360 that are non-mold or non-encapsulant materials (e.g., polymers, polyimides, organic or inorganic dielectrics, or other suitable dielectrics known in the art).

[0051] Planarizing the encapsulant layers 180, 230, 280, 380 improves flatness, planarity, and uniformity, reducing surface profile issues. As shown in FIGS. 1A-1E and known in the art, distortions 510 (e.g., dimples, waves, or undulations resulting from following contours from underlying layers) can be magnified or exaggerated in subsequently formed layers, increasing or exacerbating distortions 510 and potentially resulting in the inability to form fine-pitch lines due to photolithography or patterning issues, reliability, and other problems. Disturbances 510 can make it extremely difficult or impractical to fabricate RDLS traces or other structures with two or more layers of 2 μm line-and-space (4 μm pitch). Similarly, submicron line-and-space pitches are extremely difficult or impractical due to the lack of planarity or flatness, thereby increasing costs and reducing processing or other desirable attributes of the final structure. The problems with the deformation 510 described above may be mitigated, limited, addressed, or ameliorated by the layered structures 150, 200, 250, 350, including planarized or flat encapsulant layers 180, 230, 280, 380, and methods of fabrication thereof, as disclosed and illustrated herein and further described with reference to FIG. 7. FIG. 7 shows further details of how the deformation 510 in the conductive layer 154 may exist within the layered structure 150 and may be ameliorated by the encapsulant layer 180. As a POSA practitioner will appreciate, the same improvements exist for the layered structures 150, 200, 250, 350 (and any desired number of layered structures), but are not explicitly shown in FIGS. 4A-4H, 5A-5B, and 6A-6B for simplicity and ease of illustration.

[0052] 4A and subsequent figures illustrate that a semiconductor assembly or package 300 may include a semiconductor component 14 including conductive studs 125 formed on and coupled to a front surface or active layer 20 of the semiconductor component 14. A first encapsulant 130 may be disposed around and in contact with at least four side surfaces 15 of the semiconductor component 14, disposed on the front surface or active layer 20 of the semiconductor component 14, and disposed in contact with at least a portion of the side surfaces 126 of the conductive studs 125. A first layered structure 150 may be formed as a build-up interconnect structure on the encapsulant 130 and on the semiconductor component 14. The first layered structure 150 may be formed as a fan-out interconnect structure 151. A second layered structure 200 may be formed as a build-up interconnect structure on the first layered structure 150 and on the planar surface 184 to improve the planarity of the second layered structure 200.

[0053] Forming the first layered structure 150 may include forming a first conductive layer 154 disposed on the first encapsulant 130 and including a RDL 156 coupled to the conductive stud 125. The conductive layer 154 may include one or more of the RDL 156, one or more traces 158, which may be disposed on the first encapsulant 130 and coupled to the conductive stud 125. The first conductive layer 154 may be formed on the encapsulant 130, the component 14, or both, as shown in FIG. 4A . In some cases, the conductive layer 154 may include conductive wiring, traces 158, as well as other features. The conductive layer 154 may include one or more features (e.g., traces, land pads, capacitors, inductors, shields, resistors, antennas or antenna feeds, or other features or structures). The description of the first conductive layer 154 is also applicable to the other conductive layers 154a, 154b, 154x, 204, 204a, 120b, 204x, 254, 254a, 254b, 254x, 304, 304a, 304b, and 304x.

[0054] The conductive layer 154 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, Ta, Co, or a coupling agent or other suitable electrically conductive material. The conductive layer 154 can be formed using PVD, CVD, electroplating, electroless plating, or other suitable processes. The conductive layer 154 can be built up within a patterned material (e.g., patterned photoresist) so that the conductive layer assumes the pattern of the patterned material. In other cases, the conductive layer 154 can be deposited as an unpatterned material and then patterned after deposition using a patterned material (e.g., patterned photoresist). Openings in the patterned material allow etching of the underlying conductive layer 154, resulting in a patterned conductive layer 154. In one embodiment, the conductive layer 154 can include a Ti diffusion barrier layer or barrier layer, a Cu seed layer, and a Cu layer formed on the Ti barrier layer and the Cu seed layer. Typically, the barrier and seed layers are deposited by a PVD process (e.g., sputtering). In addition to providing good adhesion and acting as a diffusion barrier to the underlying material on which it is deposited, the barrier and seed layers provide a plating bath that allows for electrolytic plating of a conductor (e.g., a plated conductive element) onto the seed layer.

[0055] 4C shows an example in which a dielectric or insulating layer 260 may be formed on the third conductive layer 254 and may include polyimide or other suitable materials. The third dielectric 260 may be formed at least partially around, contact, reinforce, or support the conductive layer 254. The third dielectric layer 260 may include one or more layers (e.g., 260a, 260b) of an insulating or dielectric material applied (e.g., over the encapsulant 230, conductive layers 254a, 254b) using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable process. The dielectric layer 260 may include, without limitation, one or more layers of organic materials, inorganic materials, and polymers (including one or more layers of SiO, SiN, SiON, CDO, TaO, AlO, polyimide, BCB, PBO, or other materials with suitable insulating and structural properties).

[0056] The discussion regarding the first dielectric layer 260 is also applicable to the other dielectric layers 160, 166, 210, 216, 266, 302, and 360.

[0057] First dielectric layer 160 may be formed around conductive layer 154, including as one or more layers below, above, and completely or partially surrounding first conductive layer 154. First dielectric layer 160, when made of, for example, a polymer or polyimide, can provide higher leakage current resistance or higher breakdown voltage than mold compound for high voltage applications, as well as superior electrical performance for high frequency signals.

[0058] The first dielectric layer 160 and layered structures 150, 200, 250 may include one or more of the features or approaches set forth in U.S. patent application Ser. No. 63 / 347,516, entitled "Molded Direct Contact Interconnect Build-up Structure Without Capture Pads," filed May 31, 2022, and may also use the features and approaches set forth in U.S. patent application Ser. No. 63 / 391,694, entitled "Molded Direct Contact Interconnect Substrate," filed July 22, 2022. U.S. patent application Ser. No. 63 / 347,516 and U.S. patent application Ser. No. 63 / 391,694 (in their entireties) are incorporated herein by reference.

[0059] Via holes, openings, or trenches 162 in the first dielectric layer 160 may be formed to facilitate subsequent electrical interconnection with one or more conductive layers, or to provide structural support or thermally conductive paths. In other cases, one or more layers of dielectric material 160, or others, may include holes, trenches, or openings through a polymer or polyimide (non-encapsulant layer) so that an encapsulant layer can interlock or connect through the openings and through the dielectric layer 160 to improve mechanical connection.

[0060] Conductive stamp 170 may be bonded to first conductive layer 154 and exposed to first dielectric layer 160. Conductive stamp 170 (e.g., conductive stamp 220, 270) may be similar to or identical to conductive stud 125, but may be formed separate from component 14 and bonded to conductive layer 154 (or conductive layer 204, 254, 304, or other suitable conductive feature, e.g., heat sink and flag).

[0061] A second encapsulant 180 may be disposed over the first conductive layer 154, the first dielectric layer 160, and the conductive stamp 170. The second encapsulant 180 (as well as the third encapsulant 230, the fourth encapsulant layer 280, or any subsequent encapsulants) may be similar to or identical to the first encapsulant 130. As shown in FIG. 7 , the bottom surface 183 of the encapsulant 180 conforms to the surface topography of the underlying dielectric layer (e.g., dielectric layer 150b), or the underlying conductive layer (e.g., conductive layer 154c), or any other layer on which it is deposited. The top surface 182 of the second encapsulant 180 may be planarized to expose the conductive stamp 170 and form a flat surface 184 for forming additional structures. Thus, a second encapsulant (such as third encapsulant 230, fourth encapsulant 280, or any subsequent encapsulant) may have a conformal and non-planar bottom surface and a planar top surface 182.

[0062] A second layered structure may be formed including a second conductive layer 204. The second conductive layer 204 is disposed on and bonded to the first layered structure 150. A second dielectric layer 210 may be formed or disposed on the second conductive layer 204. The third encapsulant 230 may be formed (e.g., deposited and then ground by a grinder 29) to include a flat or planarized upper surface 234 disposed on the second conductive layer 204 and the second dielectric layer 210. The flatness and planarity of the planarized upper surface 234 may be the same as or similar to the flatness and planarity of the planarized surface of the encapsulant 130.

[0063] A portion of one or more encapsulant layers 180, 230, 280, 380 may form the multilayer encapsulant body 240 (as shown by the dotted lines in FIGS. 4B, 4G, 4H, or 5B) to provide the interlocking structurally reinforced assembly 330. For example, a portion of the second encapsulant 180 may form the multilayer encapsulant body 240. The multilayer encapsulant body 240 may directly contact the first encapsulant 130 through or around one or more of the first conductive layer 154 and at least a portion of the first dielectric layer 160. The multilayer encapsulant body 240 may also directly contact the third encapsulant 230 through or around one or more of the second conductive layer 204 and at least a portion of the second dielectric layer 210. The second encapsulant 180 and the third encapsulant 230 may be formed without a semiconductor chip or additional component 14 disposed therein.

[0064] As shown in Figure 4A, in some cases, layered structures 150, 200, 250 and build-up interconnect structure 300 may collectively include seven to eight conductive metal layers (e.g., seven conductive RDL and one conductive UBM layer 320). Figure 4B is a close-up view of a portion of Figure 4A taken along the detail mark labeled "Figure 4B" in Figure 4A, showing an enlarged view of the same portion.

[0065] As will be appreciated by those skilled in the art (POSA), multiple conductive layers (including simultaneous RDL layers (or vertically stacked and separated layers used within a single assembly)) can depend on the specific materials, equipment, and interconnect design and electrical performance requirements. In some cases, one or more conductive layers (including associated dielectric layers at one or more locations, including adjacent to the top, bottom, and sides of the conductive layer) are used. One or more conductive layers can be part of a single-layer structure (or multi-layer structure) disposed between (or sandwiched between) encapsulant layers. When dielectric layers are adjacent to the sides of the conductive layers, the structure differs from when voids are formed along or laterally offset from the conductive traces, with dielectric formed above and below the traces.

[0066] In other cases, four or more conductive layers (including associated dielectric layers above, below, or both above and below the conductive layer) may be used per conductive layer, used as a single layer structure, or disposed between (or sandwiched between) encapsulant layers. Any desired number of layers and layered structures may be used based on the desired output and necessary constraints (e.g., yield, cost, and performance). Conductive layers (e.g., RDL layers, signal lines, clock lines, traces, ground planes, power planes, shields, inductors, or any other desired conductive structures, or structures comprising conductive and other materials), as well as dielectric layers (e.g., polyimide or other suitable dielectric layers), may have thicknesses ranging from 1 to 20 μm, or 2 to 7 μm thick.

[0067] One to four layers of RDL may be used for each "layered structure." Various copper thicknesses and trace densities may also be accommodated (e.g., 2 μm line-and-space versus 4 μm pitch, or larger pitches up to 200 μm, as well as smaller pitches of 3 μm, 2 μm, or 1 μm). In some cases, for electrical performance reasons (e.g., signal integrity, power drop, or other factors), it is desirable for conductive layers used primarily for ground or power distribution to be thicker than conductive layers used primarily for signal or clock lines; an example is shown in and described with respect to FIG. 5B. Conductive layers can have dielectrics above, below, around, or simultaneously above, below, and around, and are in direct contact with each other. Unit-specific patterning, or customized patterning for fine pitch and other desired applications (i.e., Adaptive Patterning®), may also be used.

[0068] One or more additional conductive layers 154x or 204x may be formed on the first dielectric layer 160, on the second dielectric layer 210, or on both the first dielectric layer 160 and the second dielectric layer 210. One or more of the second encapsulant 180 and the third encapsulant 230 may be formed or disposed on and in direct contact with the one or more additional conductive layers 154x or 204x.

[0069] FIG. 4C shows a close-up view of layered structures 200, 250 and a conventional build-up interconnect structure 300 taken along detail line 4C shown in FIG. 4B. As illustrated, conventional build-up interconnect structure 300 includes dielectric layer 302, or its lower portion 302a, and conductive layer 304, or its lower portion 304. When forming an encapsulant layer (e.g., encapsulants 230 and 280), the encapsulant may include a molding compound placed using a mold. Using a mold allows the top surface of the encapsulant or molding compound to have a flat or planar surface (e.g., 234 or 284). In some cases, the encapsulant may be molded or placed to a desired thickness with the resulting mold surface resulting in a flat or planar top surface of the molding compound, and the flat or planar mold surface may remain after molding to a desired height. In other cases, the encapsulant may be ground away, for example, with a grinder 29, to remove some of the material. 4C also shows conductive stamp 22 formed on and coupled to second conductive layer 204. A third conductive layer 254a is formed on interstitial dielectric layer 266 below a third dielectric lower portion 260a. A third conductive layer upper portion 254b and a third dielectric layer upper portion 260a are also formed thereon as part of third layered structure 250.

[0070] FIG. 4D shows a typical layered structure from a portion of a larger semiconductor assembly 330. By having encapsulant layers between (or interleaved with) one or more conductive and dielectric layers, surface topography changes (as shown in FIGS. 1A-1E) can be limited, stopped, or "reset" by each encapsulant layer (see, e.g., FIG. 7), providing a new planar or flat surface on which subsequent conductive layers are formed, while also improving the electrical properties and performance of conductive layers formed above, below, and around the dielectric layer. In FIG. 4D, the top conductive layers 154b and 204b in layered structures 150 and 200, respectively, are formed with dielectrics 160 and 210 formed below the conductive materials 154b and 204b.

[0071] 4D also shows that an interstitial dielectric layer 216 may be disposed between the first encapsulant 130 and the first conductive layer 154 to provide improved performance for the first conductive layer 154. In some cases, one or more of the first dielectric layer 160, the second dielectric layer 210, and the interstitial dielectric layer 166 comprise polyimide. In other cases, the first conductive layer 154 may be formed directly on or in direct contact with the first encapsulant 130 without the interstitial dielectric layer 166 disposed therebetween, as shown, for example, in FIGS. 5F, 5A, or 5B.

[0072] Figure 4E shows another exemplary layered structure, which differs from that shown in Figure 4D because the top conductive layer 154b in the layered structure 150 is formed with a dielectric 160 formed both below (160a) and above (160b) the conductive material 154b.

[0073] Figure 4F shows another exemplary layered structure, which differs from those shown in Figures 4D and 4E because the bottom (or first) conductive layer 154a in the layered structure 150 is formed directly on the encapsulant or mold compound 130, without an additional interstitial dielectric 166 first being formed directly below or in contact with the conductive layer 154a. An example of a structure or package 330 using such features is shown, for example, in Figure 5A.

[0074] 4G shows that a portion of the second encapsulant 180 passes through or around at least a portion of the first conductive layer 154 and the first dielectric layer 160 to form a multi-layer encapsulant body 240 in direct contact with the first encapsulant 130. Similarly, a portion of the second encapsulant 180 passes through or around at least a portion of the second conductive layer 204 and the second dielectric layer 210 to form a multi-layer encapsulant body 240 in direct contact with the third encapsulant 230. Thus, the multi-layer encapsulant body 240 provides an interlocking encapsulant or mold compound that provides adhesion between vertically separated encapsulant layers or mold compounds.

[0075] In some cases, the top of one or more layered structures may be formed without disposing an encapsulant on the conductive and dielectric layers, or in other words, a conventional build-up interconnect structure 300 may be formed on one or more layered structures 150, 200, 250, or any desired number of layered structures.

[0076] 4H shows another example where the encapsulant 130, 180, 230, 280 extends vertically through the laminations at the package edges, interconnecting the various laminations or dielectric and conductive layers, interlocking the encapsulant or mold compound, and providing adhesion between vertically separated encapsulant or mold compound layers, thereby forming a multi-layer encapsulant body 240.

[0077] 4H further illustrates that package interconnects 322 may be formed on the second layered structure 200, on the planarized top surface 234, and on other subsequently formed layers. The package interconnects 322 may include one or more of solder bumps, LGAs, pins, or BGAs, phased array antennas, or other suitable or desired structures.

[0078] 5A-5B show various views of forming a layered structure including an encapsulant, similar to those shown in FIGS. 4A-4H, in which separate dielectric and conductive layers are formed above or below the encapsulant layer to form the layered structure. FIG. 5A differs from FIG. 4A in that a first conductive layer 154a is formed in direct contact with the encapsulant 130 that encapsulates or is disposed around the semiconductor component 14.

[0079] 5B includes a close-up view of a portion of FIG. 5A. As shown in FIG. 5B, in some cases, the semiconductor assembly 330 may include multiple layer structures 150, 20, 250, which may collectively include nine conductive metal layers (e.g., eight conductive RDLs and one conductive UBM layer 320). Various configuration features may be tailored within the semiconductor assembly 330 to accommodate device requirements and other needs. The dielectric and RDL layer thicknesses may be tailored as needed. Any desired number of layers and layer structures may be used based on the desired output and necessary constraints (e.g., yield, cost, and performance).

[0080] 5B further illustrates a specific example in which the first layered structure 150 may be formed as follows: First, one or more first conductive layers 154 (e.g., bottom conductive layer 154a, middle first conductive layer 154b, and top first conductive layer 154c) may be formed above or directly on the encapsulant 130 and may be formed as a plane 310 (e.g., ground plane 311 or power plane 312). Then, the first dielectric layer 160 may be formed on the bottom first conductive layer 154a. The middle first conductive layer 154b may be formed as a layer thinner than the bottom first conductive layer 154a and may be formed on the first dielectric layer 160. The first conductive layer 154 may include one or more of 154a, 154b, and 154c and may be formed as part of a stripline, as shown by 154b in FIG. 5B, or as a microstrip, differential pair, or impedance-controlled structure for conducting or transmitting signals. The upper first dielectric layer 154c may have a thickness similar to that of the lower first conductive layer 154a, which is greater than the thickness of the middle first conductive layer 154b. Various layers of the first conductive layer 154 may be formed as thicker layers when formed as part of a power plane, ground plane, clock, or clock tree (such as within an RDL as part of a chiplet). The dielectric layer 160 or other dielectric layers may be thinner or thicker to improve or optimize electrical performance based on design and function or specific aspects. Thinner signal line layers (e.g., the middle first conductive layer 154b) may be used to minimize broadside coupling capacitance, and thicker power and ground planes 312 and 311 may be used to minimize power distribution network impedance. Plane 310 (eg, ground plane 311 or power plane 312) may be formed as part of a power plane pair.Although the features of stripline, microstrip, differential pairs, impedance control structures for conducting or transmitting signals, plane 310, ground plane 311, and power plane 312 have been described with respect to conductive layer 154 and first layered structure 150, POSA will recognize that the same or similar features may be formed as part of any other conductive layer and as part of any other layered structure (e.g., second layered structure 200 and third layered structure 250).

[0081] FIG. 6A provides further details on some features. First, FIG. 6A shows an example in which both the dielectric 250 and the encapsulant 280 touch or contact the sidewall 273 of the conductive stamp 270. Further details of this are shown in FIG. 6B. FIG. 6A also shows layered structures on both the front surface 20 and back surface 18 of the component 14 or assembly 330. The first layered structure 150 is coupled to a back surface layered structure 350 through a conductive through-mold vertical interconnect 340. The back surface layered structure or back surface build-up interconnect structure 350 includes a back surface conductive layer 354, which may be similar to the conductive layer 154, and further includes a back surface dielectric, insulating, or passivation layer 360, which may be similar to the dielectric layer 160. The back surface layered structure 350 further includes a conductive stamp 370, which may be similar to the conductive stamp 170. The back surface layered structure 350 also includes a back surface encapsulant layer 380. The backside encapsulant layer 380 may include a flat top surface 384 similar to the second encapsulant 180 and the flat top surface 184, respectively. A backside conventional build-up interconnect structure 390 similar to the conventional build-up interconnect structure 300 may be formed on the backside layered structure 350. The backside conventional build-up interconnect structure 390 may include a dielectric layer 392 and a conductive layer 394.

[0082] Figure 6B shows an enlarged or close-up view of a portion of Figure 6A indicated by detail marker 6B shown in Figure 6A. More specifically, Figure 6B shows that the third dielectric layer 260 can be formed such that an upper portion 260c of the third dielectric layer 260 contacts a lower portion 273a of the sidewall 273 of the conductive stamp 270. Additionally, the fourth encapsulant 280 can contact an upper portion 273b of the sidewall 273 of the conductive stamp 270.

[0083] 7 provides further details regarding how a layered structure (e.g., first layered structure 150) can correct for deformation 510 using an encapsulant (e.g., encapsulant 180), as discussed above. Deformation 510 may be limited or absent in lower first conductive layer 154a and lower first dielectric 160a. Deformation 510 may be present and more pronounced or exaggerated in upper first conductive layer 154b and lower first dielectric 160b by being formed on a patterned portion of lower first conductive layer 154a. A second encapsulant may be formed on first conductive layer 154a, lower first dielectric 160a, first conductive layer 154b, and lower first dielectric 160b to form the top or upper portion of layered structure 150. The lower surface 183 of the second encapsulant 180 includes an undulating contour that follows the deformation 510 of the upper first conductive layer 154b. The flat upper surface 184 of the second encapsulant 180 does not include an undulating contour and is shaped to follow the deformation 510 of the upper first conductive layer 154b or the lower surface 183.

[0084] Considering the difference in thickness of the encapsulant 180 resulting from the contoured lower surface 183 of the second encapsulant 180 and the flat upper surface 184 of the second encapsulant 180, the conductive stamps 170 extending through the second encapsulant 180 also include different heights. By way of example, FIG. 7 shows a lower conductive stamp 170a having a first height H1 and a taller conductive stamp 170b having a second height H2.

[0085] FIG. 8A illustrates a method for manufacturing a semiconductor assembly 400. Element 410 of the method includes providing a semiconductor component including a first encapsulant disposed around the semiconductor component. Element 414 of the method includes forming a first layered structure including a first dielectric layer, a conductive layer, and an encapsulant disposed on the dielectric and conductive layers. Element 415 of the method includes planarizing a top surface of the second encapsulant of the first layered structure. Element 416 of the method includes forming a second layered structure including a second dielectric layer, a second conductive layer, and a third encapsulant disposed on the second dielectric and second conductive layers. Element 417 of the method includes planarizing a top surface of the third encapsulant of the second layered structure.

[0086] 8B further illustrates additional elements that may optionally be included in the method of manufacturing semiconductor assembly 400. Element 420 of the method includes forming a multi-layer encapsulant body as part of one or more of the layered structures. Element 422 of the method includes forming a second encapsulant and a third encapsulant without a semiconductor chip disposed therein.

[0087] While the present disclosure includes numerous embodiments in different forms, it is understood that the specific embodiments presented are to be considered as illustrative of the principles of the disclosed structures, devices, methods, and systems, and are not intended to limit the broad aspects of the disclosed concepts to the illustrated embodiments. As a POSA would understand, many further implementations or variations are possible. Moreover, a POSA would understand that other structures, manufacturing arrangements, and examples can be mixed and substituted for those provided. Where the foregoing description refers to specific embodiments, it should be readily apparent that many changes can be made without departing from the spirit thereof, and that these embodiments and implementations can be applied to other technologies. Accordingly, the disclosed subject matter is intended to embrace all such changes, modifications, and variations that are within the spirit and scope of the disclosure and the knowledge of those skilled in the art. It is therefore apparent that various modifications and changes can be made without departing from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the drawings and specification are to be regarded in an illustrative, and not a restrictive, sense.

Claims

1. 1. A method of manufacturing a semiconductor assembly, comprising: providing a semiconductor component, the semiconductor component including a conductive stud, the conductive stud formed on and coupled to a front surface of the semiconductor component; providing a first encapsulant disposed around and in contact with at least four sides of the semiconductor component, disposed on the front surface of the semiconductor component, and disposed in contact with at least a portion of a side of the conductive stud; forming a first layered structure as a build-up interconnect structure on the encapsulant and on the semiconductor component, the forming of the first layered structure comprising: forming a first conductive layer including a redistribution layer (RDL), the redistribution layer disposed on the first encapsulant and coupled to the conductive stud; forming a first dielectric layer on the first conductive layer; forming a conductive stamp coupled to the first conductive layer and exposed to the first dielectric layer; disposing a second encapsulant over the first conductive layer, the first dielectric layer, and the conductive stamp; planarizing a top surface of the second encapsulant to expose the conductive stamp and form a flat top surface for forming additional structures; forming a forming a second layered structure on the first layered structure and on the planar upper surface as a build-up interconnect structure, wherein improving the planarity of the second layered structure and forming the second layered structure includes: forming a second conductive layer on the first layered structure; forming a second dielectric layer disposed on the second conductive layer; forming a third encapsulant, the third encapsulant including a planarized upper surface disposed on the second conductive layer and the second dielectric layer; forming a Including, A portion of the second sealing material is at least a portion of the first conductive layer and the first dielectric layer for direct contact with the first encapsulant; and at least a portion of the second conductive layer and the second dielectric layer for direct contact with the third encapsulant; forming a multi-layer encapsulant body through or around one or more of the second encapsulant and the third encapsulant are formed without disposing a semiconductor chip therein; method.

2. The method of claim 1 , wherein an interstitial dielectric layer is disposed between the first encapsulant and the first conductive layer.

3. The method of claim 2 , wherein one or more of the first dielectric layer, the second dielectric layer, and the gap dielectric layer comprises polyimide.

4. The method of claim 1 , wherein the first conductive layer is formed directly on the first encapsulant without an interstitial dielectric layer.

5. 10. The method of claim 1, further comprising forming package interconnects on the second layered structure and on the planarized top surface, the package interconnects comprising one or more of solder bumps, pins, a land grid array (LGA), or a ball grid array (BGA).

6. forming one or more additional conductive layers on the first dielectric layer, on the second dielectric layer, or on both the first and second dielectric layers; forming one or more of the second encapsulant and the third encapsulant on and in direct contact with the one or more additional conductive layers; The method of claim 1 further comprising:

7. A portion of the second sealing material is at least a portion of the first conductive layer and the first dielectric layer for direct contact with the first encapsulant; and at least a portion of the second conductive layer and the second dielectric layer for direct contact with the third encapsulant; The method of claim 1 , further comprising forming a multi-layer encapsulant body through or around one or more of:

8. forming the first dielectric layer such that a portion of the first dielectric layer contacts a lower portion of a sidewall of the conductive stamp; disposing the second encapsulant layer such that a portion of the second encapsulant layer contacts an upper portion of the sidewall of the conductive stamp; The method of claim 1 further comprising:

9. The method of claim 1 , further comprising forming a backside layer structure on a backside of the semiconductor component.

10. 1. A method of manufacturing a semiconductor assembly, comprising: providing a semiconductor component disposed within a first encapsulant, the encapsulant being disposed around and in contact with at least four sides of the semiconductor component and on a front surface of the semiconductor component; forming a first layered structure as a build-up interconnect structure on the encapsulant and on the semiconductor component, the forming of the first layered structure comprising: forming a first conductive layer, the first conductive layer including a redistribution layer (RDL), the redistribution layer disposed on the first encapsulant and coupled to the semiconductor component; forming a first dielectric layer on the first conductive layer; forming a conductive stamp coupled to the first conductive layer; disposing a second encapsulant over the first conductive layer, the first dielectric, and the conductive stamp; planarizing a top surface of the second encapsulant to expose the conductive stamp and form a flat top surface for forming additional structures; forming a forming a second layered structure on the first layered structure and on the planar upper surface as a build-up interconnect structure, wherein forming the second layered structure includes: forming a second conductive layer on the first layered structure; forming a second dielectric disposed on the second conductive layer; forming a third encapsulant, the third encapsulant including a planarized upper surface disposed on the second conductive layer and the second dielectric; forming a A method comprising:

11. A portion of the second sealing material is at least a portion of the first conductive layer and the first dielectric for direct contact with the first encapsulant; and at least a portion of the second conductive layer and the second dielectric for direct contact with the third encapsulant; 11. The method of claim 10, further comprising forming a multi-layer encapsulant body through or around one or more of:

12. the semiconductor component includes a chip, the chip includes a conductive stud, the conductive stud is formed on and coupled to the front surface of the semiconductor component; the encapsulant contacts the sides of the conductive stud; The method of claim 10.

13. The method of claim 10 , wherein an interstitial dielectric is disposed between the first encapsulant and the first conductive layer.

14. The method of claim 10 , wherein the first conductive layer is formed directly on the first encapsulant without an interstitial dielectric.

15. The method of claim 10 , wherein the first layered structure and the second layered structure each include a RDL.

16. forming one or more additional conductive layers on the first dielectric layer, on the second dielectric layer, or on both the first and second dielectric layers; forming one or more of the second encapsulant and the third encapsulant on and in direct contact with the one or more additional conductive layers; The method of claim 10 further comprising:

17. The method of claim 10 , wherein the second encapsulant and the third encapsulant are formed without a semiconductor chip disposed therein.

18. forming the first dielectric such that a portion of the first dielectric contacts a lower portion of a sidewall of the conductive stamp; disposing the second encapsulant layer such that a portion of the second encapsulant layer contacts an upper portion of the sidewall of the conductive stamp; The method of claim 10 further comprising:

19. The method of claim 10 , further comprising forming a backside layer structure on a backside of the semiconductor component.

20. forming a lower surface of the second encapsulant including an undulating contour that conforms to deformation of the first conductive layer; forming the flat upper surface of the second encapsulant to be free of contours and to not follow the deformation of the first conductive layer; The method of claim 10 further comprising:

21. 1. A method of manufacturing a semiconductor assembly, comprising: providing a semiconductor component disposed within a first encapsulant, the encapsulant being disposed around and in contact with at least four sides of the semiconductor component and on a front surface of the semiconductor component; forming a first layered structure as a build-up interconnect structure on the encapsulant and on the semiconductor component, the forming of the first layered structure comprising: forming a first conductive layer on the first encapsulant; forming a first dielectric layer on the first conductive layer; disposing a second encapsulant over the first conductive layer and over the first dielectric; planarizing a top surface of the second encapsulant to form a flat surface for forming additional structures; forming a A method comprising:

22. 22. The method of claim 21, wherein an interstitial dielectric is disposed between the first encapsulant and the first conductive layer.

23. 22. The method of claim 21, wherein the first conductive layer is formed directly on the first encapsulant without an interstitial dielectric.

24. forming a second layered structure as a build-up interconnect structure on the first layered structure and on the planar surface to improve planarity of the second layered structure; further comprising the first layered structure and the second layered structure each include a redistribution layer (RDL); 22. The method of claim 21.

25. 22. The method of claim 21, further comprising forming package interconnects on the first layered structure and on the planar surface, the package interconnects comprising one or more of solder bumps, pins, a land grid array (LGA), or a ball grid array (BGA).

26. forming a second layered structure, the second layered structure comprising: a second conductive layer disposed on the first layered structure; a second dielectric disposed on the second conductive layer; either a third encapsulant including a planarized top surface disposed on the second conductive layer and the second dielectric, or a third dielectric including a via disposed on the second conductive layer and the second dielectric such that the second layered structure does not include an encapsulant; 22. The method of claim 21, comprising:

27. forming a second conductive layer on the first dielectric; forming the second encapsulant on and in direct contact with the second conductive layer; 22. The method of claim 21, further comprising:

28. 27. The method of claim 26, wherein the second encapsulant and the third encapsulant are formed without a semiconductor chip disposed therein.

29. A portion of the second sealing material is at least a portion of the first conductive layer and the first dielectric for direct contact with the first encapsulant; and at least a portion of the second conductive layer and the second dielectric for direct contact with the third encapsulant; 27. The method of claim 26, further comprising forming a multi-layer encapsulant body through or around one or more of:

30. forming a conductive stamp coupled to the first conductive layer; forming the first dielectric such that a portion of the first dielectric contacts a lower portion of a sidewall of the conductive stamp; disposing the second encapsulant layer such that a portion of the second encapsulant layer contacts an upper portion of the sidewall of the conductive stamp; 22. The method of claim 21, further comprising:

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