Method for manufacturing a multilayer structure including a porous silicon layer - Patents.com

Abstract

The invention relates to a process for manufacturing a multilayer structure, comprising the following steps: providing a carrier substrate (40) comprising a carrier layer (41) and a porous silicon layer (42); providing a donor substrate (50) comprising a buried plane of weakness (50B) and a surface layer (51); assembling (S3) the carrier substrate (40) and the donor substrate (50) by bonding, the surface layer (51) of the donor substrate being placed in contact with the carrier substrate; Separating the surface layer (51) from the donor substrate (50) via fracture along a buried plane of weakness (50B); and providing a degraded portion (60) so as to prevent at least one of the carrier substrate and the donor substrate (40, 50), referred to as the degraded substrate, from being bonded to the other of the carrier substrate and the donor substrate (50, 40) in an assembly step, the degraded portion (60) having a ring or substantially ring shape and located less than 25 mm from an edge of said degraded substrate.

Description

[Technical Field]

[0001] The technical field of the invention is that of semiconductor materials for microelectronic components. The invention relates in particular to multilayer structures adapted for high performance radio frequency applications and including a buried porous silicon layer. [Background technology]

[0002] Radio frequency (RF) integrated circuits are widely used in telecommunications (e.g., cell phones, Wi-Fi, Bluetooth). These circuits are formed on substrates (also called wafers) that primarily serve as a support for their fabrication. As the integration and performance of RF circuits increase, there is an ever-increasing coupling between the performance of the RF circuits and the properties of the substrates on which they are formed.

[0003] As an example of circuit-to-board coupling, the electromagnetic fields from high frequency signals propagating through RF circuits penetrate deep into the board and interact with charge carriers located within the board, causing problems such as nonlinear distortion of the signal (harmonics), unnecessary dissipation of some of the signal energy due to insertion loss, and possible circuit-to-circuit influences.

[0004] Radio frequency (RF) circuits such as RF signal transceiver modules (so-called "front-end" modules), antenna switches and adapters, power amplifiers, etc. can be fabricated on a variety of substrate types.

[0005] FIG. 1 shows a multilayer structure 10 that is derived from a silicon-on-insulator (SOI) multilayer structure and that can be generally used in the fabrication of RF integrated circuits.

[0006] This multilayer structure 10, called "TR-SOI," comprises, in order, a support layer 11 of high-resistivity silicon (>1 kΩ.cm), a charge-trapping layer 12 (also called a trap-rich layer), a buried oxide layer 13, and an active layer 14 of monocrystalline silicon. The trapping layer 12 prevents parasitic conduction at the interface between the support layer 11 and the buried oxide layer 13, which is typically caused by free electrons accumulating at the interface under the influence of fixed positive charges contained in the buried oxide layer 13. Due to the trapping layer 12, the electrons are trapped and can no longer circulate. Therefore, the effective resistivity of the support layer 11 increases relative to a multilayer structure without a trapping layer (called "HR-SOI"). The trapping layer 12 can be composed of polycrystalline silicon. The traps are located at the grain boundaries of the polycrystalline silicon.

[0007] The combination of high resistivity support layer 11 and trapping layer 12 reduces exemplary circuit-to-substrate coupling, thereby significantly improving the RF performance, particularly in terms of linearity and crosstalk, of integrated circuits fabricated from multi-layer structure 10. Passive elements (inductors, capacitors, etc.) formed on active layer 14 can achieve a higher quality factor as a result.

[0008] However, substrates provided with polycrystalline silicon trapping layers have RF performance that deteriorates with increasing operating temperature. Indeed, polycrystalline silicon has the drawback of undergoing partial recrystallization during thermal treatment steps at high temperatures, which contributes to a reduction in the trap density within the layer.

[0009] FIG. 2 schematically represents another multilayer structure 20 adapted for radio frequency applications and described in document WO2021 / 001066A1.

[0010] The multilayer structure 20 comprises a support layer 21 of silicon (resistivity 0.5 Ω.cm-4 Ω.cm), a porous silicon layer 22 disposed on the support layer 21, a dielectric layer 23 (e.g. a layer of silicon oxide) disposed on the porous silicon layer 22, and an active layer 24 (e.g. a layer of silicon), also referred to as a surface layer, disposed on the dielectric layer 23.

[0011] The method for producing this multi-layer structure 20 comprises: - providing a silicon support substrate; - porosifying a portion of the support substrate to form a porous silicon layer 22; - depositing a dielectric layer 23 on the porous silicon layer 22; - providing a donor substrate with embedded brittle planes that delimit the surface layer 24; - assembling a donor substrate on the dielectric layer by disposing a surface layer 24 in contact with the dielectric layer 23; a separation step along the buried brittle plane to transfer the surface layer 24 onto the dielectric layer 23; one or more heat treatment steps aimed at improving the crystalline quality of the surface layer 24 or its surface condition (roughness, defect condition) This particularly includes:

[0012] However, surface layer 24 may crack during the separation step and / or the final substrate formed by multi-layer structure 20 may warp excessively after the separation step, especially during thermal treatment steps, such defects rendering the substrate unusable for RF circuit fabrication. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] International Publication No. 2021 / 001066 Summary of the Invention [Problem to be solved by the invention]

[0014] The aim of the present invention is to reduce the risk of cracking when transferring a surface layer from a donor substrate onto a support substrate comprising a porous silicon layer and to limit the bending phenomenon of the multilayer structure thus obtained. [Means for solving the problem]

[0015] According to the present invention, this object tends to be achieved by providing a method for producing a multi-layer structure, said method comprising: - providing a support substrate comprising a support layer and a porous silicon layer disposed on the support layer; - providing a donor substrate having a first surface, a buried brittle plane, and a surface layer bounded by the first surface and the buried brittle plane; - assembling the support substrate and the donor substrate by bonding, wherein the surface layer of the donor substrate is disposed in contact with the support substrate; - separating the surface layer from the donor substrate by fracturing along the buried brittle plane; Includes.

[0016] This manufacturing method is notable in that at least one of the support substrate and the donor substrate, called the depleted substrate, is provided with a depleted portion that prevents it from being bonded to the other of the support substrate and the donor substrate during the assembly step, the depleted portion having a ring shape or a substantially ring shape and located less than 25 mm from a side of the depleted substrate, preferably less than 5 mm from a side of the depleted substrate.

[0017] In some implementations of the manufacturing method, the support substrate further comprises a peripheral non-porous silicon portion disposed around the porous silicon layer, and the degraded portion is located in vertical alignment with the interface between the peripheral non-porous silicon portion and the porous silicon layer upon assembly of the support substrate and the donor substrate.

[0018] In another implementation, the porous silicon layer comprises a central portion having a substantially constant first thickness and a peripheral portion having a second thickness that increases toward a side of the support substrate, and the degraded portion is located vertically aligned with a transition between the central and peripheral portions of the porous silicon layer upon assembly of the support substrate and the donor substrate.

[0019] In another implementation, the support substrate further comprises a peripheral non-porous silicon portion disposed around the porous silicon layer, and the degraded portion comprises a cavity extending into the porous silicon layer and located less than 2 mm from the interface between the peripheral non-porous silicon portion and the porous silicon layer, the cavity being advantageously filled with a material having a Young's modulus lower than that of the porous silicon.

[0020] In addition to the characteristics described in the paragraphs above, the manufacturing method according to the invention may have one or more additional characteristics from the following, individually or according to any technically possible combination: - the degraded portion extends further to the side of said degraded substrate; - the degraded portion is spaced from a side of said degraded substrate and has a width between 10 μm and 4 mm; - The deteriorated area consists of a recessed area; - the concave part belongs to the donor substrate; - the step of providing a donor substrate comprises the step of implanting light ions into the first substrate at an implantation depth to form a buried brittle plane, and the recessed portion is obtained by forming a cavity having a depth greater than the implantation depth; - the concave part belongs to the supporting substrate; - The deteriorated area consists of textured areas with a surface roughness of 1 nm or more; - The deteriorated area consists of a chamfered area; the support substrate further comprises a dielectric layer disposed on the porous silicon layer; the degraded portion is substantially annular and the degraded substrate comprises a so-called non-degraded portion located as an extension of the degraded portion, said non-degraded portion being bonded to the other of the support substrate and the donor substrate during the assembly step.

[0021] Further characteristics and advantages of the present invention will become clearly apparent from the description that follows, given for purposes of no limitation and with reference to the accompanying drawings, in which: FIG. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a diagram illustrating a prior art multi-layer structure that can be used as a starting substrate for the manufacture of radio frequency integrated circuits, as described above. [Figure 2] 1A and 1B are diagrams illustrating another prior art multilayer structure adapted for the manufacture of radio frequency circuits, as described above. [Figure 3A] 1A and 1B are diagrams illustrating a first implementation of a method for manufacturing a multilayer structure according to the present invention. [Figure 3B] 1A and 1B are diagrams illustrating a first implementation of a method for manufacturing a multilayer structure according to the present invention. [Figure 3C] 1A and 1B are diagrams illustrating a first implementation of a method for manufacturing a multilayer structure according to the present invention. [Figure 4A] 10A and 10B are diagrams illustrating a second implementation of the multilayer structure manufacturing method. [Figure 4B] 10A and 10B are diagrams illustrating a second implementation of the multilayer structure manufacturing method. [Figure 4C] 10A and 10B are diagrams illustrating a second implementation of the multilayer structure manufacturing method. [Figure 5A] 10A and 10B are diagrams illustrating a third implementation of a multilayer structure manufacturing method. [Figure 5B] 10A and 10B are diagrams illustrating a third implementation of a multilayer structure manufacturing method. [Figure 5C] 10A and 10B are diagrams illustrating a third implementation of a multilayer structure manufacturing method. [Figure 6A] FIG. 10 is a diagram illustrating a fourth implementation of the multilayer structure manufacturing method. [Figure 6B] FIG. 10 is a diagram illustrating a fourth implementation of the multilayer structure manufacturing method. [Figure 6C] FIG. 10 is a diagram illustrating a fourth implementation of the multilayer structure manufacturing method. [Figure 7A] FIG. 10 is a diagram illustrating a fifth implementation of the multilayer structure manufacturing method. [Figure 7B] FIG. 10 is a diagram illustrating a fifth implementation of the multilayer structure manufacturing method. [Figure 7C] FIG. 10 is a diagram illustrating a fifth implementation of the multilayer structure manufacturing method. [Figure 8A] FIG. 10 is a diagram showing a sixth implementation of the multilayer structure manufacturing method. [Figure 8B]FIG. 10 is a diagram showing a sixth implementation of the multilayer structure manufacturing method. [Figure 8C] FIG. 10 is a diagram showing a sixth implementation of the multilayer structure manufacturing method. [Figure 9A] FIG. 10 is a diagram showing a seventh implementation of the multilayer structure manufacturing method. [Figure 9B] FIG. 10 is a diagram showing a seventh implementation of the multilayer structure manufacturing method. [Figure 9C] FIG. 10 is a diagram showing a seventh implementation of the multilayer structure manufacturing method. [Figure 10A] 1A-1C illustrate implementations of the step of providing a support substrate comprising a porous silicon layer. [Figure 10B] 1A-1C illustrate implementations of the step of providing a support substrate comprising a porous silicon layer. [Figure 10C] 1A-1C illustrate implementations of the step of providing a support substrate comprising a porous silicon layer. [Figure 11] 1 is a diagram illustrating a major surface of a substrate including a substantially annular degradation zone; DETAILED DESCRIPTION OF THE INVENTION

[0023] For greater clarity, identical or similar elements will be identified with the same reference symbols throughout the figures.

[0024] 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, and 9A-9C show different implementations of a method for manufacturing a multilayer structure 30. The multilayer structure 30 is intended to serve as a support for the manufacture of microelectronic components, in particular radio frequency (RF) integrated circuits. The multilayer structure thus forms a wafer.

[0025] These figures represent cross-sectional views of only a portion of the multilayer structure 30 and the substrates 40, 50 required for its production. The multilayer structure 30 and the substrates 40, 50 each comprise two main faces (commonly called the front and rear faces), e.g., disc-shaped, which extend perpendicular to the cross-section of the figure. Furthermore, the multilayer structure 30 and the substrates 40, 50 advantageously have a plane of symmetry depicted by a dashed dotted line (and passing through the centers of the two main faces).

[0026] As is common to all implementations, the method for manufacturing the multi-layer structure 30 includes the following steps S1 to S4: - S1: providing a support substrate 40 including a support layer 41 and a porous silicon layer 42 disposed on the support layer 41 (see [FIGS. 3A], [FIGS. 4A], [FIGS. 5A], [FIGS. 6A], [FIGS. 7A], [FIGS. 8A] and [FIGS. 9A]); - S2: Providing a donor substrate 50 having a first surface 50A, a buried brittle plane 50B, and a surface layer 51 separated by the first surface 50A and the buried brittle plane 50B (see [Figures 3A], [Figures 4A], [Figures 5A], [Figures 6A], [Figures 7A], [Figures 8A] and [Figures 9A]); - S3: Assembling the support substrate 40 and the donor substrate 50 by bonding, wherein the surface layer 51 of the donor substrate 50 is disposed in contact with the support substrate 40 (see [FIGS. 3B], [FIGS. 4B], [FIGS. 5B], [FIGS. 6B], [FIGS. 7B], [FIGS. 8B] and [FIGS. 9B]); S4: Separating the surface layer 51 from the donor substrate 50 by fracturing along the buried brittle plane 50B (see [Figures 3C], [Figures 4C], [Figures 5C], [Figures 6C], [Figures 7C], [Figures 8C] and [Figures 9C]).

[0027] The multi-layer structure 30 comprising the porous silicon layer 42 is adapted for radio frequency applications aimed at: - Low insertion loss (low signal attenuation) and good linearity (low signal distortion leading to harmonics); - temperature stability, especially in the range of use of RF integrated circuits [-40°C to 150°C], even up to 225°C; - Low capacitive coupling between the RF integrated circuit and the support layer 41 due to the dielectric constant of the dielectric being typically lower than that of silicon.

[0028] The support layer 41 of the support substrate 40 is intended to ensure the mechanical strength of the multilayer structure 30 and to allow it to be handled in particular during the manufacturing steps of microelectronic components. Its thickness may be between 500 μm and 1 mm. The support layer 41 is preferably made of silicon. Advantageously, the silicon of the support layer 41 has an electrical resistivity between 5 mΩ.cm and 20 Ω.cm, preferably between 0.5 Ω.cm and 4 Ω.cm.

[0029] The porous silicon layer 42 comprises hollow pores, the diameter of which is preferably between 2 nm and 50 nm. Hollow pores refer to pores that are not completely filled with a solid material. The inner walls of the pores are advantageously lined with an oxide, for example silicon dioxide (SiO2). The fact that the inner walls of the pores are lined with an oxide reflects a stabilized state of the porous silicon layer 42, in which dangling bonds of the Si-Hx type have been mainly replaced by much more stable Si-O-Si bonds. This improves the mechanical stability of the porous silicon layer 42.

[0030] Advantageously, the porosity of the porous silicon layer 42 is between 40% and 70%. This level of porosity ensures a good balance between the mechanical and electrical properties of the porous silicon layer 42.

[0031] The porous silicon layer 42 advantageously has a resistivity greater than 20 kΩ.cm.

[0032] The thickness of the porous silicon layer 42 is preferably between 5 μm and 50 μm. The thickness of the porous silicon layer 42, in combination with its morphology (pore size, porosity), determines the mechanical strength of the porous silicon layer 42.

[0033] 3A, 4A, 5A, 6A, 7A, 8A, and 9A, step S1 of providing a support substrate 40 may include a substep of porosifying a surface portion of the first silicon substrate. The surface portion (or layer) refers to a portion (layer) extending from the (main) surface of the first substrate. The porosified portion of the first substrate constitutes a porous silicon layer 42, while the remaining non-porosified portion of the first substrate constitutes a support layer 41.

[0034] The porosification step is generally carried out electrochemically or photoelectrochemically. It is based on the anodic dissolution of silicon from the first substrate in an acidic medium. For example, the first substrate is immersed in a hydrofluoric acid (HF)-based solution. The first substrate is in contact with an anode, and a cathode is placed on the first substrate opposite the surface to be porosified.

[0035] Porosification devices come in various configurations. The most common configurations are called "single cell" and "double cell." In the first case, only one side of the first substrate is in contact with the acidic medium. In the second case, both sides of the first substrate are in contact with the acidic medium, which may contain the same solution on both sides or two different solutions.

[0036] In one alternative implementation, only the surface portion of the first substrate (the portion to be made porous) is silicon, while the remaining portion of the first substrate is intended to form the support layer 41 and may consist of another material (semiconductor or non-semiconductor).

[0037] After this porosification substep, step S1 of providing a support substrate 40 advantageously comprises a substep of annealing the porous silicon layer 42 in an oxidizing atmosphere at a temperature between 300° C. and 400° C. to stabilise the porous silicon layer 42. Preferably, the duration of the annealing in the oxidizing atmosphere is between 5 and 200 minutes.

[0038] This annealing allows the dangling bonds of Si-Hx type, especially those present on the inner walls of the pores, to be mainly replaced by much more stable Si-O-Si bonds.

[0039] Advantageously, the annealing in an oxidizing atmosphere is followed by an annealing in a neutral atmosphere, for example nitrogen, at a temperature between 400° C. and 450° C., for example 420° C. The annealing in a neutral atmosphere usually lasts between 2 and 16 hours, for example 10 hours.

[0040] Annealing in a neutral atmosphere avoids outgassing, in particular during subsequent thermal treatments applied to the multilayer structure 30, which may degrade the quality of said structure. Furthermore, annealing in a neutral atmosphere tends to stabilize the curvature of the support substrate 40 on which the porous silicon layer 42 is provided, limiting the phenomenon of curvature of the multilayer structure 30 after these thermal treatments.

[0041] Finally, step S1 of providing the support substrate 40 may include a sub-step of forming a dielectric layer 43 on the porous silicon layer 42. The dielectric layer 43 is an electrically insulating layer. It may be made of a nitride such as silicon nitride (Si3N4) or an oxide such as silicon dioxide (SiO2) or aluminum oxide (Al2O3). Its thickness may be between 200 nm and 2 μm.

[0042] Dielectric layer 43 can be formed by chemical vapor deposition techniques such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or even high density plasma chemical vapor deposition (HDP-CVD).

[0043] 3A, 4A, 5A, 6A, 7A, 8A, and 9A, at least one so-called "active" portion of the surface layer 51 of the donor substrate 50 is formed of a material selected from silicon, germanium, silicon carbide, piezoelectric materials (e.g., LiNbO3, LiTaO3, etc.), binary, ternary, or quaternary alloys of IV-IV system (e.g., SiGe), III-V, or II-VI system semiconductor materials. The surface layer 51 is intended to be transferred onto the support substrate 40, and its active portion is intended to receive active components, such as transistors, during the fabrication of microelectronic components from the multilayer structure 30. The thickness of the active portion is preferably between 50 nm and 1.5 μm.

[0044] The surface layer 51 can be formed by a thin film (50 nm-1.5 μm) of piezoelectric or semiconducting material (silicon, germanium, silicon carbide, IV-IV, III-V or II-VI alloys, etc.), intrinsic or doped (see FIGS. 3A, 4A, 5A, 6A and 9A). It is then fully intended to receive the active components. This is also known as the active layer.

[0045] Alternatively, the surface layer 51 may be formed of a stack of several sublayers (see Figures 7A and 8A), for example a stack comprising an active sublayer 511 of piezoelectric or semiconductor material (whose thickness may be between 50 nm and 1.5 μm) and a dielectric sublayer 512 (whose thickness may be between 50 nm and 500 nm) disposed on the active sublayer 511.

[0046] Step S2 of providing a donor substrate 50 preferably includes the substep of forming a buried brittle plane 50B in a second substrate, which is preferably made of a material selected from silicon, germanium, silicon carbide, piezoelectric materials (e.g., LiNbO3, LiTaO3, etc.), and binary, ternary, or quaternary alloys of IV-IV (e.g., SiGe), III-V, or II-VI semiconductor materials.

[0047] The buried brittle plane 50B is advantageously formed by implanting light ions through the first surface of the second substrate. The ions are implanted into the second substrate at a given implantation depth measured from the first surface of the second substrate. The implantation depth may be between 50 nm and 1.5 μm, for example 400 nm. Light ions herein refer to ions of chemical species with an atomic number of 5 or less. The light ions are preferably hydrogen or helium ions, which aid in the formation of microcavities around the implantation depth and facilitate the Smart Cut process. TM The buried brittle plane 50B is created as described in the method for manufacturing SOI substrates known as .

[0048] Before or after the implantation substep, step S2 of providing the donor substrate 50 may also include depositing a dielectric sublayer 512 (see Figures 7A and 8A) on the first surface of the second substrate (this dielectric sublayer 512 forms part of the surface layer 51).

[0049] Steps S3 and S4, described below, relate to the transfer of surface layer 51 from donor substrate 50 to support substrate 40.

[0050] Step S3 of assembling support substrate 40 and donor substrate 50 includes bonding donor substrate 50 on its first surface 50A to support substrate 40. This assembling step S3 is also referred to as a step of transferring donor substrate 50 onto support substrate 40.

[0051] In a preferred implementation of assembly step S3 shown in FIGS. 3B, 4B, 5B, 6B and 9B, surface layer 51 of donor substrate 50 is contacted with dielectric layer 43 of support substrate 40.

[0052] 7B, the surface layer 51 comprises a dielectric sub-layer 512 thereon in contact with the dielectric layer 43 of the support substrate 40. The dielectric sub-layer 512 of the donor substrate 50 and the dielectric layer 43 of the support substrate 40 are advantageously formed of the same dielectric material, preferably an oxide (e.g., SiO2).

[0053] Finally, in an alternative implementation depicted in FIG. 8B, the support substrate 40 does not include the dielectric layer 43, and the surface layer 51 comprises a dielectric sub-layer 512 on its surface that contacts the porous silicon layer 42 of the support substrate 40.

[0054] Assembling the support substrate 40 and the donor substrate 50 can be achieved by any known bonding technique, preferably by molecular adhesive direct bonding. This technique will not be described in detail herein. Nevertheless, it should be noted that prior to bonding, the support substrate 40 and the donor substrate 50 preferably undergo a series of cleaning and / or surface activation treatment steps to ensure the quality of the bonding interface in terms of defectivity and bonding energy. Furthermore, the support substrate 40 and the donor substrate 50 preferably undergo a polishing step (e.g., by chemical mechanical planarization, i.e., CMP) of their bonding surfaces to obtain a surface roughness strictly lower than 0.7 nm. This roughness value, as well as all values ​​presented below, is expressed as a root-mean-square value. The root-mean-square roughness (denoted Rq) is determined by statistical analysis of atomic force microscope images and is measured on a 1 × 1 μm sample. 2 Take the surface area of

[0055] Step S4 of separating the surface layer 51 by fracturing along the buried brittle plane 50B makes it possible to separate the surface layer 51 from the donor substrate 50, thus obtaining on the one hand the multilayer structure 30 and on the other hand the remainder of the donor substrate 50, which can be reused to transfer another surface layer during a new iteration of the manufacturing method.

[0056] Preferably, step S4 of separating the surface layer 51 comprises a heat treatment. For the silicon surface layer 51 (or active sub-layer 511), this heat treatment is carried out at a temperature between 200° C. and 500° C., preferably between 350° C. and 450° C. Such a heat treatment can increase the embrittlement level of the buried brittle plane 50B, and this phenomenon is the basis of Smart Cut TM It is at the heart of the method.

[0057] A temperature of around 400° C. is advantageous in that the assembly is subjected to less mechanical stress due to the different expansion coefficients of the materials comprising support substrate 40 and donor substrate 50. In fact, excessively high stresses can affect the integrity of porous silicon layer 42.

[0058] After the separation step S4, the method for producing the multilayer structure 30 may include one or more heat treatment steps to improve the crystalline quality and / or surface condition (roughness, defect state) of the surface layer 51 (so-called finish annealing of the surface layer 51) or to solidify the bonding interface (so-called interface solidification annealing).

[0059] In the implementations of Figures 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, and 8A-8C, the support substrate 40 further includes a non-porous silicon (or bulk silicon) peripheral portion 44 disposed around the porous silicon layer 42. In other words, the porous silicon layer 42 does not extend to the sides of the support substrate 40. This is particularly true when a "dual cell" type porosification device is used to form the porous silicon layer 42 (the peripheral seal is placed on the side of the first substrate that contacts the acidic medium). The non-porous silicon peripheral portion 44 has a width L1 ranging from 1 mm to 5 mm (e.g., depending on the device used). The width of a portion of a substrate herein refers to the dimension of this portion measured along the radius of the substrate. The thickness of the peripheral portion 44 is equal to the thickness of the porous silicon layer 42.

[0060] The peripheral portion 44 of non-porous silicon tends to reduce the curvature of the multi-layer structure 30 during subsequent heat treatment steps (steps for finishing the surface layer 51 or for manufacturing the component), but it also contributes to arc-shaped cracks that may appear in the surface layer 51 during the separation step S4.

[0061] The separation of the surface layer 51 is the result of the propagation of at least one spallation wave in the buried brittle plane 50B. The spallation wave initiates at a point on the buried brittle plane 50B, usually at an edge (usually circular), and in the case described herein, the spallation wave propagates in all directions across the buried brittle plane 50B at different speeds due to the heterogeneous composition of the underlying support substrate 40. Specifically, the spallation wave propagates much faster over non-porous silicon than over porous silicon, which absorbs more of the spallation energy. This is the cause of the observed cracks.

[0062] To significantly reduce the risk of cracking of the surface layer 51 during the separation step S4, at least one of the support substrate 40 and the donor substrate 50 comprises a degraded portion 60 that is configured not to be bonded to the other of the support substrate 40 and the donor substrate 50 during the assembly step S3. Thus, bonding of the support substrate 40 and the donor substrate 50 is only partial (i.e., occurs outside of one or more degraded portions 60). A substrate comprising a degraded portion 60 will hereinafter be referred to as a degraded substrate.

[0063] Due to the local absence of bonding between the support substrate 40 and the donor substrate 50, a crack (at the buried brittle plane 50B) facing the degraded portion 60 cannot be realized due to the lack of reinforcement. In this way, the surface layer 51 of the donor substrate 50 is not transferred to the support substrate 40 facing the degraded portion 60.

[0064] The degraded portion 60 has an annular or substantially annular shape. The term "substantially annular" refers to a segment of a ring having a circumference (outer circumference) that is 90% or more of the circumference of the ring (as a whole). It also refers to several segments of the same ring whose total circumference is 90% or more of the circumference of the ring.

[0065] 3A-3C, the depleted substrate is the donor substrate 50. In other words, the depleted portion 60 belongs to the donor substrate 50. It is located in vertical alignment with the interface between the porous silicon layer 42 and the peripheral non-porous silicon portion 44 in the assembly of the substrates 40 and 50 (in other words, the vertical projection of the interface passes through the depleted portion 60). It further extends to the side of the depleted substrate (hereinafter, the donor substrate 50).

[0066] The degraded portion 60 in Figures 3A-3C is formed by a recessed portion relative to the first surface 50A of the donor substrate 50. This recessed portion, also called a recessed portion, is obtained by forming a (circular or substantially circular) cavity in the donor substrate 50 from the first surface 50A (see Figure 3A). The depth P of this cavity, measured from the first surface 50A, is greater than the contour of the edge of the support substrate 40 (so as to avoid the risk of bonding to the support substrate). It is also advantageously greater than the implantation depth of the light ions to form the buried brittle plane 50B. It is preferably between 200 nm and 10 μm, for example 6 μm. The cavity is obtained by etching or micromilling.

[0067] One advantage of this first implementation is that the surface layer 51 transferred onto the support substrate 40 then has a clean profile (see FIG. 3C). In addition, when the cavity depth P is equal to or greater than twice the implantation depth, the donor substrate 50 can be reused without the need to form the cavity again.

[0068] 4A-4C, the degraded substrate is instead the support substrate 40. In other words, the degraded portion 60 belongs to the support substrate 40. As mentioned above, the degraded portion extends from the side of the degraded substrate (here, the support substrate 40) until it reaches or protrudes from the vertical projection of the interface between the porous silicon layer 42 and the peripheral portion 44.

[0069] 4A-4C is composed of a textured portion of the dielectric layer 43, which is textured to have a surface roughness of 1 nm or more. In fact, too high a roughness would prevent the support substrate 40 and the donor substrate 50 from being bonded together. The surface roughness of the support substrate 40 and the donor substrate 50, excluding the degraded portion 60, is therefore strictly less than 1 nm.

[0070] The textured portion can be obtained by etching the dielectric layer 43, by chemical treatment, by plasma treatment, by ion beam bombardment, by nanosecond laser annealing, or by creating defects using a textured ring (punching).

[0071] In a first alternative implementation (not represented in the figures), the degraded portion 60 is a textured portion (Rq≧1 nm) belonging to the donor substrate 50 and more particularly to the surface layer 51 .

[0072] In a second alternative implementation (also not represented in the figures), the degraded portion 60 is a recessed portion belonging to the support substrate 40, and more particularly to the dielectric layer 43. The depth of the corresponding cavity is preferably strictly smaller than the thickness of the dielectric layer 43.

[0073] Thus, in these first two implementations and their alternatives, the depleted portion 60 is positioned to obtain a breaking wave propagating above a homogeneous medium, including the porous silicon layer 42, and therefore without cracks. The width L2 of the depleted portion 60 is strictly greater than the width L1 of the peripheral portion 44, preferably between 2 mm and 6 mm.

[0074] In the third implementation shown in Figures 5A-5C, the degraded portion 60 belongs to the support substrate 40. It is also located (in the assembly of substrates 40 and 50) vertically aligned with the interface between the porous silicon layer 42 and the peripheral portion 44. However, in contrast to the second implementation (Figures 4A-4C), the degraded portion does not extend to the side of the support substrate 40. In other words, it is spaced apart from the side of the support substrate 40. It is located at a distance d of less than 5 mm from the side of the support substrate 40.

[0075] The degraded portion 60 may be formed by a recessed portion of the dielectric layer 43, as shown in Figures 5A-5C (and in the second alternative implementation), or by a rough, textured portion of the dielectric layer 43 (as in the implementation of Figures 4A-4C).

[0076] In the fourth implementation shown in FIGS. 6A-6C , the degraded portion 60 resides in the donor substrate 50. It is also located vertically aligned with the interface between the porous silicon layer 42 and the peripheral portion 44. However, unlike the first implementation ( FIGS. 3A-3C ), the degraded portion does not extend to the side of the donor substrate 50. Nevertheless, it is located at a distance d of less than 5 mm from the side of the donor substrate 50. The degraded portion 60 may be formed by a recessed portion relative to the first side 50A of the donor substrate 50, as shown in FIGS. 6A-6C (and in the implementation shown in FIGS. 3A-3C ), or by a rough, textured portion of the surface layer 51 (as in the first alternative implementation).

[0077] In these third and fourth implementations, the depleted portion 60 is positioned to obtain two breaking waves each propagating to a specific region (peripheral or central) of the buried brittle plane 50B above the homogeneous medium (including either the porous silicon layer 42 or the peripheral portion 44). Therefore, given that the breaking waves do not propagate facing the depleted portion 60 (there is no bonding of the surface layer 51), there are only two possible fracture fronts that cannot meet. The width L3 of the depleted portion 60 is preferably between 10 μm and 4 mm.

[0078] The third and fourth implementations of the manufacturing method furthermore make it possible (unlike the preceding implementations) to obtain an (annular) portion of the active layer at the periphery of the multilayer structure 30, which may prove useful for the integration of microelectronic components.

[0079] 7A-7C, the degraded portion 60 comprises a cavity (annular or substantially annular) extending into the porous silicon layer 42 (from the bonding surface of the support substrate 40), the cavity being at a distance d of less than 7 mm from the side of the support substrate 40 and at a distance d' of less than 2 mm from the interface between the porous silicon layer 42 and the peripheral portion 44. The cavity 60 can be formed by etching, micromilling, or nanosecond laser annealing. Its width L4 is preferably between 10 μm and 1 mm.

[0080] Advantageously, the cavity 60 extends through the entire thickness of the porous silicon layer 42 .

[0081] The cavity 60 allows the porous silicon layer 42 to deform (or rearrange) at least partially laterally rather than vertically, while avoiding protrusions or inhomogeneities that may impair bond quality (and thus create non-transfer zones).

[0082] The dielectric material, typically the material that forms dielectric layer 43, may cover, but not completely fill, the bottom and sidewalls of cavity 60. Additionally, cavity 60 may be partially or completely filled (with or without a dielectric coating on the bottom and sidewalls) with a material that absorbs breaking waves, thus forming a box of absorbing material. The absorbing material has a Young's modulus lower than that of porous silicon (i.e., less than 20 GPa).

[0083] Again, the cavity 60 or absorbing chamber makes it possible to distinguish two different zones for the propagation of the breaking waves above a homogeneous or substantially homogeneous medium, preventing the appearance of cracks.

[0084] 8A-8C, the degraded portion 60 is created in one of the substrates 40-50 (in the example of FIGS. 8A-8C, both) by optimizing the wafer edge chamfer, for example by edge grinding, so that the chamfer of the wafer edge (which constitutes the degraded portion 60) extends all the way to the porous silicon layer 42 (before assembly to the support substrate 40 and after assembly to the donor substrate 50) without any bond beyond the porous silicon layer 42.

[0085] 9A-9C, the porous silicon layer 42 includes a central portion 421 having a substantially constant thickness e1 and a peripheral portion 422 having a thickness e2 that increases toward the side surface of the support substrate 40. By substantially constant, we mean that the thickness e1 of the central portion 421 does not vary by more than 5%, while the thickness e2 of the peripheral portion 422 may vary by more than 30% between the interface with the central portion 421 and the side surface of the support substrate 40.

[0086] Such a porous silicon layer 42 is obtained in particular when a "single cell" type porosification device is used (in fact, one entire face of the first substrate is exposed to the acidic medium). The peripheral portion 422 of increased thickness has a width L1', which may vary between 2 mm and 25 mm.

[0087] In this case, the multilayer structure 30 is substantially immune to cracking phenomena, since the fracture waves propagate above a generally homogeneous (compositional) medium. On the other hand, the non-uniformity of the porous silicon thickness at the wafer edge causes increased curvature of the multilayer structure 30 during annealing, especially during solidification annealing of the bonded interface, which can reach 1000°C (the multilayer structure 30 can have a deflection of 600 μm after annealing).

[0088] To limit or offset the effect of the thickness gradient, and thus reduce curvature of the multilayer structure 30, the depleted portion 60 is disposed in at least one of the support substrate 40 and the donor substrate 50. The depleted portion 60 is located in vertical alignment with the transition between the central portion 421 and the peripheral portion 422 of the porous silicon layer 42 upon assembly of the support substrate 40 and the donor substrate 50.

[0089] The degraded portion 60 may be a recessed portion, a textured portion (with a roughness of 1 nm or more; see Figures 9A-9C), a cavity (filled or not with an absorbing material), or a chamfered portion of the wafer edge as described above. The degraded portion may extend to the side of the degraded substrate (L2>L1'). Its width L2 is advantageously between 3 mm and 26 mm.

[0090] The recessed portion of the dielectric layer 43 is the most preferred solution since the dielectric layer 43 also contributes to the curvature of the multi-layer structure 30 .

[0091] More typically, the degraded portion 60 is located less than 25 mm from the side of the degraded substrate, preferably less than 7 mm for the implementations of Figures 7A-7C and less than 5 mm for the implementations of Figures 3A-3C, 4A-4C, 5A-5C, 6A-6C, and 8A-8C, thereby reducing the risk of cracking of the surface layer 51 and / or excessive bending of the multilayer structure 30 caused by inhomogeneities at the edges of the assembly.

[0092] 10A-10C show implementations of the step of providing a support substrate 40, which are capable of reproducing a structure including a peripheral portion of non-porous silicon 44, even though a "single-cell" type porosification device is employed to form the porous silicon layer 42 (see FIGS. 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C).

[0093] 10A, a first silicon substrate 90 is recessed (for example by etching) to form a central cavity 91 bounded laterally by a (silicon) ring 92. The ring 92 constitutes a peripheral portion of the first substrate 90.

[0094] The thickness e3 of this ring 92 (equal to the etching depth) is equal to or greater than the maximum thickness (e2) of the porous silicon layer to be formed (i.e., the thickness at the side). Therefore, during the second porosification substep S12 by the "single-cell" type porosification device (see FIG. 10B), the porous silicon layer 42' formed does not extend over the entire ring 92. The buried portion 921 of the ring 92 remains intact. Preferably, the width L5 of the ring 92 is such that the peripheral portion where the thickness of the porous silicon layer 42' is increased is entirely within the ring 92.

[0095] Finally, in a third substep S23 (see FIG. 10C), the ring 92 is entirely removed to obtain a flat surface with a central portion of the porous silicon layer 42' (of substantially constant thickness e1).

[0096] Thus, by delimiting the ring 92 around the periphery of the first substrate 90 during the first sub-step S11, it is possible to protect the silicon portion underlying the porosification process (forming the peripheral portion 44 of the support substrate 40), which silicon portion is arranged around the porous silicon portion that will ultimately be retained (forming the porous silicon layer 42 of the support substrate 40).

[0097] This particular implementation of step S1 of providing the support substrate 40 also avoids porous silicon extending over the sides of the multilayer structure 30, which may cause embrittlement or contamination (e.g., penetration by etching or cleaning solutions employed during component fabrication).

[0098] As noted above, degraded portion 60 of support substrate 40 or donor substrate 50 may have a shape that is not perfectly circular ("substantially circular"). In other words, a portion of support substrate 40 or donor substrate 50 may be left intact for the purpose of creating a fracture initiation zone at the edge.

[0099] 11 shows, by way of example, the bonding surface of the support substrate 40 of FIG. 4A. The dotted circle represents the interface between the porous silicon layer 42 at the center of the substrate and the peripheral non-porous silicon portion 44. The non-depleted portion 70 (here of the dielectric layer 43) is positioned as an extension of the depleted portion 60 as a ring segment, completing the ring. By "non-depleted portion" is meant the portion that will be bonded to the other side of the substrate during assembly step S3.

[0100] The non-degraded portion 70 is advantageously configured to include a notch 80 in the support substrate 40 (or donor substrate 50), as depicted in FIG.

[0101] 3C, 4C, 5C, 6C, 7C, 8C and 9C, the multilayer structure 30 therefore comprises a support layer 41, a porous silicon layer 42 disposed on the support layer 41, a dielectric layer 43, 512 (dielectric layer 43 and / or dielectric sub-layer 512) disposed on the porous silicon layer 42, and an active layer 51, 511 (surface / active layer 51 or active sub-layer 511) disposed on the dielectric layer 43, 512.

[0102] In the case of oxide, the dielectric layer 43, 512 may also be referred to as a buried oxide layer or BOX.

[0103] A feature of the multilayer structure 30 is that the active layers 51, 511 are provided with annular or substantially annular recesses 510. The recesses 510 extend down to the dielectric layer 43, in other words through the entire thickness of the active layers 51, 511. Therefore, the active layers 51, 511 do not completely cover the support layer 41.

[0104] Such depressions in the active layers 51, 511 near the sides of the multi-layer structure 30 are much less damaging than excessive bending or cracking for microelectronic component fabrication (which generally extend further toward the center of the wafer).

Claims

1. A method for manufacturing a multi-layer structure (30), comprising: - providing (S1) a support substrate (40) comprising a support layer (41) and a porous silicon layer (42) disposed on the support layer; - providing (S2) a donor substrate (50) comprising a first surface (50A), a buried brittle plane (50B) and a surface layer (51) bounded by the first surface and the buried brittle plane; - a step (S3) of assembling the support substrate (40) and the donor substrate (50) by bonding, the surface layer (51) of the donor substrate being placed in contact with the support substrate, - a step (S4) of separating the surface layer (51) from the donor substrate (50) by fracturing along the buried brittle plane (50B); wherein at least one of the support substrate and the donor substrate (40, 50), referred to as a degraded substrate, is provided with a degraded portion (60) to prevent it from bonding to the other of the support substrate and the donor substrate (50, 40) during an assembly step, the degraded portion (60) having a ring or substantially ring shape and located less than 25 mm from a side of said degraded substrate.

2. 2. The method of claim 1, wherein the support substrate further comprises a non-porous silicon peripheral portion disposed around the porous silicon layer, and wherein the degraded portion is located in vertical alignment with an interface between the non-porous silicon peripheral portion and the porous silicon layer upon assembly of the support substrate and the donor substrate.

3. 2. The method of claim 1, wherein the porous silicon layer comprises a central portion having a substantially constant first thickness and a peripheral portion having a second thickness that increases toward a side of the support substrate, and the degraded portion is located vertically aligned with a transition between the central portion and the peripheral portion of the porous silicon layer upon assembly of the support substrate and the donor substrate.

4. The method of any one of claims 1 to 3, wherein the depleted portion (60) further extends to the side of the depleted substrate.

5. 4. The method of any one of claims 1 to 3, wherein the depleted portion (60) is spaced from a side of the depleted substrate and has a width (L3) between 10 μm and 4 mm.

6. The method according to any one of claims 1 to 5, wherein the deteriorated portion (60) comprises a recessed portion.

7. The method of claim 6, wherein the recessed portion resides in a donor substrate (50).

8. 8. The method according to claim 7, wherein the step (S2) of providing a donor substrate (50) includes the substep of implanting light ions into the first substrate at an implantation depth to form a buried brittle plane (50B), the recessed portion being obtained by forming a cavity having a depth (P) greater than the implantation depth.

9. 6. The method according to any one of claims 1 to 5, wherein the degraded portion (60) comprises a textured portion having a surface roughness of 1 nm or more.

10. 2. The method of claim 1, wherein the support substrate (40) further comprises a non-porous silicon peripheral portion (44) disposed around the porous silicon layer (42), and the degraded portion (60) comprises a cavity extending into the porous silicon layer (42), the cavity being located at a distance (d') of less than 2 mm from an interface between the non-porous silicon peripheral portion (44) and the porous silicon layer (42).

11. The method of claim 10 , wherein the cavity is filled with a material having a Young's modulus lower than that of porous silicon.

12. 12. The method of any one of claims 1 to 11, wherein the support substrate (40) further comprises a dielectric layer (43) disposed on the porous silicon layer (42).

13. 13. The method according to any one of claims 1 to 12, wherein the degraded portion (60) is substantially annular and the degraded substrate comprises a so-called non-degraded portion (70) located as an extension of the degraded portion (60), the non-degraded portion (70) being bonded to the other of the support substrate and the donor substrate (50, 40) during the assembly step (S3).

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