Back contact battery and its manufacturing method

Abstract

This application discloses a back-contact cell and a manufacturing method thereof, which increase the light utilization rate on the back side of the back-contact cell and help improve the photoelectric conversion efficiency of the back-contact cell, and relates to the technical field of photovoltaics. The back-contact cell includes a silicon substrate and a first doped semiconductor layer formed on a partial region on the back side of the silicon substrate. The region on the back side of the silicon substrate corresponding to the first doped semiconductor layer is a first region, and the remaining region is a second region. The first and second regions are alternately distributed. The second region has a groove structure recessed into the silicon substrate relative to the surface of the first region. The end of the first doped semiconductor layer adjacent to the second region is raised. The manufacturing method for the back-contact cell is for manufacturing the back-contact cell.

Description

[Technical Field]

[0001] This application relates to the field of photovoltaics, and more particularly to back-contact cells and methods of making same.

[0002] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority from a Chinese patent application bearing application number 202410111962.8 and entitled "Back-contact battery and manufacturing method thereof," filed with the China Patent Office on January 26, 2024, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] A back-contact battery is a solar cell in which there are no electrodes on the light-receiving surface of the battery cell, and the positive and negative electrodes are all located on the back side of the battery cell. This reduces the shielding of the electrodes from the battery cell, increases the short-circuit current of the battery cell, and improves the energy conversion efficiency of the battery cell.

[0004] However, back contact cells according to the related art have a low light utilization rate on the back side, which is disadvantageous for improving the photoelectric conversion efficiency of back contact cells. Summary of the Invention [Problem to be solved by the invention]

[0005] The present application aims to provide a back contact cell and a manufacturing method thereof, which can increase the light utilization rate on the back side of the back contact cell and help improve the photoelectric conversion efficiency of the back contact cell. [Means for solving the problem]

[0006] To achieve the above object, in a first aspect, the present application provides a back-contact battery including a silicon substrate and a first doped semiconductor layer formed on a partial region of the back surface of the silicon substrate. Here, the region of the back surface of the silicon substrate corresponding to the first doped semiconductor layer is a first region, and the remaining region is a second region. The first and second regions are alternately distributed. The second region has a recessed groove structure recessed into the silicon substrate relative to the surface of the first region. An end of the first doped semiconductor layer adjacent to the second region is provided so as to be raised.

[0007] When the above technical solution is adopted, when the back-contact cell provided in the present application is in an operating state, light rays are refracted from the light-receiving surface side into the silicon substrate in a direction from the light-receiving surface to the back surface. When the silicon substrate absorbs photon energy, electrons and holes can be generated. The electrons and holes then migrate to the first doped semiconductor layer and a portion of the second region, respectively, and are finally extracted by the corresponding electrodes to form a photocurrent. However, not all of the light rays entering the silicon substrate are absorbed and utilized by the silicon substrate; some of the light rays are refracted outward from the back surface of the silicon substrate. In this case, because the end of the first doped semiconductor layer located on the back surface of the silicon substrate, adjacent to the second region, is raised, some of the light rays refracted outward from the back surface of the silicon substrate can be reflected back into the silicon substrate and absorbed and utilized by the silicon substrate due to the reflection effect of the raised end of the first doped semiconductor layer adjacent to the second region. This increases the light utilization rate of the back-contact cell and helps improve the photoelectric conversion efficiency of the back-contact cell.

[0008] In addition, in the back-contact battery provided in the present application, the second region on the back surface of the silicon substrate has a groove structure recessed into the silicon substrate relative to the surface of the first region, which allows the surface of the first region and the surface of the second region to be misaligned in the thickness direction of the silicon substrate, which helps to at least partially misalign the first doped semiconductor layer and the corresponding doped region located in the second region (or the second doped semiconductor layer formed in the second region), which are located on the back side of the silicon substrate and have opposite conductivity types, in the thickness direction of the silicon substrate, thereby reducing the risk of leakage on the back side and improving the electrical reliability of the back-contact battery.

[0009] As one possible implementation, the depth of the groove structure is between 200 nm and 2500 nm.

[0010] When the above technical solution is adopted, in the actual manufacturing process, a groove structure recessed into the silicon substrate relative to the surface of the first region is formed in the second region on the back side of the silicon substrate, allowing the edge of the first doped semiconductor layer adjacent to the second region to be raised. Based on this, by setting the depth of the groove structure within the above range, it is possible to prevent the edge of the first doped semiconductor layer adjacent to the second region from having a small raised installation height due to a small depth, which would result in a weak reflection effect of the edge. This helps the edge of the first doped semiconductor layer adjacent to the second region to return more light back into the silicon substrate, thereby ensuring a high light utilization rate of the back-contact cell. Furthermore, the small groove size also prevents a small misalignment in the thickness direction of the silicon substrate between the first doped semiconductor layer and the corresponding doped region in the second region (or the second doped semiconductor layer formed in the second region), which is also located on the back side of the silicon substrate and has the opposite conductivity type, thereby further reducing the risk of backside leakage. The depth of the groove structure can prevent the edge of the first doped semiconductor layer from being affected by the etching solution that etches the silicon substrate, thereby reducing the length of the edge that is floating above the second region of the silicon substrate, and the reflection effect of the edge that is adjacent to the second region of the first doped semiconductor layer and has a relatively long length can ensure that more light is returned into the silicon substrate.The depth of the groove structure can also prevent the silicon substrate from being thick, which reduces the manufacturing cost of back contact batteries and helps realize the production of thinner back contact batteries.

[0011] As one possible implementation means, the length of the floating end of the first doped semiconductor layer in the arrangement direction of the first and second regions is greater than 0 and not more than 3000 nm.

[0012] When the above technical solution is adopted, it can be understood that the longer the floating end of the first doped semiconductor layer, the greater the coverage length in the second region. Because two doped regions of opposite conductivity types are provided on the back side of a back-contact battery, by setting the length of the floating end of the first doped semiconductor layer within the above range in the arrangement direction of the first and second regions, it is possible to prevent a small gap between the first doped semiconductor layer and the corresponding doped region located in the second region (or the second doped semiconductor layer formed in the second region) due to the long floating end of the first doped semiconductor layer, which would otherwise be prone to electrical leakage, thereby ensuring high electrical reliability of the back-contact battery. Furthermore, when the length of the floating end of the first doped semiconductor layer is greater than 0 and less than or equal to 3000 nm, the selectable length of the floating end is wider, which helps to reduce the difficulty of manufacturing a first doped semiconductor layer with a consistent length and improves the suitability of the back-contact battery provided in the present application for different applications.

[0013] In one possible implementation, at least a portion of the sidewall surface of the groove structure is inclined relative to the horizontal plane so that the cross-sectional area of ​​at least a portion of the groove structure gradually increases from the light-receiving surface toward the back surface. In this case, the groove bottom area of ​​the groove structure is smaller than the groove opening area, which helps increase the distance between the first doped semiconductor layer and a corresponding doped region (or a second doped semiconductor layer formed in the second region) of the opposite conductivity type to the first doped semiconductor layer in the arrangement direction of the first and second regions, thereby reducing the risk of backside leakage and ensuring high electrical reliability of the back-contact cell. In addition, the inclined portion of the sidewall of the groove structure also helps reflect light, further reducing the probability of light being refracted outward from the back side of the back-contact cell, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0014] In one possible implementation, the surface of the sidewall of the groove structure near the groove mouth is perpendicular to the horizontal plane, which provides another possible implementation for the shape of the groove structure in the back contact battery provided herein and helps improve the suitability of the back contact battery provided herein for different applications.

[0015] As a possible implementation, the angle between the horizontal plane and the portion of the side wall of the groove structure that is inclined relative to the horizontal plane is 52° to 58°.

[0016] When the above technical solution is adopted, by ensuring that the included angle between the horizontal plane and the portion of the sidewall of the groove structure that is inclined with respect to the horizontal plane is within the above range, it is possible to prevent the portion of the sidewall of the groove structure that is inclined with respect to the horizontal plane from having a weak effect of reflecting light back into the silicon substrate, which would be caused by the included angle being too large or too small. The strong reflecting effect of the portion of the sidewall of the groove structure that is inclined with respect to the horizontal plane ensures that more light can be returned into the silicon substrate and reused by the silicon substrate, thereby further improving the light utilization rate of the back-contact battery.

[0017] As a possible implementation, the sidewall of the groove structure has a plane parallel to the horizontal plane between the surface of the part close to the groove mouth and the surface of the part close to the groove bottom. In this case, the sidewall of the groove structure can have at least two surfaces with different angles to the horizontal plane, which helps to reflect light at different angles depending on the different parts of the sidewall of the groove structure, and the reflection effect of the sidewall of the groove structure helps to return more light into the silicon substrate and allow it to be reused by the silicon substrate.

[0018] As one possible implementation, the length of a plane parallel to the horizontal plane on the sidewall of the groove structure in the arrangement direction of the first and second regions is greater than 0 and less than 2 μm.

[0019] When the above technical solution is adopted, the length of the plane parallel to the horizontal plane on the sidewall of the trench structure in the arrangement direction of the first and second regions within a certain range is directly proportional to the etching time for the trench structure. Based on this, by setting the length of the plane parallel to the horizontal plane on the sidewall of the trench structure within the above range, it is possible to prevent the etching time for the trench structure from being prolonged due to the long length, and to ensure that the end of the first doped semiconductor layer adjacent to and floating above the second region of the trench structure has a predetermined length after the trench structure is formed.

[0020] In one possible implementation, the minimum distance from a plane parallel to the horizontal plane on the sidewall of the groove structure to the groove opening in the arrangement direction of the first and second regions is greater than 0 and less than 1 μm. In this case, the large distance between the plane parallel to the horizontal plane on the sidewall of the groove structure and the groove opening in the arrangement direction of the first and second regions can be prevented from deteriorating the reflective cooperation between the plane and the floating edge of the first doped semiconductor layer, ensuring that the plane and the floating edge work together to reflect more light back into the silicon substrate, further improving the light utilization efficiency of the back-contact cell.

[0021] In one possible implementation, at least a portion of the groove bottom of the groove structure has a textured surface. In this case, the textured surface has uneven surface characteristics. Therefore, if the entire groove bottom surface of the groove structure is textured, it can increase the surface area of ​​the corresponding doped region (or second doped semiconductor layer) formed at the groove bottom of the groove structure, further increasing the contact area between the corresponding doped region (or second doped semiconductor layer) and the electrode, reducing contact resistance and improving the photoelectric conversion efficiency of back-contact cells. Furthermore, if the groove bottom of the groove structure has a textured surface on the exposed surface of the second passivation layer and the second doped semiconductor layer stacked thereon, this can provide a certain light trapping effect on this surface, allowing more light to penetrate through the groove bottom of the groove structure and reach the silicon substrate. At the same time, the second passivation layer formed on the flat portion of the groove bottom improves the passivation effect of the second passivation layer on this surface, thereby improving the photoelectric conversion efficiency of back-contact cells.

[0022] In one possible implementation, the back contact cell further includes a first passivation layer located between the first region and the first doped semiconductor layer.

[0023] When the above technical solution is adopted, the first passivation layer and the first doped semiconductor layer can form a selective contact structure, thereby realizing chemical passivation for the corresponding region on the back surface of the silicon substrate, realizing selective collection of carriers of the corresponding conductivity type, reducing the carrier recombination rate on the back surface side, and helping to improve the photoelectric conversion efficiency of the back contact cell.

[0024] In one possible implementation, the back-contact cell further includes a second doped semiconductor layer formed at the bottom of the groove structure and having a conductivity type opposite to that of the first doped semiconductor layer.

[0025] In one possible implementation, when the back contact cell includes a first passivation layer, and the first passivation layer is a tunnel passivation layer, the first doped semiconductor layer is a doped polycrystalline silicon layer.

[0026] In one possible implementation, when the back-contact cell includes a second doped semiconductor layer, the back-contact cell further includes a second passivation layer located between the silicon substrate and the second doped semiconductor layer.

[0027] In one possible implementation, when the back contact cell includes a second doped semiconductor layer, the distance between the first doped semiconductor layer and the second doped semiconductor layer in the direction of arrangement of the first and second regions is 20 μm or more and 110 μm or less.

[0028] When the above technical solution is adopted, by keeping the distance between the first and second doped semiconductor layers of opposite conductivity types within the above range, it is possible to prevent leakage of electricity between the first and second doped semiconductor layers due to a small distance, thereby ensuring high electrical reliability of the back-contact battery, and also to prevent carriers on the back side from being collected by the first and second doped semiconductor layers and extracted by the corresponding electrode due to a large distance, thereby further reducing the carrier recombination rate on the back side.

[0029] In one possible implementation, the second passivation layer is a tunnel passivation layer and the second doped semiconductor layer is a doped polycrystalline silicon layer.

[0030] In a second aspect, the present application further provides a method for manufacturing a back-contact battery, the method comprising the steps of: first providing a silicon substrate; then forming, on a back surface of the silicon substrate, a doped semiconductor material layer that is provided over the entire layer and a mask layer that is located on a portion of the doped semiconductor material layer; then using the mask layer as a mask to selectively etch the doped semiconductor material layer to form a first doped semiconductor layer in the remaining portion of the doped semiconductor material layer; then using the mask layer as a mask to form, in a second region, a groove structure that is recessed into the silicon substrate with respect to the surface of the first region, so that an end of the first doped semiconductor layer adjacent to the second region is raised;

[0031] In one possible implementation, the material of the first doped semiconductor layer includes silicon, and the step of forming a doped semiconductor material layer covering the entire layer on the back surface of the silicon substrate and a mask layer located on a portion of the doped semiconductor material layer includes the steps of: forming an intrinsic semiconductor material layer covering the entire layer on the back surface of the silicon substrate, doping the intrinsic semiconductor material layer to form the doped semiconductor material layer with the intrinsic semiconductor material layer and forming a doped silica glass layer covering the entire layer on the doped semiconductor material layer, subsequently heat-treating a portion of the doped silica glass layer by a laser etching process to form a mask layer with the unheat-treated portion of the doped silica glass layer, and subsequently removing the heat-treated portion of the doped silica glass layer.

[0032] When the above technical solution is adopted, if the material of the first doped semiconductor layer contains silicon, the material of the intrinsic semiconductor material layer used to fabricate the doped semiconductor material layer also contains silicon. Based on this, not only can the doped semiconductor material layer be obtained after doping the intrinsic semiconductor material layer, but also a doped silica glass layer can be formed over the entire doped semiconductor material layer. Subsequently, a portion of the doped silica glass layer is heat-treated using a laser etching process. In this case, the portion of the doped silica glass layer treated by the laser is less dense and more easily removed. However, the portion of the doped silica glass layer not treated by the laser is more dense and more difficult to remove. Therefore, after the heat treatment, different portions of the doped silica glass layer have different etching selectivities, thereby forming a mask layer for patterning the doped semiconductor material layer. To obtain the mask layer, there is no need to form a separate mask material or perform a separate mask deposition process, which helps reduce the manufacturing costs of back-contact batteries and simplify the manufacturing process of back-contact batteries.

[0033] In one possible implementation, a wet chemical process is used to form a trench structure in the second region that is recessed into the silicon substrate relative to the surface of the first region using the mask layer as a mask, wherein the process temperature of the wet chemical process is between 65°C and 85°C, and / or the process time of the wet chemical process is between 50s and 500s.

[0034] When the above technical solution is adopted, both the process temperature and process time of the wet chemical process affect the specifications of the trench structure formed by the wet chemical process and the specifications of the raised end of the first doped semiconductor layer. Based on this, by setting the process temperature of the wet chemical process within the above range, it is possible to prevent the depth of the trench structure and the raised installation height and length of the raised end of the first doped semiconductor layer from being reduced due to low process temperature. It is also possible to prevent the depth of the trench structure from being increased due to high process temperature. The beneficial effects of preventing the depth of the trench structure and the raised installation height and length of the raised end of the first doped semiconductor layer from being reduced and preventing the depth of the trench structure from being increased can be seen above. Furthermore, the beneficial effects of setting the process time within the above range are similar to those of setting the process temperature between 65°C and 85°C, and therefore will not be described in detail here.

[0035] In one possible implementation, after the step of providing a silicon substrate and before the step of forming a doped semiconductor material layer covering the entire layer on a back surface of the silicon substrate and a mask layer located on a portion of the doped semiconductor material layer, the method for manufacturing a back contact cell further includes the step of forming a first passivation material layer covering the entire layer on the back surface of the silicon substrate, and after the step of selectively etching the doped semiconductor material layer using the mask layer as a mask and before the step of forming a trench structure in the second region using the mask layer as a mask, the trench structure being recessed into the silicon substrate relative to the surface of the first region using the mask layer as a mask, the method for manufacturing a back contact cell further includes the step of selectively etching the first passivation material layer using the mask layer as a mask to form the first passivation layer on a remaining portion of the first passivation material layer.

[0036] As one possible implementation method, a step of forming a groove structure in the second region that is recessed into the silicon substrate relative to the surface of the first region is performed using a mask layer as a mask, and at the same time, a texturing process is performed on the groove bottom of the groove structure, thereby forming the groove bottom of the groove structure into a textured surface.

[0037] In one possible implementation, after using the mask layer as a mask to form a trench structure in the second region that is recessed into the silicon substrate relative to the surface of the first region, the method for manufacturing a back-contact battery further includes forming a second doped semiconductor layer at the bottom of the trench structure.

[0038] In one possible implementation, after the step of forming a trench structure in the second region that is recessed into the silicon substrate relative to the surface of the first region using the mask layer as a mask and before the step of forming a second doped semiconductor layer at the bottom of the trench structure, the method for manufacturing a back-contact battery further includes the step of forming a second passivation layer at the bottom of the trench structure.

[0039] In one possible implementation, the mask layer is used as a mask to form a groove structure in the second region, the groove bottom of which is flat, and after the step of forming the second doped semiconductor layer on the groove bottom of the groove structure, a texturing process is performed on the exposed portion of the second doped semiconductor layer on the groove bottom of the groove structure.

[0040] The beneficial effects of the second aspect of the present application and its various implementation forms can be referred to the analysis of the beneficial effects of the first aspect and its various implementation forms, and will not be described here. [Brief explanation of the drawings]

[0041] The drawings described herein are intended to further the understanding of the present application and constitute a part of the present application, and the illustrative embodiments and descriptions thereof are intended to interpret the present application and are not intended to unduly limit the present application.

[0042] [Figure 1]FIG. 1 is a longitudinal cross-sectional schematic diagram of a first structure of a back-contact battery provided in an embodiment of the present application. [Figure 2] FIG. 2 is a longitudinal cross-sectional schematic diagram of a second structure of a back-contact battery provided in an embodiment of the present application. [Figure 3] FIG. 2 is a longitudinal cross-sectional schematic diagram of a third structure of a back-contact battery provided in an embodiment of the present application. [Figure 4] 1 is an SEM view of the structure of a back-contact cell provided in an example of the present application at the edge adjacent to the second region of the first doped semiconductor layer. [Figure 5] 2 is an SEM view of the structure of a back-contact cell provided in an example of the present application at the edge adjacent to the second region of the first doped semiconductor layer. [Figure 6] 3 is an SEM view of the structure of a back-contact cell provided in an example of the present application at the edge adjacent to the second region of the first doped semiconductor layer. [Figure 7] 4 is an SEM view of the structure of a back-contact cell provided in an example of the present application at the edge adjacent to the second region of the first doped semiconductor layer. [Figure 8] 5 is an SEM view of the structure of a back-contact cell provided in an example of the present application at the edge adjacent to the second region of the first doped semiconductor layer. [Figure 9] FIG. 2 is an enlarged schematic view of the structure of a back-contact cell provided in an example of the present application at the end adjacent to the second region of the first doped semiconductor layer. [Figure 10] FIG. 2 is a longitudinal cross-sectional schematic diagram of a fourth structure of a back-contact battery provided in an embodiment of the present application. [Figure 11] FIG. 1 is a longitudinal cross-sectional schematic diagram of a fifth structure of a back-contact battery provided in an embodiment of the present application. [Figure 12] 1 is an SEM view of a partial structure of a back-contact cell provided in an example of the present application, where the back-contact cell further comprises a second doped semiconductor layer. [Figure 13] 2 is an SEM view of a partial structure of a back-contact cell provided in an example of the present application, where the back-contact cell further comprises a second doped semiconductor layer. [Figure 14] 3 is an SEM view of a partial structure of a back-contact cell provided in an example of the present application, where the back-contact cell further includes a second doped semiconductor layer. [Figure 15] 1 is an SEM view of the structure of the sidewall of the second doped semiconductor layer facing the first doped semiconductor layer of a back-contact cell provided in an example of the present application. [Figure 16] 2 is an SEM view of the structure of the sidewall of the second doped semiconductor layer facing the first doped semiconductor layer of the back-contact cell provided in the examples of the present application. [Figure 17] 3 is an SEM view of the structure of the sidewall of the second doped semiconductor layer facing the first doped semiconductor layer of the back-contact cell provided in the examples of the present application. [Figure 18] FIG. 4 is an SEM image of the structure of the sidewall of the second doped semiconductor layer facing the first doped semiconductor layer of the back-contact cell provided in the examples of the present application. [Figure 19] FIG. 1 is a longitudinal cross-sectional schematic diagram of a sixth structure of a back-contact battery provided in an embodiment of the present application. [Figure 20] 1 is a schematic diagram of the structure of the back contact battery in the manufacturing process provided in the examples of the present application. [Figure 21] 2 is a schematic diagram of the structure of the back-contact battery in the manufacturing process provided in the examples of the present application. [Figure 22] 3 is a schematic diagram of the structure of the back contact battery in the manufacturing process provided in the examples of the present application. [Figure 23] 4 is a schematic diagram 4 of the structure in the manufacturing process of the back contact battery provided in the examples of the present application. [Figure 24] 5 is a schematic diagram of the structure in the manufacturing process of the back contact battery provided in the examples of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0043] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are merely illustrative and do not limit the scope of the present disclosure. In the following description, descriptions of known structures and techniques will be omitted to avoid unnecessary confusion with the concept of the present disclosure.

[0044] The drawings show various structural schematic diagrams according to embodiments of the present disclosure. These drawings are not drawn to scale, and some details may be enlarged and some details may be omitted for clarity. The shapes of various regions and layers shown in the drawings, as well as the relative sizes and positional relationships between them, are merely exemplary, and may vary in practice due to manufacturing tolerances and technical limitations. Furthermore, those skilled in the art can separately design regions / layers having different shapes, sizes, and relative positions according to actual needs.

[0045] In the context of the present disclosure, when a layer / element is described as being "on" another layer / element, this layer / element may be directly on top of this other layer / element, or there may be an intermediate layer / element therebetween. Also, if a layer / element is "on" another layer / element in one orientation, it may be "under" the other layer / element when the orientation is changed. In order to make the technical problems, technical solutions, and beneficial effects that the present application aims to solve more clear, the present application will be described in more detail below in combination with figures and examples. It should be understood that the specific examples described herein are merely for the purpose of interpreting the present application, and are not intended to limit the present application.

[0046] Additionally, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or the quantity of the technical features indicated. Thus, a feature qualified as "first" or "second" may expressly or imply the inclusion of one or more of that feature. In the description of this application, unless expressly and specifically limited, "plurality" means two or more than two. Unless expressly and specifically limited, "some" means one or more than one.

[0047] In the description of this application, as should be explained, unless otherwise clearly defined or limited, the terms "attach," "couple," and "connect" should be understood in a broad sense. For example, they may refer to fixed connection, detachable connection, integral connection, mechanical connection, electrical connection, direct connection, indirect connection via an intermediate medium, internal communication between two elements, or an interaction between two elements. Those skilled in the art may understand the specific meaning of the above terms in this application according to specific circumstances.

[0048] Currently, solar cells are widely used as an alternative renewable energy source. A photovoltaic solar cell is a device that converts solar light energy into electrical energy. Specifically, a solar cell generates carriers using the photovoltaic principle and then extracts the carriers using electrodes, thereby contributing to the efficient use of electrical energy. When the positive and negative electrodes of a solar cell are both located on the back surface of the solar cell, the solar cell is called a back-contact cell. Back-contact cells have a higher short-circuit current (Isc) because they do not have the problem of the front surface being blocked by a metal electrode. This has become one of the technological trends toward achieving high-efficiency crystalline silicon cells.

[0049] Specifically, a back-contact battery according to the related art includes at least a silicon substrate and a first doped semiconductor layer formed on a portion of the backside of the silicon substrate. The first doped semiconductor layer may have the opposite conductivity type to that of the silicon substrate or the same conductivity type as that of the silicon substrate. In this case, the back-contact battery further includes a second doped semiconductor layer of the opposite conductivity type formed on a portion of the backside of the silicon substrate. Regardless of the specific structure of the back-contact battery, the backside of the back-contact battery has two doped regions of opposite conductivity types, and the two doped regions of opposite conductivity types are spaced apart to prevent short circuits.

[0050] In the actual manufacturing process of the back-contact cell, a doped semiconductor layer is first formed over the entire back surface of a silicon substrate, and then the doped semiconductor layer located in a portion of the back surface is selectively removed to obtain the first doped semiconductor layer. However, in the manufacturing method of the related art, the first doped semiconductor layer is entirely in contact with the silicon substrate. In this case, after light is refracted from the light-receiving surface and enters the silicon substrate, a small portion of the unused light that strikes the two doped regions of opposite conductivity types can be reflected from the back surface of the silicon substrate and reused. However, most of the unused light that strikes the two doped regions of opposite conductivity types passes through the silicon substrate. That is, most of the light is reflected once from the back surface of the silicon substrate and cannot return to the silicon substrate. Therefore, in the back-contact cell of the related art, the reflectivity of the back surface to reflect the light back to the silicon substrate is low, which further reduces the light utilization rate of the back-contact cell, which is disadvantageous for improving the photoelectric conversion efficiency of the back-contact cell. In addition, in the manufacturing method according to the related art, the doped semiconductor material layer is usually selectively etched using a laser etching process, but the high-temperature laser used to completely remove the corresponding portion of the doped semiconductor material layer may damage the silicon substrate, which is detrimental to improving the yield of back-contact cells.

[0051] To solve the above technical problems, in a first aspect, an embodiment of the present application provides a back-contact battery. As shown in FIG. 1 , the back-contact battery provided in the embodiment of the present application includes a silicon substrate 11 and a first doped semiconductor layer 12 formed on a partial region of the back surface of the silicon substrate 11. Here, the region of the back surface of the silicon substrate 11 corresponding to the first doped semiconductor layer 12 is a first region 13, and the remaining region is a second region 14. The first region 13 and the second region 14 are alternately distributed. The second region 14 has a groove structure 15 recessed into the silicon substrate 11 relative to the surface of the first region 13. The end of the first doped semiconductor layer 12 adjacent to the second region 14 is raised.

[0052] When the above technical solution is adopted, when the back-contact cell provided in the embodiment of the present application is in an operating state, light rays are refracted from the light-receiving surface side into the silicon substrate in the direction from the light-receiving surface to the back surface. When the silicon substrate absorbs photon energy, electrons and holes can be generated. The electrons and holes then migrate to the first doped semiconductor layer and a part of the second region, respectively, and finally extracted by the corresponding electrode to form a photocurrent. However, not all of the light rays entering the silicon substrate are absorbed and utilized by the silicon substrate; some light rays are refracted out from the back surface of the silicon substrate. In this case, as shown in FIG. 1, the end of the first doped semiconductor layer 12 located on the back side of the silicon substrate 11, adjacent to the second region 14, is arranged to be floating. Therefore, part of the light refracted outward from the back side of the silicon substrate 11 can be reflected by the end of the first doped semiconductor layer 12, adjacent to the second region 14 and arranged to be floating, and can return to the silicon substrate 11 and be absorbed by the silicon substrate 11. This increases the light utilization rate of the back-contact cell and helps improve the photoelectric conversion efficiency of the back-contact cell. Furthermore, as shown in FIGS. 1 and 2, in the back-contact battery provided in the examples of the present application, a groove structure 15 is formed in the second region 14 on the back surface of the silicon substrate 11, which is recessed into the silicon substrate 11 relative to the surface of the first region 13. This allows the surfaces of the first region 13 and the second region 14 to be misaligned in the thickness direction of the silicon substrate 11, which helps to at least partially misalign the first doped semiconductor layer 12 and the corresponding doped region located in the second region 14 (or the second doped semiconductor layer 17 formed in the second region 14), which are located on the back side of the silicon substrate 11 and have opposite conductivity types, in the thickness direction of the silicon substrate 11, thereby reducing the risk of leakage from the back side and improving the electrical reliability of the back-contact battery.

[0053] In this specification, the end portion adjacent to the second region of the first doped semiconductor layer and floating therefrom may also be referred to as the end portion of the first doped semiconductor layer that is floating therefrom, or the end portion adjacent to the second region of the first doped semiconductor layer, or the end portion adjacent to the groove structure of the first doped semiconductor layer, etc.

[0054] In actual application, the light-receiving surface of the silicon substrate 11 may be flat, as shown in Figures 1 and 2, or may be textured, as shown in Figure 3. Here, because the textured surface has a light-trapping effect, when the light-receiving surface of the silicon substrate 11 is textured, the reflectance of the light-receiving surface can be reduced, so that more light rays are refracted by the light-receiving surface into the silicon substrate 11 and absorbed by the silicon substrate 11 for use, which further improves the photoelectric conversion efficiency of the back-contact cell.

[0055] 1 and 2, the first doped semiconductor layer 12 is entirely located in the first region 13 except for the floating end portion thereof adjacent to the second region 14. A corresponding doped region (or a second doped semiconductor layer 17) having the opposite conductivity type to the first doped semiconductor layer 12 and collecting carriers is formed in the second region 14. Therefore, the ranges of the first region 13 and the second region 14 on the back surface of the silicon substrate 11 can be determined according to the range of the first doped semiconductor layer 12, the length of the floating end portion of the first doped semiconductor layer 12, the range of the corresponding doped region (or the second doped semiconductor layer 17), and the leakage prevention gap between the first doped semiconductor layer 12 and the corresponding doped region (or the second doped semiconductor layer 17) required for actual applications, and are not specifically limited herein.

[0056] In an actual manufacturing process, a groove structure recessed into the silicon substrate relative to the surface of the first region is formed in the second region on the back side of the silicon substrate, allowing the edge of the first doped semiconductor layer adjacent to the second region to be raised. Based on this, the shape of the groove structure formed in the second region can be determined according to the actual manufacturing process, as long as the groove structure can realize the edge of the first doped semiconductor layer adjacent to the second region to be raised.

[0057] For example, the depth of the groove structure may be 200 nm to 2500 nm. For example, the depth of the groove structure may be 200 nm, 500 nm, 1000 nm, 1500 nm, 2000 nm, or 2500 nm. In this case, by setting the depth of the groove structure within the above range, it is possible to prevent a small floating installation height of the edge adjacent to the second region of the first doped semiconductor layer due to the small depth, which would result in a weak reflection effect of the edge. This helps the reflection effect of the edge adjacent to the second region of the first doped semiconductor layer to return more light into the silicon substrate, thereby ensuring a high light utilization rate of the back-contact cell. 1 and 2, the small size of the grooves 15 can prevent the first doped semiconductor layer 12 and the corresponding doped region (or the second doped semiconductor layer 17 formed in the second region 14), which are located on the back side of the silicon substrate 11 and have opposite conductivity types, from being misaligned in the thickness direction of the silicon substrate 11, further reducing the risk of backside leakage. The large depth of the groove structure 15 can also prevent the end of the first doped semiconductor layer 12 from being affected by the etchant that etches the silicon substrate 11, thereby preventing the length of the end floating above the second region 14 from being reduced. The reflection effect of the relatively long end of the first doped semiconductor layer 12 adjacent to the second region 14 ensures that more light is returned into the silicon substrate 11. In addition, the deep groove structure 15 can prevent the back contact battery provided in the embodiment of the present application from requiring a thick silicon substrate 11, thereby reducing the manufacturing cost of the back contact battery and helping to realize the production of thin back contact batteries.

[0058] 1 and 2, the groove bottom of the groove structure 15 may be flat. Alternatively, as shown in FIG. 3, at least a portion of the groove bottom of the groove structure 15 may have a textured surface. Specifically, as shown in FIG. 3, the entire groove bottom of the groove structure 15 may have a textured surface. In this case, the textured surface has uneven surface characteristics. Therefore, when the groove bottom of the groove structure 15 has a textured surface, the surface area of ​​the corresponding doped region (or second doped semiconductor layer) formed at the groove bottom of the groove structure 15 can be increased, which in turn increases the contact area between the corresponding doped region (or second doped semiconductor layer) and an electrode (not shown), reducing the contact resistance and improving the photoelectric conversion efficiency of the back-contact cell. 12 to 14, the surface of the groove structure 15 exposed outside the stacked second passivation layer 18 and second doped semiconductor layer 17 (the stacked structure and second passivation layer 18 will be described in detail below, see FIG. 19) may be textured, thereby providing a certain light trapping effect on the surface, allowing more light to penetrate through the groove bottom of the groove structure 15 and reach the silicon substrate 11. At the same time, because the second passivation layer 18 is formed on the flat portion of the groove bottom, the passivation effect of the second passivation layer 18 on the surface of the groove bottom is improved, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0059] The sidewalls of the groove structure may be oriented perpendicular to a horizontal plane, with the cross-sectional area of ​​each portion of the groove structure being the same in the depth direction. Alternatively, as shown in Figures 1 to 4, at least a portion of the sidewall surface of the groove structure 15 is inclined relative to a horizontal plane so that the cross-sectional area of ​​at least a portion of the groove structure 15 gradually increases from the light-receiving surface toward the back surface. In this case, the groove bottom area of ​​the groove structure 15 is smaller than the groove opening area, which helps to increase the distance between the first doped semiconductor layer 12 and the corresponding doped region (or second doped semiconductor layer 17 formed in the second region 14) of the opposite conductivity type to the first doped semiconductor layer 12 in the arrangement direction of the first region 13 and the second region 14, thereby reducing the risk of backside leakage in back-contact batteries and ensuring high electrical reliability of the back-contact batteries. In addition, the inclined portions of the sidewalls of the groove structure 15 relative to the horizontal plane also serve to reflect light, further reducing the probability of light being refracted outward from the back side of the back-contact cell, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0060] Here, in the above-mentioned case, the included angle between the horizontal plane and the portion of the sidewall of the groove structure that is inclined relative to the horizontal plane can be determined according to the actual manufacturing process and the requirements for light reflection by the sidewall of the groove structure, and is not specifically limited here.

[0061] For example, the angle between the horizontal plane and the inclined portion of the sidewall of the groove structure may be 52° to 58°. For example, the angle between the horizontal plane and the inclined portion of the sidewall of the groove structure may be 52°, 53°, 54°, 55°, 56°, 57°, or 58°. In this case, by keeping the angle between the horizontal plane and the inclined portion of the sidewall of the groove structure within the above range, it is possible to prevent the inclined portion of the sidewall of the groove structure from being weak in reflecting light back into the silicon substrate due to a large or small included angle. The strong reflection effect of the inclined portion of the sidewall of the groove structure from the horizontal plane ensures that more light can be returned to the silicon substrate for reuse by the silicon substrate, thereby further improving the light utilization rate of the back-contact cell.

[0062] In the above case, as shown in FIGS. 4 to 6, the entire surface of the side wall of the groove structure 15 may be inclined relative to the horizontal plane.

[0063] 7 to 9, only a portion of the sidewall of the groove structure 15 may be inclined relative to the horizontal plane, and at least a portion of the remaining surfaces may be perpendicular to the horizontal plane, or at least a portion of the surfaces may be parallel to the horizontal plane. In this case, the sidewall configuration of the groove structure 15 can be divided into at least the following three types:

[0064] In the first sidewall configuration, as shown in FIG. 7, the surface of the sidewall of the groove structure 15 near the groove mouth is provided perpendicular to the horizontal plane, and all other surfaces are provided at an angle relative to the horizontal plane.

[0065] As a second sidewall form, as shown in Figure 8, the surface of the part of the sidewall of the groove structure 15 close to the groove opening is arranged perpendicular to the horizontal plane, and the surface of the part close to the groove bottom is arranged at an angle to the horizontal plane, and a plane is provided between the surface of the part close to the groove opening and the surface of the part close to the groove bottom, which is arranged parallel to the horizontal plane.

[0066] As a third sidewall form, as shown in Figure 9, the surface of the part of the sidewall of the groove structure 15 close to the groove opening is inclined with respect to the horizontal plane, the surface of the part close to the groove bottom is inclined with respect to the horizontal plane, and there is a plane parallel to the horizontal plane between the surface of the part close to the groove opening and the surface of the part close to the groove bottom.

[0067] Here, the height of the surface perpendicular to the horizontal plane on the side wall of the groove structure, the length of the plane parallel to the horizontal plane on the side wall of the groove structure in the arrangement direction of the first and second regions, and the size of the gap between the plane parallel to the horizontal plane on the side wall of the groove structure and the groove opening of the groove structure in the arrangement direction of the first and second regions can be determined in accordance with the actual manufacturing process, and are not specifically limited here.

[0068] 9, the length L2 of the flat surface parallel to the horizontal plane on the sidewall of the trench structure in the arrangement direction of the first and second regions may be greater than 0 and less than 2 μm. For example, the length L2 of the flat surface parallel to the horizontal plane on the sidewall of the trench structure may be 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, or 2 μm. In this case, within a predetermined range, the length of the flat surface parallel to the horizontal plane on the sidewall of the trench structure in the arrangement direction of the first and second regions is directly proportional to the etching time for the trench structure. Based on this, by setting the length of the flat surface parallel to the horizontal plane on the sidewall of the trench structure within the above range, it is possible to prevent the etching time for the trench structure from being prolonged due to the long length and to ensure that the end of the trench structure adjacent to and floating above the second region of the first doped semiconductor layer 12 has a predetermined length after the trench structure is formed.

[0069] 9 , the minimum distance L1 from a flat surface on the sidewall of the groove structure parallel to the horizontal plane to the groove opening in the arrangement direction of the first and second regions may be greater than 0 and less than 1 μm. For example, the minimum distance L1 from the flat surface on the sidewall of the groove structure parallel to the horizontal plane to the groove opening may be 0.1 μm, 0.3 μm, 0.6 μm, 0.9 μm, or 1 μm. In this case, the large distance between the flat surface on the sidewall of the groove structure parallel to the horizontal plane and the groove opening in the arrangement direction of the first and second regions can prevent a reduction in the reflective cooperation between the flat surface and the floating edge of the first doped semiconductor layer 12. The cooperation between the flat surface and the floating edge can ensure that more light is reflected back into the silicon substrate 11, further improving the light utilization efficiency of the back-contact cell.

[0070] 4 to 9, in the back-contact battery provided in the embodiment of the present application, the groove structure 15 located in the second region 14 can be realized in various shapes, which helps to improve the suitability of the back-contact battery provided in the embodiment of the present application for different applications. In addition, when the surface of the sidewall of the groove structure 15 adjacent to the groove mouth and the surface of the sidewall adjacent to the groove bottom have a plane parallel to the horizontal plane, the sidewall of the groove structure 15 can have at least two surfaces with different angles relative to the horizontal plane, which helps to reflect light at different angles depending on different parts of the sidewall of the groove structure 15. The reflective effect of the sidewall of the groove structure 15 helps to return more light into the silicon substrate 11 for reuse by the silicon substrate 11.

[0071] In terms of material, the first doped semiconductor layer may be a semiconductor material such as silicon, germanium silicon, germanium, or gallium arsenide, etc. In terms of material arrangement form, the crystalline phase of the first doped semiconductor layer may be amorphous, microcrystalline, nanocrystalline, single crystalline, or polycrystalline, etc.

[0072] The thickness of the first doped semiconductor layer can be set according to actual needs and is not specifically limited herein, for example, the thickness of the first doped semiconductor layer may be 100 nm or more and 500 nm or less.

[0073] As can be seen from the above, the floating edge of the first doped semiconductor layer adjacent to the second region has a reflective effect on light, so that a portion of the light refracted outward from the backside of the silicon substrate is reflected by the edge and returned to the silicon substrate for reuse by the silicon substrate. It can also be understood that the longer the floating edge of the first doped semiconductor layer, the greater the coverage length with the second region. Because the backside of a back-contact cell has two doped regions of opposite conductivity types, the longer the floating edge of the first doped semiconductor layer adjacent to the second region, the greater the likelihood of electrical leakage. Based on this, the length of the floating edge of the first doped semiconductor layer can be determined according to the light utilization rate and leakage requirements of the back-contact cell in practical applications.

[0074] For example, the length of the floating end of the first doped semiconductor layer in the arrangement direction of the first region and the second region may be greater than 0 and less than or equal to 3000 nm. For example, the length of the floating end of the first doped semiconductor layer may be 1 nm, 50 nm, 100 nm, 500 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, or 3000 nm. In this case, by keeping the length of the floating end of the first doped semiconductor layer within the above range, it is possible to prevent a small gap between the first doped semiconductor layer and the corresponding doped region located in the second region (or the second doped semiconductor layer formed in the second region) due to the large length of the floating end of the first doped semiconductor layer, which may lead to electrical leakage, and ensure high electrical reliability of the back-contact battery. Furthermore, when the length of the floating end of the first doped semiconductor layer is greater than 0 and less than or equal to 3000 nm, the length of the floating end has a wider selectable range, which helps to reduce the difficulty of manufacturing a first doped semiconductor layer with a consistent length and also improves the suitability of the back contact battery provided in the examples of the present application for different applications.

[0075] In actual application, as shown in Figures 1 to 3, a portion of the first doped semiconductor layer 12 may be formed directly on the first region 13 of the silicon substrate 11. Alternatively, as shown in Figure 10, the back-contact cell further includes a first passivation layer 16 located between the first region 13 and the first doped semiconductor layer 12. In this case, the first passivation layer 16 and the first doped semiconductor layer 12 can form a selective contact structure, which provides chemical passivation for the corresponding region on the back surface of the silicon substrate 11, selectively collects carriers of the corresponding conductivity type, reduces the carrier recombination rate on the back surface side, and helps improve the photoelectric conversion efficiency of the back-contact cell.

[0076] Specifically, the material of the first passivation layer can be determined according to the material of the first doped semiconductor layer and the type of selective contact structure composed of the first passivation layer and the first doped semiconductor layer in actual applications, and is not specifically limited here.

[0077] For example, when the selective contact structure composed of the first passivation layer and the first doped semiconductor layer is a tunnel passivation contact structure, the first doped semiconductor layer is a doped polycrystalline silicon layer, and the first passivation layer is a tunnel passivation layer, which may be made of silicon oxide, aluminum oxide, titanium oxide, etc., and may also be called a tunnel oxide layer.

[0078] Furthermore, for example, when the selective contact structure composed of the first passivation layer and the first doped semiconductor layer is a heterocontact structure, the first doped semiconductor layer is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the first passivation layer is an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0079] The thickness of the first passivation layer can be set according to actual needs and is not specifically limited herein, for example, the thickness of the first passivation layer may be 0.5 nm or more and 3 nm or less.

[0080] As described above, the conductivity type of the first doped semiconductor layer may be opposite to that of the silicon substrate, or may be the same as that of the silicon substrate. In this case, the back-contact cell provided in the embodiments of the present application further includes a second doped semiconductor layer formed at the bottom of the groove structure and having a conductivity type opposite to that of the silicon substrate.

[0081] It should be noted that, as shown in Figures 2 and 11, regardless of whether the conductivity type of the first doped semiconductor layer 12 is the same as or opposite to that of the silicon substrate 11, all of the back-contact batteries provided in the embodiments of the present application may include a second doped semiconductor layer 17 formed at the bottom of the groove structure 15. The second doped semiconductor layer 17 has a conductivity type opposite to that of the first doped semiconductor layer 12. The second doped semiconductor layer 17 is formed only at the bottom of the groove structure 15, and the sidewalls of the groove structure 15 are exposed outside the second doped semiconductor layer 17. At the same time, the first doped semiconductor layer 12 and the second doped semiconductor layer 17 are distributed at a distance and do not contact each other, preventing leakage.

[0082] Specifically, the material of the second doped semiconductor layer may be a semiconductor material such as silicon, germanium silicon, germanium, or gallium arsenide. The crystalline phase of the second doped semiconductor layer may be amorphous, nanocrystalline, microcrystalline, single crystalline, or polycrystalline. Furthermore, the embodiments of the present application do not specifically limit the thickness of the second doped semiconductor layer, as long as it is applicable to the back-contact battery provided in the embodiments of the present application.

[0083] The distance between the first doped semiconductor layer and the second doped semiconductor layer in the arrangement direction of the first region and the second region can be determined according to the leakage prevention requirements for the back contact battery in actual applications, and is not specifically limited here.

[0084] For example, the distance between the first doped semiconductor layer and the second doped semiconductor layer in the arrangement direction of the first and second regions may be 20 μm to 110 μm. For example, the distance between the first doped semiconductor layer and the second doped semiconductor layer may be 20 μm, 40 μm, 60 μm, 80 μm, 100 μm, or 110 μm. In this case, by keeping the distance between the first doped semiconductor layer and the second doped semiconductor layer, which have opposite conductivity types, within the above range, electrical leakage between the first doped semiconductor layer and the second doped semiconductor layer due to the small distance can be prevented, ensuring high electrical reliability of the back-contact battery. Furthermore, it can also prevent carriers on the back side from being collected by the first doped semiconductor layer and the second doped semiconductor layer and extracted by the corresponding electrode due to the large distance, further reducing the carrier recombination rate on the back side.

[0085] In addition, the sidewall of the second doped semiconductor layer facing the first doped semiconductor layer may be perpendicular to a horizontal plane. Alternatively, as shown in Figures 12 to 18, the sidewall of the second doped semiconductor layer 17 facing the first doped semiconductor layer 12 may be inclined with respect to a horizontal plane. In this case, the risk of lateral leakage of electricity between the first doped semiconductor layer 12 and the second doped semiconductor layer 17 can be reduced, ensuring high electrical reliability of the back-contact battery. The size of the included angle at which the sidewall of the second doped semiconductor layer 17 facing the first doped semiconductor layer 12 is inclined with respect to a horizontal plane can be determined according to the actual application and is not specifically limited herein.

[0086] 19, the back-contact cell provided in the embodiments of the present application may further include a second passivation layer 18 located between the silicon substrate 11 and the second doped semiconductor layer 17. In this case, the second passivation layer 18 and the second doped semiconductor layer 17 can form a selective contact structure, thereby achieving chemical passivation for the corresponding region on the back surface of the silicon substrate 11, enabling selective collection of carriers of the corresponding conductivity type, reducing the carrier recombination rate on the back surface side, and helping to improve the photoelectric conversion efficiency of the back-contact cell.

[0087] Specifically, the material of the second passivation layer can be determined according to the material of the second doped semiconductor layer and the type of selective contact structure composed of the second passivation layer and the second doped semiconductor layer in actual applications, and is not specifically limited here.

[0088] For example, when the selective contact structure composed of the second passivation layer and the second doped semiconductor layer is a tunnel passivation contact structure, the second doped semiconductor layer is a doped polycrystalline silicon layer, and the second passivation layer is a tunnel passivation layer, the material of which may include silicon oxide, aluminum oxide, or titanium oxide.

[0089] Furthermore, for example, when the selective contact structure composed of the second passivation layer and the second doped semiconductor layer is a heterocontact structure, the second doped semiconductor layer is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the second passivation layer is an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0090] In a second aspect, an embodiment of the present application provides a method for manufacturing a back contact battery. The manufacturing process is described below based on the cross-sectional views of the operation shown in Figures 20 to 24. Specifically, the method for manufacturing the back contact battery includes the following steps:

[0091] First, a silicon substrate is provided, and the specific structure of the silicon substrate can be referred to above, so a detailed description thereof will be omitted here.

[0092] Next, as shown in FIG. 23, a doped semiconductor material layer 19 is formed on the rear surface of the silicon substrate 11 over the entire layer, and a mask layer 20 is formed on part of the doped semiconductor material layer 19 .

[0093] In an actual manufacturing process, the doped semiconductor material layer is used to manufacture the first doped semiconductor layer of the back contact cell described above, so the material and thickness of the doped semiconductor material layer can be determined based on the material and thickness of the first doped semiconductor layer described above, and the specific material of the doped semiconductor material layer can be used to determine the specific process for forming the doped semiconductor material layer and the specific process for forming the mask layer.

[0094] For example, when the material of the first doped semiconductor layer includes silicon, the step of forming a doped semiconductor material layer and a mask layer located on a portion of the doped semiconductor material layer on a silicon substrate may include: forming an intrinsic semiconductor material layer 21 over the entire layer on the back surface of the silicon substrate 11, as shown in FIG. 20; then, doping the intrinsic semiconductor material layer to form a doped semiconductor material layer 19 from the intrinsic semiconductor material layer, as shown in FIG. 21; and forming a doped silica glass layer 22 over the entire layer on the doped semiconductor material layer 19; subsequently, heat-treating a portion of the doped silica glass layer by a laser etching process to form a mask layer 20 from the unheat-treated portion of the doped silica glass layer, as shown in FIG. 22; and subsequently, removing the heat-treated portion of the doped silica glass layer, as shown in FIG. 23.

[0095] Specifically, the term "the material of the first doped semiconductor layer contains silicon" may refer to the material of the first doped semiconductor layer containing only silicon, or may refer to the material of the first doped semiconductor layer containing silicon and other semiconductor materials, such as germanium silicon. Next, in an actual manufacturing process, an intrinsic semiconductor material layer can be formed over the entire backside surface by a process such as chemical vapor deposition. The intrinsic semiconductor material layer can then be doped by a process such as diffusion. After the doping process, not only can the doped semiconductor material layer be obtained, but also a doped silica glass layer can be formed over the entire doped semiconductor material layer. Subsequently, a portion of the doped silica glass layer is heat-treated by a laser etching process. In this case, as shown in FIG. 22, the laser-treated portion of the doped silica glass layer becomes less dense and is more easily removed. However, since the portions of the doped silica glass layer that are not treated with the laser are highly dense and difficult to remove, different portions of the doped silica glass layer have different etching selectivities after heat treatment, thereby obtaining a mask layer 20 for patterning the doped semiconductor material layer 19. This eliminates the need for a separate mask material or mask deposition process to obtain the mask layer 20, thereby reducing the manufacturing cost of back-contact batteries and simplifying the manufacturing process of back-contact batteries. The specific conditions for the laser etching process can be determined according to the actual application and are not specifically limited herein.

[0096] For example, the laser used in the laser etching process may be a nanosecond laser, a picosecond laser, or a femtosecond laser, etc. The processing power used in the laser etching process may be 10 W or more and 100 W or less, and the diameter of the laser spot may be 50 μm or more and 300 μm or less.

[0097] Of course, whether the material of the first doped semiconductor layer contains silicon or does not contain silicon, a doped semiconductor material layer can be formed over the entire backside layer using a process such as chemical vapor deposition and doping, followed by a process such as chemical vapor deposition and etching to form another masking layer made of silicon nitride or the like.

[0098] It should be noted that if the back-contact battery to be manufactured further includes a first passivation layer located between the first region and the first doped semiconductor layer, after the step of providing a silicon substrate and before the step of forming a doped semiconductor material layer over the entire layer on the back surface of the silicon substrate and a mask layer located on a portion of the doped semiconductor material layer, the method for manufacturing a back-contact battery further includes the step of forming a first passivation material layer 23 over the entire layer on the back surface of the silicon substrate 11, as shown in FIG. 20 .

[0099] Specifically, the first passivation material layer can be formed by a process such as chemical vapor deposition, etc. Since the first passivation material layer is for manufacturing the first passivation layer, the material and thickness of the first passivation material layer can be determined based on the material and thickness of the first passivation layer.

[0100] 24, the doped semiconductor material layer is selectively etched using the mask layer 20 as a mask, thereby forming a first doped semiconductor layer 12 from the remaining portion of the doped semiconductor material layer. The region on the back surface of the silicon substrate 11 corresponding to the first doped semiconductor layer 12 is a first region 13, and the remaining region is a second region 14. The first region 13 and the second region 14 are alternately distributed. Next, using the mask layer 20 as a mask, a groove structure 15 is formed in the second region 14, recessed into the silicon substrate 11 relative to the surface of the first region 13, so that the end of the first doped semiconductor layer 12 adjacent to the second region 14 is raised.

[0101] In actual manufacturing processes, a wet chemical process or other process can be used to form a recessed groove structure in the second region that is recessed into the silicon substrate relative to the surface of the first region, using the mask layer as a mask, thereby preventing damage to the silicon substrate from high-temperature lasers and improving the yield of back-contact batteries. Furthermore, when forming the recessed groove structure using a wet chemical process, the etching method of the silicon substrate using the wet chemical solution is a substantially isotropic etching method, which helps increase the length of the floating edge of the first doped semiconductor layer.

[0102] Specifically, the process conditions for selectively etching the doped semiconductor material layer can be determined according to the etching process used, the material of the doped semiconductor material layer, the specifications of the groove structure to be formed, etc., and are not specifically limited here.

[0103] For example, when a wet chemical process is used to form a trench structure in the second region that is recessed into the silicon substrate relative to the surface of the first region using a mask layer as a mask, the process temperature of the wet chemical process may be 65°C to 85°C. The process time of the wet chemical process may be 50 seconds to 500 seconds. For example, the process temperature of the wet chemical process may be 65°C, 70°C, 75°C, 80°C, or 85°C. The process time of the wet chemical process may be 50 seconds, 100 seconds, 200 seconds, 300 seconds, 400 seconds, or 500 seconds. In this case, both the process temperature and the process time of the wet chemical process affect the dimensions of the trench structure formed by the wet chemical process and the dimensions of the raised end of the first doped semiconductor layer. Therefore, by setting the process temperature of the wet chemical process within the above range, it is possible to prevent the depth of the trench structure and the raised installation height and length of the raised end of the first doped semiconductor layer from being reduced due to low process temperature. In addition, it is possible to prevent the depth of the groove structure from increasing due to a high process temperature. The above description can be referred to for the beneficial effects of preventing the depth of the groove structure, the floating installation height and length of the floating end of the first doped semiconductor layer from all decreasing, and preventing the depth of the groove structure from increasing. Furthermore, the beneficial effects of keeping the process time within the above range are similar to the beneficial effects of setting the process temperature between 65°C and 85°C, and therefore will not be described in detail here.

[0104] It should be noted that if the first passivation material layer is formed on the back side before forming the doped semiconductor layer, after the step of selectively etching the doped semiconductor material layer using the mask layer as a mask and before the step of forming a groove structure in the second region using the mask layer as a mask, which is recessed into the silicon substrate relative to the surface of the first region, the manufacturing method for the back contact battery includes the step of selectively etching the first passivation material layer using a process such as wet chemistry as a mask, to form a first passivation layer with the remaining part of the first passivation material layer.

[0105] In addition, when the bottom of the groove structure in the back-contact battery to be manufactured is a textured surface, the step of forming a groove structure in the second region that is recessed into the silicon substrate relative to the surface of the first region is performed using the mask layer as a mask, and at the same time, the bottom of the groove structure can be formed into a textured surface by performing a texturing process on the groove bottom of the groove structure.

[0106] Specifically, a groove structure having a textured bottom can be formed by adding a texturing additive to a wet chemical solution used to etch a portion of a silicon substrate. Specifically, the type of texturing additive and the proportion of the texturing additive in the wet chemical solution can be determined according to the actual application.

[0107] For example, the texturing aid additive may include sodium benzoate, antifoaming agents, surfactants, etc. The proportion of the texturing aid additive in the wet chemical solution may be 0.5% to 5%.

[0108] If the back-contact battery to be fabricated further includes the second doped semiconductor layer, after the step of forming a groove structure in the second region that is recessed into the silicon substrate relative to the surface of the first region using the mask layer as a mask, the method for fabricating the back-contact battery further includes the step of forming a second doped semiconductor layer at the bottom of the groove structure. Specifically, the second doped semiconductor layer can be formed using processes such as chemical vapor deposition and selective etching. The material and thickness of the second doped semiconductor layer can be referenced above, and therefore will not be described in detail here.

[0109] If the back-contact battery to be fabricated further includes a second passivation layer located between the silicon substrate and the second doped semiconductor layer, after forming a groove structure in the second region using the mask layer as a mask, the groove structure is recessed into the silicon substrate relative to the surface of the first region, and before forming the second doped semiconductor layer at the groove bottom of the groove structure, the fabrication method for the back-contact battery further includes forming a second passivation layer at the groove bottom of the groove structure, the material and thickness of which can be referenced above.

[0110] Specifically, after forming the trench structure and before forming the second doped semiconductor layer, a second passivation layer can be formed at the bottom of the trench structure using a process such as chemical vapor deposition and selective etching.

[0111] Alternatively, a second passivation material layer and a second doped semiconductor material layer can be sequentially formed over the entire backside layer using a process such as chemical vapor deposition, followed by selectively removing portions of the second passivation material layer and the second doped semiconductor material layer using a process such as laser etching, thereby obtaining the second passivation layer and the second doped semiconductor layer located only at the bottom of the trench structure.

[0112] It should be noted that when the back-contact cell to be fabricated further includes a second passivation layer and a second doped semiconductor layer, the bottom of the groove structure formed in the second region using the mask layer as a mask may be flat. In this case, when the second passivation layer is formed on the bottom of the groove structure using the above method, the second passivation layer can be formed on a flat surface, which helps to improve the passivation effect of the second passivation layer on the corresponding surface of the silicon substrate. In addition, after the step of forming the second doped semiconductor layer on the bottom of the groove structure, the exposed portion of the second doped semiconductor layer at the bottom of the groove structure can be textured. This allows the exposed surface of the second doped semiconductor layer at the bottom of the groove structure to have a certain light trapping effect, allowing more light to penetrate through the exposed surface of the second doped semiconductor layer at the bottom of the groove structure and reach the silicon substrate, improving the photoelectric conversion efficiency of the back-contact cell.

[0113] Specifically, in an actual manufacturing process, when a wet chemical process is used to pattern a second doped semiconductor material layer for manufacturing the second doped semiconductor layer, a texturing additive can be added to the etchant used in the wet chemical process, thereby simultaneously manufacturing the second doped semiconductor layer and forming a textured surface. The specific components and proportions of the texturing additive can be found above, so a detailed description will be omitted here.

[0114] The beneficial effects of the second aspect and its various implementation forms in the embodiments of the present application may be referred to the analysis of the beneficial effects of the first aspect and its various implementation forms, and will not be described here.

[0115] In addition, the present application also provides one comparative example and one example to illustrate the manufacturing process and performance of the back contact batteries provided in the present application examples. Table 1 shows the test results of the back contact batteries corresponding to Example 1 and Comparative Example 1. Example 1

[0116] In step 1, a single crystal silicon wafer is subjected to an alkaline polishing treatment using an alkaline solution with a concentration of 15% to obtain a smooth and clean silicon surface.

[0117] In step 2, a tunnel oxide layer and an intrinsic polysilicon layer are sequentially deposited on the surface of the single crystal silicon wafer, where the tunnel oxide layer is 1.8 nm thick and the intrinsic polysilicon layer is 350 nm thick.

[0118] In step 3, the deposited intrinsic polycrystalline silicon layer is doped with boron to convert the intrinsic polycrystalline silicon layer into a doped polycrystalline silicon layer, and a borosilicate glass layer is formed on the doped polycrystalline silicon layer. Here, the boron doping concentration is 8×10 19 / cm 3 is.

[0119] In step 4, a mask layer having a specific pattern is fabricated by heat treating the borosilicate glass layer using a laser etching process, where the laser can be a picosecond laser generator, the processing power can be 40 W, and the spot diameter is 200 μm.

[0120] In step 5, the mask layer is used as a mask to selectively remove a portion of the doped polycrystalline silicon layer. The single-crystalline silicon wafer is then subjected to a surface etching process to form a groove structure, while simultaneously raising the edge of the doped polycrystalline silicon layer adjacent to the groove structure. The etching solution mainly comprises an alkali and a texturing additive. The alkali concentration in the etching solution is 5%, the etching temperature is 82°C, the process time is 300 seconds, and the proportion of the texturing additive is 2%. The main components of the texturing additive include sodium benzoate, an antifoaming agent, and a surfactant.

[0121] In step 6, a tunnel oxide layer and an N-type doped polysilicon layer are sequentially formed at the bottom of the trench structure, where the thickness of the N-type doped polysilicon layer is 150 nm to 180 nm, and the thickness of the tunnel oxide layer is 0.5 nm to 3 nm. Comparative Example 1

[0122] The manufacturing method corresponding to Comparative Example 1 has the same manufacturing flow as Example 1, except for steps 4 and 5. Here, in the manufacturing method provided in Comparative Example 1, after the deposited intrinsic polycrystalline silicon layer is doped with boron and before the tunnel oxide layer and the N-type doped polycrystalline silicon layer are formed in sequence at the bottom of the trench structure, the borosilicate glass layer is removed, and the formed tunnel oxide layer and the doped polycrystalline silicon layer are directly and selectively etched using a laser etching process to form a trench structure in the silicon substrate whose sidewalls are perpendicular to a horizontal plane.

[0123] [Table 1]

[0124] As can be seen from the data in Table 1, in the back-contact battery formed by the manufacturing method provided in Example 1, the edge adjacent to the groove structure of the first doped semiconductor layer is raised, allowing more light to be reflected back into the silicon substrate and reused by the silicon substrate, resulting in higher operating efficiency, open circuit voltage, short circuit current, and fill factor than the back-contact battery obtained by the manufacturing method corresponding to Comparative Example 1. In other words, the back-contact battery provided in the examples of the present application has higher operating performance.

[0125] The above description does not provide a detailed description of the technical details of each layer, such as the structure and etching of each layer. However, those skilled in the art should understand that layers, regions, etc. of desired shapes can be formed using various technical means. Furthermore, those skilled in the art can design methods that are not completely identical to the methods described above to form the same structure. Furthermore, although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used together.

[0126] The above describes the embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is limited by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all of these substitutions and modifications are intended to fall within the scope of the present disclosure. [Explanation of symbols]

[0127] 11 Silicon substrate 12 First doped semiconductor layer 13 First area 14 Second area 15 Groove structure 16 First passivation layer 17 Second doped semiconductor layer 18 Second passivation layer 19 doped semiconductor material layer 20 mask layers 21 Intrinsic semiconductor material layer 22 doped silica glass layer 23 First passivation material layer.

Claims

1. a silicon substrate; and a first doped semiconductor layer formed on a partial region of a rear surface side of the silicon substrate; a back-contact battery in which a region on the back surface of the silicon substrate corresponding to the first doped semiconductor layer is a first region, and the remaining region is a second region, the first region and the second region are alternately distributed, and a groove structure recessed into the silicon substrate with respect to the surface of the first region is formed in the second region, and an end of the first doped semiconductor layer adjacent to the second region is arranged to be floating.

2. The depth of the groove structure is 200 nm or more and 2500 nm or less, and / or 2. The back contact battery of claim 1, wherein the length of the floating end of the first doped semiconductor layer in the alignment direction of the first region and the second region is greater than 0 and less than or equal to 3000 nm.

3. at least a portion of the surface of the side wall of the groove structure is inclined with respect to a horizontal plane so that a cross-sectional area of ​​at least a portion of the groove structure gradually increases from the light-receiving surface toward the back surface, and / or 2. The back-contact battery of claim 1, wherein the surface of the sidewall of the groove structure adjacent to the groove mouth is perpendicular to a horizontal plane.

4. 4. The back-contact battery of claim 3, wherein an included angle between the horizontal plane and the portion of the sidewall of the groove structure that is inclined relative to the horizontal plane is 52° to 58°.

5. 5. The back-contact battery of claim 3, wherein the sidewall of the groove structure has a flat surface parallel to the horizontal plane between the surface of the portion close to the groove mouth and the surface of the portion close to the groove bottom.

6. In the arrangement direction of the first region and the second region, the length of a plane parallel to the horizontal plane on the sidewall of the groove structure is greater than 0 μm and less than 2 μm, and / or 6. The back-contact battery of claim 5, wherein in the arrangement direction of the first region and the second region, the minimum distance from a plane parallel to the horizontal plane on the sidewall of the groove structure to the groove opening of the groove structure is greater than 0 and less than 1 μm.

7. The back-contact battery of claim 1 , wherein at least a portion of the surface of the groove bottom of the groove structure is a textured surface.

8. a first passivation layer located between the first region and the first doped semiconductor layer; and / or 2. The back contact battery of claim 1, further comprising a second doped semiconductor layer formed at the bottom of the groove structure and having a conductivity type opposite to that of the first doped semiconductor layer.

9. and / or, if the first passivation layer is a tunnel passivation layer, the first doped semiconductor layer is a doped polycrystalline silicon layer; and / or If a second doped semiconductor layer is included, a second passivation layer is located between the silicon substrate and the second doped semiconductor layer; and / or 9. The back-contact battery of claim 8, wherein when the back-contact battery includes a second doped semiconductor layer, the distance between the first doped semiconductor layer and the second doped semiconductor layer is 20 μm or more and 110 μm or less in the arrangement direction of the first region and the second region.

10. 10. The back contact cell of claim 9, wherein said second passivation layer is a tunnel passivation layer and said second doped semiconductor layer is a doped polycrystalline silicon layer.

11. providing a silicon substrate; forming a doped semiconductor material layer over the entire surface of the back surface of the silicon substrate and a mask layer over a portion of the doped semiconductor material layer; selectively etching the doped semiconductor material layer using the mask layer as a mask to form a first doped semiconductor layer using the remaining portion of the doped semiconductor material layer; using the mask layer as a mask, forming a groove structure in the second region that is recessed into the silicon substrate relative to the surface of the first region, so that an end of the first doped semiconductor layer adjacent to the second region is provided so as to be raised; A method for manufacturing a back-contact battery, wherein a region on the back surface of the silicon substrate corresponding to the first doped semiconductor layer is a first region, and the remaining region is a second region, and the first region and the second region are distributed alternately.

12. the material of the first doped semiconductor layer comprises silicon; The step of forming a doped semiconductor material layer over the entire back surface of the silicon substrate and a mask layer located on a portion of the doped semiconductor material layer includes: forming an intrinsic semiconductor material layer disposed over the entire back surface of the silicon substrate; doping the intrinsic semiconductor material layer to form the doped semiconductor material layer from the intrinsic semiconductor material layer, and forming a doped silica glass layer disposed over the doped semiconductor material layer; heat-treating a portion of the doped silica glass layer in a laser etching process to form the mask layer with the unheat-treated portion of the doped silica glass layer; and removing said heat treated portion of said doped silica glass layer.

13. 12. The method for manufacturing a back-contact battery of claim 11, wherein a wet chemical process is used to form the groove structure in the second region, recessed into the silicon substrate relative to the surface of the first region, using the mask layer as a mask, and the process temperature of the wet chemical process is 65°C or more and 85°C or less, and / or the process time of the wet chemical process is 50 seconds or more and 500 seconds or less.

14. After the step of providing a silicon substrate and before the step of forming a doped semiconductor material layer disposed over the entire surface of a back surface of the silicon substrate and a mask layer located on a portion of the doped semiconductor material layer, the method further includes the step of forming a first passivation material layer disposed over the entire surface of the back surface of the silicon substrate; 14. The method for manufacturing a back contact battery of claim 11, further comprising the step of selectively etching the doped semiconductor material layer using the mask layer as a mask, and before the step of forming a trench structure in the second region using the mask layer as a mask, the trench structure being recessed into the silicon substrate relative to the surface of the first region, by selectively etching the first passivation material layer using the mask layer as a mask, to form a first passivation layer with remaining portions of the first passivation material layer.

15. 14. The method for manufacturing a back-contact battery according to claim 11, wherein the step of forming a groove structure recessed into the silicon substrate relative to the surface of the first region is performed in the second region using the mask layer as a mask, and simultaneously, a texturing process is performed on the groove bottom of the groove structure to form a textured surface.

16. After the step of forming a groove structure in the second region, which is recessed into the silicon substrate relative to the surface of the first region, using the mask layer as a mask, 14. The method for fabricating a back-contact battery according to claim 11, further comprising forming a second doped semiconductor layer on the bottom of the groove structure.

17. after the step of forming a trench structure in the second region, the trench structure being recessed into the silicon substrate relative to the surface of the first region, using the mask layer as a mask, and before the step of forming a second doped semiconductor layer at the bottom of the trench structure; 17. The method for manufacturing a back-contact battery of claim 16, further comprising forming a second passivation layer on the groove bottom of the groove structure.

18. a groove bottom of the groove structure formed in the second region using the mask layer as a mask is flat; 17. The method for manufacturing a back-contact battery according to claim 16, wherein after the step of forming a second doped semiconductor layer on the groove bottom of the groove structure, a texturing treatment is performed on the exposed portion of the second doped semiconductor layer on the groove bottom of the groove structure.

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