Image sensor column readout amplifiers

Abstract

Examples include a column readout amplifier and an image sensor including the same. In one example, the column readout amplifier includes a signal amplifier having an amplifier output and first and second amplifier inputs, a filter capacitor having first and second terminals, the second terminal connected to a ground terminal, a buffer amplifier having a buffer amplifier input and a buffer amplifier output, a switching network configured to switchably connect the amplifier output to the buffer amplifier input and the buffer amplifier output to the first terminal of the filter capacitor during a first period and to switchably connect the amplifier output directly to the first terminal of the filter capacitor during a second period, and a low pass filter connected in a feedback path of the signal amplifier between the amplifier output and the first amplifier input, the low pass filter including a series resistor and a capacitor.

Description

[Background technology]

[0001] Image sensors, such as CMOS image sensors, are widely used in a wide variety of applications spanning a large portion of the electromagnetic spectrum. Many image sensor designs use a two-dimensional array of sensors that capture interacting light over a given region. Each sensor can be considered a single pixel in a sensor array having pixels arranged in any number of rows and columns. Each pixel sensor contains some form of photodetector and readout circuitry that converts the charge accumulated by the photodetector ("photocharge") during image exposure into a voltage that is read out by a readout amplifier shared by all of the pixel sensors in a column (hence the term column readout amplifier). The pixel sensors in each row are read out in parallel using the column readout amplifier.

[0002] To maintain low noise, the time between the transfer of photocharges to the readout circuitry within the pixel sensor and the readout of those charges must be as short as possible, as noise accumulates in the pixel sensor during this stage. To limit noise in the column readout amplifiers, low-bandwidth amplifiers can be utilized. The lower the bandwidth of the column readout amplifiers, the lower the readout noise from the column readout amplifiers. However, reducing the bandwidth of the column readout amplifiers increases the time required to readout the pixel sensor, because amplifiers with reduced bandwidth take longer to settle. Thus, there is a trade-off between readout time and readout noise. Therefore, reducing noise in column readout amplifiers remains a challenge for image sensors. Summary of the Invention

[0003] Aspects and embodiments are directed to column readout amplifiers and methods of using same. In particular, certain aspects are directed to column readout amplifier circuits that incorporate low pass filtering in the amplifier feedback path to reduce readout noise.

[0004] In one embodiment, the column readout amplifier comprises: a signal amplifier having an amplifier output, a first amplifier input, and a second amplifier input, the second amplifier input being connected to a reference voltage terminal; a filter capacitor having first and second terminals, the second terminal being connected to a ground terminal; a buffer amplifier having a buffer amplifier input and a buffer amplifier output; a switching network configured to switchably connect the amplifier output to the buffer amplifier input and the buffer amplifier output to the first terminal of the filter capacitor during a first period, and to switchably connect the amplifier output directly to the first terminal of the filter capacitor during a second period; and a low pass filter connected in a feedback path of the signal amplifier between the amplifier output and the first amplifier input, the low pass filter including a series resistor and a capacitor.

[0005] In another embodiment, an image sensor includes a bit line conductor, a pixel array having at least one column of addressable pixel sensors, each pixel sensor connected to the bit line conductor in response to a word select signal, and a column amplifier connected to the bit line conductor, the column amplifier including: a signal amplifier having an amplifier output, a first amplifier input, and a second amplifier input, the second amplifier input connected to a reference voltage terminal; a filter capacitor having first and second terminals, the second terminal connected to a ground terminal; a buffer amplifier having a buffer amplifier input and a buffer amplifier output; a switching network configured to switchably connect the amplifier output to the buffer amplifier input and the buffer amplifier output to the first terminal of the filter capacitor during a first period and to switchably connect the amplifier output directly to the first terminal of the filter capacitor during a second period; and a low pass filter connected in a feedback path of the signal amplifier between the amplifier output and the first amplifier input, the low pass filter including a series resistor and a capacitor.

[0006] Examples of column amplifiers and image sensors may include any one or more of the following features.

[0007] In one example, the column readout amplifier further comprises a capacitor connected between the amplifier output and a ground terminal.

[0008] In another example, the column readout amplifier further comprises a feedback capacitor connected in series with the series resistor in the feedback path of the signal amplifier.

[0009] In one example, the signal amplifier comprises a capacitive transimpedance amplifier configured with a gain greater than one.

[0010] In another example, a capacitor is connected between a node between the series resistor and the feedback capacitor and a ground terminal.

[0011] In another example, the capacitance of the capacitor is less than the capacitance of the filter capacitor.

[0012] In another example, the capacitance of the filter capacitor is variable.

[0013] In one example, the buffer amplifier output is disconnected from the filter capacitor during a second period of time.

[0014] In another example, the buffer amplifier has a gain substantially equal to one.

[0015] In another example, the column readout amplifier further comprises an input capacitor connected to the first input of the signal amplifier.

[0016] Further aspects, embodiments, and advantageous effects of these exemplary aspects and embodiments are described in detail below. The embodiments disclosed herein may be combined with other embodiments in any manner consistent with at least one of the principles disclosed herein, and references to "embodiments," "some embodiments," "alternative embodiments," "various embodiments," "one embodiment," etc. are not necessarily mutually exclusive but rather indicate that a particular feature, structure, or characteristic described may be included in at least one embodiment. Appearances of such terms herein do not necessarily all refer to the same embodiment. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a block diagram of an example image sensor system using a pixel array and column readout amplifiers according to aspects of the present disclosure. [Figure 2] FIG. 1 is a circuit diagram illustrating an example of a prior art column readout amplifier connected to one pixel sensor in a column of pixel sensors. [Figure 3] FIG. 3 is a timing diagram for various signals that control certain aspects of the readout of the pixel sensor shown in FIG. 2. [Figure 4] FIG. 2 is a circuit diagram illustrating an example of a column readout amplifier connected to one pixel sensor in a column of pixel sensors according to an embodiment of the present disclosure. [Figure 5] 5 is a comparative graph illustrating simulated noise detection examples for readouts from the circuit of FIG. 2 and the circuit of FIG. 4 according to an embodiment of the present disclosure. [Figure 6] FIG. 2 is a block diagram of an example of a computing platform that may include the image sensor of FIG. 1 according to an aspect of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0018] A column readout amplifier structure is disclosed that exhibits reduced noise, particularly at high readout frame rates, with no or relatively little increase in power consumption. Column readout amplifier embodiments may include low-pass filtering circuitry in the amplifier's feedback path to reduce readout noise, as described in more detail below. In one example, the column readout amplifier may be used with an image sensor that includes an array of light-sensitive pixel sensors.

[0019] Overview Image sensors operating at high frame rates generally require high bandwidth column readout amplifiers to ensure that the amplifier output settles sufficiently over the short readout times available at high frame rates. However, as noted above, the higher the bandwidth of the column readout amplifier, the higher the readout noise from the column readout amplifier. High readout noise can be problematic for some imaging applications, especially those in which the image sensor may operate in very low illumination conditions.

[0020] Accordingly, techniques are disclosed herein for designing column readout amplifiers that exhibit reduced readout noise at both high and low readout frame rates. According to one example, the column amplifier includes a low-pass filter in the amplifier feedback path, which contributes to reducing readout noise by about 10% at high frame rates (e.g., rates of about 120 frames per second (fps)) and by about 5% at low frame rates (e.g., rates of about 30 fps) for the same power consumption.

[0021] In some embodiments, the image sensor includes a pixel array having at least one column of addressable pixel sensors and a column readout amplifier connected to the at least one column of addressable pixel sensors. The column readout amplifier may include a signal amplifier having an amplifier output, a first amplifier input, and a second amplifier input, the second amplifier input connected to a reference voltage terminal, and a filter capacitor having first and second terminals, the second terminal connected to a ground terminal. The column readout amplifier may further include a buffer amplifier having a buffer amplifier input and a buffer amplifier output, and a switching network configured to switchably connect the amplifier output to the buffer amplifier input and the buffer amplifier output to the first terminal of the filter capacitor during a first period and to switchably connect the amplifier output directly to the first terminal of the filter capacitor during a second period. The column readout amplifier may further include a low-pass filter connected in a feedback path of the signal amplifier between the amplifier output and the first amplifier input, the low-pass filter including a series resistor and a capacitor.

[0022] System Architecture FIG. 1 is a block diagram of an example image sensor 100 according to some embodiments. Image sensor 100 may represent or be an integral part of a charge-coupled device (CCD) camera or other type of imaging device. In some embodiments, image sensor 100 may be configured to capture various portions of the electromagnetic spectrum, such as visible light, ultraviolet light, infrared light, or X-rays, to name a few. Image sensor 100 may include a pixel array 110, column readout amplifiers 120, an analog-to-digital converter (ADC) 130, and a processor 140. Each of the described components may be included together on the same printed circuit board (PCB) or together in a single chip package (e.g., a system-in-package or system-on-chip). In some other embodiments, any one or more of the elements may be provided in separate chip packages and / or separate PCBs.

[0023] In some embodiments, the pixel array 110 includes a plurality of pixel sensors 112 arranged in a matrix. Each pixel sensor 112 in the pixel array 110 may have a similar architecture, including a photodetector and readout circuitry. The photodetection area of ​​each pixel sensor, which may be affected by incident light, may vary from one embodiment to the next, but in some example cases has a physical size of approximately 1 μm×1 μm to approximately 5 μm×5 μm. Similarly, the shape of the photodetection area (e.g., photodiode) and lens configuration (if present) may also vary from one example to the next, depending on factors such as the desired fill factor of the array. In some embodiments, each row of pixel sensors may be connected to one another via a common row select line (e.g., word line) to provide an independently addressable row of pixel sensors.

[0024] In some embodiments, outputs from pixel sensors 112 in N different columns are received by column readout amplifiers 120. In some embodiments, column readout amplifiers 120 represent N separate column readout amplifiers, with a given column readout amplifier configured to receive outputs from pixel sensors in a corresponding column of pixel array 110. In this manner, pixel sensors in a given row of pixel array 110 may be selected via a row select line and simultaneously read out via N column readout amplifiers 120. In some embodiments, column readout amplifiers 120 may include any type of amplifier configuration, such as any number of source follower FETs or operational amplifiers. In some embodiments, a single column readout amplifier 120 may be used in conjunction with a multiplexer to receive each of the N column outputs from pixel array 110.

[0025] According to some embodiments, the outputs from the column readout amplifiers 120 are received by the ADC 130. As noted above, the ADC 130 may represent N different ADCs, with a given ADC configured to receive the outputs from a corresponding column readout amplifier 120. The ADC 130 may be any known type of ADC, without limitation.

[0026] The processor 140 may be configured to receive the digitally converted signals from the ADCs 130 (i.e., N digitally converted signals across the N ADCs) and perform any number of operations using the signals. For example, the processor 140 may receive signal data from pixel sensors in a given row of the pixel array 110 and use the signal data to generate an image, or a portion of an image, captured via the pixel array 110. In some embodiments, the processor 140 may provide control inputs 122 to the column readout amplifiers to change the amplifier's operating mode, as described further below. As used herein, the term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. The processor 140 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, custom semiconductors, or any other suitable processing device.

[0027] Column Readout Amplifier Design The manner in which a column readout amplifier according to embodiments disclosed herein provides advantageous effects can be more easily understood with reference to FIG. 2. FIG. 2 shows a prior art column readout amplifier 200 connected to one pixel sensor 202 (e.g., one of the pixel sensors 112) in a column of pixel sensors. The particular pixel sensor 202 connected to a bit line 204 is identified by a signal on a corresponding word line 206. The column readout amplifier 200 includes a capacitive transimpedance amplifier 210, which includes an operational amplifier 212, an input capacitor 214 connected to one input of the operational amplifier 212, and a feedback capacitor 216. Prior to detecting the voltage on the bit line 204, the input and output of the capacitive transimpedance amplifier 210 are shorted by closing a switch 218 to reset the amplifier. The gain of the capacitive transimpedance amplifier 210 is given by the ratio of the capacitances of the capacitors 214 and 216 and is typically on the order of 30. The bandwidth of the capacitive transimpedance amplifier 210 is set by a capacitor C3.

[0028] FIG. 3 is a timing diagram for various signals associated with the readout operation of pixel sensor 202 using column amplifier 200. As shown in FIG.

[0029] 2 and 3, the pixel sensor 202 includes a photodiode 208 that accumulates charge during image exposure. At the end of image exposure, the floating diffusion node 220 is reset to voltage Vrst by closing gate 222 using a signal on the reset line (Reset). The voltage at the floating diffusion node 220 after the reset operation is detected via source follower 224 and column readout amplifier 200 and stored in the sample-and-hold circuit of capacitor C1 in the column readout amplifier 200. After this voltage detection, gate 226 is made conductive in response to the Tx signal. The positive potential at the floating diffusion node 220 transfers all of the charge in the photodiode 208 to the floating diffusion node 220. The transferred charge causes the potential at the floating diffusion node 220 to drop below the reset potential. The potential at the floating diffusion node 220 is then detected by the column readout amplifier 200 and stored in the sample-and-hold circuit of capacitor C2. The voltage difference across capacitors C1 and C2 is then used to determine the charge generated by photodiode 208 during exposure.

[0030] A readout operation using column amplifier 200 can be viewed as occurring in four phases, as shown in Figure 3. During Phase 1 (S1 = High, S2 = High, S3 = High, S3 = Low), capacitive transimpedance amplifier 210 is connected to capacitor C3, and the output of capacitive transimpedance amplifier 210 (V out1 ) is routed to a buffer amplifier 228 which charges a filter capacitor C4. The gain (G b =1), the output voltage of the buffer amplifier, V out2 is the voltage V out1 Continued. Output voltage V out2 When is statically determined, its value is V out2 =V out1 +V os (1) It is given by V osis the offset voltage of the buffer amplifier. If the value of C3 is low (small capacitance), the bandwidth of the capacitive transimpedance amplifier 210 may be relatively high, resulting in high read noise in this phase. Furthermore, V out2 The noise level at V is due to the high current gain associated with the buffer amplifier 228. out1 This can increase significantly relative to the noise level at

[0031] To begin phase 2, as shown in FIG. 3, switch S3 transitions from high to low, and switch S3 goes from low to high. During phase 2 (S1=High, S2=High, S3=Low, S3=High), the capacitive transimpedance amplifier 210 is connected to capacitors C1, C2, C3, and C4. Because the gain of the buffer amplifier 228 is equal to 1, the buffer amplifier 228 can drive large capacitances, and C4 can be much larger than any of C1, C2, and C3. As a result, the bandwidth of the capacitive transimpedance amplifier 210 decreases due to the increased capacitance, especially when C4 is large. This can reduce read noise during this phase. Furthermore, during phase 2, switch S3 is opened to disconnect the buffer amplifier 228. Therefore, the offset voltage V of the buffer amplifier decreases. os is removed, so V out1 =V out2 This becomes:

[0032] 2 in Phases 3 and 4 are similar to those in Phases 1 and 2, respectively. The difference is that, as noted above, S1 is low and photocharge from the photodiode 208 is transferred to the floating diffusion node 220 by the Tx gate 226. During Phases 2 and 4, the buffer amplifier 228 may be turned off to conserve power. Towards the end of Phase 4, when S2 goes from high to low, the readout output becomes V out =V outp -V outm (2) (i.e.) given by the voltage difference across capacitors C1 and C2 as described above.

[0033] There are several drawbacks associated with the column amplifier 200 of FIG. 2 , including the persistent issue of high read noise, particularly at higher read frame rates. As mentioned above, keeping C3 small to achieve high bandwidth may be necessary for high frame rates, but results in high read noise during phase 1. While the read noise in phase 2 can be reduced by using a large value capacitor for C4, this reduces the bandwidth of the capacitive transimpedance amplifier 210 and limits the frame rate. Therefore, it may be necessary to keep C4 small for operation at high frame rates, resulting in still high read noise.

[0034] Accordingly, aspects and embodiments address these shortcomings and provide a column readout amplifier that can operate with reduced readout noise compared to column amplifier 200, particularly at high frame rates, at the same power consumption. Figure 4 is a circuit diagram of an example column readout amplifier 300 according to aspects of the present disclosure. For simplicity, elements of column readout amplifier 300 that perform similar functions as those shown in Figure 2 for column readout amplifier 200 are numbered the same and will not be described in further detail. Additionally, the signal timing of column readout amplifier 300 is the same as that shown in Figure 3 for column readout amplifier 200 and will therefore not be described further below.

[0035] 4, there is shown a column readout amplifier 300 connected to the pixel sensor 202 and configured to read out a voltage corresponding to the photocharge accumulated by the pixel sensor 202, as described above. The column readout amplifier 300 includes a signal amplifier 302, which in the illustrated example is a capacitive transimpedance amplifier. The gain (G a) is greater than 1. The output of the signal amplifier is connected to a first terminal of a first capacitor 304, and switchably connected to a first terminal of a filter capacitor 306, either directly (when switch S3 is open and switch S3 is closed) or via a buffer amplifier 308 (when switch S3 is closed and switch S3 is open), similar to the configuration described above with reference to Figures 2 and 3. The second terminals of capacitors 304 and 306 are connected to ground. The voltage V out2 is read out via an analog memory (sample and hold circuit) by capacitors C1 and C2, as described above. In one example, the use of a pair of capacitors C1 and C2 for correlated double sampling (CDS), as described above, helps reduce low frequency noise.

[0036] The buffer amplifier 308 may be a unitary gain amplifier (i.e., a gain G approximately equal to 1 within reasonable tolerances). b Therefore, when the buffer amplifier 308 is connected to the output of the signal amplifier 302, the voltage V out2 is the voltage V out1 Continued. Voltage V out2 and voltage V out1 The difference between the noise from the buffer amplifier 308 and the offset voltage V os This may occur as a result of any slight difference in the gain of buffer amplifier 308 relative to a gain of V. Typically, the gain of buffer amplifier 308 is set substantially equal to 1. The amount by which the gain may differ from 1 depends on the amount of potential mismatch that is acceptable for filter capacitor 306. Any mismatch will be tolerated if the voltage on filter capacitor 306 drops below V after switch S3 is opened. out1 , the amount of additional time generally depends on the particular application. Buffer amplifier 308 operates to accelerate the charging rate of filter capacitor 306 during the phase of the read operation when the buffer amplifier is connected to the output of signal amplifier 302 (i.e., when switch S3 is closed and switch S3 is open).

[0037] In some examples, the filter capacitor 306 may have a variable capacitance that can be increased or decreased depending on the application and current operating mode of the column readout amplifier 300. For example, in situations where the readout operation has a relatively low frame rate (e.g., approximately 30 fps), the bandwidth of the signal amplifier 302 can be reduced due to the slow readout, and the capacitance of the filter capacitor 306 can be increased to reduce readout noise. As described above, the unit gain buffer amplifier 308 may be capable of driving a high capacitance, allowing the capacitance value of the filter capacitor 306 to be significantly larger than that of C1, C2, and / or capacitor 304. In situations where the readout operation has a high frame rate, and therefore a higher bandwidth is required for the signal amplifier 302, the capacitance of the filter capacitor 306 can be reduced. A variable capacitance value may be achieved by implementing the capacitor 306 using one or more variable capacitors and / or one or more switchable fixed-value capacitors that can be switchably connected and disconnected to generate the desired composite capacitance value.

[0038] As mentioned above, in some examples, the capacitor 304 may be selected to have a very small capacitance so that the signal amplifier 302 has a high bandwidth, which may be necessary for high frame rate readout operations. Also, configuring the capacitor 304 to have a very small capacitance value may be necessary when the amplifier gain is very high (e.g., G a ≈32), the output voltage V from the signal amplifier 302 out1 This can advantageously contribute to faster settling. A faster settling time also enables readout operations at higher frame rates. However, as mentioned above, using a small filter capacitor 306 in conjunction with a small filter capacitor 304 for high frame rate readout operations can result in high readout noise.

[0039] To alleviate this problem, the column readout amplifier 300 includes a low pass filter in the feedback path (indicated by arrow 312) of the signal amplifier 302. FIG. 4 shows an input capacitor 214 (C in ) and capacitor 314 (C f ) the gain G given by the ratio of the capacitances a (G a =G in / C f ) in high gain mode. In one example, the gain G a may be approximately 30, for example 32. The low pass filter includes a series resistor 316 connected in series with a capacitor 314, and a shunt capacitor 318 connected between a node between the series resistor 316 and the capacitor 314 and ground, as shown. By adding the low pass filters 316, 318 in the feedback path, a sum node 320 (V in ) vs. amplifier output voltage V out1 In other words, the low pass filters 316, 318 contribute to reducing the total noise at node 320, which in turn reduces the effect of noise on the amplifier output V in the forward path. out1 This contributes to reducing noise in the

[0040] In one example, to maintain the power consumption and amplifier slew rate of the signal amplifier 302, the capacitance of the shunt capacitor 318, which forms part of the low pass filter, is much smaller than the capacitance of the filter capacitor 306. In one example, the capacitance of the shunt capacitor 318 is in the range of approximately 0.1 to 0.5 picofarads (pF), e.g., 0.15 pF, and the series resistor 316 has a resistance of approximately 200 kiloohms (KΩ). The low pass filters 316, 318 are configured to provide a V out2 At lower frame rates, the capacitance of the filter capacitor 306 can be very large as discussed above, so that the voltage V out1 and V out2The noise level at V may be lower, however, the addition of the low pass filters 316, 318 still acts to reduce noise for the column readout amplifiers 200. For example, the low pass filters 316, 318 may reduce the noise level at V at a readout frame rate of 30 fps. out2 This can contribute to a read noise reduction of about 5% (relative to column readout amplifier 200) at 100 MHz. Simulations have confirmed the read noise reduction of column readout amplifier 300 relative to column readout amplifier 200 under the same conditions.

[0041] 5 is a graph showing noise simulation results at 120 fps for an example of column readout amplifier 200 (curve 502) and an example of column readout amplifier 300 (curve 504) under the same conditions. It can be seen that the readout noise associated with column readout amplifier 300 is reduced relative to the readout noise associated with column amplifier 200.

[0042] Thus, aspects and embodiments provide a column readout amplifier that helps reduce readout noise at high frame rates without increasing power consumption. Embodiments of column readout amplifier 300 may be used as column readout amplifier 120 in image sensor 100 to enable the image sensor to operate with lower noise and therefore higher sensitivity, which may be advantageous in many applications, particularly low-light imaging applications.

[0043] Exemplary Computing Platform 6 illustrates an exemplary computing platform 600 interfacing with image sensor 100 configured in accordance with certain embodiments of the present disclosure. In some embodiments, computing platform 600 may host or be incorporated into a personal computer, a workstation, a server system, a laptop computer, an ultra-laptop computer, a tablet, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a mobile phone, a combination mobile phone and PDA, a smart device (e.g., a smartphone or smart tablet), a mobile internet device (MID), a messaging device, a data communication device, an imaging device, a wearable device, an embedded system, or the like. Any combination of various devices may be used in a particular embodiment. Computing platform 600 may host a controller area network (CAN) used in a vehicle. In some embodiments, computing platform 600 represents one system in a network of systems interconnected via a CAN bus.

[0044] In some examples, the computing platform 600 may include any combination of a processor 602, memory 604, an embodiment of the image sensor 100, a network interface 606, an input / output (I / O) system 608, a user interface 610, and a storage system 612. In some embodiments, one or more components of the image sensor 100 are implemented as part of the processor 602. As shown in FIG. 6 , buses and / or interconnects are also provided to enable communication between the various components listed above and / or other components not shown. The computing platform 600 may be connected to a network 616 via the network interface 606 to enable communication with other computing devices, platforms, or resources. Other components and functionality not reflected in the block diagram of FIG. 6 will be apparent in light of this disclosure, and it should be understood that other embodiments are not limited to a particular hardware configuration.

[0045] Processor 602 may be any suitable processor and may include one or more coprocessors or controllers that assist in control and processing operations associated with computing platform 600. In some embodiments, processor 602 may be implemented as any number of processor cores. A processor (or processor core) may be any type of processor, such as, for example, a microprocessor, an embedded processor, a digital signal processor (DSP), a graphics processor (GPU), a network processor, a field programmable gate array, or other device configured to execute code. A processor may be a multithreaded core that may include two or more hardware thread contexts (i.e., "logical processors") per core. In some examples, processor 602 may include or be part of processor 140, described above.

[0046] Memory 604 may be implemented using any suitable type of digital storage, such as, for example, flash memory and / or random access memory (RAM). In some embodiments, memory 604 may include various layers of memory hierarchy and / or memory caches known to those skilled in the art. Memory 604 may be implemented as a volatile memory device, such as, but not limited to, a RAM, a dynamic RAM (DRAM), or a static RAM (SRAM) device. Storage system 612 may be implemented as a non-volatile storage device, such as, but not limited to, one or more of a hard disk drive (HDD), a solid-state drive (SSD), a universal serial bus (USB) drive, an optical disk drive, a tape drive, an internal storage device, an external storage device, flash memory, a battery-backed synchronous DRAM (SDRAM), and / or a network-accessible storage device. In some embodiments, storage system 612 may include technology to enhance storage performance and protection for valuable digital media when multiple hard drives are included.

[0047] Processor 602 may be configured to execute operating system (OS) 614, which may comprise any suitable operating system, such as Google Android® (Google, Inc., Mountain View, Calif.), Microsoft Windows® (Microsoft Corporation, Redmond, Wash.), Apple OS X (Apple Inc., Cupertino, Calif.), Linux®, or a real-time operating system (RTOS). As will be appreciated in light of this disclosure, the techniques provided herein may be implemented regardless of the particular operating system provided in conjunction with computing platform 600, and thus may be implemented using any suitable existing or later-developed platform.

[0048] The network interface 606 may be any suitable network chip or chipset that enables wired and / or wireless connections between the computing platform 600 and / or other components of the network 616, thereby enabling the computing platform 600 to communicate with other local and / or remote computing systems, servers, cloud-based servers, and / or other resources. The wired communication may conform to existing (or yet to be developed) standards such as, for example, Ethernet. The wireless communication may conform to existing (or yet to be developed) standards such as, for example, Long Term Evolution (LTE), Wireless Fidelity (Wi-Fi), Bluetooth, and / or Near Field Communication (NFC). Exemplary wireless networks include, but are not limited to, wireless local area networks, wireless personal area networks, wireless metropolitan area networks, cellular networks, and satellite networks.

[0049] The I / O system 608 may be configured to interface between various I / O devices and other components of the computing platform 600. The I / O devices may include, but are not limited to, a user interface 610. The user interface 610 may include devices (not shown), such as a display element, a touchpad, a keyboard, a mouse, and speakers. The I / O system 608 may include a graphics subsystem configured to process images for rendering on a display element. The graphics subsystem may be, for example, a graphics processing unit or a visual processing unit (VPU). An analog or digital interface may be used to communicatively connect the graphics subsystem to the display element. For example, the interface may be any of High-Definition Multimedia Interface (HDMI), DisplayPort, Wireless HDMI, and / or any other suitable interface using wireless high-definition enabled technology. In some embodiments, the graphics subsystem may be integrated into the processor 602 or any chipset of the computing platform 600.

[0050] It should be appreciated that in some embodiments, the various components of computing platform 600 may be combined or integrated into a system-on-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0051] In various embodiments, computing platform 600 may be implemented as a wireless system, a wired system, or a combination of both. If implemented as a wireless system, computing platform 600 may include components and interfaces suitable for communication over a wireless shared medium, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, control logic, etc. Examples of wireless shared media may include portions of a wireless spectrum, such as the radio frequency spectrum. If implemented as a wired system, computing platform 600 may include components and interfaces suitable for communication over a wired communication medium, such as input / output adapters, physical connectors connecting the input / output adapters to corresponding wired communication media, network interface cards (NICs), disk controllers, video controllers, audio controllers, etc. Examples of wired communication media may include wires, cable metal leads, printed circuit boards (PCBs), backplanes, switch fabrics, semiconductor materials, twisted pair wires, coaxial cable, fiber optics, etc.

[0052] Unless otherwise specified, terms such as "processing," "computing," "calculating," "determining," and the like may be understood to refer to the operations and / or processing of a computer or computer system or similar electronic computing device that manipulates and / or transforms data represented as physical quantities (e.g., electronic quantities) in the registers and / or memory units of the computer system into other data similarly represented as physical quantities in the registers, memory units, or other such information storage and transmission or display of the computer system. Embodiments are not limited in this context.

[0053] The term "circuit" or "circuitry" as used herein in any embodiment may include, for example, alone or in any combination, hardwired circuitry, programmable circuitry such as a computer processor with one or more individual instruction processing cores, state machine circuitry, and / or firmware that stores instructions executed by the programmable circuitry. The circuitry may include a processor and / or controller configured to execute one or more instructions to perform one or more operations described herein. The instructions may be embodied, for example, as an application, software, firmware, etc. configured to cause the circuitry to perform any of the operations described above. Software may be embodied as a software package, code, instructions, instruction sets, and / or data recorded on a computer-readable storage device. Software may be implemented or performed to include any number of processes, and processes may be implemented or performed to include any number of threads, etc., in a hierarchical manner. Firmware may be embodied as hard-coded (e.g., non-volatile) code, instructions, instruction sets, and / or data in a memory device. The circuits may be implemented as circuits that collectively or individually comprise part of a larger system, such as an integrated circuit (IC), an application specific integrated circuit (ASIC), a system on a chip (SoC), a desktop computer, a laptop computer, a tablet computer, a server, a smartphone, etc. Other embodiments may be implemented as software executed by a programmable control device. As described herein, various embodiments may be implemented using hardware elements, software elements, or any combination thereof. Examples of hardware elements may include a processor, a microprocessor, a circuit, a circuit element (e.g., a transistor, a resistor, a capacitor, an inductor, etc.), an integrated circuit, an application specific integrated circuit (ASIC), a programmable logic device (PLD), a digital signal processor (DSP), a field programmable gate array (FPGA), a logic gate, a register, a semiconductor device, a chip, a microchip, a chipset, etc.

[0054] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices, digital signal processors, FPGAs, GPUs, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The decision of whether an embodiment is implemented using hardware and / or software elements may depend on any number of factors, such as desired computational speed, power levels, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speeds, and other design or performance constraints.

[0055] Additional Examples Example 1 is a column readout amplifier comprising: a signal amplifier having an amplifier output, a first amplifier input, and a second amplifier input, the second amplifier input terminal being connected to a reference voltage terminal; a filter capacitor having first and second terminals, the second terminal being connected to a ground terminal; a buffer amplifier having a buffer amplifier input and a buffer amplifier output; a switching network configured to switchably connect the amplifier output to the buffer amplifier input and the buffer amplifier output to the first terminal of the filter capacitor during a first period, and to switchably connect the amplifier output terminal directly to the first terminal of the filter capacitor during a second period; and a low pass filter connected in a feedback path of the signal amplifier between the amplifier output and the first amplifier input, the low pass filter including a series resistor and a capacitor.

[0056] A second embodiment includes the column readout amplifier of the first embodiment, further comprising a capacitor connected between the amplifier output and the ground terminal.

[0057] Example 3 includes the column readout amplifier of one of Examples 1 and 2, further comprising a feedback capacitor connected in series with the series resistor in the feedback path of the signal amplifier.

[0058] Example 4 includes the column readout amplifier of example 3, wherein the signal amplifier comprises a capacitive transimpedance amplifier configured with a gain greater than one.

[0059] A fifth embodiment includes the column readout amplifier of one of the third and fourth embodiments, wherein the capacitor is connected between the node between the series resistor and the feedback capacitor and the ground terminal.

[0060] Example 6 includes the column readout amplifier of any one of examples 1 to 5, wherein the capacitance of the capacitor is less than the capacitance of the filter capacitor.

[0061] A seventh embodiment includes the column readout amplifier of the sixth embodiment, wherein the capacitance of the filter capacitor is variable.

[0062] Example 8 includes the column readout amplifier of any one of examples 1 to 7, wherein the buffer amplifier output is decoupled from the filter capacitor during the second time period.

[0063] Example 9 includes the column readout amplifier of any one of examples 1 to 8, wherein the buffer amplifier has a gain substantially equal to one.

[0064] Example 10 includes the column readout amplifier of any one of Examples 1 to 9, further comprising an input capacitor connected to the first input of the signal amplifier.

[0065] Example 11 is an image sensor comprising: a bit line conductor; a pixel array having at least one column of addressable pixel sensors, each pixel sensor connected to the bit line conductor in response to a word select signal; and a column amplifier connected to the bit line conductor, the column amplifier comprising: a signal amplifier having an amplifier output, a first amplifier input, and a second amplifier input, the second amplifier input being connected to a reference voltage terminal; a filter capacitor having first and second terminals, the second terminal being connected to a ground terminal; a buffer amplifier having a buffer amplifier input and a buffer amplifier output; a switching network configured to switchably connect the amplifier output to the buffer amplifier input and the buffer amplifier output to the first terminal of the filter capacitor during a first period, and to switchably connect the amplifier output directly to the first terminal of the filter capacitor during a second period; and a low pass filter connected in a feedback path of the signal amplifier between the amplifier output and the first amplifier input, the low pass filter including a series resistor and a capacitor.

[0066] A twelfth embodiment includes the image sensor of the eleventh embodiment, further comprising a capacitor connected between the amplifier output and the ground terminal.

[0067] Example 13 includes the image sensor of one of Examples 11 and 12, further comprising a feedback capacitor connected in series with the series resistor in the feedback path of the signal amplifier.

[0068] Example 14 includes the image sensor of example 13, wherein the signal amplifier comprises a capacitive transimpedance amplifier configured with a gain greater than one.

[0069] A fifteenth embodiment includes the image sensor of one of the thirteenth and fourteenth embodiments, wherein the capacitor is connected between the ground terminal and a node between the series resistor and the feedback capacitor.

[0070] Example 16 includes the image sensor of any one of Examples 11 to 15, wherein the capacitance of the capacitor is less than the capacitance of the filter capacitor.

[0071] A seventeenth embodiment includes the image sensor of the sixteenth embodiment, wherein the capacitance of the filter capacitor is variable.

[0072] Example 18 includes the image sensor of any one of Examples 11 to 17, wherein the buffer amplifier output is decoupled from the filter capacitor during the second time period.

[0073] Example 19 includes the image sensor of any one of Examples 11 to 18, wherein the buffer amplifier has a gain substantially equal to unity.

[0074] Example 20 includes the image sensor of any one of Examples 11 to 19, further comprising an input capacitor connected to the first input of the signal amplifier.

[0075] While several aspects of at least one embodiment have been described, it should be understood that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure and are within the scope of the present invention. Accordingly, the foregoing description and drawings of various embodiments have been presented by way of example only. These examples are not intended to be exhaustive or to limit the invention to the precise form disclosed. The methods and apparatuses may be implemented in other embodiments and may be practiced or carried out in various ways. Moreover, the language and terminology used herein is for purposes of description and not of limitation. Any reference to an example, component, element, or act of a system or method referred to herein in the singular may also include the plural, and any reference to an example, component, element, or act referred to herein in the plural may also include the singular. References in the singular or plural do not limit the currently disclosed systems or methods, their components, acts, or elements. The use herein of "comprises," "has," "contains," "involves," and variations thereof is meant to encompass the subsequently listed items and equivalents thereof, as well as additional items. References to "or / or" may be interpreted as inclusive, such that any term listed with "or / or" may refer to one, more than one, or all of the listed terms. The scope of the invention should be determined from proper interpretation of the appended claims and their equivalents.

Claims

1. a column readout amplifier, a signal amplifier having an amplifier output, a first amplifier input, and a second amplifier input, the second amplifier input being connected to a reference voltage terminal; a filter capacitor having a first terminal and a second terminal, the second terminal being connected to a ground terminal; a buffer amplifier having a buffer amplifier input and a buffer amplifier output; a switching network configured to switchably connect the amplifier output to the buffer amplifier input and the buffer amplifier output to the first terminal of the filter capacitor during a first period of time, and to switchably connect the amplifier output directly to the first terminal of the filter capacitor during a second period of time; a low pass filter connected in a feedback path of the signal amplifier between the amplifier output and the first amplifier input, the low pass filter including a series resistor and a capacitor; a column readout amplifier comprising:

2. The column readout amplifier of claim 1 further comprising a capacitor connected between the amplifier output and the ground terminal.

3. 2. The column readout amplifier of claim 1, further comprising a feedback capacitor connected in series with the series resistor in the feedback path of the signal amplifier.

4. 4. The column readout amplifier of claim 3, wherein the signal amplifier comprises a capacitive transimpedance amplifier configured with a gain greater than unity.

5. 4. The column readout amplifier of claim 3, wherein the capacitor is connected between the node between the series resistor and the feedback capacitor and the ground terminal.

6. The column readout amplifier of claim 1 , wherein the capacitance of the capacitor is less than the capacitance of the filter capacitor.

7. 7. The column readout amplifier of claim 6, wherein the capacitance of the filter capacitor is variable.

8. 2. The column readout amplifier of claim 1, wherein the buffer amplifier output is disconnected from the filter capacitor during the second period of time.

9. 2. The column readout amplifier of claim 1, wherein the buffer amplifier has a gain substantially equal to unity.

10. 2. The column readout amplifier of claim 1, further comprising an input capacitor connected to the first amplifier input of the signal amplifier.

11. a bit line conductor; a pixel array having at least one column of addressable pixel sensors, each pixel sensor connected to said bit line conductor in response to a word select signal; a column amplifier connected to the bit line conductor; Equipped with The column amplifiers a signal amplifier having an amplifier output, a first amplifier input, and a second amplifier input, the second amplifier input being connected to a reference voltage terminal; a filter capacitor having a first terminal and a second terminal, the second terminal being connected to a ground terminal; a buffer amplifier having a buffer amplifier input and a buffer amplifier output; a switching network configured to switchably connect the amplifier output to the buffer amplifier input and the buffer amplifier output to the first terminal of the filter capacitor during a first period of time, and to switchably connect the amplifier output directly to the first terminal of the filter capacitor during a second period of time; a low pass filter connected in a feedback path of the signal amplifier between the amplifier output and the first amplifier input, the low pass filter including a series resistor and a capacitor; An image sensor comprising:

12. The image sensor of claim 11 , further comprising a capacitor connected between the amplifier output and the ground terminal.

13. 12. The image sensor of claim 11, further comprising a feedback capacitor connected in series with the series resistor in the feedback path of the signal amplifier.

14. 14. The image sensor of claim 13, wherein the signal amplifier comprises a capacitive transimpedance amplifier configured with a gain greater than unity.

15. 14. The image sensor of claim 13, wherein the capacitor is connected between the ground terminal and a node between the series resistor and the feedback capacitor.

16. The image sensor of claim 11 , wherein the capacitance of the capacitor is less than the capacitance of the filter capacitor.

17. 17. The image sensor of claim 16, wherein the capacitance of the filter capacitor is variable.

18. The image sensor of claim 11 , wherein the buffer amplifier output is disconnected from the filter capacitor during the second period of time.

19. 12. The image sensor of claim 11, wherein the buffer amplifier has a gain substantially equal to unity.

20. 12. The image sensor of claim 11, further comprising an input capacitor connected to the first amplifier input of the signal amplifier.

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