Semiconductor die bonding techniques in stacked memory architectures

Abstract

Methods, systems, and devices are described for semiconductor die bonding techniques in stacked memory architectures. A semiconductor system may include a semiconductor unit formed of multiple semiconductor dies, each of which may be separately and separably manufactured. Each semiconductor die may include a respective portion of a circuit associated with the semiconductor unit. The multiple semiconductor dies may be coupled to a carrier, and each semiconductor die may be coupled (e.g., electrically and communicatively coupled) to at least one other semiconductor die. At least some of the semiconductor dies may be coupled to a respective set of one or more memory arrays, and each memory array may be operable based on the coupling between the multiple semiconductor dies.

Description

[Technical Field]

[0001] cross reference This patent application claims priority to U.S. patent application Ser. No. 18 / 776,197, filed July 17, 2024, by Bhushan et al., entitled "TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES," and U.S. patent application Ser. No. 63 / 588,642, filed October 6, 2023, by Bhushan et al., entitled "TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES," each of which is assigned to the assignee hereof and each of which is expressly incorporated by reference in its entirety.

[0002] The following relates to one or more systems for memory, which include semiconductor die bonding techniques in a stacked memory architecture. [Background technology]

[0003] Memory devices are widely used in devices such as computers, user devices, wireless communication devices, cameras, and digital displays to store information. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often designated as a logic one or a logic zero. In some embodiments, a single memory cell can support two or more states, any one of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, obtain, determine) a state from the memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to the memory cell.

[0004] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, negative-or (NOR) memory devices, and negative-and (NAND) memory devices. Memory cells may be described in terms of volatile or nonvolatile configurations. Memory cells in nonvolatile configurations may maintain a stored logic state for an extended period of time, even in the absence of an external power source. Memory cells in volatile configurations may lose their stored state when disconnected from an external power source. [Brief explanation of the drawings]

[0005] [Figure 1] 1 illustrates an example system supporting semiconductor die bonding techniques in a stacked memory architecture, according to embodiments disclosed herein. [Figure 2] 1 illustrates an example system supporting semiconductor die bonding techniques in a stacked memory architecture, according to embodiments disclosed herein. [Figure 3] 1 illustrates an example interface architecture that supports semiconductor die bonding techniques in a stacked memory architecture, according to embodiments disclosed herein. [Figure 4A] 1 illustrates an example semiconductor component and die assembly that supports semiconductor die bonding techniques in a stacked memory architecture, according to embodiments disclosed herein. [Figure 4B] 1 illustrates an example semiconductor component and die assembly that supports semiconductor die bonding techniques in a stacked memory architecture, according to embodiments disclosed herein. [Figure 5] 1 illustrates example operations for forming a semiconductor system utilizing semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. [Figure 6] 1 illustrates example operations for forming a semiconductor system utilizing semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. [Figure 7] 1 illustrates example operations for forming a semiconductor system utilizing semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. [Figure 8] 1 illustrates example operations for forming a semiconductor system utilizing semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. [Figure 9] 1 illustrates example operations for forming a semiconductor system utilizing semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. [Figure 10] 1 illustrates example operations for forming a semiconductor system utilizing semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. [Figure 11] 1 illustrates example operations for forming a semiconductor system utilizing semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. [Figure 12] 1 illustrates example operations for forming a semiconductor system utilizing semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. [Figure 13] 1 shows a flowchart illustrating a method for supporting semiconductor die bonding techniques in a stacked memory architecture, according to embodiments disclosed herein. [Figure 14] 1 shows a flowchart illustrating a method for supporting semiconductor die bonding techniques in a stacked memory architecture, according to embodiments disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0006] Some memory systems may include a stack of semiconductor dies, including one or more memory dies (e.g., array dies) or one or more stacks of stacked memory dies stacked together with a logic die operable to access a set of memory arrays distributed across the one or more memory dies. Such stacked architectures may be implemented as part of a high-bandwidth memory (HBM) system or a tightly coupled dynamic random access memory (TCDRAM) system and may support memory-centric logic solutions such as graphics processing units (GPUs), among other implementations. In some examples, an HBM system may include a stack of memory dies located (e.g., positioned, arranged) above a logic die. In some examples, a TCDRAM system may be tightly coupled (e.g., physically coupled, electrically coupled, directly coupled) to a processor, such as a GPU or other host, as part of a physical memory map accessible to the processor. Such coupling may include one or more processors implemented on the same semiconductor die (e.g., as part of a logic die) as at least a portion of the HBM system or TCDRAM system, or on a die directly coupled (e.g., fused) with another die including at least a portion of the HBM system or TCDRAM system, or on a die coupled otherwise (e.g., via a silicon interposer or other intermediary component) with another die including at least a portion of the HBM system or TCDRAM system. Unlike cache-based memory, the TCDRAM system may not be backed by an external memory level with the same physical address. For example, the TCDRAM system may be associated with and located within a dedicated base address, and portions of the TCDRAM system do not overlap within the dedicated base address.

[0007] Some semiconductor dies (e.g., logic dies) may include multiple components, such as interface blocks (e.g., memory interface blocks, interface circuits), logic blocks, controllers, processors, and other components. In some embodiments, such dies may have a relatively low manufacturing yield, which may be related to the relative size or complexity of integrating multiple components on the same die. For example, if at least one of the die's components fails an evaluation procedure, the die may be rejected (e.g., discarded) during the manufacturing process. That is, even if most of the die's components are able to meet evaluation, the failure of just one component may cause the die to be rejected. Thus, the likelihood that each component of a relatively complex or relatively large die will meet evaluation may be relatively low, and thus, the yield of such a die may be relatively low.

[0008] According to embodiments disclosed herein, a semiconductor component (e.g., a semiconductor unit, a semiconductor subsystem, a logic unit, a logic portion of an HBM system, a logic portion of a TCDRAM system, a heterogeneous semiconductor device) may be formed with multiple semiconductor die portions (e.g., smaller dies, each including a respective subset of the components of the logic unit) bonded to a carrier and interconnected with one another. At least some, if not all, of the die portions may be individually qualified (e.g., known good die (KGD) before interconnection). In some embodiments, the die portions may be referred to as “chiplets” (e.g., logic chiplets), and each chiplet may include a respective portion of circuitry that may be differently associated with the functionality of the larger die. For example, such a semiconductor component may be formed with a first chiplet including memory interface circuitry, a second chiplet including processor circuitry, and a third chiplet including logic circuitry, among other circuit subdivisions. The multiple chiplets may be interconnected with conductive paths (e.g., through the backside of at least some of the chiplets in a redistribution layer (RDL)) and one or more through silicon vias (TSVs) in each of the chiplets, which may involve various semiconductor fabrication techniques for bonding chiplets. At least some of the chiplets may be further coupled with one or more memory dies (e.g., stacked memory dies). In some implementations, one or more stacked memory dies may have dedicated conductive paths for power supply signals or other signals (e.g., for a power distribution network (PDN) using through reconfiguration vias (TRVs)) that bypass the chiplet (e.g., bypass one or more dies in the logic layer).

[0009] By supporting the subdivision and joining of multiple chiplets (e.g., multiple chiplets comprising a multi-die semiconductor unit), relatively small wafer portions may be rejected (e.g., based on rejection of chiplets that fail evaluation), which may support increased wafer yield. Accordingly, the manufacturing yield of multi-die semiconductor units (e.g., logic units) may be improved compared to the yield of single-die semiconductor units (e.g., based on increased yield due to interconnection of relatively small KGD chiplets). Furthermore, dedicated conductive paths (e.g., conductive paths dedicated to powering one or more memory dies) may have lower resistance and may not occupy area within the substrate of other dies (e.g., other dies in a single-die logic system), which may support increased semiconductor circuit area, increased wafer circuit yield, and improved memory system performance.

[0010] In addition to the applicability of the systems described herein, semiconductor die bonding techniques in stacked memory architectures may generally be implemented to support artificial intelligence or machine learning applications, among other types of computationally intensive applications. The increasing use of artificial intelligence to support machine learning, analytics, decision-making, or other related applications may create a demand for electronic devices that support artificial intelligence applications and processes. For example, artificial intelligence applications may involve accessing relatively large amounts of data for analytical purposes and may benefit from memory systems that can effectively and efficiently store relatively large amounts of data or that can access the stored data relatively quickly. Implementing the techniques described herein may support artificial intelligence and machine learning techniques by supporting improved device yield and interconnectivity, including supporting artificial intelligence and machine learning techniques by forming semiconductor units (e.g., logic die in an HBM system, logic die in a TCDRAM system) from relatively small semiconductor die portions (e.g., rather than as a single monolithic unit). Such techniques may enable the rejection of relatively small components and the acceptance of remaining relatively small components, thereby improving the manufacturing yield of devices supporting artificial intelligence and machine learning techniques. Furthermore, yields of such devices may be improved based on dedicated vias for power delivery to the memory array (e.g., instead of power delivery through circuitry on other dies), which may support increased circuit density on the wafer. Furthermore, the techniques herein may improve the power efficiency of memory arrays (e.g., memory arrays in tightly coupled stacks of array dies) and support increased performance and reduced latency in stacked memory architectures.

[0011] Features of the present disclosure are illustrated and described with reference to systems and dies, and are further illustrated and described with reference to interface architectures, semiconductor components, die assemblies, exemplary manufacturing techniques, and flow charts.

[0012] 1 illustrates an example system 100 supporting semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. System 100 may comprise part of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, or other system. System 100 includes a host system 105, a memory system 110, and one or more channels 115 that couple host system 105 with memory system 110 (e.g., to provide a communicative coupling). While system 100 may include one or more memory systems 110, aspects of the one or more memory systems 110 may be described in terms of a single memory system 110.

[0013] Host system 105 may be an example of a processing system (e.g., a circuit, one or more processors, an application processing system, a processing circuit, one or more processing components) that uses memory to execute a process (e.g., an application, a function, a calculation), such as a processing system in a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a wearable device, an internet-connected device, a vehicle controller, a system-on-a-chip (SoC), or other fixed or portable electronic device, among other examples. Host system 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., peripheral components, input / output controllers, not shown). The components of host system 105 may be coupled to each other using a bus 135.

[0014] External memory controller 120 may be configured to enable communication of information (e.g., data, commands, control information, configuration information) between components of system 100 (e.g., between components of host system 105 and memory system 110, such as processor 125). For example, external memory controller 120 may generate commands to write data to or read data from memory system 110, or otherwise communicate with memory system 110 (e.g., in response to or otherwise supporting an application of host system 105). External memory controller 120 may process (e.g., translate, convert) communications exchanged between host system 105 and memory system 110. In some embodiments, external memory controller 120, or other components of system 100, or related functionality described herein, may be performed by or part of processor 125. For example, external memory controller 120 may be hardware, firmware, or software (e.g., instructions), or some combination thereof, implemented by processor 125 or other components of system 100 or host system 105. Although external memory controller 120 is shown external to memory system 110, in some embodiments, external memory controller 120 or its functionality described herein may be implemented by one or more components of memory system 110 (e.g., memory system controller 155, local memory controller 165), or vice versa. In various embodiments, host system 105 or external memory controller 120 may be referred to as a host.

[0015] Processor 125 may be operable to provide functionality (e.g., control functions, processing functions) for system 100 or host system 105. Processor 125 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof (e.g., any combination as one or more processing components individually or collectively configured to support an application of host system 105). In some embodiments, processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or an SoC, among other examples.

[0016] In some embodiments, system 100 or host system 105 may include input components, output components, or a combination thereof. Input components may include, among other examples, a sensor, a microphone, a keyboard, another processor (e.g., another processor on a printed circuit board), an interface (e.g., a user interface, an interface between other devices), or a peripheral device that interfaces with system 100 through one or more peripheral components. Output components may include, among other examples, a display, an audio speaker, a printing device, another processor on a printed circuit board, or a peripheral device that interfaces with system 100 through one or more peripheral components.

[0017] Memory system 110 may be a component of system 100 operable to provide physical memory locations (e.g., addresses) that system 100 (e.g., host system 105) may use or reference. Memory system 110 may include a memory system controller 155 and one or more memory dies 160 (e.g., memory chips) to support data storage capacity. Memory system 110 may be configurable to operate with one or more different types of host systems 105 and may execute in response to commands provided by host system 105 (e.g., via external memory controller 120). For example, memory system 110 (e.g., memory system controller 155) may receive a write command indicating that memory system 110 should store data received from host system 105, a read command indicating that memory system 110 should provide data stored on memory die 160 to host system 105, or a refresh command indicating that memory system 110 should refresh data stored on memory die 160, among other types of commands and operations.

[0018] Memory system controller 155 may include components (e.g., circuits, logic, instructions) operable to control the operation of memory system 110. Memory system controller 155 may include hardware, firmware, or instructions that enable memory system 110 to perform various operations and may be operable to receive, send, or execute commands, data, or control information related to the operation of memory system 110. Memory system controller 155 may be operable to communicate with one or more of external memory controller 120, one or more memory dies 160, or processor 125. In some embodiments, memory system controller 155 may cooperate with local memory controller 165 of memory die 160 to control the operation of memory system 110.

[0019] Each memory die 160 may include one or more local memory controllers 165 and one or more memory arrays 170. A memory array 170 may be a collection of memory cells, each operable to store one or more bits of data. A memory array 170 may include a two-dimensional (2D) array of memory cells or a three-dimensional (3D) array of memory cells. In some embodiments, a two-dimensional (2D) memory die 160 may include a single memory array 170. In some embodiments, a three-dimensional (3D) memory die 160 may include two or more memory arrays 170, which may be stacked on top of each other or positioned side-by-side (e.g., relative to a substrate).

[0020] Local memory controller 165 may include components (e.g., circuitry, logic, instructions) operable to control operation of memory die 160. In some embodiments, local memory controller 165 may be operable to communicate with memory system controller 155 (e.g., receive or send data or commands, or both). In some embodiments, memory system 110 may not include memory system controller 155, and local memory controller 165 or external memory controller 120 may perform various functions described herein. Thus, local memory controller 165 may be operable to communicate with memory system controller 155, or with other local memory controllers 165, or directly with external memory controller 120, or processor 125, or any combination thereof. Examples of components that may be included in the memory system controller 155, or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating transmitted signals, a detection component for detecting states of memory cells in the memory array 170, a write component for writing states to memory cells in the memory array 170, or various other components operable to support the operation of the described memory system 110.

[0021] Host system 105 (e.g., external memory controller 120) and memory system 110 (e.g., memory system controller 155) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission medium, electrical conductors, conductive paths) between terminals associated with components of system 100. For example, channel 115 may be associated with a first terminal in host system 105 (e.g., a terminal including one or more pins, a terminal including one or more pads) and a second terminal in memory system 110. The terminals may be examples of conductive input or output points of devices in system 100, and the terminals may be operable to function as part of channel 115. In some implementations, at least channel 115 between host system 105 and memory system 110 may include or be referred to as a host interface (e.g., a physical host interface). In some implementations, the host interface may include or be associated with interface circuitry (e.g., signal drivers, signal latches) in host system 105 (e.g., external memory controller 120), in memory system 110 (e.g., memory system controller 155), or both.

[0022] In some embodiments, channel 115 (e.g., associated signal paths and terminals) may be specialized for communicating one or more types of information. For example, channel 115 may include one or more command and address channels, one or more clock signal channels, one or more data channels, or combinations thereof, among other channels. In some embodiments, signaling may be communicated over channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered per clock cycle (e.g., on the rising edge or falling edge of the clock signal). In DDR signaling, two modulation symbols of a signal may be registered per clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0023] In some embodiments, at least a portion of system 100 may implement a stacked die architecture in which multiple semiconductor dies are physically and communicatively coupled. In some such implementations, circuitry for accessing one or more memory arrays 170 (e.g., circuitry of memory system 110) may be distributed across multiple semiconductor dies in a stack (e.g., a stack of multiple directly coupled semiconductor dies). For example, a first die may include a set of multiple first interface blocks (e.g., memory interface blocks, instances of a first interface circuit), and one or more second dies may include corresponding second interface blocks, each coupled to a first interface block of the first die, and each first interface block configured to access one or more memory arrays of the second die. In some embodiments, the system may include a controller (e.g., a memory controller, an interface controller, a host interface controller, at least a portion of external memory controller 120) for each set of one or more first interface blocks to support access operations (e.g., operations to access one or more memory arrays 170) via the set of first interface blocks. In some embodiments, such a controller may be located on the same first die as the first interface block.

[0024] In some embodiments, multiple semiconductor dies of memory system 110 or system 100 (e.g., an HBM system including aspects of memory system 110, a TCDRAM system including aspects of memory system 110 and host system 105) include one or more array dies (e.g., memory die 160) stacked with a logic die (e.g., a logic die including aspects of host system 105, a logic die coupled with another die or other component that includes host system 105), where the logic die includes an interface block operable to access a set of memory arrays 170 distributed across one or more second dies. System 100 or portions of system 100 having a stacked memory architecture may support semiconductor die bonding techniques in stacked memory architectures. For example, a semiconductor unit (e.g., a semiconductor component, a logic unit) may be formed of multiple semiconductor die portions (e.g., chiplets, logic chiplets), which are interconnected after an evaluation procedure (e.g., as interconnections of logic chiplets that meet an evaluation such as KGD). At least some of the chiplets may be further coupled with one or more stacked memory arrays 170, which may also have dedicated power supply vias (e.g., PDN through vias (TVs), TRVs). Thus, the manufacturing yield of memory system 110 or system 100 (e.g., HBM system, TCDRAM system) may be improved based on forming a semiconductor unit with multiple semiconductor chiplets and dedicated vias, and improved power efficiency may be provided to memory system 110 based on supplying power to one or more stacked memory arrays 170 through one or more dedicated vias.

[0025] 2 illustrates an example system 200 (e.g., a semiconductor system, a system of bonded semiconductor dies, an HBM system, a TCDRAM system) supporting semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. System 200 illustrates an example die 205 (e.g., die 205-a, a semiconductor die, a logic die, a processor die, a host die, a logic unit) bonded with one or more die 240 (e.g., dies 240-a-1 and 240-a-2, a semiconductor die, a memory die, an array die, a memory unit). Die 205 or die 240 may be formed using a respective semiconductor substrate (e.g., a substrate of a crystalline semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or gallium nitride), a silicon-on-insulator (SOI) substrate (e.g., a silicon-on-glass (SOG) substrate, a silicon-on-sapphire (SOS) substrate), or an epitaxial semiconductor material formed on another substrate, among other examples. While the depicted example of system 200 includes two dies 240, system 200 in accordance with the techniques of the present description may include any number of one or more dies 240 combined with die 205, among other dies, in a stacked or other combined layout. Moreover, while the non-limiting example of system 200 herein is generally described in terms of its applicability to a memory system, memory subsystem, memory device, or combinations thereof, the example of system 200 is not so limited. For example, aspects of the present disclosure may likewise apply to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem used in applications such as data collection, data processing, data storage, networking, communications, power, artificial intelligence, system-on-chip, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0026] System 200 illustrates an example of interface circuitry between a host and memory (e.g., circuitry via a host interface, circuitry via a physical host interface), where the interface circuitry is implemented on (e.g., divided among) multiple semiconductor dies (e.g., a stack of directly coupled dies). For example, die 205-a may include a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2, memory interface blocks), and each die 240 may include a set of one or more interface blocks 245 (e.g., access interface blocks) and one or more memory arrays 250 (e.g., die 240-a-1 includes interface block 245-a-1 coupled to a set of one or more memory arrays 250-a-1, and die 240-a-2 includes interface block 245-a-2 coupled to a set of one or more memory arrays 250-a-2). Memory array 250 may be an example of memory array 170, which may include memory cells of various architectures, such as RAM, DRAM, SDRAM, SRAM, FeRAM, MRAM, RRAM, PCM, chalcogenide, NOR, or NAND memory cells, or any combination thereof.

[0027] Although example system 200 is shown including one interface block 245 on each die 240, die 240 in accordance with the techniques of this description may include any number of one or more interface blocks 245, with each interface block 245 coupled to a respective set of one or more memory arrays 250 and coupled to an interface block 220 of die 205. Thus, interface circuitry of system 200 may include one or more interface blocks 220 of die 205, with each interface block 220 coupled to (e.g., communicating with) one or more interface blocks 245 of die 240 (e.g., external to die 205). In some embodiments, the coupled combination of interface block 220 and interface block 245 (e.g., coupled via a bus associated with one or more channels, such as one or more data channels, one or more control channels, one or more clock channels, one or more pseudo channels, or a combination thereof) may comprise or be referred to as a data path associated with a respective set of one or more memory arrays 250.

[0028] In some implementations (e.g., TCDRAM implementations), die 205 may include host processor 210. Host processor 210 may be an example of host system 105, or a portion thereof (e.g., processor 125, aspects of external memory controller 120, or both). Host processor 210 may be configured to perform operations that implement storage in memory array 250 (e.g., to support applications or other functions of host system 105 that may require access of memory array 250). For example, host processor 210 may receive data read from memory array 250, send data to be written to memory array 250, or do both (e.g., in accordance with an application or other operation of host processor 210). Additionally or alternatively, host processor 210 may reside external to die 205 (e.g., in an HBM implementation), e.g., host processor 210 may reside on another semiconductor die or other component that is coupled (e.g., communicatively coupled, directly coupled, bonded, coupled via another intervening component) to die 205 via one or more contacts 212 (e.g., externally accessible terminals of die 205).

[0029] Host processor 210 may be configured to communicate (e.g., send, receive) signaling with interface block 220 via host interface 216 (e.g., physical host interface), which may implement aspects of channel 115 described with reference to FIG. 1 . In some embodiments, host interface 216 may provide a communicative coupling between a physical or functional boundary between host system 105 and memory system 110. For example, host processor 210 may be configured to communicate access signaling (e.g., control signaling, access command signaling, data signaling, configuration signaling) via host interface 216 to support access operations (e.g., read operations, write operations) to memory array 250, among other operations. While example system 200 includes a single host interface 216, a system consistent with the techniques of the present description may include any number of one or more host interfaces 216 for accessing memory array 250 of the system.

[0030] In some embodiments, each host interface 216 may be coupled between a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2) and a respective controller 215. Controller 215 may be an example of control circuitry (e.g., memory controller circuitry, host interface control circuitry) associated with host system 105 and may be associated with implementing a respective instance of one or more aspects of external memory controller 120, one or more aspects of memory system controller 155, or a combination thereof. For example, controller 215 may be operable to respond to instructions (e.g., requests, commands) from host processor 210 to access one or more memory arrays 250 in support of functions or applications of host processor 210, send associated commands (e.g., to one or more interface blocks 220) to access one or more memory arrays 250, and communicate data (e.g., write data, read data) with host processor 210, among other functions.

[0031] In some embodiments, one or more controllers 215 may be implemented on die 205 (e.g., the same die that includes one or more interface blocks 220), regardless of whether host processor 210 is included on die 205 or is external to die 205. In some other embodiments, controller 215 or related circuitry or functionality may be implemented external to die 205 (e.g., on a separate die, not shown, for each host interface 216, coupled to a respective interface block 220 via a respective terminal), which may be the same die as the die that includes host processor 210 or a different die than the die that includes host processor 210. Interface block 220 may be operable through a single controller 215 or by one or more of a set of multiple controllers 215 (e.g., according to a controller multiplexing scheme). In some other embodiments, aspects of one or more controllers 215 may be included in host processor 210 (e.g., as a memory interface for host processor 210, as a memory interface for host system 105).

[0032] In some embodiments, the controller 215 may be directly coupled to one or more interface blocks 220 (not shown), while in some other embodiments, the controller 215 (e.g., the host interface 216) may be coupled to a set of multiple interface blocks 220 via logic blocks 225 (e.g., logic circuits for a channel set, logic circuits for the host interface 216, multiplexing circuitry). For example, the logic block 225 may be coupled to the interface block 220-a-1 via bus 223-a-1 and to the interface block 220-a-2 via bus 223-a-2. The controller 215 and one or more corresponding interface blocks 220 may communicate (e.g., cooperate) using the host interface 216 and via the logic blocks 225 to perform one or more operations (e.g., scheduling operations, access operations, operations initiated by the host processor 210) involving accessing a corresponding set of one or more memory arrays 250.

[0033] In some embodiments, logic block 225, controller 215, or host interface 216, or combinations thereof, may be associated with a “channel set” corresponding to multiple memory arrays 250 (e.g., for parallel or otherwise coordinated access of multiple memory arrays 250). For example, such a channel set may be associated with multiple memory arrays 250 accessed via a single interface block 245, or multiple memory arrays 250 each accessed via a respective interface block 245, or multiple memory arrays 250 each accessed via a respective interface block 220, any of which may be associated with signaling via a single logic block 225, a single host interface 216, or a single controller 215. These and other configurations for implementing one or more channel sets in a system may support various techniques for parallel processing and high-bandwidth data transfer, memory management operations, repair and replacement techniques, or power and heat distribution (e.g., due to the high-bandwidth memory configuration of system 200, due to the tightly coupled configuration of system 200), among other techniques that leverage the described coupling of components and interfaces between multiple semiconductor dies. In some embodiments, such techniques may be implemented (eg, in or using logic block 225) in a manner that is transparent to host interface 216 or other aspects of host system 105.

[0034] In some embodiments, host interface 216 may include a respective set of one or more signal paths for each logic block 225 or interface block 220, such that host processor 210 may communicate with each logic block 225 or each interface block 220 via its corresponding set of signal paths (e.g., according to host processor 210 selecting the corresponding set to perform an access operation via the selected logic block 225 or interface block 220). Additionally or alternatively, host interface 216 may include one or more signal paths shared among multiple logic blocks 225 (not shown) or multiple interface blocks 220, and logic block 225, interface block 220, or host processor 210, or any of them, may interpret, ignore, respond to, or suppress response to signaling via the shared signal paths of host interface 216 based on logical instructions (e.g., based on address instructions, interface enable signals, or interface select signals associated with logic block 225 or interface block 220, which may be provided by host processor 210, the corresponding logic block 225, or the corresponding interface block 220 depending on the direction of the signaling).

[0035] In some embodiments, host processor 210 may determine to access an address (e.g., a logical address of memory array 250, a physical address of memory array 250, an address of logic block 225, an address of interface block 220, or an address of host interface 216 in response to an application of host processor 210 or an application supported by host processor 210) and determine which controller 215 to send access signaling to access the address (e.g., the controller 215, logic block 225, or interface block 220 corresponding to the address). In some embodiments, the address may be associated with a row of memory cells of memory array 250, a column of memory cells of memory array 250, or both. Host processor 210 may send access signaling (e.g., one or more access signals, one or more access commands) to the determined controller 215, which may then send the access signaling to the corresponding logic block 225 or interface block 220. The corresponding interface block 220 may then send access signaling to the coupled interface block 245 to access the determined address (eg, the address of the corresponding memory array 250).

[0036] Die 205 may also include logic blocks 230 (e.g., shared logic blocks, central logic blocks, common logic circuits, evaluation circuits, memory system configuration circuits, memory system management circuits), which may be configured to communicate (e.g., send, receive) signaling with logic blocks 225, interface blocks 220, or both of die 205. In some cases, logic blocks 230 may be configured to communicate information (e.g., commands, instructions, data) with one or more logic blocks 225 or interface blocks 220 to facilitate operation of system 200. For example, logic blocks 230 may be configured to send configuration signaling (e.g., initialization signaling, evaluation signaling, mapping signaling), which may be received by logic blocks 225 or interface blocks 220 to support configuration of logic blocks 225 or interface blocks 220 or other aspects of operating die 240 (e.g., via respective interface blocks 245). Logic block 230 may be coupled to each logic block 225 and each interface block 220 via a respective bus. In some embodiments, each such bus may include a respective set of one or more signal paths, such that logic block 230 may communicate with each logic block 225 or each interface block 220 via a respective set of signal paths. Additionally or alternatively, such a bus may include one or more signal paths shared among multiple logic blocks 225 or interface blocks 220 (not shown).

[0037] In some implementations, logic block 230 may be configured to communicate (e.g., send, receive) signaling with host processor 210 (e.g., via a bus, via contacts 212 of host processor 210 external to die 205), and thus logic block 230 may support an interface between host processor 210 and logic block 225 or interface block 220. For example, host processor 210 may be configured to send initialization signaling (e.g., boot commands) or other configuration or operation signaling, which may be received by logic block 230 to support initialization, configuration, evaluation, or other operation of logic block 225 or interface block 220. Additionally or alternatively, in some implementations, logic block 230 may be configured to communicate (e.g., send, receive) signaling with components external to system 200 (e.g., via contacts 234, which may be externally accessible terminals of die 205), thereby allowing logic block 230 to support an interface that bypasses host processor 210. Additionally or alternatively, logic block 230 may communicate with host processor 210 and may communicate with one or more memory arrays 250 of one or more dies 240 (e.g., to perform self-test operations to access memory arrays 250). In some examples, such implementations may support evaluation, configuration, or other operation of system 200 during manufacturing, assembly, verification, or other operation related to system 200 (e.g., prior to coupling with host processor 210, without host processor 210 installed, and for operation independent of the host processor) via one or more contacts 234 accessible at the system's physical interface. Additionally or alternatively, logic block 230 may implement one or more aspects of controller 215. For example, logic block 230 may include one or more controllers 215, or may operate as one or more controllers 215, and may perform operations attributed to controller 215.

[0038] Each interface block 220 may be coupled to at least a respective bus 221 of die 205 and a respective bus 246 of die 240, which are configured to communicate signaling with corresponding interface blocks 245 (e.g., via one or more associated signal paths). For example, interface block 220-a-1 may be coupled to interface block 245-a-1 via bus 221-a-1 and bus 246-a-1, and interface block 220-a-2 may be coupled to interface block 245-a-2 via bus 221-a-2 and bus 246-a-2. In some embodiments, die 240 may include a bus, such as bus 255, that bypasses the operational circuitry of die 240 (e.g., bypasses interface block 245 of a given die 240). For example, interface block 220-a-2 may be coupled to interface block 245-a-2 of die 240-a-2 via bus 255-a-1 of die 240-a-1, which may bypass interface block 245 of die 240-a-1. Such techniques may be extended for interconnections between more than two dies 240 (e.g., for interconnections of multiple dies 240 via their respective buses 255).

[0039] The signal paths of each of buses 221, 246, and 255 may be coupled to one another from one die to another via various arrangements of contacts (e.g., exposed contacts, metal surfaces of the respective dies) on the surfaces of the interfacing dies. For example, bus 221-a-1 may be coupled to bus 246-a-1 via contact 222-a-1 (e.g., on its surface) of die 205-a and contact 247-a-1 of die 240-a-1, bus 221-a-2 may be coupled to bus 255-a-1 via contact 222-a-2 of die 205-a and contact 256-a-1 of die 240-a-1, bus 255-a-1 may be coupled to bus 246-a-2 via contact 257-a-1 of die 240-a-1 and contact 247-a-2 of die 240-a-2, and so on. While each bus is shown as a single line coupled through a single contact, it should be understood that each signal path of a given bus may be associated with a respective contact and support a separate communication coupling through each signal path of a given bus. In some embodiments, bus 255 may traverse a portion of die 240 (e.g., in a plane direction, along a direction other than the thickness direction, in a waterfall arrangement, in a staircase arrangement), which may support, among other contacts, an arrangement in which contacts 222 along the surface of die 205 are coupled to interface blocks 245 of different die 240 along the stacking direction (e.g., coupled via respective contacts 256 and 257 that do not overlap when viewed along the thickness direction).

[0040] The interconnection of the interface contacts may be supported by various techniques. For example, in hybrid bonding implementations, the interface contacts may be coupled by fusing the conductive (e.g., electrically conductive) materials of the interface contacts (e.g., without solder or other intervening material between the contacts). For example, in an assembled situation, coupling of die 205-a to die 240-a-1 may include fusing the conductive material of contact 222-a-2 with the conductive material of contact 256-a-1, coupling of die 240-a-1 to die 240-a-2 may include fusing the conductive material of contact 257-a-1 with the conductive material of contact 247-a-2, and so on. In some embodiments, such coupling may include inoperable coupling (e.g., non-communicative coupling, physical coupling) of the contacts, such as fusing contacts that are not coupled to the operational circuitry of either die 240-a-1 or 240-a-2, such as fusing contact 260-a-1 with contact 256-a-2. In some embodiments, such techniques may be implemented to improve coupling strength or uniformity (e.g., contacts 260 are implemented that may not be in operable coupling with interface block 245 or interface block 220), or such coupling may be a by-product of component repetition, which may be operable or inoperable in various configurations (e.g., in die 240 having a common arrangement of contacts 256 and 257, contacts 256-a-1 and 257-a-1 provide a communication path between interface block 245-a-2 and interface block 220-a-2, but contacts 256-a-2 and 257-a-2 do not provide a communication path between interface block 245 and interface block 220).

[0041] In some embodiments, fusing of conductive material between dies (e.g., between contacts) may involve fusing of other materials on one or more surfaces of the interfacing die. For example, in an assembly situation, bonding of die 205 and die 240-a-1 may include fusing dielectric material 207 (e.g., a non-conductive material) of die 205-a with dielectric material 242 of die 240-a-1, and bonding of die 240-a-1 and die 240-a-2 may include fusing dielectric material 242 of die 240-a-1 with dielectric material 242 of die 240-a-2. In some embodiments, such dielectric material may include an oxide, nitride, carbide, oxynitride, oxycarbide, or other transformation or doping of the substrate material (e.g., semiconductor substrate material) of die 205 or die 240, among other materials that may support such fusing. However, the bond between die 205 and die 240 may be implemented according to other techniques that may implement solder, adhesives, thermally conductive materials, and other intervening materials.

[0042] In some embodiments, the dies 240 may be bonded in a stack (e.g., forming a "cube" or other structure of dies 240), and then one or more of such stacks may be bonded to a die 205 (e.g., in a stack-to-chip bonding structure). In some embodiments, a respective set(s) of one or more dies 240 may be bonded to each die 205 of a plurality of dies 205 formed on a wafer (e.g., a chip-to-wafer bonding structure, a stack-to-wafer bonding structure, before sawing the wafer of dies 205), and the dies 205 of the wafer to which each set(s) of dies 240 is respectively bonded may be separated from one another (e.g., by sawing at least the wafer of dies 205). In some other embodiments, a respective set(s) of one or more dies 240 may be bonded to each respective die 205 after the dies 205 are separated from the wafer of dies 205 (e.g., in a chip-to-chip bonding structure). In some other embodiments, each set of one or more wafers, each including a plurality of dies 240, may be bonded in a stack (e.g., in a wafer-to-wafer bonding configuration). In various embodiments, after such a technique, the stack of dies 240 may be separated from the bonded wafers, or the stack of wafers with dies 240 may be bonded to another wafer including a plurality of dies 205 (e.g., in a second wafer-to-wafer bonding configuration), followed by separation of system 200 from the bonded wafers. In some other embodiments, a wafer-to-wafer bonding technique may be implemented by stacking one or more wafers of dies 240 (e.g., sequentially) onto a wafer of dies 205 prior to separation into system 200, among other examples, to form system 200.

[0043] Buses 221, 246, and 255 may be implemented to provide configuration signaling (e.g., regulation signaling, logic signaling, modulation signaling, digital signaling) between interface block 220 and corresponding interface block 245, which may include various modulation or encoding techniques by the transmitting interface block (e.g., via a driver component of the transmitting interface block). In some embodiments, such signaling may be supported by (e.g., may involve) clock signaling communicated over the respective bus (e.g., in conjunction with signal transmission). For example, the buses may be configured to carry one or more clock signals transmitted by interface block 220 for reception by interface block 245 (e.g., to support clock operation of interface block 245, to trigger signal reception by latches or other receiving components of interface block 245). Additionally or alternatively, the bus may be configured to carry one or more clock signals transmitted by the interface block 245 for reception by the interface block 220 (e.g., to support clocking of the interface block 220, to trigger signal reception by latches or other receiving components of the interface block 220). Such clock signals may be associated with communication (e.g., unidirectional, bidirectional, deterministic) of various signaling, such as control signaling, command signaling, data signaling, or any combination thereof. For example, the bus may include one or more signal paths for data bus communication (e.g., one or more data channels, DQ buses via a data interface of the interface block) according to one or more corresponding clock signals (e.g., data clock signals), or one or more signal paths for control bus communication (e.g., a command / address (C / A) bus via a command interface of the interface block) according to one or more clock signals (e.g., control clock signals), or any combination thereof.

[0044] Interface block 220, interface block 245, logic block 225, and logic block 230 may each include circuitry (signal circuitry, multiplexing circuitry, processing circuitry, controller circuitry, logic circuitry, physical components, hardware) in various configurations (e.g., hardware configurations, logic configurations, software configurations, or instruction configurations) that support the functions assigned to the respective block for accessing or otherwise manipulating the corresponding set of memory array 250. For example, interface block 220 may include circuitry configured to perform a first subset of operations that support accessing memory array 250, and interface block 245 may include circuitry configured to perform a second subset of operations that support accessing memory array 250. In some embodiments, interface block 220, interface block 245, and logic block 225 may support functional partitioning or distribution of functionality associated with memory system controller 155, local memory controller 165, or both, across multiple dies (e.g., die 205 and at least one die 240). In some implementations, logic block 230 may be configured to coordinate or configure aspects of the operation of interface block 220, interface block 245, logic block 225, or combinations thereof, and may support the implementation of one or more aspects of memory system controller 155. Such operations or a subset of operations may include operations performed in response to commands from host processor 210 or controller 215, or operations performed without commands from host processor 210 or controller 215 (e.g., operations determined or initiated by logic block 225, operations determined or initiated by interface block 220, operations determined or initiated by interface block 245, operations determined or initiated by logic block 230), or various combinations thereof.

[0045] In some implementations, system 200 may include one or more instances of non-volatile storage (e.g., non-volatile storage 235 of die 205, non-volatile storage 270 of one or more dies 240, or a combination thereof). In some examples, logic block 230, logic block 225, interface block 220, interface block 245, or a combination thereof may be configured to communicate signaling with one or more instances of non-volatile storage. For example, logic block 230, logic block 225, interface block 220, or interface block 245 may be coupled to one or more instances of non-volatile storage via one or more buses (not shown) or respective contacts (not shown), and, if applicable, these buses and contacts may each include one or more signal paths operable to communicate signaling (e.g., command signaling, data signaling). In some embodiments, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof, may configure one or more operations based on information (e.g., instructions, configurations, parameters) stored in one or more instances of non-volatile storage. Additionally or alternatively, in some embodiments, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may write information (e.g., configuration information, evaluation information) to store in one or more instances of non-volatile storage. In some embodiments, such non-volatile storage may include fuses, antifuses, or other types of one-time programmable storage elements, or any combination thereof.

[0046] In some implementations, system 200 may include one or more sensors (e.g., one or more sensors 237 on die 205, one or more sensors 275 on one or more dies 240, or a combination thereof). In some implementations, logic block 230, logic block 225, interface block 220, interface block 245, or a combination thereof may be configured to receive one or more instructions based on measurements of one or more sensors of system 200. For example, logic block 230, logic block 225, interface block 220, or interface block 245 may be coupled to one or more sensors via one or more buses (not shown) or respective contacts (not shown). Such sensors may include temperature sensors, current sensors, voltage sensors, counters, and other types of sensors. In some implementations, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may configure one or more actions based on the output of the one or more sensors. For example, logic block 230 may configure one or more operations of logic block 225 or interface block 220 based on signaling (e.g., instructions, data) received from one or more sensors. Additionally or alternatively, logic block 225 or interface block 220 may generate access signaling for transmission to a corresponding interface block 245 based on the one or more sensors.

[0047] In some embodiments, the circuitry of logic block 225, interface block 220, interface block 245, or logic block 230, or any combination thereof, may include components (e.g., transistors) formed at least in part from doped portions of the substrate of the respective die. In some embodiments, the substrate of die 205 may have different characteristics (e.g., material, material properties, physical shape, or dimensions) than the substrate of die 240. Additionally or alternatively, in some embodiments, transistors formed from the substrate of die 205 may have different characteristics (e.g., manufacturing characteristics, performance characteristics, physical shape, or dimensions) than transistors formed from the substrate of die 240 (e.g., according to a different transistor architecture, according to a different transistor design).

[0048] In some embodiments, interface block 220 may support a layout of one or more components within interface block 220. For example, the layout may include pairing components to share access ports (e.g., command port, data port). Additionally, in some embodiments, the layout may support an interface of controller 215 (e.g., host interface 216) that is different from the interface of interface block 245 (e.g., via bus 221). For example, host interface 216 may be synchronous and have separate channels for read and write operations, while the interface between interface block 220 and one or more interface blocks 245 may be asynchronous and support both read and write operations on the same channel. In some embodiments, signaling of host interface 216 may be implemented with deterministic timing (e.g., determinism between controller 215 and logic block 225 or one or more interface blocks 220), and the deterministic timing may be associated with configured timing between a first signal and a responsive second signal. In some embodiments, signaling between interface block 220 and one or more interface blocks 245 may be performed with timing that may be deterministic or non-deterministic (e.g., according to a different clock frequency, according to a timing offset such as a phase offset) that differs from the timing of host interface 216.

[0049] The die 240 may include one or more units 265 (e.g., modules) separated from a semiconductor wafer having a pattern (e.g., a two-dimensional pattern) of the units 265. Although each die 240 of the system 200 is shown with a single unit 265 (e.g., unit 265-a-1 of die 240-a-1 and unit 265-a-2 of die 240-a-2), a die 240 according to the techniques of the present description may include any number of units 265, which may be arranged in various patterns (e.g., a set of one or more units 265 along a row direction, a set of one or more units 265 along a column direction, among other patterns). Each unit 265 includes at least the circuitry of a respective interface block 245, which may involve memory array(s) 250, a bus 251, a bus 246, and one or more contacts 247 corresponding to the respective interface block 245. In some embodiments, where applicable, each unit 265 may also include one or more buses 255, contacts 256, contacts 257, or contacts 260 (e.g., buses or contacts associated with respective interface blocks 245 of units 265 of different dies 240), which may support various degrees of stackability or modularity between or through units 265 of other dies 240. Although examples of non-volatile storage 270 and sensors 275 are shown outside of unit 265, in some other embodiments, non-volatile storage 270, sensors 275, or both may additionally or alternatively be included in unit 265.

[0050] In some embodiments, interface block 220 may include circuitry configured to receive first access command signaling (e.g., from host processor 210, from controller 215, from logic block 225, via host interface 216, from host processor 210 or controller 215 external to die 205 via one or more contacts 212, based on a request from a host application) and to transmit second access command signaling to (e.g., coupled to) a respective interface block 245 based on (e.g., in response to) the received first access command signaling. Thus, interface block 245 may include circuitry configured to receive second access command signaling from a respective interface block 220 and, in some embodiments, to access a respective set of one or more memory arrays 250 based on (e.g., in response to) the received second access command signaling. In various embodiments, the first access command signaling may include an access command associated with a type of operation (e.g., a read operation, a write operation, a refresh operation, a memory management operation), and the access command may be associated with an indication of an address (e.g., a logical address, a physical address) of one or more memory arrays 250. In some embodiments, the first access command signaling may include an indication of a logical address associated with memory array 250, and circuitry in interface block 220 may be configured to generate the second access command signaling to indicate a physical address associated with memory array 250 (e.g., using a row address, a column address, a logical-to-physical (L2P) table, or other mapping or computational function of interface block 220).

[0051] In some embodiments, to support write operations of system 200, the circuitry of interface block 220 may be configured to receive first data signaling associated with first access command signaling (e.g., from host processor 210, from controller 215, from logic block 225) and to transmit second data signaling (e.g., second data signaling associated with the second access command signaling) based on the received first access command signaling and first data signaling. Accordingly, interface block 245 may be configured to receive the second data signaling and to write data to one or more memory arrays 250 based on the received second access command signaling and second data signaling (e.g., according to an instruction address associated with the first access command signaling). In some embodiments, interface block 220 may include error control functionality (e.g., error detection circuitry, error correction circuitry, error correction code (ECC) logic, ECC engine) that supports interface block 220 in generating second data signaling based on the received first data signaling to perform error control operations (e.g., detecting or correcting errors in the first data signaling, identifying one or more parity bits to be conveyed in the second data signaling and written with the data).

[0052] In some embodiments, to support read operations of system 200, circuitry in interface block 245 may be configured to read data from memory array 250 based on received second access command signaling and to transmit first data signaling based on the read data. Accordingly, interface block 220 may be configured to receive the first data signaling and to transmit second data signaling (e.g., to host processor 210, to controller 215, to logic block 225) based on the received first data signaling. In some embodiments, interface block 220 may include error control functionality that supports interface block 220 generating the second data signaling based on performing error control operations using the received first data signaling (e.g., detecting or correcting errors in the first data signaling, which may include calculations involving one or more parity bits received with the first data signaling).

[0053] In some embodiments, the access command signaling sent to interface block 245 may be generated (e.g., based on an access configuration to memory array 250 modified in interface block 220 or logic block 225) according to various determination or generation techniques configured in interface block 220 or logic block 225, among other signaling (e.g., based on an access command signaling received from host processor 210, based on an initiation signaling received from host processor 210, without receiving a signaling from host processor 210, or independently of a signaling from host processor 210). In some embodiments, such techniques may include signaling or other coordination with logic block 230, logic block 225, host processor 210, one or more controllers 215, one or more instances of non-volatile storage, one or more sensors, or any combination thereof. Such techniques may support interface block 220 or logic block 225 in configuring aspects of access operations that each interface block 245 performs on memory array 250, among other operations. For example, interface block 220 or logic block 225 may include evaluation circuitry, access configuration circuitry, signaling circuitry, scheduling circuitry, repair circuitry, refresh circuitry, error control circuitry, reverse access (e.g., row hammer) mitigation circuitry, and other circuitry operable to configure operations associated with one or more dies (e.g., operations associated with accesses to memory array 250 of die 240).

[0054] According to embodiments disclosed herein, the functionality of die 205 may be implemented as a semiconductor unit (e.g., a semiconductor system) formed of multiple semiconductor die portions (e.g., semiconductor chiplets, smaller semiconductor dies, KGDs), where each die portion may include a respective portion of the circuitry associated with die 205. For example, unit 280 may represent a portion of a circuit component included in a die portion (e.g., a chiplet), and a die portion may include an integer number of units 280. In some embodiments, each semiconductor die portion of a semiconductor unit may include a different respective portion of the circuitry. As a non-limiting example, a semiconductor unit (e.g., having the functionality of die 205) may be formed by one or more first die portions having one or more units 280-a-1 and one or more second die portions having one or more units 280-a-2. One or more units 280-a-1 may include one or more interface blocks 220, logic blocks 225, or any combination thereof, and one or more units 280-a-2 may include host processor 210, one or more controllers 215, logic blocks 230, or any combination thereof. While non-limiting examples of units 280 are shown, each unit 280 may include any combination of components of die 205 or other components. For example, unit 280-a-1 may further include logic block 230, or logic block 225 may be included in a different unit 280 (e.g., a different unit 280 of another chiplet, a different unit 280 in a partitioned HBM or TCDRAM implementation). In some embodiments, each set of one or more dies 240 may be stacked on a corresponding die portion (e.g., a die portion having one or more units 280-a-1), and the corresponding die portion may include circuitry for operating (e.g., controlling) the respective set of one or more dies 240 (e.g., unit 280-a-1 may correspond to one or more units 265 of each die 240 in the respective set).

[0055] According to the techniques herein, the first die portion and the second die portion may be formed separately (e.g., may have separate substrates and may be cut from different wafers) and may be coupled (e.g., electrically and functionally) to one another during a manufacturing process (e.g., after establishing the die portions as KGDs according to semiconductor manufacturing techniques) as part of forming a semiconductor unit (e.g., rather than forming die 205 from a wafer as a single monolithic unit). In some examples, the first die portion may be coupled to the second die portion via one or more conductive signal paths, which may be included in one or more conductive layers of the RDL (e.g., on the first die portion and the second die portion). The one or more conductive paths may be or include host interface 216, bus 231, bus 232, bus 233, or other examples of conductive signal paths described herein. In some embodiments, one or more conductive paths may be formed simultaneously with one or more other conductors (e.g., TSVs, PDN TRVs) along multiple (e.g., two, three, or more) different depths as part of the manufacturing process of the semiconductor unit, such as in a double damascene operation, a triple damascene operation, or a combination thereof.

[0056] 3 illustrates an example interface architecture 300 supporting semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. Interface architecture 300 illustrates an example in which interface block 245-b (e.g., of die 240) is coupled to interface block 220-b (e.g., of die 205). Interface block 245-b may be communicatively coupled to interface block 220-b via one or more of buses 301, 302, 303, and 304, each of which may be an example of one or more signal paths of buses 221 and 246, as well as bus 255, where applicable. Interface block 245-b may further be coupled to one or more buses 306 (e.g., a power supply bus, a PDN TRV, a communication bus), which may directly supply power to interface block 245-b or components of memory array 250-b (or, for example, some other component of die 240).

[0057] Interface block 245-b includes a control interface 310 (e.g., a command interface), which may be configured to communicate signaling with interface block 220-b. For example, control interface 310 may include circuitry (e.g., a receiver, one or more latches) configured to receive control signaling (e.g., modulated control signaling, access command signaling, configuration signaling, address signaling such as row address signaling or column address signaling) via bus 301-a. Control interface 310 may also include circuitry configured to receive clock signaling (e.g., clock signaling associated with control interface 310, clock signaling having one or more phases such as a true phase and a complementary phase, dk_t / c signaling from interface block 220-b) via bus 302-a, and control interface 310 may use bus 302-a to receive the control signaling of bus 301-a (e.g., to trigger one or more latches). The control interface 310 may send (eg, forward) control signaling and clock signaling (eg, for timing of other operations of the interface block 245-b) to the interface controller 320.

[0058] Interface block 245-b also includes two data interfaces 330 (e.g., data interfaces 330-a-1 and 330-a-2), which may also be configured to communicate signaling with interface block 220-b. Each data interface 330 may include corresponding buses and circuitry, the operation of which may be associated with (e.g., controlled by, coordinated with, or performed based on) control signaling via control interface 310. While an example of interface block 245-b includes two data interfaces 330 associated with control interface 310 (e.g., in a “channel pair” or “pseudo channel pair” configuration), the techniques described herein for interface block 245 may include any number of data interfaces 330, one or more, and associated buses and circuitry, for a given control interface 310 of interface block 245.

[0059] Each data interface 330 may be associated with a respective data path circuit, which may include a respective first-in-first-out (FIFO) and serialization / deserialization (SERDES) circuit (e.g., FIFO / SERDES 340), a respective write / sense circuit 350, a respective synchronization and sequencing circuit (e.g., sync / sequence logic 360), and a respective timing circuit 370, along with interconnect signal paths (e.g., one or more buses). However, in some other embodiments, the data path circuitry may be arranged in a different manner or may include different circuit components, including circuitry dedicated to each data path, circuitry shared between data paths, or various combinations thereof. Each data interface 330 may also be associated with a respective set of one or more memory arrays 250. In some embodiments, each memory array 250 may be understood to include, among other array circuitry, its own addressing circuitry, such as bank logic or decoders (e.g., row decoder, column decoder), or memory cell sense amplifier circuitry. However, in some other embodiments, at least a portion of such circuitry may be included in interface block 245.

[0060] Each data interface 330 may include circuitry (e.g., one or more latches, one or more drivers) configured to communicate (e.g., receive, transmit) data signaling (e.g., modulated data signaling, DQ signaling) over its respective bus 303. Each data interface 330 may also include circuitry for communicating clock signaling over its respective bus 304, and the circuitry may support clock signal reception by the data interface 330 (e.g., a first clock signaling associated with the data interface 330, clock signaling having one or more phases such as a true phase and a complementary phase, DQS_t / c signaling from interface block 220-b, clock signaling associated with a data receive operation or a write operation), or both, or clock signal transmission by the data interface 330 (e.g., a second clock signaling associated with the data interface 330, RDQS_t / c signaling to interface block 220-b, clock signaling associated with a data transmit operation or a read operation). In some embodiments, the data interface 330, the bus 303, or the combination of the bus 303 and the bus 304 may be associated with a "pseudo channel," and multiple pseudo channels may be associated with the same control interface 310 or the same control bus (e.g., bus 301, the combination of the bus 301 and the bus 302). In some implementations, the pseudo channels of multiple interface blocks 245 may be grouped together (e.g., functionally, logically, electrically, such as via hardwired signal paths or multiplexing circuitry) to support a channel set (e.g., a channel set associated with a corresponding host interface 216). Each data interface 330 may send clock signaling (e.g., received clock signaling, DQS_t / c signaling) to the synchronization / sequencing logic 360 via its respective bus (e.g., for timing of other operations of the interface block 245-b).

[0061] The interface controller 320 may support various functions (e.g., control functions, configuration functions) of the interface block 245-b for accessing or managing the operation of the coupled memory array 250. For example, the interface controller 320 may support, among other functions, adjustment or configuration of access commands, latency or timing compensation, buffering of access commands (e.g., according to a FIFO or other organization scheme), mode registers or logic for configuration settings, or test functions (e.g., evaluation functions, BIST functions), or combinations thereof. For each data path of the interface block 245 (e.g., each data path associated with a respective data interface 330), the interface controller 320 may be configured to send signaling (e.g., address signaling such as row address signaling or row activation signaling) to the respective memory array 250 via the bus. For each data path of the interface block 245, the interface controller 320 may communicate signaling (e.g., timing signaling, control signaling, which may be based on clock signaling received from the control interface 310) with the respective timing circuit 370 and synchronization / sequencing logic 360 via a respective bus.

[0062] For each data path, a respective timing circuit 370 may support the timing of various operations (e.g., activation, coupling operations, signal latching, signal driving) associated with timing signaling received from interface controller 320. For example, timing circuit 370 may include a timing chain (e.g., a global column timing chain) configured to generate one or more clock signals or other initiating signals to control the operation of the respective data path, and such signaling may include transitions (e.g., rising-edge transitions, falling-edge transitions, on / off transitions) that are offset, at a different rate, or otherwise different from those of the signaling from interface controller 320 to support a given operation or combination of operations. For example, the timing circuit 370 may be configured to send signaling (e.g., address signaling such as column address signaling or column activation signaling) to each memory array 250, to send signaling (e.g., latch or driver timing signaling) to each write / sense circuit 350, and to send signaling (e.g., timing signaling) to each synchronization / sequence logic.

[0063] For each data path, the respective FIFO / SERDES 340 may be configured to convert between data signaling of a first bus width (e.g., a relatively wide bus width, a data read / write (DRW) bus, a bus for communication with the write / sense circuit 350 having a relatively large number of signal paths) and data signaling of a second bus width (e.g., a relatively narrow bus width, a bus for communication with the data interface 330 having a relatively small number of signal paths). In some embodiments, such conversion may involve changing the signaling rate between the signaling from the data interface 330 and the signaling from the write / sense circuit 350 (e.g., to maintain a given throughput). In various embodiments, FIFO / SERDES 340 may receive data signaling from data interface 330 and send the data signaling to write / sense circuit 350 (e.g., to support a write operation), or may receive data signaling from sense circuit 350 and send the data signaling to data interface 330 (e.g., to support a read operation). In some embodiments (e.g., to support a read operation), FIFO / SERDES 340 may be configured to send clock signaling (e.g., RDQS_t / c signaling) to data interface 330, which may be forwarded to interface block 220-b.

[0064] Timing or other synchronization of operations performed by FIFO / SERDES 340 may be supported by, among other signaling, one or more clock signals received from respective synchronization / sequencing logic 360. For example, synchronization / sequencing logic 360 may generate or adjust clock signaling (e.g., based on received clock signaling) to support different rates of signaling for different buses. Additionally or alternatively, FIFO / SERDES 340 may operate in one direction (e.g., in the data transmission direction to data interface 330, in the data reception direction from data interface 330) or in other modes based on configuration signaling received from synchronization / sequencing logic 360.

[0065] For each data path, a respective write / sense circuit 350 may be configured to support access (e.g., data signaling, write signaling, read signaling) to a respective set of one or more memory arrays 250. For example, the write / sense circuit 350 may be coupled to the memory arrays 250 via a bus (e.g., a global input / output (GIO) bus), which may include a respective signal path associated with each memory array 250 or a signal path shared by all memory arrays 250 in the set, in which case the memory array circuitry may include multiplexing circuitry operable to couple the bus to a selected one of the memory arrays 250. In some embodiments, the bus between the write / sense circuit 350 and the set of one or more memory arrays 250 may include the same number of signal paths as the bus between the write / sense circuit 350 and the FIFO / SERDES 340 (e.g., a bus for signaling GIO[287:0]) or the same number of signal paths as the number of columns in each memory array 250. In some other embodiments, memory array 250 may include an integer multiple of the number of signal paths of the bus, in which case memory array circuitry (e.g., each memory array 250) may include decoding circuitry operable to couple a subset of the columns of memory cells or associated circuitry to the bus.

[0066] To support write operations, write / sense circuitry 350 may be configured to drive signaling operable (e.g., based on received data, based on received timing signaling, based on data signaling received via bus 303, and based on control signaling received via bus 301-a) to write one or more logic states to memory cells of memory array 250. In some embodiments, such signaling may be sent (e.g., as a signal output corresponding to the logic state to be written) to support circuitry of memory array 250 or circuitry otherwise associated with memory array 250, including sense amplifier circuitry, voltage sources, current sources, or other driver circuitry operable, among other examples, to apply a bias across the storage elements of the memory cells (e.g., across a capacitor, across a ferroelectric capacitor) or to apply a charge, current, or other signaling to the storage elements of the memory cells (e.g., to apply a current to a chalcogenide or other configurable memory material, to apply a charge to the gate of a NAND memory cell).

[0067] To support read operations, write / sense circuit 350 may be configured to receive signaling that write / sense circuit 350 may further amplify for communication via interface block 245-b. For example, write / sense circuit 350 may be configured to receive signaling corresponding to logic states read from memory array 250, which may have a relatively low drive strength (e.g., relatively “analog” signaling that may involve relatively low drive strengths of the sense amplifiers of memory array 250). Accordingly, write / sense circuit 350 may include additional sense amplifiers (e.g., data sense amplifiers (DSAs) between the signal paths between the write / sense circuit and the set of one or more memory arrays and between the write / sense circuit and the FIFO / SERDES), which may each have a relatively high drive strength (e.g., to drive the relatively “digital” signaling).

[0068] To support semiconductor systems having multiple dies, such as the various examples of system 200, the features of interface architecture 300 may be replicated in various numbers and arrangements. In an exemplary embodiment, each die 240 may be configured with 64 instances of interface blocks 245-b, thereby supporting a data signaling width of 9,216 signal paths per die 240 (e.g., each bus 303 of a channel pair is associated with 72 signal paths). For a system 200 having a stack of eight dies 240 combined with die 205, die 205 may thus be configured with 512 instances of interface blocks 220-b, thereby supporting an overall data signaling width of 73,738 signal paths for system 200. However, in other embodiments, die 205 and die 240 may be configured with different numbers of interface blocks 220 and 245, respectively, and system 200 may be configured with different numbers of dies 240 per die 205.

[0069] According to the techniques herein, a semiconductor unit (e.g., logic unit, semiconductor assembly) may be formed from multiple relatively small semiconductor dies (e.g., chiplets, logic chiplets). The relatively small semiconductor dies may include one or more interface blocks 220-b. Accordingly, a set of memory dies (e.g., array dies) stacked in a die portion may include one or more interface blocks 245-b along with multiple memory arrays 250-b. In some embodiments, each of bus 301-a, bus 302-a, bus 303, and bus 304 may include, or be examples of, TSVs, bond pads, conductive paths, or other mechanisms supporting coupling between a die portion and a set of memory dies (e.g., between a logic chiplet and a stack of memory dies). Additionally, one or more buses 306 (e.g., PDN TRV) may bypass the interface block 220-b (e.g., bypass portions of the die), which may allow for more efficient power delivery to the set of memory dies (e.g., compared to power delivery via the interface block 220-b or other components of the logic die).

[0070] 4A and 4B illustrate examples of a semiconductor component 400 and a die assembly 450 supporting semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. In FIG. 4A , the semiconductor component 400-a (e.g., a wafer, a die group) may include multiple dies 405 (e.g., logic dies), and each of the dies 405 may include multiple components (e.g., subcomponents). For example, the die 405 may include multiple portions of a circuit, such as an interface circuit, a memory controller circuit, a host controller circuit, and a host processor circuit, among other examples. In some cases, the die 405 may be an example of or include the die 205. Although the semiconductor component 400-a is shown as including four dies 405, the semiconductor component 400-a may include any number of dies 405.

[0071] As part of the manufacturing procedure, each of the die 405 may be evaluated to verify proper operation. The manufacturing yield may refer to the number or percentage of die 405 that meet the evaluation (e.g., the number of “good” die). For example, the evaluation procedure may determine whether the die 405 contains faults 415 (e.g., defects, errors) that cause the die 405 to operate improperly. If the die 405 is found to contain faults 415, the die 405 may be rejected (e.g., discarded). A relatively large die (e.g., die 405) may be more likely to be rejected than a relatively small die. For example, if a fault 415 is found in at least one portion of the circuitry of the die 405, the entire die 405 may be rejected. Thus, the semiconductor component 400-a may have a relatively low yield (e.g., because each of the die 405 contains a fault 415).

[0072] To improve the manufacturing yield (e.g., wafer yield) of semiconductor component 400, it may be desirable to manufacture (e.g., fabricate) relatively small portions of die 405 (e.g., smaller dies separable as individual portions of die 405, separately fabricating various portions of die 405's circuitry). For example, semiconductor component 400-b may include multiple dies 410 (e.g., chiplets, die portions), where the dies 410 may be smaller than die 405. Each die 410 may include its own portion (e.g., a subset, less than all) of die 405's circuitry and may be reduced in complexity relative to die 405. Because the dies 410 may be individually separable, the relatively small die 410 may be rejected (e.g., defects 415 may be isolated to a relatively small portion of the die), rather than the entire die 405 being rejected, thereby improving the overall manufacturing yield (e.g., of known good die 410). In the illustrated embodiment, semiconductor component 400-a and semiconductor component 400-b may include faults 415 in the same portion of the circuit. A fault 415 in semiconductor component 400-a may cause each of the dies 405 (e.g., the entire semiconductor component 400-a) to be rejected (e.g., even if semiconductor component 400-a includes some good die portions). In contrast, the same fault 415 in semiconductor component 400-b may cause only a portion of the die 410 to be rejected (e.g., die 410-a), while the other die may be accepted (e.g., die 410-b). For example, die 410-b may be accepted (e.g., may be an example of KGD) based on satisfying an evaluation procedure (e.g., evaluating the circuitry or functionality of the circuitry of die 410-b).

[0073] According to embodiments described herein, to improve manufacturing yields of semiconductor circuits, die assemblies 450 having one or more semiconductor units 420 may be formed by interconnecting smaller dies 410 (e.g., chiplets, logic chiplets, smaller semiconductor dies) to otherwise support the functionality of a larger die 405. For example, multiple dies 410 may be coupled with conductive lines 425 (e.g., via RDLs) to form semiconductor units 420 (e.g., units having the functionality of die 205, die 405, or other dies). In some embodiments, each of the dies 410 may be fabricated from a different wafer or from the same wafer. In some embodiments, the semiconductor units 420 may be functionally equivalent to die 405. Gaps between the dies 410 may be filled with one or more dielectric materials 435 (e.g., silicon oxide gap fill), which separate each of the dies 410 (e.g., separate the substrates of the dies 410). In some embodiments, different dies 410 may use various fabrication techniques (e.g., different techniques for transistor formation). For example, a first fabrication technique (e.g., memory fabrication flow) may be used to fabricate transistors (e.g., FinFET, planar transistors) of die 410-c (e.g., for interface block 220), and a second fabrication technique (e.g., logic fabrication flow, foundry process) may be used to fabricate transistors (e.g., FinFET, all-around gate transistors) of die 410-d (e.g., for host processor 210, for controller 215). Furthermore, the different fabrication techniques may involve sourcing each die 410 from different wafers, from different manufacturers, or both. In some embodiments, multiple dies 410, along with conductive lines 425, dielectric material 435, and any other circuitry (e.g., TRVs), may be formed as part of a reconstructed KGD wafer (e.g., a KGD wafer assembly), which may be of various sizes (e.g., 200 millimeters, 300 millimeters, or other sizes).

[0074] 5-12 illustrate example operations for forming a semiconductor system 500 (e.g., a heterogeneous device, a heterogeneous die semiconductor system, a heterogeneous HBM system, a heterogeneous TCDRAM system) using semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. For example, FIGS. 5-12 may illustrate aspects of a series of operations that may support the fabrication of system 100 or a portion of system 100, system 200 (e.g., die 205, a unit supporting the functionality of die 405), die assembly 450, or any other device herein, which may increase device yield during fabrication and improve power delivery to stacked memory dies. Each of the figures may be described with reference to the x, y, and z directions of coordinate system 501. The operations shown in and described with reference to Figures 5-12 may be performed by a manufacturing system, such as a semiconductor fabrication system configured to perform additive operations (e.g., deposition, epitaxy, bonding), removal operations (e.g., etching, trenching, planarization, polishing), modification operations (e.g., oxidation, doping, reacting, converting), and support operations (e.g., masking, patterning, photolithography, aligning), among other operations in support of the described techniques.

[0075] 5 illustrates a portion of semiconductor system 500 after a first set of one or more manufacturing operations have been performed. For example, semiconductor system 500 may include die 410-e-1 and die 410-e-2 (e.g., KGD, which may be heterogeneous KGD), which may be bonded to carrier 505.

[0076] The carrier 505 (e.g., a sacrificial silicon carrier) may include one or more material levels, such as a substrate 510 (e.g., a carrier substrate, a wafer substrate) and a bonding layer 515. The carrier 505 may provide a surface for bonding (e.g., mounting) multiple dies 410-e and may provide structural support for the semiconductor unit. Each die 410-e may include a material level, such as a substrate 535 (e.g., a semiconductor substrate, a crystalline substrate) and a bonding layer 520. Although two dies 410-e are shown, any number of dies 410-e may be formed on the carrier 505 (e.g., arranged along the x direction, arranged along the y direction). Each die 410-e may be an instance of a die 410 (e.g., a semiconductor die, a chiplet, a portion of a semiconductor unit).

[0077] Bonding layer 515 may include one or more alignment features 545 (e.g., alignment marks, fiducial marks), such as alignment features 545-a-1, 545-a-3, 545-a-5, and 545-a-6. Alignment features 545 may comprise a material different from other materials of bonding layer 515, thereby visualizing proper alignment of or between carrier 505 and one or more dies 410-e. In some examples, alignment features 545 may comprise a conductive material, which may or may not support electrical coupling (e.g., alignment features 545-a-1 and 545-a-6 may support electrical coupling, and alignment features 545-a-2, 545-a-3, 545-a-4, and 545-a-5 may not support electrical coupling).

[0078] The first set of manufacturing operations may include bonding (e.g., by chip-to-wafer bonding, by face-to-face bonding) semiconductor dies 410-e to carrier 505. Each of dies 410-e may include a respective circuit 525 that includes a portion of the circuitry associated with the semiconductor unit (e.g., a respective portion of the functionality associated with die 205 or die 405), and each respective circuit 525 may have been evaluated for acceptable performance prior to bonding in the first set of operations. In some embodiments, at least some instances of circuitry 525 may each include memory interface circuitry (e.g., interface block 220, interface block 245, logic block 225), memory controller circuitry (e.g., logic block 230, controller 215), host controller circuitry, host processor circuitry (e.g., host processor 210), sensor circuitry (e.g., sensors 237, sensors 275), storage circuitry (e.g., memory array 250, non-volatile storage 235, non-volatile storage 270), other circuitry (e.g., graphics circuitry, peripheral circuitry), or any combination thereof. In some embodiments, circuitry 525 on one die 410 may be different from circuitry 525 on another die 410 (e.g., in a heterogeneous chiplet configuration) or may be the same circuitry. For example, circuitry 525-a-1 may include memory interface circuitry and circuitry 525-a-2 may include host processor circuitry, among other examples of differentiation between dies 410. In some embodiments, circuitry 525-a may include circuitry associated with one or more units 280-a-1, but may not include at least some of the circuitry associated with one or more units 280-a-2 (e.g., host system 105 or host processor 210 may be separately coupled, such as in an HBM implementation). In some other embodiments, circuitry 525-a may not include circuitry associated with one or more units 280-a-1 (e.g., one or more units 280-a-1 may be separately coupled), but may include circuitry associated with one or more units 280-a-2 (e.g., host processor 210 and controller 215).In some embodiments, at least a portion of circuit 525 (e.g., one or more transistors of circuit 525, complementary metal-oxide semiconductor (CMOS) circuitry) may be formed from a portion of substrate 535 of die 410-e (e.g., a doped portion of substrate 535, a doped semiconductor material, a doped crystalline semiconductor). In some embodiments, one or more instances of circuit 525 may include front-end (FEOL) circuitry (e.g., transistor circuitry), back-end (BEOL) circuitry (e.g., interconnect circuitry, one or more conductive paths formed on a transistor circuit), or both.

[0079] Each die 410-e may include a bonding layer 520, which may be on an opposite side of the die 410-e from the substrate 535 (e.g., along the z-direction). Multiple dies 410-e may at least partially overlap along a direction from the carrier (e.g., along the z-direction, along the thickness dimension). Bonding the die 410-e may include bonding a front side of the die 410-e (e.g., a front side of the die 410-e) opposite the substrate 535 of the die 410-e to a front side of the carrier 505 (e.g., a front side of the carrier 505) opposite the substrate 510 of the carrier 505. The die 410-e and the carrier 505 may be bonded according to face-to-face bonding (e.g., chip-to-wafer front-to-front fusion bonding), and the bonding may be fusion bonding of one or more materials of the bonding layer 520-a with one or more materials of the bonding layer 515 of the carrier 505. In some embodiments, bonding of multiple semiconductor dies 410-e to carrier 505 can be based on alignment features 545 on carrier 505, alignment features 545 on die 410-e (e.g., alignment features 545-a-2, alignment features 545-a-4 included in bonding layer 520-a), or both. In some embodiments, bonding die 410-e to carrier 505 can provide a mechanical bond between die 410 and carrier 505 without an accompanying electrical bond.

[0080] 6 illustrates a portion of the semiconductor system 500 after one or more second set of manufacturing operations have been performed. For example, the second set of operations may include removing a portion of material from at least one die 410-e (e.g., die 410-e-1, die 410-e-2) after bonding the multiple dies 410-e to the carrier 505. For example, at least a portion of the substrate 535 of the die 410-e may be removed by a chemical mechanical planarization (CMP) technique or other techniques such as thinning, grinding, cutting, polishing, planarizing, or etching. By removing the portion of material (e.g., excess silicon, excess substrate 535), the size of the die 410-e may be reduced from a first thickness to a second thickness (e.g., along the z-direction in a silicon thinning operation). In some embodiments, the second set of manufacturing operations may be optional and may not be performed as part of the manufacturing process (e.g., there may be no excess material to remove from the die 410-e).

[0081] 7 illustrates a portion of semiconductor system 500 after a third set of one or more fabrication operations has been performed. For example, the third set of operations may include forming one or more dielectric materials 705 (e.g., silicon dioxide, gap-fill material, oxide, nitride, carbide, oxynitride, oxycarbide, other conversions or dopings of a substrate material, or some other dielectric material). In some embodiments, the one or more dielectric materials 705 may be formed between multiple dies 410-e and at least along carrier 505. The one or more dielectric materials 705 may separate the respective substrates 535 of the dies 410-e (e.g., separate each chiplet). For example, the one or more dielectric materials 705 may separate substrate 535-a-1 of die 410-e-1 from substrate 535-a-2 of die 410-e-2. Thus, at least prior to a subsequent interconnection operation, each of the die 410-e may be electrically insulated from the other die 410-e by one or more dielectric materials 705 (e.g., each die 410-e may be insulated by one or more dielectric materials 705 on each side other than the side bonded to the carrier 505). The one or more dielectric materials 705 may also provide structural support for various components of the semiconductor system 500.

[0082] 8 illustrates a portion of semiconductor system 500 after a fourth set of one or more fabrication operations has been performed. For example, the fourth set of operations may include removing a portion of one or more dielectric materials 705 (e.g., in some embodiments, removing excess material, with at least some dielectric material remaining over die 410-e). For example, after forming one or more dielectric materials at least along carrier 505, at least a portion of one or more dielectric materials 705 overlying die 410-e (e.g., along the z-direction) may be removed. In some embodiments, removing a portion of one or more dielectric materials 705 may include CMP (e.g., silicon oxide CMP).

[0083] 9 illustrates a portion of semiconductor system 500 after a fifth set of one or more fabrication operations has been performed. For example, the fifth set of operations may include forming conductive pathways 906 (e.g., forming at least a portion of a RDL, forming conductive signal pathways, forming conductive pathways 906 at least partially on the backside of die 410-e, forming conductive pathways along various directions in the xy plane), which may include forming one or more first cavities through one or more dielectric materials 705 to a first depth (e.g., from a surface of one or more dielectric materials 705 along the z direction). In some embodiments, each of the conductive pathways 906 may contact (e.g., provide electrical coupling between) at least two die 410-e (e.g., via vias 910-a-3 and 910-a-4).

[0084] The fifth set of operations may also include forming one or more vias 910 (e.g., TSVs, forming vias 910 on the backside of die 410-e, forming vias 910 through substrate 535), which may include forming one or more second cavities through at least one or more dielectric materials 705 to a second depth, each second cavity may also penetrate at least a portion of die 410-e (e.g., may contact circuitry 525-a or may expose a portion of circuitry 525-a). In some embodiments, the one or more vias 910 may support an interface between die 410-e and at least one of a set of one or more other semiconductor dies (e.g., memory die, die stack 240) and may be at least TSVs based formed through substrate 535. Additionally or alternatively, the one or more vias 910 may provide an interface between die 410-e and at least one other die 410-e. For example, circuit 525-a-1 of die 410-e-1 and circuit 525-a-2 of die 410-e-2 may be coupled (e.g., communicatively coupled, electrically coupled) based on via 910-a-3 through substrate 535-a-1 and via 910-a-4 through substrate 535-a-2, which may be coupled by one or more conductors (e.g., conductive path 906) of the RDL.

[0085] The fifth set of operations may also include forming one or more vias 915 (e.g., TV, PDN TRV, bypass via), which may include forming one or more third cavities through at least one or more dielectric materials 705 to a third depth. Each third cavity may be formed between, beside, or otherwise around the dies 410-e (e.g., along the x-direction, along the y-direction, or along both directions) and may contact the carrier 505 (e.g., may be filled with a conductive material that contacts the alignment features 545-a, or may otherwise contact or penetrate the carrier 505). The vias 915 may be formed through a layer 905 (e.g., a logic layer, a layer containing logic chiplets). Vias 915 may bypass die 410-e and may provide an interface (e.g., to which may later be bonded) between a set of one or more other semiconductor dies (e.g., die 240) disposed on layer 905 and a surface of one or more dielectric materials 705 opposite the set of one or more other semiconductor dies.

[0086] Forming the conductive pathways 906, the vias 910, and the vias 915 may include simultaneously or sequentially filling one or more first cavities, one or more second cavities, and one or more third cavities with one or more conductive materials (e.g., according to a simultaneous damascene process, a triple damascene process, or a backside triple damascene process). Thus, in some embodiments, the conductive pathways 906, the vias 910, and the vias 915 may be referred to as or be included in a backside triple damascene RDL. Forming the semiconductor unit 920 may be based on filling the plurality of conductive pathways 906, the one or more vias 910, and in some embodiments, the one or more vias 915, with one or more conductive materials (e.g., a single conductive material, a conductive liner material, and a conductive fill material). For example, based on forming the conductive paths 906, each of the multiple die 410-e may be electrically coupled (e.g., connected) with at least one other die 410-e via an RDL (e.g., via an RDL that may include the multiple conductive paths 906) (e.g., die 410-e-1 may be electrically coupled to die 410-e-2). That is, electrically connecting the die 410-e may be based on forming an RDL that includes the multiple conductive paths 906 on the die 410-e. Forming the semiconductor unit 920 may be based on coupling each of the multiple die 410-e to at least one other die 410-e. The semiconductor unit 920 may be an example of an implementation of the functionality of the die 205, the die 405, a logic die, or some other die.

[0087] 10 illustrates a portion of semiconductor system 500 after a sixth set of one or more fabrication operations have been performed. For example, the sixth set of operations may include forming layer 1005 (e.g., at least a portion of a RDL), which may include one or more dielectric materials 1010 and one or more conductive pads 1015 (e.g., bonding pads) over die 410-e. In some embodiments, layer 1005 may also include conductive paths between conductive pads 1015 (e.g., including signal paths in the RDL along various directions in the xy plane, not shown), providing electrical coupling between vias 910, vias 915, or a combination thereof. In some examples, each conductive pad 1015 may couple (e.g., enable coupling of) one or more other semiconductor dies (e.g., die 240) stacked on layer 1005 to a PDN (e.g., via 915, PDN TRV, through carrier 505), to via 910 of die 410-e, to an RDL (e.g., conductive path 906) on die 410-e, or any combination thereof. The sixth set of manufacturing operations may also include forming one or more pads 1020 (e.g., redundant pads, dummy pads, conductive pads) that may be used for purposes other than electrical coupling of components (e.g., as alignment features). In some examples, at least some of the conductive pads 1015 may implement the functionality of contacts 222. In some embodiments, forming conductive pad 1015 and pad 1020, along with corresponding vias (e.g., vias through layer 1005 to couple with layer 905) and signal paths in layer 1005, may be based on simultaneously filling cavities with one or more conductive materials (e.g., according to a simultaneous damascene process, a double damascene process, or a backside double damascene process). Thus, in some embodiments, conductive pad 1015, pad 1020, and corresponding signal paths and vias in layer 1005 may be referred to as a backside double damascene RDL or may be included in a backside double damascene RDL, which may correspond to a backside double damascene process RDL formed on a triple damascene process RDL associated with a fifth set of operations (e.g., an operating set of devices of heterogeneous die 410-e).

[0088] 11 shows a portion of semiconductor system 500 after a seventh set of one or more manufacturing operations have been performed. For example, the seventh set of operations may include forming (e.g., stacking, assembling, bonding) layer 1105 (e.g., including die 240, memory die, array die) on carrier 505, layer 905, and layer 1005. The components of semiconductor system 500 may include various layers and materials, such as bonding layer 1115, bonding layer 1120, one or more dielectric materials 1130 (e.g., silicon dioxide), substrate 1135 (e.g., a silicon substrate), and one or more conductive materials 1140 (e.g., copper, aluminum, or some other material).

[0089] In some examples, forming layer 1105 may include coupling (e.g., bonding) a respective set (e.g., stack) of one or more dies 1145-a onto (e.g., with) at least one of dies 410-e (e.g., via one or more RDLs, via layer 1005), where each die of the respective set of dies 1145-a may include circuitry 1125-a, such as, for example, memory circuitry (e.g., multiple memory arrays, memory array 250), interface circuitry (e.g., interface block 245, or components of interface block 245), or other circuitry (e.g., non-volatile storage 270, sensor 275, or other circuitry associated with other circuitry). In some examples, die 1145 or stacks of dies 1145 may be separately coupled, as a respective set, to at least one of dies 410-e. In some other embodiments, the multiple dies 1145 (e.g., multiple dies 1145 in a layer of dies 1145) or stack of dies 1145 may be contiguous (e.g., as part of a wafer or other semiconductor component, as part of a stack of wafers or other semiconductor components) or otherwise mechanically connected (e.g., along the x-direction, along the y-direction, not shown), which may include subsequent separation (e.g., singulation) into semiconductor units. In some such other embodiments, the die 1145 may be part of a reconstructed wafer or other reconstructed semiconductor component of dies 1145 (e.g., known-good dies 1145), in which case such reconstructing may include bonding the singulated or otherwise separate dies 1145 to a carrier (e.g., similar to bonding die 410 to carrier 505, not shown).Thus, in some embodiments, a wafer of die 1145, or a reconstructed wafer of die 1145, may be bonded (e.g., bonded) to a semiconductor unit 920 formed at least in part from a bonded die 410 (e.g., an RDL provides at least a portion of such a bond, such as an RDL between a reconstructed wafer of die 1145 and a reconstructed wafer of die 410).

[0090] The circuits 1125-a may include FEOL circuits (e.g., transistor circuits, circuits formed at least partially from doped portions of the substrate 1135) and BEOL circuits (e.g., interconnect circuits). Each instance of the circuits 1125-a may be operable via one or more interconnect regions 1150-a based on the instance of the circuits 525-a of the die 410-e to which the respective set is bonded. In some embodiments, the interconnect regions 1150-a may include components or circuitry (e.g., TSVs, bonding pads, BEOL circuitry) that couple the circuits 1125 with other circuits 1125 of the respective die 1145-a (e.g., coupling between circuits 1125-a-1 and 1125-a-2), couple the circuits 1125 with conductive pads 1110, or couple the circuits 1125 with conductive pads 1112, or various combinations thereof.

[0091] In some examples, bonding one die 1145-a to another die 1145-a can include bonding one or more conductive pads 1110-a to one or more conductive pads 1112-a. For example, among other examples, conductive pad 1110-a can be an implementation of contact 247 or contact 256, and conductive pad 1112-a can be an implementation of contact 257 or contact 260. In some examples, conductive pad 1112-a (e.g., conductive pad 1112-a-1) of a first die 1145-a can be bonded (e.g., fused) with conductive pad 1110-a (e.g., conductive pad 1110-a-3) of a second die 1145-a, including using a hybrid bonding implementation (e.g., wafer-to-wafer or die-to-die front-to-back hybrid bonding). In some embodiments, such bonding may involve bonding of respective dielectric portions (e.g., surfaces) of die 1145-a, such as fusing dielectric material 242. In some embodiments, material 1160 (e.g., additional silicon, additional substrate material) may be formed or disposed on top of semiconductor system 500 and bonded to die 1145-a that is on top of a stack of dies 1145-a, including using a fusion bonding implementation (e.g., wafer-to-wafer front-to-back fusion bonding).

[0092] In some embodiments, bonding of a respective set of one or more dies 1145-a to die 410-e may be based on one or more conductive pads 1110-a in each set of dies 1145-a and one or more conductive pads 1015-a in die 410-e. For example, a set of dies 1145-a may be bonded to die 410-e through a hybrid bonding implementation (e.g., stack-to-wafer front-to-back hybrid bonding). Interconnect regions 1150-a may be coupled to the conductive pads 1110-a to provide a communication interface between die 410-e and die 1145-a. In some embodiments, interconnect regions 1150-a may implement the functionality of buses 255, 246, 251, 301, 302, 303, 304, or a combination thereof. For example, one or more conductive pads 1110-a (e.g., conductive pad 1110-a-2) may be bonded by vias 910 (e.g., TSVs), one or more conductive paths 906 (e.g., RDLs), or both, which may penetrate substrate 535-a of die 410-e to which the respective set of die 1145-a is bonded. Vias 910 and conductive paths 906 may provide an interface between the respective set of one or more die 1145-a and die 410-e. In some embodiments, one or more conductive pads 1110-a (e.g., conductive pad 1110-a-1) may be bonded to vias 915 (e.g., PDN TRVs), which may provide an interface through layer 905, bypassing die 410-e. In some embodiments, bonding the respective sets of one or more dies 1145-a to die 410-e may be based on fusing between the respective conductive portions and fusing between the respective dielectric portions (e.g., surface-to-wafer bonding, front-to-back bonding, hybrid bonding of both dielectric and conductive materials). In some embodiments, at least some, but not all, of the dies 1145-a may meet (e.g., be verified to meet) an evaluation (e.g., an operational evaluation) before bonding the respective sets of one or more dies 1145-a to die 410-e.

[0093] 12 illustrates a portion of semiconductor system 500 after an eighth set of one or more manufacturing operations has been performed. For example, the eighth set of operations may include forming one or more contacts 1205 (e.g., electrical contacts, solder balls, microbumps, contactor collapse chip connect (C4) bumps) at one or more depths (e.g., along the z-direction) relative to carrier 505. Forming the contacts 1205 may include forming cavities through at least a portion of carrier 505. In some embodiments, forming one or more contacts 1205-a (e.g., for each of die 410-e) may be based on forming cavities through at least a portion of the carrier and at least a portion of die 410-e, and forming one or more conductive materials in each of the cavities. Forming contacts 1205 may include forming at least some contacts 1205 (e.g., contacts 1205-a-2 and contacts 1205-a-3) on a surface of semiconductor system 500 (e.g., on a surface of carrier 505 opposite multiple die 410-e) and coupling to circuitry 525 of die 410-e. In some embodiments, one or more contacts 1205 (e.g., contacts 1205-a-1 and contacts 1205-a-4) may be formed on a surface of semiconductor system 500 and coupled to at least one set of one or more die 1145-a, which may bypass die 410-e. For example, vias 915 may provide an interface between the set of die 1145-a and a surface of the semiconductor unit opposite the respective set of die 1145-a (e.g., a surface of layer 905) via contacts 1205. In some embodiments, the semiconductor system 500 may include a combination of one or more first contacts 1205 (e.g., contact 1205-a-1) that may be coupled to one or more vias 915 (e.g., PDN TRVs) and one or more second contacts 1205 (e.g., contact 1205-a-2) that may be coupled to one or more dies 410-e (e.g., that may be coupled to pads of a logic chiplet), which may involve different depths along the z-direction.Upon formation of one or more contacts 1205, the semiconductor system 500 may be capable of being communicatively coupled to other components (eg, a GPU or other peripheral components).

[0094] After the eighth set of manufacturing operations, the semiconductor system 500 may be ready for packaging, which may include separating (e.g., dicing) multiple semiconductor units 920 from one another on the same carrier 505. According to the techniques described with reference to FIGS. 5-12 , the semiconductor system 500 may include multiple dies 410-e (e.g., chiplets, logic chiplets, logic die, semiconductor die, die portions) electrically coupled via conductive paths 906 (e.g., included in RDLs) to form one or more semiconductor units 920 (e.g., semiconductor units 920 associated with the functionality of the logic die, die 205, or die 405). The semiconductor system 500 may further include one or more sets of die 1145-a (e.g., die 240, semiconductor die, array die, DRAM die, stack of memory die), which may be bonded to a respective die 410-e (e.g., die 410-e of a respective semiconductor unit 920) via one or more bonding pads 1015-a (e.g., in layer 1005) and one or more vias 910 (e.g., TSVs). For example, layer 905 (e.g., a lower die in the stack) may be associated with one or more units 280, and layer 1105 may be associated with one or more die 240. The one or more sets of die 1145-a may also be bonded to one or more vias 915 (e.g., PDN TRVs), which may provide an interface (e.g., a power supply interface) to the set of die 1145-a at the surface of the semiconductor system 500 (e.g., via contacts 1205-a).

[0095] Utilizing one or more techniques described herein may support increased manufacturing yields of wafers associated with components of semiconductor system 500 (e.g., HBM devices, TCDRAM devices). For example, techniques herein may enable the fabrication and evaluation of relatively small, individually separable semiconductor dies (e.g., die 410) and the reconstruction of a relatively large semiconductor unit (e.g., die 205 or a semiconductor unit implementing the functionality of die 405) using multiple relatively small dies (e.g., using die 410 that meets evaluation). Furthermore, the described techniques may enable direct power delivery to one or more stacked memory dies (e.g., die 1145-a, die 240) with low resistance, based on which one or more vias 915 may bypass die 410-e and support more efficient use of die area. Accordingly, manufacturing of semiconductor system 500 may involve increased yields, and semiconductor system 500 may operate with improved efficiency. Although some of the described techniques are described in the context of a memory system, the techniques described herein may be implemented in other semiconductor systems implementing heterogeneous semiconductor components (e.g., dies associated with different functions, including different logic functions, different storage functions, or processing functions, or any combination thereof), including heterogeneous semiconductor components interconnected within a layer, between layers, or any combination thereof.

[0096] 13 shows a flowchart illustrating a method 1300 for supporting semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. The operations of method 1300 may be performed by a manufacturing system or one or more controllers associated with a manufacturing system. In some embodiments, the one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using dedicated hardware.

[0097] At 1305, the method may include bonding a plurality of first semiconductor dies to the carrier, each of the first semiconductor dies including a respective portion of the circuitry of the semiconductor unit.

[0098] At 1310, the method may include forming a semiconductor unit based at least in part on electrically connecting each of the plurality of first semiconductor dies with at least one other of the first semiconductor dies after bonding the plurality of first semiconductor dies to the carrier.

[0099] At 1315, the method may include bonding a respective set of one or more second semiconductor dies to at least one of the plurality of first semiconductor dies, each second semiconductor die in the respective set including a memory array, the memory array operable based at least in part on a respective portion of the circuitry of the semiconductor unit of the first semiconductor die to which the respective set is bonded.

[0100] In some examples, an apparatus (e.g., a manufacturing system) described herein may perform a method(s), such as method 1300. The apparatus may include mechanisms, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof, for performing the following aspects of the present disclosure:

[0101] Aspect 1: Bonding a plurality of first semiconductor dies (e.g., die 410) to a carrier (e.g., carrier 505), each of the first semiconductor dies including a respective portion of a circuit (e.g., circuit 525) of a semiconductor unit (e.g., semiconductor unit 920); forming the semiconductor unit based at least in part on electrically connecting each of the plurality of first semiconductor dies with at least one other of the first semiconductor dies after bonding the plurality of first semiconductor dies to the carrier; bonding a respective set of one or more second semiconductor dies (e.g., die 240, die 1145) to at least one of the plurality of first semiconductor dies, wherein each second semiconductor die of the respective set includes a memory array (e.g., at least one memory array 250 of circuit 1125), the memory array being operable based at least in part on the respective portion of the circuit of the semiconductor unit of the first semiconductor die to which the respective set is bonded; A method or apparatus that includes operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing a function.

[0102] Aspect 2: The method or apparatus of aspect 1, wherein, for each of the first semiconductor dies, the respective portion of the circuitry includes a memory interface circuit, a memory controller circuit, a host controller circuit, a host processor circuit, or any combination thereof.

[0103] Aspect 3: The method or apparatus of any of Aspects 1-2, wherein a first respective portion of a circuit of a first semiconductor die of the semiconductor unit is associated with a first logic function, and a second respective portion of a circuit of another first semiconductor die of the semiconductor unit is associated with a second logic function different from the first logic function.

[0104] Aspect 4: The method or apparatus of any of Aspects 1-3, wherein the first respective set of one or more second semiconductor dies and the second respective set of one or more second semiconductor dies are included in a reconstructed wafer of second semiconductor dies bonded to the semiconductor unit.

[0105] Aspect 5: The method or apparatus of any of aspects 1 to 4, further comprising: forming one or more dielectric materials (e.g., dielectric material 705) along the carrier between at least the plurality of first semiconductor dies, the one or more dielectric materials separating the substrates (e.g., substrate 535) of each of the first semiconductor dies; and further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing the forming.

[0106] Aspect 6: forming a plurality of first cavities through the one or more dielectric materials to a first depth, each of the first cavities contacting at least two of the first semiconductor dies; forming a plurality of second cavities through the one or more dielectric materials to a second depth, each of the second cavities passing through at least a portion of a respective one of the first semiconductor dies; forming a plurality of third cavities through the one or more dielectric materials to a third depth, each of the third cavities residing between the plurality of first semiconductor dies and in contact with the carrier; simultaneously (e.g., sequentially) forming one or more conductive materials within the plurality of first cavities, the plurality of second cavities, and the plurality of third cavities; 6. The method or apparatus of embodiment 5, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing:

[0107] Aspect 7: The method or apparatus of aspect 6 further includes forming one or more conductive pads (e.g., bonding pad 1015, pad 1020), one or more conductive paths, and one or more vias in one or more second dielectric materials (e.g., layer 1005) adjacent to the one or more conductive materials (e.g., conductive path 906), wherein the one or more conductive pads, the one or more conductive paths, and the one or more vias are formed at least in part based on simultaneously forming one or more second conductive materials in cavities associated with the one or more conductive pads, the one or more conductive paths, and the one or more vias, and further including an operation, mechanism, circuit, logic, means, or instructions, or any combination thereof, for performing the forming.

[0108] Aspect 8: The method or apparatus of any of Aspects 1-7, further comprising an operation, mechanism, circuitry, logic, means, or instructions, or any combination thereof, for removing a portion of the one or more dielectric materials overlying the plurality of first semiconductor dies after forming the one or more dielectric materials at least along the carrier.

[0109] Aspect 9: The method or apparatus of any of aspects 1 to 8, further comprising: forming one or more vias (e.g., via 915) through one or more dielectric materials between the plurality of first semiconductor dies, each of the one or more vias being coupled to one of the sets of one or more second semiconductor dies; and further comprising: an operation, mechanism, circuit, logic, means, or instructions, or any combination thereof, for performing the forming.

[0110] Aspect 10: The method or apparatus of aspect 9, wherein at least one of the one or more vias provides an interface (e.g., supports an interface, is part of an interface) between a respective set of the one or more second semiconductor dies and a surface of the semiconductor unit opposite the respective set of the one or more second semiconductor dies.

[0111] Embodiment 11: A method or apparatus according to any of embodiments 9-10, further comprising an operation, mechanism, circuit, logic, means, or instruction for forming one or more electrical contacts in each of the one or more vias based at least in part on forming a cavity through at least a portion of the carrier and forming one or more conductive materials within the cavity.

[0112] Aspect 12: A method or apparatus according to any of aspects 1 to 11, wherein electrically connecting each of the plurality of first semiconductor dies is based at least in part on forming a plurality of conductive signal paths (e.g., conductive path 906) on the first semiconductor die of the semiconductor unit.

[0113] Aspect 13: The method or apparatus of aspect 12, further comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for verifying that each first semiconductor die of the plurality of first semiconductor dies and each respective set of the one or more second semiconductor dies meets an operational evaluation before bonding each respective set of the one or more second semiconductor dies to the at least one of the plurality of first semiconductor dies.

[0114] Aspect 14: A method or apparatus according to any of aspects 1 to 13, wherein bonding each of the sets of one or more second semiconductor dies to the at least one of the plurality of first semiconductor dies is based at least in part on forming one or more vias (e.g., via 910) through a substrate of the first semiconductor die to which the each of the sets is bonded.

[0115] Aspect 15: The method or apparatus of aspect 14, wherein each via provides an interface between a respective set of the one or more second semiconductor dies and the at least one first semiconductor die, an interface between the at least one first semiconductor die and at least one other first semiconductor die, or both of these interfaces.

[0116] Aspect 16: The method or apparatus of any of aspects 1 to 15, further comprising: forming a plurality of conductive pads (e.g., conductive pad 1015) on the plurality of first semiconductor dies, each of the plurality of conductive pads coupling a respective set of the one or more second semiconductor dies to a PDN via the carrier, to a TSV of the plurality of first semiconductor dies, to a RDL on the plurality of first semiconductor dies, or to any combination thereof; and further comprising: an operation, mechanism, circuit, logic, means, or instruction for performing the forming, or any combination thereof.

[0117] Aspect 17: A method or apparatus according to any of aspects 1 to 16, wherein bonding each of the sets of one or more second semiconductor dies to the at least one of the plurality of first semiconductor dies is based at least in part on fusing between the respective conductor portions and fusing between the respective dielectric portions.

[0118] Embodiment 18: The method or apparatus of any of embodiments 1 to 17, further including an operation, mechanism, circuit, logic, means, or instructions, or any combination thereof, for forming one or more electrical contacts on each of the first semiconductor dies based at least in part on forming a cavity through at least a portion of the carrier and forming one or more conductive materials within the cavity.

[0119] Aspect 19: The method or apparatus of any of aspects 1 to 18, wherein bonding the plurality of first semiconductor dies to the carrier includes, for at least one first semiconductor die, bonding a surface of the at least one semiconductor die opposite the substrate of the at least one semiconductor die to the carrier.

[0120] Aspect 20: A method or apparatus according to any of aspects 1 to 19, further comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for removing a portion of material from at least one of the plurality of first semiconductor dies after bonding the first semiconductor dies to the carrier.

[0121] Aspect 21: The method or apparatus of any one of Aspects 1 to 20, wherein the plurality of first semiconductor dies at least partially overlap along a direction from the carrier.

[0122] Aspect 22: A method or apparatus according to any of aspects 1 to 21, wherein the bonding of the plurality of first semiconductor dies to the carrier is based at least in part on one or more alignment features (e.g., alignment feature 545) of the carrier.

[0123] Aspect 23: A method or apparatus according to any of Aspects 1 to 22, wherein the bonding of the plurality of first semiconductor dies to the carrier provides a mechanical bond between the plurality of first semiconductor dies and the carrier without an accompanying electrical bond.

[0124] 14 shows a flowchart illustrating a method 1400 for supporting semiconductor die bonding techniques in a stacked memory architecture according to embodiments disclosed herein. The operations of method 1400 may be performed by a manufacturing system or one or more controllers associated with a manufacturing system. In some embodiments, the one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using dedicated hardware.

[0125] At 1405, the method may include bonding a plurality of first semiconductor dies to the carrier, each first semiconductor die including a respective portion of a circuit of a semiconductor unit of the semiconductor system.

[0126] At 1410, the method may include coupling each of the plurality of first semiconductor dies to at least one other first semiconductor die via an RDL including a plurality of conductive signal paths, wherein a semiconductor unit is formed with the coupled first semiconductor dies.

[0127] At 1415, the method may include forming a dielectric portion of the semiconductor unit between the plurality of first semiconductor dies, the dielectric portion including one or more dielectric materials.

[0128] At 1420, the method may include forming a plurality of vias through the dielectric portion between the plurality of first semiconductor dies.

[0129] At 1425, the method may include bonding at least one set of one or more second semiconductor dies to the semiconductor unit, each second semiconductor die including a memory array, the memory array operable by one of the coupled first semiconductor dies, the bonding being based at least in part on fusing a plurality of first bonding pads of the first semiconductor die with a plurality of second bonding pads of the at least one set of second semiconductor dies and bonding a plurality of third bonding pads coupled with the plurality of vias with a plurality of fourth bonding pads of the at least one set of second semiconductor dies.

[0130] In some examples, an apparatus (e.g., a manufacturing system) described herein may perform a method(s), such as method 1400. The apparatus may include mechanisms, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof, for performing the following aspects of the present disclosure:

[0131] Aspect 24: Bonding a plurality of first semiconductor dies to a carrier, each first semiconductor die including a respective portion of a circuit of a semiconductor unit of the semiconductor system; coupling each of the plurality of first semiconductor dies to at least one other first semiconductor die via a RDL including a plurality of conductive signal paths, wherein the semiconductor unit is formed by the coupled first semiconductor dies; forming a dielectric portion of the semiconductor unit between the plurality of first semiconductor dies, the dielectric portion including one or more dielectric materials; forming a plurality of vias through the dielectric portion between the plurality of first semiconductor dies; bonding at least one set of one or more second semiconductor dies to the semiconductor unit, each second semiconductor die including a memory array, the memory array operable by one of the coupled first semiconductor dies, the bonding being based at least in part on fusing a plurality of first bonding pads of the first semiconductor die with a plurality of second bonding pads of the at least one set of second semiconductor dies, and bonding a plurality of third bonding pads coupled to the plurality of vias with a plurality of fourth bonding pads of the at least one set of second semiconductor dies; A method or apparatus that includes operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing a function.

[0132] It should be noted that the methods described herein describe possible implementations, and that the acts and steps may be rearranged or otherwise modified, and that other implementations are possible. Additionally, portions of two or more of the methods may be combined.

[0133] SYSTEMS DESCRIBE Below, an overview of aspects of the systems described herein is provided.

[0134] Aspect 25: A carrier including one or more material levels; a plurality of first semiconductor dies bonded to the carrier, each first semiconductor die including a respective substrate, the respective substrate being separated from the respective substrate of each of the other first semiconductor dies, and each first semiconductor die including a respective portion of a circuit of a semiconductor unit, the respective portion being electrically coupled to the respective portion of the circuit of the semiconductor unit of at least one other first semiconductor die; at least one set of one or more second semiconductor dies, each set of one or more second semiconductor dies electrically coupled to a respective first semiconductor die of the plurality of first semiconductor dies, each second semiconductor die including one or more memory arrays, the one or more memory arrays operable based at least in part on the respective first semiconductor die to which the second semiconductor die is connected; Including, the system.

[0135] Aspect 26: The system of aspect 25, wherein, for each of the first semiconductor dies, the respective portion of the circuitry includes a memory interface circuit, a memory controller circuit, a host controller circuit, a host processor circuit, or any combination thereof.

[0136] Aspect 27: The system described in any of aspects 25 to 26, further comprising a dielectric portion of one or more dielectric materials between the respective substrates of the plurality of first semiconductor dies.

[0137] Aspect 28: The system described in aspect 27, further including one or more vias penetrating the dielectric portion between the plurality of first semiconductor dies, each of the one or more vias being coupled to one set of the one or more second semiconductor dies and bypassing the plurality of first semiconductor dies.

[0138] Aspect 29: The system described in aspect 28, wherein at least one of the one or more vias provides an interface between the one of the one or more sets of second semiconductor dies and a surface of the semiconductor unit opposite the respective set of the one or more second semiconductor dies.

[0139] Aspect 30: The system described in any of aspects 25 to 29, further including a RDL including a plurality of conductive signal paths, each first semiconductor die being electrically coupled to at least one other first semiconductor die via the RDL.

[0140] Aspect 31: The system described in any of aspects 25 to 30, further including one or more vias formed through the respective substrate of at least one first semiconductor die of the plurality of first semiconductor dies, each via providing an interface between at least one set of the one or more second semiconductor dies and the respective first semiconductor die, an interface between the at least one first semiconductor die and at least one other first semiconductor die, or both of these interfaces.

[0141] Aspect 32: The system described in any of aspects 25 to 31, further including a plurality of conductive pads on the plurality of first semiconductor dies, each of the plurality of conductive pads coupling a respective set of the one or more second semiconductor dies to a PDN via the carrier, to a TSV of the plurality of first semiconductor dies, to an RDL on the plurality of first semiconductor dies, or to any combination thereof.

[0142] Aspect 33: One or more first electrical contacts present on a surface of the system and coupled to at least one first semiconductor die of the plurality of first semiconductor dies; one or more second electrical contacts present on the surface of the system, coupled to at least one set of the one or more second semiconductor dies, and bypassing the plurality of first semiconductor dies; 33. The system according to any one of aspects 25 to 32, further comprising:

[0143] SYSTEMS DESCRIBE Below, an overview of aspects of the systems described herein is provided.

[0144] Aspect 34: Bonding a plurality of first semiconductor dies to a carrier, each of the first semiconductor dies including a respective portion of a circuit of a semiconductor unit; forming the semiconductor unit based at least in part on electrically connecting each of the plurality of first semiconductor dies with at least one other of the first semiconductor dies after bonding the plurality of first semiconductor dies to the carrier; bonding a respective set of one or more second semiconductor dies to at least one of the plurality of first semiconductor dies, each second semiconductor die of the respective set including a memory array, the memory array operable based at least in part on the respective portion of the circuit of the semiconductor unit of the first semiconductor die to which the respective set is bonded; A system formed by the processes that execute the

[0145] SYSTEMS DESCRIBE Below, an overview of aspects of the systems described herein is provided.

[0146] Aspect 35: A system including a plurality of first semiconductor dies, the plurality of first semiconductor dies being electrically coupled to form a semiconductor unit of the system, the system further comprising: a dielectric material separating respective substrates associated with each of the plurality of first semiconductor dies; a RDL including a plurality of conductive paths, the plurality of conductive paths electrically connecting each of the plurality of first semiconductor dies to at least one other first semiconductor die; one or more sets of second semiconductor dies, each second semiconductor die including a plurality of memory arrays; one or more bonding pads coupling each set of second semiconductor dies to a respective first semiconductor die of the plurality of first semiconductor dies; a plurality of vias extending through the dielectric material between the plurality of first semiconductor dies, each of the plurality of vias being coupled to at least one set of second semiconductor dies; The system comprising:

[0147] Aspect 36: A first portion including one or more first conductive materials formed continuously along three depths relative to the thickness of the system; a second portion overlying the first portion, the second portion including one or more second conductive materials formed continuously along two depths relative to the thickness of the system; 36. The system of embodiment 35, further comprising:

[0148] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, signaling data, instructions, commands, information, signals, bits, or symbols that may be referred to throughout the above description may be represented as voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. While in some figures a signal may be shown as a single signal, the signal may represent a bus of signals, and the bus may have various bit widths.

[0149] The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (e.g., in conductive contact, connected, coupled) with one another if any electrical path (e.g., a conductive path) exists between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. A conductive path between components that are in electronic communication (e.g., in conductive contact, connected, coupled) with one another may be an open circuit or a closed circuit at any time based on the operation of the device including the connected components. A conductive path between connected components may be a direct conductive path between the components, or a conductive path between connected components may be an indirect conductive path, which may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components may be temporarily interrupted using one or more intermediate components, such as, for example, switches or transistors.

[0150] The description set forth herein with reference to the accompanying drawings illustrates example configurations and does not represent every embodiment that may be implemented or that is within the scope of the claims. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0151] In the accompanying figures, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label with one or more dashes and an additional label that distinguishes the similar components. When only a first reference label is used in the specification, the description is applicable to any of the similar components having the same first reference label, regardless of any additional reference labels.

[0152] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuits, processing circuits, logic circuits), firmware, or any combination thereof. If the functions are implemented in software executed by a processing system, the functions may be stored on or transmitted as one or more instructions (e.g., code) on a computer-readable medium. Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or any combination thereof. The mechanisms that implement the functions may be physically located in various locations, including being distributed so that portions of the functions are implemented in different physical locations.

[0153] The example blocks and modules described herein may be implemented or performed by one or more processors, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof, designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0154] As used herein, including the claims, "or" when used in a list of items (e.g., a list of items ending in a phrase such as "at least one of" or "one or more of") indicates an inclusive list; for example, a list of at least one of A, B, or C means A, or B, or C, or AB, or AC, or BC, or ABC (i.e., A and B and C). Also, the phrase "based on" as used herein should not be construed as referring to a closed set of conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, the phrase "based on" as used herein should be interpreted the same as the phrase "based at least in part on."

[0155] As used herein, including the claims, the article "a" before a noun is understood to be open-ended and refer to "at least one" of that noun or "one or more" of that noun. Thus, the terms "a," "at least one," "one or more," and "at least one of one or more" may be interchangeable. For example, when a claim recites a "component" that performs one or more functions, each of the distinct functions may be performed by a single component or by any combination of multiple components. Thus, the term "a component" having a property or performing a function may refer to "at least one of one or more components" that has the particular property or performs the particular function. Reference to a component introduced with the article "a" followed by the words "the" or "said" may refer to any or all of the one or more components. For example, a component introduced with the article "a" can be understood to mean "one or more components," and a subsequent reference in a claim to "the component" can be understood to be equivalent to a reference to "at least one of the one or more components." Similarly, a subsequent reference to a component introduced as "one or more components" using the terms "the" or "said" can refer to any or all of the one or more components. For example, a subsequent reference in a claim to "the one or more components" can be understood to be equivalent to a reference to "at least one of the one or more components."

[0156] Computer-readable media includes both non-transitory computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media may be any available medium that can be accessed by a computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, Electrically Erasable Programmable Read-Only Memory (EEPROM), Compact Disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer or processor. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disc, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with a laser. Combinations of the above are also included within the scope of computer-readable media.

[0157] The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the embodiments and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. bonding a plurality of first semiconductor dies to a carrier, each of the first semiconductor dies comprising a respective portion of a circuit of a semiconductor unit; forming the semiconductor unit based at least in part on electrically connecting each of the plurality of first semiconductor dies to at least one other of the first semiconductor dies after bonding the plurality of first semiconductor dies to the carrier; bonding a respective set of one or more second semiconductor dies to at least one of the plurality of first semiconductor dies, each second semiconductor die of the respective set comprising a memory array, the memory array operable based at least in part on the respective portion of the circuit of the semiconductor unit of the first semiconductor die to which the respective set is bonded; A method comprising:

2. 10. The method of claim 1, wherein, for each of the first semiconductor dies, the respective portion of circuitry comprises a memory interface circuit, a memory controller circuit, a host controller circuit, a host processor circuit, or any combination thereof.

3. 10. The method of claim 1, wherein a first respective portion of a circuit on a first semiconductor die of the semiconductor unit is associated with a first logic function, and a second respective portion of a circuit on another first semiconductor die of the semiconductor unit is associated with a second logic function different from the first logic function.

4. 10. The method of claim 1, wherein the first respective set of one or more second semiconductor dies and the second respective set of one or more second semiconductor dies are included in a reconstructed wafer of second semiconductor dies bonded to the semiconductor unit.

5. 10. The method of claim 1, further comprising forming one or more dielectric materials between the plurality of first semiconductor dies at least along the carrier, the one or more dielectric materials separating respective substrates of the first semiconductor dies.

6. forming a plurality of first cavities through the one or more dielectric materials to a first depth, each of the first cavities contacting at least two of the first semiconductor dies; forming a plurality of second cavities through the one or more dielectric materials to a second depth, each of the second cavities passing through at least a portion of a respective one of the first semiconductor dies; forming a plurality of third cavities through the one or more dielectric materials to a third depth, each of the third cavities residing between the plurality of first semiconductor dies and contacting the carrier; simultaneously forming one or more conductive materials within the plurality of first cavities, the plurality of second cavities, and the plurality of third cavities; The method of claim 5 further comprising:

7. 7. The method of claim 6, further comprising forming one or more conductive pads, one or more conductive paths, and one or more vias in one or more second dielectric materials adjacent to the one or more conductive materials, wherein the one or more conductive pads, the one or more conductive paths, and the one or more vias are formed at least in part based on simultaneously forming one or more second conductive materials in cavities associated with the one or more conductive pads, the one or more conductive paths, and the one or more vias.

8. 10. The method of claim 1, further comprising forming one or more vias through one or more dielectric materials between the plurality of first semiconductor dies, each of the one or more vias being coupled to one of the set of one or more second semiconductor dies.

9. 9. The method of claim 8, wherein at least one of the one or more vias provides an interface between a respective set of the one or more second semiconductor dies and a surface of the semiconductor unit opposite the respective set of the one or more second semiconductor dies.

10. 9. The method of claim 8, further comprising forming one or more electrical contacts in each of the one or more vias based at least in part on forming a cavity through at least a portion of the carrier and forming one or more conductive materials in the cavity.

11. 10. The method of claim 1, wherein electrically connecting each of the plurality of first semiconductor dies is based at least in part on forming a plurality of conductive signal paths on the first semiconductor die of the semiconductor unit.

12. 12. The method of claim 11 , further comprising verifying that each first semiconductor die of the plurality of first semiconductor dies and each respective set of one or more second semiconductor dies meets an operational evaluation before bonding each respective set of one or more second semiconductor dies to the at least one of the plurality of first semiconductor dies.

13. 10. The method of claim 1, wherein bonding the respective set of one or more second semiconductor dies to the at least one of the plurality of first semiconductor dies is based at least in part on forming one or more vias through a substrate of the first semiconductor die to which the respective set is bonded.

14. 10. The method of claim 1, further comprising forming one or more electrical contacts on each of the first semiconductor dies based at least in part on forming a cavity through at least a portion of the carrier and forming one or more conductive materials in the cavity.

15. 10. The method of claim 1, wherein bonding the plurality of first semiconductor dies to the carrier comprises, for at least one first semiconductor die, bonding a side of the at least one semiconductor die opposite a substrate of the at least one semiconductor die to the carrier.

16. a carrier containing one or more material levels; a plurality of first semiconductor dies bonded to the carrier, each first semiconductor die including a respective substrate, the respective substrate being separated from the respective substrates of each of the other first semiconductor dies, and each first semiconductor die including a respective portion of a circuit of a semiconductor unit, the respective portion being electrically coupled to the respective portion of the circuit of the semiconductor unit of at least one other first semiconductor die; at least one set of one or more second semiconductor dies, each set of one or more second semiconductor dies electrically coupled to a respective first semiconductor die of the plurality of first semiconductor dies, each second semiconductor die including one or more memory arrays operable at least in part based on the respective first semiconductor die to which the second semiconductor die is connected; A system comprising:

17. 17. The system of claim 16, wherein, for each of the first semiconductor dies, the respective portion of circuitry comprises a memory interface circuit, a memory controller circuit, a host controller circuit, a host processor circuit, or any combination thereof.

18. 20. The system of claim 16, further comprising one or more dielectric portions of dielectric material between the respective substrates of the plurality of first semiconductor dies.

19. 20. The system of claim 18, further comprising: one or more vias passing through the dielectric portion between the plurality of first semiconductor dies, each of the one or more vias being coupled to one of the set of one or more second semiconductor dies and bypassing the plurality of first semiconductor dies.

20. 20. The system of claim 19, wherein at least one of the one or more vias provides an interface between the one of the set of one or more second semiconductor dies and a surface of the semiconductor unit opposite the respective set of one or more second semiconductor dies.

21. 17. The system of claim 16, further comprising: a redistribution layer including a plurality of conductive signal paths, each first semiconductor die electrically coupled to the at least one other first semiconductor die through the redistribution layer.

22. 17. The system of claim 16, further comprising: one or more vias formed through the respective substrate of at least one first semiconductor die of the plurality of first semiconductor dies, each via providing an interface between at least one set of the one or more second semiconductor dies and the respective first semiconductor die, an interface between the at least one first semiconductor die and at least one other first semiconductor die, or both.

23. 17. The system of claim 16, further comprising: a plurality of conductive pads on the plurality of first semiconductor dies, each of the plurality of conductive pads coupling a respective set of the one or more second semiconductor dies via the carrier to a power distribution network, through silicon vias of the plurality of first semiconductor dies, a redistribution layer above the plurality of first semiconductor dies, or any combination thereof.

24. one or more first electrical contacts present on a surface of the system and coupled to at least one first semiconductor die of the plurality of first semiconductor dies; one or more second electrical contacts present on the surface of the system, coupled to at least one set of the one or more second semiconductor dies, and bypassing the plurality of first semiconductor dies; The system of claim 16 further comprising:

25. 1. A system comprising a plurality of first semiconductor dies, the plurality of first semiconductor dies being electrically coupled to form a semiconductor unit of the system, the system further comprising: a dielectric material separating respective substrates associated with each of the plurality of first semiconductor dies; a redistribution layer including a plurality of conductive paths, the plurality of conductive paths electrically connecting each of the plurality of first semiconductor dies to at least one other first semiconductor die; one or more sets of second semiconductor dies, each second semiconductor die including a plurality of memory arrays; one or more bonding pads coupling each set of second semiconductor dies to a respective first semiconductor die of the plurality of first semiconductor dies; a plurality of vias extending through the dielectric material between the plurality of first semiconductor dies, each of the plurality of vias being coupled to at least one set of second semiconductor dies; The system comprising:

26. The redistribution layer is a first portion including one or more first conductive materials formed continuously along three depths relative to the thickness of the system; a second portion overlying the first portion, the second portion including one or more second conductive materials formed continuously along two depths relative to the thickness of the system; 26. The system of claim 25, comprising:

Images