Electrical switching device for generating a current-controlled electrical signal

Abstract

An electrical switching device for generating a current-controlled electrical signal for functional internal stimulation in the manner of a controlled cascode current mirror is described, comprising first, second, third, and fourth transistors each assigned a source terminal, a drain terminal, and a gate terminal, the second and fourth transistors being connected as an output cascode, the source terminal of the fourth transistor being connected to the drain terminal of the second transistor, and the drain terminal of the fourth transistor being connected to an output contact assignable to the electrical switching device, at which a voltage potential assigned to the current-controlled electrical signal can be tapped. The invention is characterized in that the gate terminal of the fourth transistor is switchably connected to at least one constantly assignable voltage potential.

Description

[Technical Field]

[0001] The present invention relates to an electrical switching device for generating a current-controlled electrical signal for functional internal stimulation in the form of a controlled cascode current mirror, comprising first, second, third and fourth transistors, each having a source, a drain and a gate terminal, the gate terminals of both the first and second transistors being connected to each other to form a current mirror, the third and first transistors being connected as an input cascode, the drain terminal of the third transistor being connected to the gate terminals of the first and second transistors, the source terminal being connected to the drain terminal of the first transistor, the gate terminal being connected to the output of an operational amplifier having at least two inputs, one input of which is connected to the drain terminal of the second transistor and the other input of which is connected to the source terminal of the third transistor, which is at the same potential as the drain terminal of the first transistor, the second and fourth transistors being connected as an output cascode, such that the source terminal of the fourth transistor is connected to the drain terminal of the second transistor and the drain terminal of the fourth transistor is connected to an output contact, and the electrical switching device can be assigned to provide at its output a voltage potential assigned to the current-controlled electrical signal. [Background technology]

[0002] Functional electrical simulation or neuronal stimulation (FES / FNS) is a method for treating various types of neurological dysfunction through the stimulation of nerves with an electrical charge. Applications range from cardiac pacemakers and corneal implants to peripheral nerve stimulators.

[0003] The known medical implant, the subject of EP 3204105 B1, used for site-selective recording of neuronal electrical signals propagating along at least one nerve fiber and for selectively electrically stimulating at least one nerve fiber, utilizes an electrode arrangement designed in the form of a cuff including multiple electrode contacts that directly contact the epineurium of a nerve fiber bundle, preferably the vagus nerve, for electrical signal transmission between the nerve fiber and the implant. It is a matter of electrically polarizing or activating each individual electrode contact in coordination with one another and for medical therapeutic or analytical purposes. To this end, the electrode contacts are each electrically connected to at least one stimulation channel, each of which can be connected to a separate output contact of an electrical switching device located on the implant side.

[0004] In principle, there are three possibilities for realizing a stimulation channel and, therefore, for the polarization of the individual electrodes: by means of voltage-, charge-, or current-based stimulation. These are physically related to each other, but represent different approaches to charge unloading, i.e., controlled by a voltage source, via capacitive discharge or via a current source. However, in the following, we will explain the principle of charge unloading by means of a current source, i.e., "current-controlled stimulation."

[0005] Therefore, since the metal electrode contact / electrolyte interface on the epineurium is characterized by the maximum allowable charge that can be transferred from each electrode contact to the biological tissue, it is important to control the charge applied locally to the epineurium via the electrode contact.

[0006] Therefore, in current-controlled stimulation, the pulse width t_w and the stimulation current amplitude l_stim can be controlled independently of impedance variations. In addition, when quadrature stimulation is used, the charge and current are connected together through Q=l_stim*t_w. However, it should be noted that for current-controlled stimulation, high load impedances require high voltages to achieve specific current levels, which necessitates the high-voltage tolerant CMOS process required for the development of application-specific integrated circuits (ASICs).

[0007] A current mirror is used as the current source for each simulation channel, forming a controllable current source with as high an output resistance as possible.

[0008] O. Charlon and W. Redman-White, in their paper "Ultra High-Compliance CMOS Current Mirrors for Low-Voltage Charge Pumps and References," September 2004, pp. 227-230, describe a possible architecture for such a current mirror. In addition to a series of current mirrors of varying complexity, FIG. 1 shows a known regulated cascode current mirror disclosed therein. This current mirror comprises first, second, third, and fourth transistors (T1, T2, T3, T4) each having a source terminal, a drain terminal, and a gate terminal assigned thereto. To form the current mirror, the gate terminals of the first and second transistors (T1, T2) are connected to each other and to an input potential (Vin) assignable to the cascode current mirror, and the third and first transistors (T3, T1) are connected as an input cascode. For this purpose, the drain terminal of the third transistor (T3) is connected to the input potential (Vin), its source terminal is connected to the drain terminal of the first transistor (T1), and its gate terminal is connected to the output (A) of the operational amplifier (OPA). The operational amplifier (OPA) has two inputs: one input (+) of the operational amplifier (OPA) is connected to the drain terminal of the second transistor (T2), and the other input (-) of the operational amplifier (OPA) is connected to the source terminal of the third transistor (T3) and the drain terminal of the first transistor (T1), which are at the same potential (Va). Furthermore, the source terminal of the fourth transistor (T4) is connected to the drain terminal of the second transistor (T2), its gate terminal is connected to the input potential (Vin), and its drain terminal is connected to an output contact (out), which can be connected to a voltage potential (Vout) assigned to the current control signal. Summary of the Invention

[0009] The object of the present invention is to further develop an electrical switching device for generating current control signals for functional internal stimulation in the form of a controlled cascode current mirror, so that the quality of the simulation channels that can be tapped off in the form of a current-controlled electrical signal on at least one output contact is improved compared to known switching topologies. Furthermore, in view of the scalability and combinability of the number of stimulation channels, the circuit structure must be designed to be as compact as possible, i.e., space-saving, yet versatile in terms of the various switchable connection possibilities between the stimulation channels and the output contacts connected to the electrode contacts.

[0010] The solution to the object forming the basis of the present invention is set out in claim 1. Features which advantageously develop the inventive concept form the subject of the dependent claims and the further description with reference to the drawings.

[0011] According to the introductory features of claim 1, the electrical switching device according to the invention for generating current-controlled electrical signals for functional internal stimulation in the form of controlled cascode current levels is characterized in that the gate terminal of the fourth transistor is switchably connected to successively addressable voltage potentials.

[0012] In contrast to the known switching device described at the beginning, in which the gate voltage of the fourth transistor is also controlled by the gate voltages of the first and second transistors, as illustrated in FIG. 1, according to the present solution the fourth transistor is always biased with a voltage which preferably originates from an external supply voltage source.

[0013] Basically, the higher the output resistance of a current source, the better. With this solution, the fourth transistor is not controlled, and the switching topology is equivalent to that of an input-controlled current mirror, but the output resistance increases significantly because of the inherent gain of the fourth transistor. Therefore, the output resistance of the drain terminal of the fourth transistor achievable with the switching topology according to the present invention is significantly higher than that of the known controlled fourth transistor shown in FIG. 1, whose gate terminal is connected to the gate terminals of the first and second transistors. Therefore, the electrical polarity of the drain terminal of the second transistor decreases to the extent that it changes from the operating region of the second transistor, i.e., the saturation region, to the linear region, where the transistor has a significantly lower output resistance than in the saturation region.

[0014] Further advantages of this switching topology solution relate to increased robustness against possible drain voltage fluctuations, since, on the one hand, the first and second transistors operate in strong inversion rather than in the linear region, and, on the other hand, the fourth transistor, with its constant gate voltage and isolated from the control circuit, acts as a buffer, which prevents undesired voltage fluctuations, especially at the drain terminal of the fourth transistor, which is directly connected to the electrode contact, from being directly noticeable in the current amplitude.

[0015] The fourth transistor acts as a static switch and therefore has a switching function. During operation, a supply voltage of, for example, 1.8 V is applied to the gate terminal. Therefore, depending on the switch position, a control or supply voltage of 0 V or 1.8 V is present on the fourth transistor.

[0016] It is advantageous to maximize the gate-source voltage when it is necessary to generate particularly high simulation currents, e.g., currents of 2 mA or more. Even with the smallest design for manufacturing the fourth transistor, preferably with the smallest width / length dimensions W / L=1-3 μm / 500 nm-1.3 μm, the maximum gate-source current can be large.

[0017] Preferably, a high-voltage protection transistor is arranged in series with the source-drain section of the fourth transistor to protect the entire electrical switching device from external high voltages between the output contact and the fourth transistor. This allows all other transistors, i.e., the first, second, third, and fourth transistors, to be designed as low-voltage transistors that can be controlled with voltages up to ±1.8 V, while the high-voltage transistor, according to the present invention, can operate with control voltages up to ±20 V, preferably ±18 V. Since the low-voltage transistors can be made smaller in size than the high-voltage transistors, this opens up the possibility of further miniaturization of the entire electrical switching device.

[0018] In addition to the first electrical switching device described above, a second switching device is provided that is inverted with respect to the first switching device and is capable of generating a current-controlled electrical signal that is inverted with respect to the current-controlled electrical signal of the first switching device. Like the first switching device, the second switching device also includes a fourth transistor connected to the output contact of the first switching device.

[0019] Due to the inverted switching topology of both switching devices relative to each other, one acts as a current source for realizing the positive stimulation channel and the other acts as a current sink for realizing the negative stimulation channel, for which both switching devices have the same structure but are implemented in each case with inverted transistor types (n-MOS; p-MOS).

[0020] Preferably, the current mirror of the electrical switching device designed according to the present solution, formed by the first and second transistors, is configured as an n-bit digital-to-analog converter, preferably a 5-bit digital-to-analog converter, each of which has 2 n -has one second transistor. 2 n- The drain terminals of the second transistors are each n - connected to the source terminal of one fourth transistor, the drain terminals of which are respectively connected to the output contacts of the electrical switching device.

[0021] In a further preferred embodiment, 2 n The drain terminals of one second transistor are connected or connectable to each other, so that those bits that are activated are always transferred through the appropriately connected drain terminals.

[0022] In a further preferred embodiment, there is the possibility of switching in each case one simulation channel to different or several output contacts and their connected electrode contacts, for example directly contacting the vagus nerve. For this purpose, a switch matrix is ​​used, which is connected on the one hand to the drain terminal of at least one fourth transistor of the electrical switching device and on the other hand to a plurality of m output contacts. For both protection against harmful power surges and reasons related to the desired reduction in component size, an additional high-voltage transistor is provided between each of the m output contacts and each fourth transistor that is part of the switch matrix. [Brief explanation of the drawings]

[0023] The invention will now be described by way of example, without limiting the general inventive concept, by way of example of embodiments, with reference to the drawings, in which: [Figure 1] 1 illustrates a known current mirror switching topology. [Figure 2] 1 shows a switching device designed according to the solution; [Figure 3] 1 shows another switching device; [Figure 4] 1 shows a schematic diagram of a switch matrix. DETAILED DESCRIPTION OF THE INVENTION

[0024] The above description is given to explain the known current mirror switching device shown in Figure 1. The switching device can be seen in Figure 9 shown in the article by O. Charlon et al. mentioned at the beginning.

[0025] The electrical switching device according to the solution shown in FIG. 2 also includes the first, second, third, and fourth transistors T1, T2, T3, and T4 already mentioned. The first and third transistors T1 and T3 are connected in series as a controlled input cascode, and the first and second transistors T1 and T2 are connected as a current mirror. To this end, the gate terminals of the first and second transistors T1 and T2 are connected to each other and to an input potential Vin applied to the input contact (in) of the switching device. A fourth transistor T4 is also added as an output cascode, with its source-drain section connected in series with the source-drain section of the second transistor T2. The fourth transistor T4 is supplied with a constant voltage VDD. The supply voltage VDD, typically 1.8 V, is switchably applied to the gate terminal of the fourth transistor T4.

[0026] Via a reference current source a basic current Iref is provided which can be scaled by means of a switching device according to the solution and tapped at the output from the switching device.

[0027] As shown in Figure 1, the third transistor T3 is connected to the output A or the operational amplifier OPA, and its output Vc controls the third transistor T3 in saturation operation. The operational amplifier OPA has two inputs, the positive input "+" of which is connected to a potential Vb applied between the second and fourth transistors T2 and T4 connected in series. The negative input "-" of the operational amplifier OPA is connected to a potential Va applied between the first transistor T1 and the third transistor T3 connected in series. is connected to

[0028] By controlling the third transistor T3 by the operational amplifier OPA, two control paths R1, R2 can be distinguished from one another within the switching device: the first control path R1 corresponds to the negative feedback of the supply voltage Va applied to the third transistor T3 via the negative input "-" of the operational amplifier OPA, and the second control path R2 relates to the positive feedback via the third, first and second transistors T3, T1 and T2 via the positive input "+" of the operational amplifier OPA. This concept of a controlled input cascode results in improved mirroring accuracy of the output current lout that can be tapped at the output.

[0029] The additional amplification provided by the operational amplifier OPA significantly increases the output resistance Rout at the output contacts, which is given by: Rout = A·Rds2·ggm4·Rds4 (where A is the amplification factor of the operational amplifier OPA, Rds2 = the small-signal resistance between the drain and source terminals of the second transistor, gm4 = the small-signal transconductance of T4, and Rds4 = the small-signal resistance between the drain and source terminals of the fourth transistor).

[0030] Furthermore, the third transistor T3 may be small in size, in particular smaller than the fourth transistor T4, so that the demands on the operational amplifier OPA for controlling the third transistor T3 are much smaller than in known switching concepts with a controlled output stage, i.e., a controlled fourth transistor T4 (see switching device in FIG. 1).

[0031] A further development of the electrical switching device shown in Figure 2 is the optional additional supervisory switching component CM, also known as compliance monitoring and indicated by the dashed line in Figure 2. The supervisory switching component CM detects irregular operating conditions of the electrical switching device, characterized by irregular voltage potentials that may form at certain nodal points of the switching device. For example, if the potential Vout available at the output of the switching device drops to a minimum potential within the switching device, an abnormal condition occurs in the switching device, causing a potential crossing, known as a "crossing", which must be detected.

[0032] The monitoring switching component CM shown in Figure 2 is a comparator K with two comparator inputs Ke1 and Ke2 and a comparator output Ka. The comparator input Ke1 is connected to the gate terminals of the first and second transistors (T1, T2) and thus to the input contact (in) of the switching device, at which the input potential Vin is present. In contrast, the comparator input Ke2 is connected to the potential Vc applied to the output (A) of the operational amplifier (OPA).

[0033] In a preferred application of the switching arrangement to generate current-controlled electrical signals for functional internal stimulation, the voltage potentials within the switching arrangement are selected so that during normal operation the input potential Vin is always less than the amplified voltage potential Vc selected by the operational amplifier OPA. Furthermore, during normal operation, all potentials on the switching nodes of the switching device ideally remain constant at their operating points.

[0034] However, if the operating point experiences a voltage shift from its normal state that exceeds the initial Vc-Vin voltage difference (preferably 140 mV), the switching circuit begins to lose reliability and accuracy. When Vin = Vc, a voltage equalization or voltage crossing occurs, which is a very suitable detection characteristic. Through circuit design, the moment when the voltage crossing, or "crossing," occurs can be determined in a defined manner, depending on how large the initial voltage difference between Vin and Vc is selected.

[0035] Depending on the potential difference between the input potential Vin and the potential Vc present at the output of the operational amplifier OPA, the comparator K generates a signal S which, as described above, acts as an alarm signal as soon as a critical operating condition is established.

[0036] The warning signal S can be used as a criterion for deactivating the switching operation of the switching device, or as a regulating or controlling parameter for matching the supply voltage VDD to the required output voltage Vout as part of power supply management. The supply voltage VDD of the switching device must always be slightly greater than the output voltage Vout that can be tapped at the output. However, the voltages VDD and Vout should not be chosen too differently to minimize power losses in the circuit. For this reason, so-called compliance monitoring is advantageous.

[0037] FIG. 3 shows an advantageously expanded switching arrangement, comprising a first switching arrangement I and a second switching arrangement II which are inverted mirror images of each other and which are connected to each other only by a respective fourth transistor T4 having at least one output contact.

[0038] It is assumed that the first switching arrangement I is used as a current sink for generating the negative stimulation channel and the second switching arrangement II is used as a current source for generating the positive stimulation channel. Both switching devices I and II are configured as mirror images, but each has an inverted transistor type, i.e., n-MOS transistors (T1, T2, T3, T4) in the case of the first switching arrangement I and p-MOS transistors (T1*, T2*, T3*, T4*) in the case of the second switching arrangement II. The first switching arrangement I operates in a lower voltage range, i.e., between voltage potentials vlvo and vlvi, than the second switching arrangement II, which operates between voltage potentials vhvo and vhvi.

[0039] Since the fourth transistors T4 and T4* each function as a switch, both switching devices can occupy at least one output contact with a positive or negative stimulus signal, preferably synchronized with each other. For this purpose, each fourth transistor T4 and T4* is connected to a static switching signal en bit_x The signal is controlled or switched by

[0040] The first and second transistors T1 or T1* and T2 or T2*, respectively wired as current mirrors IDAC,N and IDAC,P, constitute the stimulus channel and are implemented in the form of a 5-bit digital-to-analog converter (DAC). In this case, the first transistor T1 or T1* is 2 5 - connected to one second transistor T2 or T2* respectively.

[0041] For high-voltage protection, a high-voltage transistor THV or THV* is connected between the fourth transistor T4 or T4* and the output contact, respectively, to protect the switching device from external power surges. In this way, all other transistors can be designed as low-voltage transistors, which can be significantly smaller in size than the high-voltage transistors, thereby significantly miniaturizing the entire switching device. The high-voltage transistor THV or THV* is connected between the static switching signal en E_x It is also switched by, where en bit_x and en E_x are independent of each other. The switching signals En bit_x determines the magnitude of the current at the output out, and the switching signal en E_x selects the electrodes to be summed at the output out.

[0042] In a preferred optional embodiment of switching arrangements I and II, the first transistor T1 or T1* is connected to the respective second transistor T2 or T2* via a dynamic switch Sen. When switch Sen is closed, a source-drain current of 20 μA flows through the respective second transistor T2 or T2*. In addition, another second transistor T2hc or T2hc* is provided, which can be connected via switch Shc, if necessary. When switch Shc is closed, a source-drain current of 30 μA flows through the respective further second transistor T2hc or T2hc*, so that when switches Sen and Shc are closed simultaneously, a total current of 50 μA can be tapped at both drain outputs of the respective further second transistor T2 / T2hc or T2* / T2hc*. By combining all current paths in the 5-bit current mirror IDAC.P as well as IDAC.N, a maximum of (2 5 -1) A stimulation current of 50μm=1.55mA can be tapped at the output.

[0043] An additional highly dynamic switch Sha, which can provide faster or shorter switching times, constitutes a further option for expanding the functionality of the switching device, thereby achieving a steeper rising edge of the stimulation current. When switches Shs and Shc are closed simultaneously, switch Shs ensures that at least the slowdown in the current rise time caused by the multiple transistors (T2+T2hc or T2*+T2hc) is compensated for.

[0044] For the sake of completeness, it is noted here that in switching arrangements I and II, for monitoring purposes, a monitoring switching component CM as described in connection with FIG. 2 may be added in each case.

[0045] In order to enable the stimulation currents that can be drawn from the output to be switched jointly or individually to multiple or different output contacts and ultimately to the electrode contacts, the switching device has a switch matrix sw_matrix, which is shown schematically and in more detail in Figure 4.

[0046] Figure 4 shows the switch matrix sw_matrix connecting k=8 stimulation channels to m output contacts, each of which can be tapped and applied directly to an organic structure, for example on the vagus nerve, by an electrode contact.

[0047] To present and implement the stimulation channels, switching arrangements such as those shown in Figure 3, Switching Arrangements I and II, are required.

[0048] Shown in Figure 4 is a switch matrix capable of electrically connecting m=12 output contacts with k=8 stimulation channels. For each first and second switching arrangement I and II, for each stimulation channel k, k first and third transistors T1, T3 and k·(2 n−1) second transistors (n=5, i.e., 5 bits) are required for each. In Figure 4, the schematic diagram of the individual stimulus channels k of switching arrangement II is omitted, since it has the same configuration as switching arrangement I. To connect k=8 stimulation channels to m=12 output connectors in an additionally activatable manner, k·(2 n -1) second transistors T2 are connected to m=12 output contacts out, i.e., m k (2 n m=1) fourth transistors T4 are required. The drain terminals of all fourth transistors T4 are in turn connected to one electrical drain, which is connected to one of the m=12 output channels. To ensure high-voltage protection against external power surges as described above, a high-voltage transistor THV is placed alongside each individual electrical drain. This means that only m=12 high-voltage transistors THV are required per switching arrangement I or II to protect all other transistors from power surges. In contrast to the high-voltage transistors THV, the latter can be much smaller in size, allowing the entire switching device to be designed in a miniaturized manner. [Explanation of symbols]

[0049] T1, T2, T3, T4 First, second, third and fourth transistors T1*, T2*, T3*, T4* First, second, third and fourth transistors in Input contact out Output contact OPA Operational Amplifier V DD Supply voltage V in Input voltage m Number of output contacts k number of stimulation channels n-bit DAC T hc Further second transistor T HVHigh Voltage Transistors S hc switch S en switch A operational amplifier output CM Monitoring Switching Components K comparator Ke1 comparator input Ke2 comparator input Ka comparator output S signal

Claims

1. 1. An electrical switching device for generating current-controlled electrical signals for functional internal stimulation in the form of a controlled cascode current mirror, comprising: first, second, third and fourth transistors (T1, T2, T3, T4) assigned source, drain and gate terminals; The gate terminals of the first transistor and the second transistor (T1, T2) are connected to each other to form a current mirror; the drain terminals of the third transistor and the first transistor (T3, T1) are connected as an input cascode; the drain terminal of the third transistor (T3) is connected to the gate terminals of the first transistor and the second transistor (T1, T2), the source terminal of the third transistor is connected to the drain terminal of the first transistor (T1), and the gate terminal of the third transistor is connected to an output (A) of an operational amplifier (OPA) having at least two inputs; One input (+) of the operational amplifier (OPA) is connected to the drain terminal of the second transistor, and the other input (-) of the operational amplifier (OPV) is connected to the source terminal of the third transistor and the drain terminal of the first transistor (T1), which are at the same potential (Va); the second transistor and the fourth transistor (T2, T4) are connected as an output cascode, such that the source terminal of the fourth transistor (T4) is connected to the drain terminal of the second transistor (T2) and the drain terminal of the fourth transistor (T4) is connected to an output contact (out) assignable to the electrical switching device; At the output contact, a voltage potential (Vout) assigned to the current control electrical signal can be taken off; the gate terminal of the fourth transistor (T4) is switchably connected to at least one constantly addressable voltage potential; Electrical switching devices.

2. 2. The electrical switching device of claim 1, wherein the voltage potential always addressable at the gate terminal of the fourth transistor (T4) comes from an external power supply voltage source (VDD) or corresponds to the voltage potential (VSS) at the source terminals of the first and second transistors (T1, T2), respectively.

3. a high voltage protection transistor (THV) disposed between the output contact (out) and the fourth transistor (T4) and connected in series with its source-drain section; In contrast to the high voltage transistor (THV), the fourth transistor (T4) is in the form of a low voltage transistor.

3. An electrical switching device according to claim 1 or 2.

4. 4. An electrical switching device according to claim 3, wherein said low voltage transistor (T4) is designed for a drain voltage of up to ±2V and said high voltage transistor (THV) is designed for a drain voltage of up to ±18V.

5. 5. The electrical switching device of claim 4, wherein the first transistor, the second transistor, and the third transistor are each designed as a low voltage transistor.

6. The current mirror formed by the first transistor and the second transistor (T1, T2) is constructed as an n-bit digital-to-analog converter, ｎ - one second transistor (T2), 2. ｎ The drain terminals of the second transistors (T2) are each ｎ - connected to the source terminal of one of the fourth transistors (T4), ｎ the drain terminal of each of the fourth transistors (T4) is connected or connectable to an output contact (out) of the electrical switching device; 6. An electrical switching device according to any one of claims 1 to 5.

7. 7. The electrical switching device according to claim 1, wherein the output contact (out) is connected to the drain terminal of a second, fourth transistor (T4*) that is part of a second electrical switching device (II) identical to the first electrical switching device (I) of claim 1, and wherein the second electrical switching device (II) is capable of generating a current control electrical signal that is inverted relative to the current control electrical signal of the first electrical switching device (I).

8. 8. An electrical switching device comprising k stimulation channels with current-controlled electrical signals for functional internal stimulation comprising k electrical switching devices according to any one of claims 1 to 7, wherein the drain terminal of each fourth transistor (T4) is connected to m output contacts (out) via a switch matrix.

9. 9. The electrical switching device of claim 8, wherein in the switch matrix, the m output contacts (out) are each connected to the drain connection of a respective one of the fourth transistors (T4) via one high voltage transistor (THV).

10. 10. An electrical switching device according to claim 1, further comprising a monitoring switching component configured to exclusively capture internal switching potentials of the electrical switching device and generate a signal in the event of an unacceptable operating condition of the electrical switching device.

11. said supervisory switching component being in the form of a comparator having two comparator inputs and one comparator output from which said signal can be derived; A potential is applied to the gate terminals of the first and second transistors (T1, T2) at one of the two comparator inputs, and a potential of the output (A) of the operational amplifier (OPA) is applied to the other of the two comparator inputs.

11. The electrical switching device of claim 10.

12. 12. An electrical switching device according to any one of claims 1 to 11, wherein the gate terminals of the first and second transistors (T1, T2) are connected to each other and to an input potential (Vin) of the electrical switching device.

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