Scalable qubit biasing device based on multiplexed charge storage

Abstract

Disclosed are embodiments including semiconductor device circuits for biasing gates of qubit devices and methods for operating the devices. The embodiments may include a multiplexed array of capacitor cells, where each capacitor cell includes a transistor-controlled capacitor, each capacitor connected between the drain of the respective transistor and ground, where the sources of all transistors of all capacitor cells are connected to a common control point, and where the gates of each transistor of the capacitor cells are individually voltage-controllable. The embodiments may include a charging unit connected to the common control point and a discharging unit connected to the common control point, where the charging unit and the discharging unit are alternately activatable.

Description

[Background technology]

[0001] This application relates generally to semiconductor device circuits, and more particularly to semiconductor device circuits for biasing gates of qubit devices. This application also relates to methods for operating semiconductor device circuits for biasing gates of qubit devices.

[0002] Quantum computing continues to be one of the hottest topics in the physical sciences, industry, and research. Classical digital computers and / or processors are gradually reaching their physical limits, leading researchers to explore new ways to address mathematical and other problems that cannot be solved by classical von Neumann machines due to physical limitations in terms of structural size, power consumption, and ultimately processing speed. Commercial companies are also interested in new computing options.

[0003] Quantum computing is therefore one of the promising areas for achieving quantum supremacy, i.e., a substantial advantage in addressing highly complex calculations or tasks in a reasonable amount of time. As is well known, conventional computers encode process information into bits, i.e., "1" and "0." Quantum computers, on the other hand, are based on so-called qubits, which operate through two key principles of quantum physics: superposition and entanglement. Superposition refers to the situation in which each qubit can represent both a 1 and a 0 inference between possible outcomes for an event. Entanglement means that superposed qubits can correlate with each other in a non-classical way, i.e., the state of one qubit, whether it be a 1, a 0, or both, can depend on the state of another qubit, and that more information is contained in a qubit when it is entangled compared to a single qubit. Summary of the Invention

[0004] According to one aspect of the invention, a semiconductor device circuit for a biasing gate of a qubit device may be provided. The semiconductor device circuit may include a multiplexed array of capacitor cells, whereby the following may apply to the array of capacitor cells: each capacitor cell may include a transistor-controlled capacitor, each capacitor may be connected between the drain of a respective transistor and ground, each source of all transistors of all capacitor cells may be connected to a common control point, and each gate of the transistors of a capacitor cell may be individually voltage-controllable.

[0005] Furthermore, the semiconductor device circuit may include a charging unit connected to a common control point and a discharging unit connected to the common control point, where the charging unit and the discharging unit are alternately activatable.

[0006] According to another aspect of the invention, a method for operating a semiconductor device circuit for a biasing gate of a qubit device may be provided. The method may include providing a semiconductor device circuit including a multiplexed array of capacitor cells. The multiplexed array of capacitor cells may include: each capacitor cell may include a transistor-controlled capacitor, each capacitor may be connected between a drain of a respective transistor and ground, respective sources of all transistors of all capacitor cells may be connected to a common control point, and respective gates of the transistors of the capacitor cells may be individually voltage-controllable. [Brief explanation of the drawings]

[0007] It should be noted that embodiments of the present invention are described with reference to different subject matters. In particular, some embodiments are described with reference to method-type claims, while other embodiments are described with reference to device-type claims. However, a person skilled in the art will infer from the above and below that, unless otherwise stated, any combination of features belonging to one type of subject matter, as well as any combination between features relating to different subject matters, in particular between features of method-type claims and features of device-type claims, is considered to be disclosed within this specification.

[0008] The aspects defined below will be apparent from and elucidated with reference to the example embodiments described hereinafter, to which the invention is not limited.

[0009] Preferred embodiments of the present invention will now be described, by way of example only, with reference to the following drawings, in which:

[0010] [Figure 1] FIG. 1 shows a block diagram of one embodiment of a semiconductor device circuit of the present invention for a biasing gate of a qubit device.

[0011] [Figure 2] 2 shows a diagram including the block diagram of FIG. 1 in the context of a current-driven biasing circuit.

[0012] [Figure 3] 3a and 3b show diagrams in which different gate voltages VG1, VG2 and VG3 of different capacitor cells are activated and the corresponding output voltage diagrams.

[0013] [Figure 4] The activation voltage VG1 is shown during a particular amount of time, twrite.

[0014] [Figure 5] 4 shows another diagram with different write periods.

[0015] [Figure 6] 10 shows a signal flow diagram of an exemplary control algorithm for a two-output exemplary embodiment.

[0016] [Figure 7] A more complete example of voltage-driven biasing is shown.

[0017] [Figure 8] 1 shows another voltage-driven biasing circuit using a DAC.

[0018] [Figure 9] 1 shows a further current-driven biasing circuit using a DAC.

[0019] [Figure 10] 1 shows a flowchart illustrating a process for operating a semiconductor device circuit for a biasing gate of a qubit device, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] Although detailed embodiments of the claimed structures and methods are disclosed herein, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. However, the present disclosure may be embodied in many different forms and should not be considered limited to the exemplary embodiments described herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0021] In the context of this description, the following technical phrases, terms and / or expressions may be used:

[0022] The term "biasing gate" may refer to a component of a qubit device that defines the confinement for the state of an active particle.

[0023] The term "qubit device" may refer to a physical device that currently operates in a temperature range typically below or much lower than 4 K to manipulate the physical states of elementary particles to enable quantum computing.

[0024] The term "capacitor cell" may refer to a component of the proposed concept, including a transistor and a capacitor, where the drain of the transistor is connected to the capacitor. The source of the transistor may be the input of the capacitor cell, and the common point between the drain of the transistor and the capacitor may be the output of the capacitor cell. Through the gate of the transistor, the capacitor cell may be controlled. Thus, the capacitor cell may include a transistor-controlled capacitor.

[0025] The term "array of capacitor cells" may refer to a plurality of capacitor cells that may be activated in a multiplexed manner. Furthermore, all capacitor cells of the array may be connected to a common control point, i.e., via the sources of the transistors of the capacitor cells.

[0026] The term "common control point" may refer to an electrical contact point to which all inputs of all capacitor cells and outputs of the charge and discharge units may be connected.

[0027] The term "individually voltage controllable" may refer to the fact that the output of each of the multiple capacitor cells can have a different voltage level (or current).

[0028] The term "charging unit" may refer to a single unit using transistors in the proposed semiconductor device circuitry that is used to control the input of supply voltage for each capacitor cell.

[0029] The term "discharge unit" may refer to a circuit using another transistor that may be activated at a time when the charge unit may be deactivated to discharge one of the capacitors of one of the capacitor cells.

[0030] The term "alternately activatable" may refer to that only one of the two charging and discharging units can be activated at the same time.

[0031] The term "first control voltage" may refer to a control signal for controlling the gate of a transistor of a charging unit.

[0032] The term "second control voltage" may refer to a control signal for controlling the gate of the transistor of the discharge unit and thus determining whether current flows through the source / drain channel of each transistor. The second control voltage may be used in the voltage drive mode.

[0033] The term "third control voltage" may refer to a control signal for controlling the gates of the transistors of the discharge unit and thus determining whether current flows from the source to the drain of the respective transistor. The third control voltage may be used in a current drive mode in which current to ground may be measured.

[0034] The term "semi-constant" may refer to the fact that the voltage, particularly the output of a capacitor cell, can be kept within a predefined tolerance range between an upper and lower voltage level.

[0035] The term "time-based activation" may refer to the fact that an activation signal may be periodically supplied to the unit to be controlled.

[0036] The term "control gate of a qubit device" may refer to a component of a qubit device that is required for confinement of the active components of the qubit device. Typically, a qubit device may include two or four control gates.

[0037] As previously discussed, quantum computing continues to be one of the hottest topics in the physical sciences, industry, and research. Classical digital computers and / or processors are gradually reaching their physical limits, leading researchers to seek new ways to address mathematical and other problems that cannot be solved by classical von Neumann machines due to physical limitations in terms of structural size, power consumption, and ultimately processing speed. Commercial enterprises are also interested in new computing options.

[0038] However, reaching quantum supremacy—the ability to use quantum computing to solve problems fundamentally unsolvable using classical computing systems—requires a relatively large number of error-free, basic quantum devices (possibly with error-correction mechanisms). Furthermore, quantum devices are operated at very low temperatures in cryostats. Three temperature ranges are typically used: (i) room temperature, i.e., approximately 300 K; (ii) 3 K–4 K; and (iii) the temperature level at which quantum devices / quantum chips are actually operated, i.e., approximately 10 mK. Furthermore, nearly all control electronics are operated at room temperature. Meanwhile, many quantum devices, particularly those mentioned above, all require control, signal-detection, and input lines. Thus, for n qubits, at least 2n coaxial cables—one for signal control, one for biasing signals, and one or less for readout—can be expected to extend from room temperature to the 10 mK region where n qubit devices are operated. For newer qubit devices, the total number of signal lines may be even larger. This presents substantial challenges and obstacles. This is because a typical coaxial cable requires a certain diameter, which also effectively imposes a physical limit.

[0039] Therefore, 1000-qubit machines require a new level of control and require management of different signal levels, which promises higher density, improved scalability, reduced power consumption, and relatively low cost for integrated electronics implemented in advanced CMOS nodes that can be operated in the 3-4K temperature range.

[0040] However, current approaches have their limitations. DACs (digital-to-analog converters) can operate at 3K but lack the more comprehensive closed-loop control and feedback circuitry or SRAM for storing DAC patterns. In other cases, it is necessary to provide a reference clock signal externally, i.e., from a waveform generator at room temperature. In still other cases, noise from the CMOS chip used can disturb the quantum state of the qubit device or can disturb the readout signal if it is driven all the way to room temperature without being digitized.

[0041] In certain designs, such as quantum dot qubit devices, more control lines may be needed to constrain the qubit degrees of freedom and force them into a frozen state, which may require more control and / or signal lines from room temperature to the qubit chip.

[0042] By way of example, reference should be made to document US 2019 / 0164959 A1, which describes a quantum integrated circuit assembly comprising a quantum circuit component having a plurality of qubits and control logic coupled to the quantum circuit component and configured to control the operation of said component, wherein the quantum circuit component and the control logic are provided on a single die. The specification also describes a method for producing such an assembly.

[0043] Furthermore, the following publication from Delft University of Technology should be mentioned: "Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing" by Luc Enthofen et al., DOI: https: / / doi.org / 10.1109 / VLSITechnologyandCir46769.2022.9830309, published in 2022, also published in the 2022 IEEE Symposium on VLSI Technology and Circuits, Proceedings of the VLSI Technology and Circuits conference. This paper presents a 15b cryo-CMOS DAC for multiplexed spin qubit biasing implemented in a 22nm FinFET process. The integrated DAC architecture and the digitally assisted robust high-voltage output stage result in low power dissipation (157μW) and small area (0.08mm), independent of the number of qubits being biased. 2 ) allowing for a 3V output range well beyond the nominal supply.

[0044] However, the problem of too many control signals and cables that may need to be routed from room temperature to the operating temperature of a quantum chip remains, thereby creating a need for a simple, cost-effective, yet powerful device for controlling the gate biasing of large numbers of qubit devices.

[0045] Therefore, semiconductor devices for biasing gates of qubit devices are highly desirable. Embodiments described herein that include semiconductor device circuitry for biasing gates of qubit devices may include a multiplexed array of capacitor cells, whereby the following may apply to the array of capacitor cells: each capacitor cell may include a transistor-controlled capacitor, each capacitor may be connected between the drain of a respective transistor and ground, each source of all transistors of all capacitor cells may be connected to a common control point, and each gate of the transistors of a capacitor cell may be individually voltage-controllable.

[0046] Furthermore, the semiconductor device circuit may include a charging unit connected to a common control point and a discharging unit connected to the common control point, where the charging unit and the discharging unit are alternately activatable.

[0047] According to another aspect of the invention, a method for operating a semiconductor device circuit for a biasing gate of a qubit device may be provided. The method may include providing a semiconductor device circuit including a multiplexed array of capacitor cells. The multiplexed array of capacitor cells may include: each capacitor cell may include a transistor-controlled capacitor, each capacitor may be connected between a drain of a respective transistor and ground, respective sources of all transistors of all capacitor cells may be connected to a common control point, and respective gates of the transistors of the capacitor cells may be individually voltage-controllable.

[0048] Furthermore, the embodiments of the semiconductor device circuit described herein may include a charging unit connected to a common control point and a discharging unit connected to the common control point, where the charging unit and the discharging unit may be alternately activatable.

[0049] Additionally, methods described herein for utilizing exemplary embodiments including semiconductor device circuitry may include selectively activating, on a time basis, one of the capacitor cells of the multiplexed array of capacitor cells.

[0050] The proposed semiconductor device circuit for biasing gates of qubit devices may provide multiple advantages, technical effects, contributions, and / or improvements.

[0051] The proposed semiconductor device circuit may address the problem of not yet being able to scale the external electronics of quantum computers very well. The proposed solution may also enable much better form factors and cost reductions, i.e., reduced heat load on cooling equipment for racks of AWGs (quantum arbitrary waveform generators), and reduced overall power consumption. This may be achieved by much better scaling of DC current and voltage signals, particularly for electrostatic control of spin qubit devices, and multiplexing control of current (e.g., magnetic flux control) for superconducting qubits. Furthermore, it may ease the path to new qubit device variants that may require many more control lines compared to today's qubit devices.

[0052] The proposed circuit may be capable of taking digital signals and DC voltages as inputs and producing a variety of different voltages or currents as outputs in a multiplexed manner. This may make the circuit suitable for scalably generating the DC control signals needed for spin and superconducting qubits, meaning that significantly fewer input signals and cables are needed to control the qubit functionality. In particular, because multiplexing occurs in the temperature range of 3K-4K, but not at room temperature, the circuit may be fully capable of controlling a large number of biasing gates in a qubit device.

[0053] Quasi-constant voltage or current multiplexing may be achieved by refreshing the capacitor cells of the circuit, which may allow different voltage levels for each addressed biasing gate. Due to the large discharge time of the capacitor compared to the required charging time, the on / off ratio may be as low as 10 4 ~10 6 As a result, hundreds or even thousands of gates may be controllable with just one circuit. This may reduce the amount of equipment required, e.g., cabling from room temperature to the temperature level of the qubit device, and the complexity of operation.

[0054] The combination of localized charge storage, i.e., the capacitors of the capacitor cells, and multiplexed charge refresh operations may enable these benefits: the ability to generate multiple quasi-static DC signals for controlling the gates of qubit devices. By controlling three charge refresh time constants (described in more detail below), it is possible to obtain DC signal level control using only one digital control signal. This type of signal generation may be well suited to be tightly integrated with qubit devices to provide the necessary DC control signals. Thus, compared to other approaches, such as those using DACs (digital analog converters), the proposed concept may be much more energy-efficient and compact for generating multiple quasi-DC levels.

[0055] Furthermore, quasi-constant voltage or current levels may be achieved in two ways: (i) by varying the duty cycle of the control signal to the transistor of the capacitor cell while keeping the frequency constant, or (ii) by varying the frequency of the control signal itself while keeping the duty cycle constant. This may also contribute to the flexibility of the proposed concept. Controlling the frequency is particularly attractive because it can be done through a relatively simple circuit, namely, a voltage-controlled oscillator. In this sense, a single voltage-controlled oscillator, together with the control logic and the proposed invention, may control the generation of a large number of DC qubit biasing levels. This is a significantly more efficient solution in terms of power and complexity compared to today's standard approaches.

[0056] Below, further embodiments of the inventive concepts are described that are largely applicable to semiconductor device circuits and methods.

[0057] According to one embodiment of the semiconductor device circuit described herein, the charging unit may include a transistor, the drain of which may be connected to a common control point and the source of which may be connected to a supply voltage, e.g., V dd and its gate may be connectable to a first control voltage for activation of the charging unit. The transistor may therefore be operable in a typical switching mode, which may depend on the first control voltage, i.e., the source / drain line may be either in an open state or a closed state controlled by the gate voltage.

[0058] According to another described embodiment of the semiconductor device circuit described herein, in particular the discharge unit in the voltage-driven mode may include a transistor, the drain of which may be connected to a common control point, the source of which may be connected to ground via a resistor, and the gate of which may be connectable to a second control voltage for activation of the discharge unit. This may allow measurement of the amount of charge, i.e., the voltage that can be stored in the capacitor of a selected one of the capacitor cells. This mode of operation may be denoted as a voltage-driven mode.

[0059] According to yet another embodiment of the semiconductor device circuit described herein, the discharge unit, particularly in the current drive mode, may include a transistor, the drain of which may be connected to a common control point, the source of which may be connected to ground via a current measurement unit, and the gate of which may be connectable to a second control voltage for activation of the discharge unit. Measurement may be performed using a voltage drop across a resistor (i.e., the current measurement unit). This mode of operation may be denoted as a current drive mode.

[0060] According to another embodiment of the semiconductor device circuit described herein, the voltage level at the drain of the transistor of the capacitor cell may be kept semi-constant by time-based activation of the gate of the transistor of each capacitor cell, i.e., successive reactivation at a constant frequency. The drain of the transistor may thereby be coupled to one connector of the capacitor (while the other contact point of the capacitor is connected, for example, to ground) and to the qubit gate. Since only leakage current may flow, "semi-constant" may equate to a capacitor loss from one of the following ranges of time-based activation cycles: less than 5%, less than 3%, or less than 2%, with less than 1% being feasible.

[0061] In other embodiments, the circuitry may be adapted to be operable in a 3K environment, approximately 3K / 4K representing the temperature range in which typical control units and control logic may operate to control the operation of qubit devices and / or qubit chips that may be operated over a 10mK temperature range.

[0062] According to another embodiment of the semiconductor device circuit, the signal level at the drain of the transistor of the capacitor cell may represent a bias voltage level for the control gate of the qubit device. Thus, the drain contact of the transistor of the capacitor cell may be in electrical contact with the control gate of the qubit device. No additional electrical components may be required. This is therefore a very straightforward and technically neat solution for controlling larger numbers of biasing gates of qubit devices without the requirement for coaxial cables to reach room temperature.

[0063] According to another embodiment of the semiconductor device circuit described herein, the discharge time of the capacitor of the capacitor cell may be at least 1000 times longer than the charge time. This may depend on the load and leakage current. However, experiments have shown that up to 1,000,000 times should be possible.

[0064] According to another embodiment of the semiconductor device circuit described herein, each transistor in the circuit is of the n-enhancement type, which is relatively easy to fabricate and can operate in a temperature range of 3K / 4K.

[0065] According to further possible embodiments, the semiconductor device circuits described herein, and in particular the capacitor cells, may also include resistors in parallel with the capacitors of the capacitor cells, which may enable the generation of controlled discharge currents, e.g., flux control, that may be used to change superconducting qubit properties due to magnetic fields that the current flow may create.

[0066] Regarding the proposed exemplary method, the following further embodiments may contribute to the advantages of the proposed concept.

[0067] According to one embodiment, the method may also include activating the charging unit by connecting a gate of the transistor of the charging unit to a first control voltage. The source of the transistor of the charging unit may be connected to a supply voltage, and the drain of the transistor of the charging unit may be connected to a common control point. In an embodiment, the method may further include deactivating the discharging unit by connecting a gate of the transistor of the discharging unit to ground. Thus, a controlled electric field at one or more qubit gates or biasing gates of the chip may be achieved by selecting respective capacitor cells and activating the charging unit.

[0068] According to another embodiment, the method may also include periodically activating one of the capacitor cells of the array of capacitor cells, i.e., using a fixed frequency, by applying a recharge voltage to the gate of the transistor of each capacitor cell, thereby achieving a quasi-constant voltage level at the drain of the transistor of one capacitor cell. In this way, multiplexing for multiple capacitor cells, and thus multiplexing for multiple biasing gates of a qubit device, may be achieved.

[0069] According to another embodiment, the method may further include activating capacitor cells of the array of capacitor cells other than the one of the capacitor cells periodically, i.e., again using a fixed frequency, thereby achieving, for example, other quasi-constant voltage levels at the drains of the transistors of the other capacitor cells. In combination with the subject matter described in the above paragraph, different capacitor cells may be activated, for example, in a round-robin manner. Furthermore, if more capacitor cells may be available, they may be activated in a more versatile multiplexed manner.

[0070] According to yet another embodiment, the method may also comprise a step of controlling the frequency of activation of one of the capacitor cells, in particular in the sense of varying, increasing / decreasing, the frequency of activation, while keeping the duration of activation constant, in particular within the period of activation, so that a quasi-constant voltage level, possibly also of another level, can be affected at the drain of the transistor of the other capacitor cell. Thus, the quasi-constant voltage level at the output of the capacitor cell can be affected by the activation time, i.e. the activation voltage at the gate of the transistor of the capacitor cell, or by the activation frequency.

[0071] According to another embodiment, the method may also include activating the discharge unit by connecting the gate of the transistor of the discharge unit to a second control voltage. Furthermore, the drain of the transistor of the discharge unit may be connected to a common control point. Furthermore, the charging unit may be simultaneously deactivated, for example, by connecting the gate of the transistor of the charging unit to ground. The discharging effect may be achieved by connecting the source of the transistor of the charging unit to ground via a discharge unit resistor and connecting the drain of the transistor of the charging unit to the common control point. It may be understood that either the charging unit or the discharging unit may be activated to prevent the creation of some kind of short circuit.

[0072] According to another embodiment, the method may also include measuring the voltage across the discharge unit resistor, whereby the voltage level of the capacitor of the capacitor cell may be measured, which may allow the amount of charge stored on the capacitor to be determined.

[0073] According to an alternative embodiment, the method may also include connecting an output resistor in parallel with the capacitor of the capacitor cell and periodically activating one of the capacitor cells of the array of capacitor cells, thereby applying a periodic current, which may again be quasi-constant, through the output resistor. This type of circuit operation may be denoted as a current-driven biasing mode, which may be used, for example, for qubit flux control, where the current implies a magnetic field that may affect the superconducting qubit device. It may also be noted that the method embodiments above in this paragraph may describe voltage-driven biasing or a voltage-driven biasing circuit.

[0074] A detailed description of the figures follows. All instructions in the figures are schematic. First, a block diagram of one embodiment of a semiconductor device circuit for a biasing gate of a qubit device of the present invention is given. Afterwards, further embodiments and embodiments of a method for operating a semiconductor device circuit for a biasing gate of a qubit device are described.

[0075] 1 shows a block diagram of a preferred embodiment of a semiconductor device circuit 100 for biasing gates of a qubit device. FIG. 1 illustrates an exemplary voltage-driven biasing circuit. The semiconductor device circuit 100 includes a multiplexed or multiplexable array of capacitor cells 102-108, whereby each capacitor cell 102-108 is coupled to a respective transistor T1-T2. n Transistor control capacitors C1 to C2 connected between the drains of the transistors and ground n The shared point between the transistor and the capacitor of the capacitor cell may also be the contact point for the biasing gate of the qubit device.

[0076] Furthermore, all the transistors T1 to T2 of all the capacitor cells 102 to 108 n The sources of the transistors T1 to T2 of the capacitor cells are connected to a common control point 111. nThe gates of each of the charge unit 110 and the capacitor cell are individually voltage controllable. Gi (i=1~n) to selectively activate the output terminal V Oi (i=1 to n) can be selectively activated with a predefined amount of charge to generate a predefined quasi-constant voltage level across the capacitors of the capacitor cells. To this end, the charging units 110 are beneficially connected to a common control point 111.

[0077] In an embodiment, to operate the semiconductor device circuit in another mode, the discharging unit 112 connected to the common control point 111 is turned on when the charging unit 110 is deactivated, i.e., the transistor T CH Instead, transistor T DIS The gate of the discharge unit transistor T DIS The source of is the measuring resistor R m A voltage measurement unit (e.g., a voltmeter) is used to measure the voltage across the capacitor C1 and its time characteristics, i.e., the voltage across each capacitor C i It is possible to measure its behavior when discharging. To achieve this, the gate of the capacitor cell should also be activated by a control voltage.

[0078] To implement these two operating modes, the charging unit and the discharging unit can be activated alternately; that is, only the charging unit or (exclusively) the discharging unit can be activated.

[0079] FIG. 1 illustrates an exemplary embodiment including a voltage-driven biasing circuit, where V O1 ~V On are activated sequentially, i.e., one at a time, i.e., in multiplexed mode.

[0080] 2 shows a diagram 200 including the same three building blocks already discussed in the context of FIG. 1: a plurality of capacitor cells 102-108, a charging unit 110, and a (slightly modified) discharging unit 202. However, in this embodiment, a current-driven biasing circuit is implemented with a modified discharging unit 202. In comparison to the discharging unit 112 (compare FIG. 1), a current measuring unit, e.g., an ammeter, is connected to the transistor T DIS A current-driven biasing circuit is implemented by connecting between the sources of the discharge transistors.

[0081] Furthermore, each resistor R i (i=1 to n) represents the capacitors C of the respective capacitor cells 102 to 108. i are connected in parallel, and each current I OI In this mode of operation, i.e., current-driven mode, the voltage controller uses multiple V1 to V2 voltages (compared to reference numeral 704 in FIGS. 7 and 8) to activate multiple (or all) capacitor cells. n are controlled in parallel (not sequentially as in the voltage drive mode).

[0082] FIG. 3a shows the gate voltages V of different capacitor cells at different time periods t1, t2, and t3. G1 ,V G2 , and V G3 is activated, whereby the Y-axis corresponds to the voltage level of the gate control signal and the X-axis represents time.

[0083] Correspondingly, Figure 3b shows a diagram 302 representing the corresponding output signals of the capacitor cells, in particular on the Y axis, where the X axis again represents time. During a first period T1, the voltage level V of the respective output signal (measured) O1 is higher than T2 and T3 for a shorter period, and V O1 >V O2 >V O3It can be seen that Figure 3b in particular should be seen as the basis for understanding the subsequent figures.

[0084] Figure 4 shows the write The activation voltage V over a period of time denoted as G1 4 shows a diagram 400 representing the gate signal V G1 is active at the gate of the transistor of each capacitor cell, the output signal V O1 Then, at time t rest During this time, the output signal V O1 decreases mainly due to leakage current, and eventually, at time t refrech During this time, the refresh signal is reactivated at the gate of the transistor of each capacitor cell. As a result, the output signal is reset to the lower voltage value V l (l=lower) and upper voltage value V u (u=upper) The output signal varies within a certain tolerance V tol It should be clear that

[0085] For the control parameters, the following applies: t write During this time, the target voltage V O puts the capacitor cell into an initial state, Q w =C*V DD *(1-e -(t_write / RC) ) and V O =Q W / C. t rest is the quasi-static V O This is used to generate a signal when the charging bias VDD ≠ V O and V u,d =V o,u *e -(t_rest / RC) ) and Qrest=C*V o,u *e -(t_rest / RC) Therefore, it is necessary. refresh sets the output signal to V o Return to target. Q refesh =Q rest +C*V DD *(1-e-(t_refresh / RC)

[0086] It should also be understood that the discharge of the capacitor of a capacitor cell occurs due to leakage. This is particularly true when the output of the capacitor cell, i.e., V o occurs when connected to the gate of a spin qubit, because such gates also have some leakage. Practical examples have shown that the discharge time is in the range of seconds, and t rest >>t refresh As a result, the DC levels at the gates of the connected qubits are potentially very static, and a high multiplexing ratio can be supported between different ones of the capacitor cells, i.e., between different qubit gates of the connected qubit gates.

[0087] In contrast, a current driven bias drive circuit requires that a capacitor be continuously charged and then discharged through a resistor, as already indicated above.

[0088] FIG. 5 shows the results for different write periods, i.e., t write1 , t write2 5 shows another diagram 500 representing t rest and t refresh The relationship is shown in a less compressed x-direction than in the previous figure, but the ratios are now more realistic. Again, assuming that the discharge of the capacitors in the capacitor cell is due to leakage, the RC time constant is the gate voltage of the transistor at each capacitor, i.e., R ON In the on state, R ON is very small, so the RC drive time constant is close to the parasitic RC time constant, i.e., it charges quickly.

[0089] In the off state, the channel resistance is R OFF This is on the order of 1 MOhm to 1 GOhm, meaning that the discharge is relatively slow. 4 ~106 (or even larger) on / off ratios can be expected. This factor is due to the higher degree of multiplexing and the flatter DC level (i.e., V Oi It can be used for various purposes (levels).

[0090] Therefore, the voltage stability factor with multiplexing factor M is given as follows: VS=(R ON / R OFF )*(M-1)

[0091] The lower part of FIG. 5 shows some examples that show that voltage stability can be expected to be very high, or even semi-stable.

[0092] Figure 6 shows a signal flow diagram 600 of an example control algorithm that can be used with the example embodiment for the two example outputs, i.e., the two capacitor cells, presented as stable in the top half of Figure 5. The bottom half of Figure 6 shows a visual representation of the two example outputs. The abbreviations are as follows: t wn :Write time of output n; t rn : Quiet time of output n; t fn :Refresh time of output n; V n :controllersignal; V Gn : drive gate signal; and V DCn : Output signal

[0093] In another embodiment, the voltage controller may output multiple parallel control signals, in which case the algorithm will always be like the single output example. To this end, the following table may be exemplary: [Table 1]

[0094] 7 shows a more complete voltage-driven biasing example 700. At the bottom, signals for qubit biasing 708 are shown (symbolically) connected to one or more gates of one or more qubit devices, e.g., spin qubit devices and / or superconducting qubit devices.

[0095] Programmable logic 702, e.g., a "program" for a quantum computing system, may be provided to control an exemplary qubit device according to embodiments described herein. Selected supply signals go from programmable logic 702 to voltage controller circuit 704, where digital signals V1 through V n is generated and provided to the gates of voltage drive biasing circuit 706, e.g., as discussed in the context of FIG. 1. Finally, voltage drive biasing circuit 706 outputs a voltage output signal V that is to be used as the qubit device biasing signal, i.e., connected to the gates of the qubit devices. O1 ~V On Thereby, the following signal characteristics may be used: Selection: Digital signal V1~V n :Digital signal V DD : Supply bias V G1 ~V Gn : digital signals, and V O1 ~V On : Analog signal

[0096] FIG. 8 shows a block diagram of an exemplary voltage-driven biasing circuit, very similar to FIG. 7. Identical control blocks are shown with the same reference numerals. The visible difference is that a digital-to-analog converter (DAC) 802 converts the digital control signal to an analog supply voltage, so that the target output signal level can be controlled through the DAC on the supply side of the voltage controller circuit. In this case, the charging voltage / current is controlled by generating the correct supply voltage level in the DAC to fully charge the capacitor, rather than controlling the charging time constant of the capacitor circuit. The benefit of such a solution is reduced operational complexity. This comes at the expense of increased DC power requirements and slightly reduced scalability.

[0097] Figure 9 shows a comparable block diagram, also very similar to Figure 7, but for a current-driven biasing circuit. The main difference here is that the voltage-driven biasing circuit (compare Figure 8) has been replaced with a current-driven biasing circuit 902, as discussed in the context of some of the figures above.

[0098] 10 shows a block diagram of an exemplary method 1000 for operating an exemplary semiconductor device circuit for a qubit device biasing gate, according to at least one embodiment. The method includes, at 1002, providing a semiconductor device circuit including a multiplexed array of capacitor cells having the following features: each capacitor cell includes a transistor-controlled capacitor; each capacitor is connected between the drain of the respective transistor and ground; each source of all transistors of all capacitor cells is connected to a common control point; each gate of the transistors of the capacitor cells is individually voltage-controllable; a charge unit connected to the common control point; and a discharge unit connected to the common control point, where the charge unit and the discharge unit are alternately activatable.

[0099] The method 1000 further includes selectively time-based activating one of the capacitor cells of the array of capacitor cells at 1004. The activation of the capacitor cells is performed in a multiplexed manner.

[0100] As an optional exemplary further step, method 1000 may further include periodically activating one of the capacitor cells of the array of capacitor cells at 1006. As can be appreciated from the "Summary of the Invention" section herein, numerous other optional method steps are possible.

[0101] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0102] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technology, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0103] In addition to the functional elements in the following claims, the corresponding structure, material, acts, and equivalents of all means or steps are intended to include any structure, material, or acts for performing a function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments have been chosen and described to best explain the principles of the invention and its practical application and to enable others skilled in the art to understand the invention in terms of various embodiments with various modifications as may be suitable for the particular uses contemplated.

Claims

1. 1. A semiconductor device circuit for a biasing gate of a qubit device, comprising: a multiplexed array of capacitor cells; wherein each of said capacitor cells has a transistor controlled capacitor; each of the transistor control capacitors is connected between the drain of the respective transistor and ground; a source of each of the respective transistors of each of the capacitor cells is connected to a common control point; a gate of each transistor-controlled capacitor of each of the transistor-controlled capacitors of each of the capacitor cells being individually voltage-controllable; a charging unit connected to the common control point; and a discharge unit connected to said common control point wherein the charging unit and the discharging unit are alternately activatable.

2. the charging unit further comprising:

10. The semiconductor device circuit of claim 9, further comprising a transistor including a drain connected to the common control point, the transistor further comprising a source connected to a supply voltage and a gate connectable to a first control voltage for activation of the charging unit.

3. The discharge unit further comprises:

10. The semiconductor device circuit of any of the preceding claims, further comprising a transistor including a drain connected to the common control point, a source connected to ground via a resistor, and a gate connectable to a second control voltage for activation of the discharge unit.

4. The discharge unit further comprises:

10. The semiconductor device circuit of claim 9, further comprising a transistor including a drain connected to the common control point, the transistor further comprising a source connected to ground via a current measurement unit, and a gate connectable to a third control voltage for activation of the discharge unit.

5. 10. A semiconductor device circuit as claimed in any of the previous claims, wherein the voltage levels at the drains of the transistors of the capacitor cells are kept semi-constant by time-based activation of the gates of the transistors of the respective capacitor cells.

6. 10. The semiconductor device circuit of any of the preceding claims, wherein the semiconductor device circuit is adapted to be operable in a 3K environment.

7. 10. The semiconductor device circuit of claim 1, wherein a signal level at the drain of the transistor of the capacitor cell represents a bias voltage level for a control gate of a qubit device.

8. 10. The semiconductor device circuit of claim 1, wherein the discharging time of the capacitor of the capacitor cell is at least 1000 times longer than the charging time.

9. 10. A semiconductor device circuit according to any of the preceding claims, wherein each transistor in the semiconductor device circuit is of the n-enhancement type.

10. 10. The semiconductor device circuit of any of the preceding claims, further comprising a resistor in parallel with the transistor controlled capacitor of the capacitor cell.

11. 1. A method for operating a semiconductor device circuit for a biasing gate of a qubit device, comprising: providing a semiconductor device circuit, said semiconductor device circuit comprising: a multiplexed array of capacitor cells, each of said capacitor cells including a transistor-controlled capacitor, each of said capacitors connected between a drain of a transistor and ground, each of said transistors of each of said capacitor cells having a source connected to a common control point, and each of said transistors of said capacitor cells having a gate that is individually voltage-controllable; a charging unit connected to the common control point; and a discharge unit connected to said common control point wherein the charging unit and the discharging unit are alternately activatable; and Selectively activating one of the capacitor cells of the multiplexed array of capacitor cells on a time basis. A method for providing the above.

12. activating the charging unit by connecting a gate of a transistor of the charging unit to a first control voltage, wherein a source of the transistor of the charging unit is connected to a supply voltage and the drain of the transistor of the charging unit is connected to the common control point; and deactivating the discharge unit by connecting the gate of the transistor of the discharge unit to ground, wherein the source of the transistor of the discharge unit is connected to a supply voltage and the drain of the transistor of the charge unit is connected to the common control point; 10. The method of claim 9, further comprising:

13. periodically activating one of the capacitor cells of the array of capacitor cells by applying a recharge voltage to the gate of the transistor of the respective capacitor cell, thereby achieving a quasi-constant voltage level at the drain of the transistor of the respective capacitor cell.

10. The method of claim 9, further comprising:

14. periodically activating another capacitor cell of the array of capacitor cells other than said one of said capacitor cells, thereby achieving a quasi-constant voltage level at the drain of the transistor of said other capacitor cell.

10. The method of claim 9, further comprising:

15. controlling the frequency of activation of said one of said capacitor cells to maintain said quasi-constant voltage level at the drain of said transistor of said other capacitor cell while keeping said activation duration constant.

10. The method of any of the preceding two claims, further comprising:

16. activating the discharge units by connecting gates of the transistors of the discharge units to a second control voltage, wherein the sources of the transistors of the discharge units are connected to a supply voltage and the drains of the transistors of the discharge units are connected to the common control point; and deactivating the charging unit by connecting the gate of the transistor of the charging unit to ground, wherein the source of the transistor of the charging unit is connected to ground via a discharge unit resistor, and the drain of the transistor of the charging unit is connected to the common control point; 10. The method of any of the preceding five claims, further comprising:

17. measuring the voltage across the discharge unit resistor 10. The method of claim 9, further comprising:

18. connecting an output resistor in parallel with the capacitor of the capacitor cell; and periodically activating each capacitor cell of the array of capacitor cells, thereby imparting a periodic current through the output resistor.

10. The method of any of the preceding two claims, further comprising:

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