Integrated circuit, processing method, electronic device and medium for memory access

Abstract

[0009] The present disclosure provides an integrated circuit, a processing method, an electronic device, and a medium for memory access, the integrated circuit including: a first bit width conversion module for converting a first write access signal of a processor into a second write access signal including two portions of original data to be written; a first memory control module for converting the target data to be written in the second write access signal into at least one set of first data to be written that meets a first protocol supported by a memory physical layer interface and determining a corresponding set of third write access signals, each set of first data to be written including two portions of the same first data to be written from the two portions of the original data to be written; and a memory physical layer interface for converting each set of third write access signals into two-path fourth write access signals that meet the memory protocol and transmitting each fourth write access signal to a corresponding memory module. The present disclosure can effectively meet the storage requirements of a relatively high security level function based on a relatively low security level memory.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This disclosure claims priority to a Chinese patent application bearing application number CN202310079654.7 and entitled "Integrated circuit, processing method, electronic device and medium for memory access," filed with the State Intellectual Property Office of the People's Republic of China on January 17, 2023, the entire contents of which are incorporated herein by reference. [Technical Field]

[0002] This application relates to semiconductor technology, and more particularly to integrated circuits, processing methods, electronic devices, and media for memory access. [Background technology]

[0003] In the field of intelligent driving, the DDR (Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory)) of intelligent driving chips is mainly used for the detection and prediction function of intelligent driving, and the current functional safety level requirement for this function is ASILB (Automotive Safety Integrity Level B). However, with the evolution of control and decision-making function algorithms, where the safety level for intelligent driving functions is ASILD (Automotive Safety Integrity Level D), the computational power and memory requirements for the control and decision-making function algorithms are becoming increasingly greater. When control and decision-making algorithms are developed using processors (or cores within processors) and RAM, memory shortages are likely to occur, which results in a lack of memory for relatively high safety levels corresponding to relatively high safety level functions. Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments of the present disclosure provide integrated circuits, processing methods, electronic devices, and media for memory access to meet the storage requirements of relatively high security level functions. [Means for solving the problem]

[0005] An integrated circuit for memory access according to one aspect of an embodiment of the present disclosure includes a first bit width conversion module for converting original data to be written in a first write access signal of a processor into target data to be written including two portions of the original data to be written according to a first predetermined conversion form, and determining a converted second write access signal based on the target data to be written; and a first bit width conversion module connected to the first bit width conversion module for converting the target data to be written in the second write access signal into at least one set of first data to be written that satisfies a first protocol supported by a memory physical layer interface, and determining each set of the first write pairs. a first memory control module for determining a corresponding set of third write access signals based on target data, wherein each set of the first target data includes two copies of the same first target data from the two copies of the original target data, and each set of the third write access signals includes two-path third write access signals; and a memory physical layer interface connected to the first memory control module for converting each set of the third write access signals into two-path fourth write access signals that satisfy a memory protocol, and transmitting each of the fourth write access signals to a corresponding memory module.

[0006] A processing method for memory access according to another aspect of an embodiment of the present disclosure includes the steps of: converting original data to be written in a first write access signal of a processor into target data to be written, including two portions of the original data to be written, according to a first predetermined conversion form, and determining a converted second write access signal based on the target data to be written; converting the target data to be written in the second write access signal into at least one set of first data to be written that meets a first protocol supported by a memory physical layer interface, and determining a corresponding set of third write access signals based on each set of first data to be written, wherein each set of first data to be written includes two portions of the same first data to be written from the two portions of the original data to be written, and each set of third write access signals includes two-path third write access signals; and converting each set of the third write access signals into two fourth write access signals that meet a memory protocol, and transmitting each fourth write access signal to a corresponding memory module.

[0007] A computer-readable storage medium according to yet another aspect of an embodiment of the present disclosure stores a computer program for executing a method according to the above embodiment of the present disclosure, or the storage medium stores data that needs to be stored by at least one hardware logic circuit of an integrated circuit described in the above embodiment of the present disclosure, thereby enabling the hardware logic circuit to realize a corresponding function when operating.

[0008] According to yet another aspect of an embodiment of the present disclosure, an electronic device includes a processor and a memory for storing instructions executable by the processor, wherein the processor reads the executable instructions from the memory and executes the executable instructions to thereby realize a method described in the above embodiment of the present disclosure; or wherein the electronic device includes an integrated circuit described in the above embodiment, and at least one module in the integrated circuit is realized by a hardware logic circuit. [Effects of the Invention]

[0009] The integrated circuit, processing method, electronic device, and medium for memory access according to the above embodiments of the present application perform bit width conversion on a first write access signal from a processor to convert the original data to be written into target data to be written, which includes two copies of the original data to be written; determine a converted second write access signal based on the target data to be written; and write the two copies of the original data to be written to two memory modules via a first memory control module and a memory physical layer interface, so that when data is read, the same data can be read from the two memory modules. The consistency of the access results from the two memory modules ensures functional safety of the relatively high safety level functions. Even when the memory controller only meets a relatively low safety level, the access operation of the relatively high safety level function can be completed, so that a relatively low safety level memory can be used for the relatively high safety level functions and the relatively high safety level functions can access the relatively low safety level memory. This helps to provide larger memory support for the relatively high safety level functions in satisfying functional safety, thereby effectively meeting the memory requirements of the relatively high safety level functions and solving problems such as insufficient memory for the relatively high safety level.

[0010] The technical configuration of the present disclosure will be described in more detail below with reference to the drawings and examples. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is an exemplary application scenario of an integrated circuit for memory access according to the present disclosure; [Figure 2] FIG. 1 illustrates an integrated circuit structure for memory access according to an exemplary embodiment of the present disclosure. [Figure 3] FIG. 10 illustrates a structure of an integrated circuit for memory access according to another exemplary embodiment of the present disclosure. [Figure 4] FIG. 2 illustrates a structure of a read data verification module 27 according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 10 illustrates a structure of an integrated circuit for memory access according to yet another exemplary embodiment of the present disclosure. [Figure 6] FIG. 2 is a diagram illustrating the structure of a memory physical layer interface 23 according to an exemplary embodiment of the present disclosure. [Figure 7] FIG. 2 is a diagram illustrating the structure of a memory physical layer interface 23 according to another exemplary embodiment of the present disclosure. [Figure 8] FIG. 1 illustrates a principle of converting original data to be written into target data to be written according to an exemplary embodiment of the present disclosure. [Figure 9] FIG. 10 illustrates an integrated circuit structure for memory access according to yet another exemplary embodiment of the present disclosure. [Figure 10] FIG. 10 illustrates an integrated circuit structure for memory access according to yet another exemplary embodiment of the present disclosure. [Figure 11] FIG. 10 is a diagram illustrating a principle of conversion from third data to fourth data according to an exemplary embodiment of the present disclosure. [Figure 12] FIG. 1 is a diagram illustrating a flow of a processing method for memory access according to an exemplary embodiment of the present disclosure. [Figure 13] FIG. 10 is a flow diagram illustrating a processing method for memory access according to another exemplary embodiment of the present disclosure. [Figure 14] FIG. 10 is a diagram illustrating a flow of data reading for memory access according to an exemplary embodiment of the present disclosure. [Figure 15] FIG. 10 is a flow diagram illustrating a processing method for memory access according to yet another exemplary embodiment of the present disclosure. [Figure 16] FIG. 10 is a diagram illustrating the structure of another application example of an electronic device according to the present disclosure. Modes for carrying out the invention

[0012] In order to understand the present disclosure, exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. The described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments, and the present disclosure is not limited to the exemplary embodiments.

[0013] Unless otherwise specifically stated, the relative deployment of components and steps, formulas and numerical values ​​described in these examples do not limit the scope of the present disclosure.

[0014] [Summary of this disclosure] In the process of realizing the present disclosure, the inventors discovered the following: In the field of intelligent driving, DDR (Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory)) of intelligent driving chips is mainly used for the detection and prediction function of intelligent driving, and the current functional safety level requirement for this function is ASILB (Automotive Safety Integrity Level B), but with the evolution of algorithms for control and decision-making functions whose safety level in intelligent driving functions is ASILD (Automotive Safety Integrity Level D), the computational power and memory requirements for the algorithms of control and decision-making functions become increasingly greater, and when control and decision-making algorithms are developed using a processor (or a core within a processor) and RAM, memory shortage problems are likely to occur, which causes a shortage of memory for relatively high safety levels corresponding to relatively high safety level functions.

[0015] [Illustrative Overview] FIG. 1 is an exemplary application scenario of an integrated circuit for memory access according to the present disclosure.

[0016] In a functional scenario of a predetermined level (ASILD level), such as intelligent driving control and decision-making, the integrated circuit for memory access of the present disclosure allows the processor responsible for executing the corresponding control and decision-making functional algorithm to access the DDR under conditions that meet the functional safety level ASILD, thereby providing strong memory capabilities based on the DDR to meet the increasingly large memory requirements. Here, the processor can be any possible processor or processor core within the intelligent driving chip, such as, but not limited to, a central processing unit (CPU), a graphics processor (GPU), a brain processor (BPU), an artificial intelligence processor (NPU), a deep learning processor (DPU), etc. Specifically, the integrated circuit for memory access of the present disclosure can include a first bit width conversion module, a first memory control module, and a memory physical layer interface. The first bit width conversion module can convert original data to be written in a first write access signal of the processor into target data to be written, including two parts of the original data to be written, according to a first predetermined conversion form, and determine a converted second write access signal based on the target data to be written. The first memory control module can be connected to the first bit width conversion module, and the first memory control module can convert the target write data in the second write access signal into at least one set of first write data that meets a first protocol supported by the memory physical layer interface, and determine a corresponding set of third write access signals based on each set of first write data, where each set of first write data can include two parts of the same first write data from the two parts of the original write data, and each set of third write access signals can include two-way third write access signals.The memory physical layer interface can be connected to the first memory control module, and the memory physical layer interface can convert each set of third write access signals into two-way fourth write access signals that meet the memory protocol, and transmit each fourth write access signal to its corresponding memory module. This allows memory access to two memory modules simultaneously, and the consistency of the access results of the two memory modules achieves a relatively high level of memory access safety, thereby enabling a memory device with a relatively large memory capacity based on a relatively low level (e.g., ASILB level) to provide memory capacity for a relatively high level (e.g., ASILD level) function scenario, which helps to solve problems such as insufficient memory for a relatively high level function scenario.

[0017] It should be noted that the integrated circuit of the present disclosure is not limited to being applied to the above-mentioned intelligent driving control and decision-making scenarios, but can be applied to any scenario that requires a relatively high level of safety according to actual requirements, and is not specifically limited.

[0018] [Example Device] 2 is a diagram illustrating the structure of an integrated circuit for memory access according to an exemplary embodiment of the present disclosure. This embodiment can be applied to electronic devices, specifically, an in-vehicle computing platform. As shown in FIG. 2, this integrated circuit for memory access (abbreviated as "integrated circuit") 20 can include a first bit width conversion module 21, a first memory control module 22, and a memory physical layer interface 23.

[0019] The first bit width conversion module 21 can convert the original write target data in the first write access signal of the processor into target write target data including two parts of the original write target data according to a first predetermined conversion form, and determine the converted second write access signal based on the target write target data.

[0020] The first memory control module 22 can be connected to the first bit width conversion module 21, and the first memory control module 22 can convert the target write target data in the second write access signal into at least one set of first write target data that meets a first protocol supported by the memory physical layer interface, and determine a corresponding set of third write access signals based on each set of first write target data, where each set of first write target data can include two parts of the same first write target data from the two parts of original write target data, and each set of third write access signals can include two-path third write access signals.

[0021] The memory physical layer interface 23 can be connected to the first memory control module 22, and the memory physical layer interface 23 can convert each set of third write access signals into a two-path fourth write access signal that meets the memory protocol, and transmit each fourth write access signal to a corresponding memory module.

[0022] Here, the processor can be any possible processor or processor core within the intelligent driving chip, such as, but not limited to, a central processing unit (CPU), a graphics processor (GPU), an artificial intelligence (AI) processor (also called an AI processor core), etc. The first write access signal can include a data signal (including the original data to be written), a control signal, and an address signal. The first predetermined conversion form can be set according to actual requirements. The first predetermined conversion form can duplicate the original data to be written into two parts, and convert the two parts of the original data to be written into target data to be written according to a predetermined format, which can be used as the data signal of the second write access signal.

[0023] The first memory control module 22 can be a control module connected to the first bit width conversion module 21 and the memory physical layer interface 23, and the first memory control module 22 can convert the second write access signal converted by the first bit width conversion module 21 into a write access signal that meets the memory physical layer interface protocol. In order to enable the two parts of the original data to be written to be written to the two memory modules respectively, when the first memory control module 22 performs protocol conversion, it can convert the target data to be written, including the two parts of the original data to be written, into at least one set of first data to be written, where each set can include two parts of the same first data to be written, and the two parts of the first data to be written in each set can be derived from the two parts of the original data to be written in the target data to be written. For example, if the original data to be written is 128 bits and the first data to be written is 16 bits, they can be converted into eight sets of first data to be written, where each of the two parts of the first data to be written in the first set can include bits 0 to 15 of the original data to be written, each of the two parts of the first data to be written in the second set can include bits 16 to 31 of the original data to be written, ..., and each of the two parts of the first data to be written in the eighth set can include bits 112 to 127 of the original data to be written. The first write target data of each part can be the data signal of the third write access signal of one path, so that at least one set of the third write access signal can be obtained after conversion, and each set can include the third write access signal of two paths.

[0024] In actual use, the specific bit widths of the original data to be written and the first data to be written can be set according to actual requirements.

[0025] The memory physical layer interface 23 can be a bridge connecting the first memory control module 22 and the memory. The memory physical layer interface 23 can convert each set of two-path third write access signals converted by the first memory control module 22 into two-path fourth write access signals that comply with the memory protocol, and transmit these two-path fourth write access signals to their corresponding memory modules. For example, the memory physical layer interface 23 can transmit one path of the fourth write access signal to the first memory module and the other path of the fourth write access signal to the second memory module. This allows the two copies of the original data to be written to be divided into multiple sets and written to the two memory modules.

[0026] In one alternative embodiment, in the various conversion processes of the write access signal, in addition to converting the data to be written, conversion of the control signal can also be included. For example, in the process of converting the first write access signal into the second write access signal, in addition to converting the original data to be written into the target data to be written, a signal representing the length of the data in the control signal can be converted. For example, when the first memory control module converts the second write access signal into each set of third write access signals, in addition to converting the target data to be written into the first data to be written, the length of the data can also be converted. Specifically, this can be set according to actual requirements.

[0027] In one alternative embodiment, the conversion of each module can be represented by converting an access signal, of which the conversion of the data portion can be converted according to the conversion form, for example, the first bit width conversion module 21 can convert a first write access signal into a second write access signal, where the target write data of the second write access signal is obtained by converting the original write data in the first write access signal according to a first predetermined conversion form, and the target write data can include two parts of the original write data. The process of converting the first write access signal into the second write access signal can further include converting a control signal, which can be specifically set according to actual requirements. In one alternative embodiment, the first memory control module 22 may be a DDR controller.

[0028] In one alternative embodiment, the memory physical layer interface 23 may be a DDR PHY (DDR Physical Interface, DDR memory physical layer interface), the corresponding first protocol may be a DFI (DDR PHY Interface) protocol, and the memory protocol may be a DDR protocol. The DDR PHY may include two independent transmission channels, and the two transmission channels of the DDR PHY may transmit the fourth write access signal of each set of two paths.

[0029] In an alternative embodiment, the specific structures of the first bit width conversion module 21, the first memory control module 22 and the memory physical layer interface 23 can be set according to actual requirements.

[0030] In one alternative embodiment, each fourth write access signal corresponds to one memory module, and each set of two-path third write access signals can be converted to obtain two-path fourth write access signals, so that it can correspond to two memory modules, which can be respectively referred to as a first memory module and a second memory module, and the two memory modules can be any two memory devices connected in the intelligent driving chip or two memory areas in the same memory device, for example, two memory areas with the same address in the DDR in the intelligent driving chip, and can be specifically set according to actual requirements.

[0031] Optionally, the integrated circuit of the embodiments of the present disclosure can be connected to the processor via any operable bus, such as an AXI, AHB, APB, or CHI bus, thereby allowing the processor to access the first memory module and the second memory module via the bus.

[0032] The memory access integrated circuit of this embodiment performs bit width conversion on a first write access signal from a processor to convert the original data to be written into target data to be written, which includes two copies of the original data to be written, and further determines a converted second write access signal based on the target data to be written. The first memory control module and the memory physical layer interface write the two copies of the original data to be written to two memory modules, so that when data is read, the same data can be read from the two memory modules. The consistency of the access results from the two memory modules ensures the functional safety of the relatively high safety level functions. Even in scenarios where the memory controller satisfies a relatively low safety level, the access operation of the relatively high safety level functions can be completed. This allows the relatively low safety level memory to be used as the relatively high safety level functions, and the relatively high safety level functions can access the relatively low safety level memory. This provides greater memory support for the relatively high safety level functions in meeting functional safety, thereby effectively meeting the memory requirements of the relatively high safety level functions and solving problems such as insufficient memory for the relatively high safety level.

[0033] FIG. 3 is a diagram illustrating a structure of an integrated circuit for memory access according to another exemplary embodiment of the present disclosure.

[0034] In one alternative embodiment, the integrated circuit of the present disclosure may further include a second memory control module 24 and a first comparison module 25 .

[0035] The second memory control module 24 can be connected to the first bit width conversion module 21, and the second memory control module 24 can convert the target write target data in the second write access signal into at least one set of second write target data that meets a first protocol supported by the memory physical layer interface 23, and determine a corresponding set of fifth write access signals based on each set of second write target data, where each set of second write target data includes two parts of the same second write target data from the two parts of original write target data, and each set of fifth write access signals can include two-path fifth write access signals.

[0036] The first comparison module 25 can be connected to the first memory control module 22 and the second memory control module 24 respectively, and the first comparison module 25 can compare the third write access signal of each set with the fifth write access signal of each set, and output an error signal in response to a mismatch in the comparison result.

[0037] Here, the specific conversion principle of the second memory control module 24 can be the same as that of the first memory control module 22, with the difference being that the fifth write access signals of each set acquired by the second memory control module 24 can be transmitted to the first comparison module 25 without being transmitted to the memory physical layer interface 23, and the third write access signals of each set acquired by the first memory control module 22 can also be transmitted to the first comparison module 25. The first comparison module 25 compares the third write access signals of each set with the fifth write access signals of each set to determine whether the processing results of the first memory control module 22 and the second memory control module 24 are consistent. If the comparison results are inconsistent, an error signal can be output so that corresponding measures can be taken in a timely manner, thereby improving the functional safety of the first memory control module 22 and avoiding dangerous situations caused by errors in the first memory control module 22.

[0038] In one optional embodiment, the first comparison module 25, in addition to comparing the third write access signal of each set with the fifth write access signal of each set, can also compare other output signals of the first memory control module 22 and the second memory control module 24 during operation, thereby realizing mutual verification of all functions of the first memory control module 22 and the second memory control module 24, and further improving the functional safety of the first memory control module 22.

[0039] In this embodiment, a second memory control module with the same functions as the first memory control module is provided to verify the processing results of the first memory control module, thereby effectively improving the accuracy and validity of the processing results of the first memory control module, thereby improving the security of write data and enabling timely detection when an error occurs in the first memory control module, so that write access to memory can meet a relatively high security level.

[0040] In an optional embodiment, the integrated circuit of the embodiment of the present disclosure may further include a second bit width conversion module 26 and a read data verification module 27 .

[0041] The memory physical layer interface 23 can further obtain at least one set of first data from the first memory module and the second memory module, respectively, convert each set of first data among the at least one set of first data into a set of second data that satisfies a first protocol, and transmit each set of second data to the first memory control module 22, where each set of first data can include first read data and second read data, and each set of second data can include third read data corresponding to the first read data and fourth read data corresponding to the second read data.

[0042] The first memory control module 22 can further convert each set of second data into third data that satisfies a second protocol supported by the second bit width conversion module 26 and transmit the third data to the second bit width conversion module 26.

[0043] The second bit width conversion module 26 can perform bit width conversion on the third data according to a second predetermined conversion form to obtain fourth data and fifth data, and transmit the fourth data to the processor.

[0044] The read data verification module 27 can compare the fourth data with the fifth data, and output an error signal in response to a mismatch between the fourth data and the fifth data.

[0045] Here, the second predetermined conversion form can be the inverse of the first predetermined conversion form. When it is necessary to read the same data after writing them to the first memory module and the second memory module, a set (including two parts) of the same data written in parallel from the first memory module and the second memory module can be read in parallel. For distinction, the data read from the first memory module can be called first read data, and the data read from the second memory module can be called second read data. The first read data and the second read data are regarded as a set of first data, and the memory physical layer interface 23 converts the first read data and the second read data in each set of first data into third read data and fourth read data that satisfy the first protocol. The third read data and the fourth read data may be a set of second data, and each set of second data may be transmitted to the first memory control module 22. For example, the memory physical layer interface may transmit the third read data and the fourth read data to the first memory control module 22 in parallel via two independent channels, and the first memory control module 22 may convert each set of second data into third data conforming to a second protocol supported by the second bit width conversion module 26. This conversion process is the reverse of the conversion process from the target write data to the first write data, and at least one set of second data may be combined into third data according to a certain format. The second bit width conversion module 26 may perform bit width conversion on the third data according to a second predetermined conversion form to obtain fourth data and fifth data. If no error occurs in the data reading, the fourth data and the fifth data should be the same data.The second bit width conversion module 26 transmits the acquired fourth data or fifth data to the processor, and can also transmit the acquired fourth data and fifth data to the read data verification module 27 for verification. The read data verification module 27 compares the fourth data with the fifth data and outputs an error signal if the comparison result is inconsistent. Since the data read reads the previously written data, the fourth data and fifth data in the data read process match the bit width of the original data to be written in the second part of the data write process, the third data in the data read process matches the bit width of the target data to be written in the data write process, the first read data and second read data in the data read process match the bit width of the data to be written in the fourth write access signal in the data write process, and the third read data and fourth read data in the read data process match the bit width of the first data to be written in the write data process.

[0046] In an alternative embodiment, the display form of the error signal can be set according to actual requirements, for example, an output of 1 indicates that an error has occurred, and is not specifically limited.

[0047] In one alternative example, the memory physical layer interface 23 can convert a set of 16-bit first data (including the first read data and the second read data) read from the first memory module and the second memory module each time into a set of 16-bit second data (third read data and fourth read data) that satisfies a first protocol and transmit it to the first memory control module 22, and the first memory control module 22 can convert the eight sets of second data transmitted from the memory physical layer interface 23 into 256-bit third data and transmit it to the second bit width conversion module 26, and the second bit width conversion module 26 can convert the third data into 128-bit fourth data and fifth data according to a second predetermined conversion form, where the fourth data is derived from the first memory module and the fifth data is derived from the second memory module.

[0048] In an optional embodiment, the error signal of the embodiment of the present disclosure may be output to an error processing module in the intelligent driving chip or to a processor, so that when an error occurs, corresponding processing can be performed in a timely manner, such as resetting the integrated circuit or sending warning information to the user, and specifically can be set according to actual requirements, and is not limited to the embodiment of the present disclosure.

[0049] In this embodiment, when reading data, the second bit width conversion module compares the fourth data and the fifth data obtained from the two memory modules, respectively. If the comparison results are not consistent, an error signal is output, and corresponding processing can be carried out in a timely manner for the error that occurs, which helps to improve the security of the read data, and thereby allows read access to the memory to meet a relatively high security level.

[0050] FIG. 4 is a diagram illustrating the structure of the read data verification module 27 according to an exemplary embodiment of the present disclosure.

[0051] In one alternative embodiment, the read data verification module 27 may include a predetermined number of exclusive OR circuits 271 and OR circuits 272 .

[0052] The two inputs of the nth exclusive OR circuit 271 can be the value of the nth bit of the fourth data and the value of the nth bit of the fifth data, respectively, and each exclusive OR circuit 271 can output 1 in response to the values ​​of the two inputs being different, and output 0 in response to the values ​​of the two inputs being the same, and the predetermined number can be the same as the bit width of the fourth data.

[0053] The input terminals of the OR circuit 272 can be connected to the output terminals of the exclusive OR circuits 271, respectively, and the OR circuit 272 can output an error signal in response to the output of any of the exclusive OR circuits 271 being 1.

[0054] Here, the predetermined number can be set according to the bit width of the fourth data. For example, if the bit width of the fourth data is 128 bits, 128 exclusive OR circuits 271 can be provided, and specifically, there is no limitation.

[0055] In one alternative embodiment, the specific structure of the OR circuit 272 can be set according to actual requirements, for example, the number of inputs of the OR circuit 272 can be set according to the number of exclusive OR circuits 271, and the internal structure of the OR circuit 272 can be realized by multiple OR elements.

[0056] In this embodiment, a bit-by-bit comparison of the fourth data and the fifth data is realized using a predetermined number of exclusive OR circuits and one OR circuit, and an error signal can be output using one output when the comparison result of any bit does not match, thereby effectively reducing the number of connection lines to other modules.

[0057] In one alternative embodiment, the predetermined number may be the same as the bit width of the first read data, in which case the fourth data and the fifth data may be grouped for comparison. For example, if the bit width of the first read data is 16 bits, the read data verification module 27 may include 16 exclusive OR circuits 271 and one OR circuit 272, and each 16 bits of the fourth data and the corresponding 16 bits of the fifth data are input to the read data verification module 27 for verification.

[0058] In one alternative embodiment, the read data verification module 27 can be realized by a serial register and one exclusive OR circuit or comparator. For example, the fourth data and the fifth data are stored by two serial registers, and the two input terminals of the exclusive OR circuit or comparator are connected to the two serial registers, respectively. By controlling the two serial registers, each bit can be input sequentially to the exclusive OR circuit or comparator, and the nth bit of the fourth data and the nth bit of the fifth data can be input to the exclusive OR circuit for comparison. If the two do not match, an error signal can be output.

[0059] FIG. 5 is a diagram illustrating a structure of an integrated circuit for memory access according to yet another exemplary embodiment of the present disclosure.

[0060] In an alternative embodiment, the integrated circuit of the present disclosure may further include a first delay module 28 and a second delay module 29 .

[0061] The first delay module 28 can be connected to the first memory control module 22 and the first comparison module 25, respectively, and the first delay module 28 can delay each set of third write access signals output from the first memory control module 22 by a first time before transmitting them to the first comparison module 25.

[0062] The second delay module 29 can be connected to the first bit width conversion module 21 and the second memory control module 24, respectively, and the second delay module 29 can delay the second write access signal output from the first bit width conversion module 21 by a first time before transmitting it to the second memory control module 24.

[0063] Here, the specific structures of the first delay module 28 and the second delay module 29 can be set according to actual requirements, such as delaying a signal, and are not limited to specific ones. For example, a timer can be used to control the transmission time of a received signal. The first time can be set according to actual requirements, such as one clock cycle or two clock cycles, and are not limited to specific ones. For the first memory control module 22, the first delay module 28 can delay the time when the output result reaches the first comparison module 25 after the first memory control module 22 completes processing. For the second memory control module 24, the time when the second write access signal reaches the second memory control module 24 before the second memory control module 24 processes is delayed, thereby realizing the time when the processing result of the second memory control module 24 reaches the first comparison module 25. The processing results of the two memory control modules can reach the first comparison module 25 simultaneously. Furthermore, the first memory control module 22 and the second memory control module 24 can convert the same second write access signal at different times. This prevents the two memory control modules from operating simultaneously and causing the same error to go undetected. For example, if the same error occurs in two memory control modules during the processing, for example, due to interference from some factor (e.g., electromagnetic interference) at the same time, causing the third write access signal of each set in which the error exists and the fifth write access signal of each set to still match, the occurrence of the error cannot be detected after comparison by the first comparison module 25.

[0064] In addition, the first delay module 28 not only delays the third write access signal of each set output from the first memory control module 22 by a first time before transmitting it to the first comparison module 25, but also delays any other signal output from the first memory control module 22 by a first time before transmitting it to the first comparison module 25. In addition, the second delay module 29 not only delays the second write access signal output from the first bit width conversion module 21 by a first time before transmitting it to the second memory control module 24, but also delays any other signal that needs to be input to the second memory control module 24 by a first time, and specifically can be set according to actual requirements.

[0065] In this embodiment, by delaying signals at different stages for the first memory control module 22 and the second memory control module 24, it is possible to effectively avoid a situation in which errors go undetected due to simultaneous errors occurring in two memory control modules, thereby improving the safety of memory access.

[0066] FIG. 6 is a diagram illustrating the structure of the memory physical layer interface 23 according to an exemplary embodiment of the present disclosure.

[0067] In one alternative embodiment, the memory physical layer interface 23 may include a first channel 231 , a second channel 232 , a control unit 233 and a monitor 234 .

[0068] The first channel 231 can transmit one fourth write access signal corresponding to each set of third write access signals to the first memory module corresponding to the first channel 231 .

[0069] The second channel 232 can transmit another fourth write access signal corresponding to each set of third write access signals to the second memory module corresponding to the second channel 232 .

[0070] The control unit 233 can be connected to the first channel 231 and the second channel 232 respectively, and the control unit 233 can generate operation clocks and reset signals for the first channel 231 and the second channel 232.

[0071] The monitor 234 can be connected to the control unit 233, and the monitor 234 can monitor and measure the operating clock and / or reset signal, and output an alarm signal based on the monitoring measurement result.

[0072] Here, the first channel 231 and the second channel 232 can be respectively connected to the first memory control module 22, the first channel 231 can also be connected to the first memory module, and the second channel 232 can also be connected to the second memory module. The first channel 231 can convert one third write access signal in each set of third write access signals into one fourth write access signal that satisfies the memory protocol and transmit this fourth write access signal to the first memory module, and similarly, the second channel 232 can convert another third write access signal in each set of third write access signals into another fourth write access signal that satisfies the memory protocol and transmit this fourth write access signal to the second memory module. The operation clock drives the first channel 231 and the second channel 232 to start operation, and the reset signal can control the first channel 231 and the second channel 232 to reset the memory and memory physical layer interface 23. The control unit 233 can be controlled by other modules (e.g., a processor, a reset management module, etc.) of the intelligent driving chip and can be specifically set according to actual requirements. For example, if a fault occurs, the processor needs to reset the integrated circuit of the embodiment of the present disclosure to perform fault processing in response to an interrupt, and can send a reset command to the reset management module or directly to the control unit 233. The control unit 233 can control the first channel 231 and the second channel 232 to perform a memory reset. The specific operation clock and reset control can be set according to actual requirements and are not limited to the embodiment of the present disclosure.The monitor 234 can monitor and measure the operation clock and / or reset signal of the control unit 233 in real time or in a timing manner, and if it monitors and measures that an error has occurred in the operation clock and / or the reset signal or that a predetermined condition is not met, it can output an alarm signal to detect the problem in a timely manner, thereby improving the functional safety of the memory physical layer interface 23. For example, the monitor 234 can check whether the count value of the generated operation clock is within a desired range, and if it is not within the desired range, it can output an alarm signal. It can also monitor and measure, for example, whether an error has occurred in the reset signal, and if the reset signal is triggered when the memory is operating normally (for example, pull-down indicates that a reset operation is triggered), it can output an alarm signal.

[0073] The memory physical layer interface of this embodiment realizes the conversion and transmission of the same set of two third write access signals through two independent channels, which can respectively store some data from two original write data in two memory modules and store two identical original write data in two memory modules, which makes it easy to verify when reading data and helps memory access to meet a relatively high security level.

[0074] In one optional embodiment, the first channel 231 can convert the first read data read from the first memory module into third read data that meets the first protocol and transmit it to the first memory control module 22, and the second channel 232 can convert the second read data read from the second memory module into fourth read data that meets the first protocol and transmit it to the first memory control module 22. The first memory control module 22 can also convert each third read data transmitted by the first channel 231 and each fourth read data transmitted by the second channel 232 into third data that meets a second protocol supported by the second bit width conversion module 26, and transmit the third data to the second bit width conversion module 26. The second bit width conversion module 26 can perform bit width conversion on the third data according to a second predetermined conversion form to obtain fourth data and fifth data, transmit the fourth data to the processor, and transmit the fourth data and fifth data to the read data verification module 27. The read data verification module 27 can compare the fourth data and the fifth data, and output an error signal in response to a mismatch in the comparison result.

[0075] 7 is a diagram illustrating a structure of the memory physical layer interface 23 according to another exemplary embodiment of the present disclosure, where monitor represents the monitor 234, clock represents an operation clock, reset represents a reset signal, MASTER represents the control unit 233, DDR channel A and DDR channel B represent two channels of a dual channel memory (e.g., dual channel SDRAM), the first channel 231 and the second channel 232 have the same structure and both include three channels, DQ, DQ, and AC, where DQ represents a data channel for transmitting data and AC represents an address / command channel for transmitting addresses and commands.

[0076] In one alternative embodiment, the first bit width conversion module 21 specifically: The original data to be written included in the first write access signal is granulated into a first bit width, and for a portion of the original data corresponding to each first bit width, the original data of this portion is duplicated into two portions of the same data, and these two portions of the same data are used as two consecutive target data of the first bit width, and the first bit width and the bit width of the data supported by the first protocol are the same, and for the target data respectively corresponding to each portion of the original data, target data to be written is determined according to the order of the original data of each portion in the original data to be written, and a signal representing the length of the original data to be written included in the control signal in the first write access signal is converted into a signal representing the length of the target data to be written to obtain the target control signal, and a second write access signal is determined based on the target data to be written and the target control signal.

[0077] In one possible example, FIG. 8 is a diagram illustrating a principle of conversion from original data to be written to target data to be written according to an exemplary embodiment of the present disclosure. Here, Byte represents a byte, 1 Byte = 8 bits, and bit represents a bit, for example, Byte0 includes 8 bits from bit0 to bit7. As shown in FIG. 8, the first bit width is 16 bits, and the original data to be written in the first write access signal is granulated into 16 bits, and portions of the original data corresponding to each first bit width (e.g., Byte0 and Byte1) are copied into two identical data, and these two identical data are used as two consecutive target data of the first bit width. Furthermore, target data (a total of eight target data) corresponding to each portion of the original data (a total of eight portions of original data) are combined according to the order of the original data of each portion in the original data to be written to obtain the target data to be written.

[0078] 9 is a diagram illustrating the structure of an integrated circuit for memory access according to yet another exemplary embodiment of the present disclosure, where the specific operating principles of each part can be referred to above, and redundant explanations will be omitted here.

[0079] In one alternative embodiment, the conversion functions of the first bit width conversion module 21 and the second bit width conversion module 24 are inverse conversions, and therefore can be realized by a single bit width conversion module in actual use. For example, FIG. 10 is a diagram showing the structure of an integrated circuit for memory access according to yet another exemplary embodiment of the present disclosure. As shown in FIG. 10, the bit width of the original data to be written is 128 bits (bits), and the bit width conversion modules can realize the functions of the first bit width conversion module 21 and the second bit width conversion module 24. When writing data, the bit width conversion module converts a first write access signal of 128 bits of original data to be written into target data to be written that includes two parts of the original data to be written and has a bit width of 256 bits through AXI (Advanced eXtensible Interface) protocol conversion. When reading data, the bit width conversion module converts the 256-bit third data transmitted from the first memory control module 22 into 128-bit fourth and fifth data through AXI protocol conversion, and transmits some of the data to the processor. In this case, a read data verification module 27 is provided within the bit width conversion module to verify the converted fourth and fifth data. The AXI protocol is a bus protocol in which the address / control (also called command) and data phases are separated, and it supports the transmission of mismatched data. A detailed description of the underlying principles will be omitted.

[0080] In one possible example, Figure 11 is a diagram illustrating the principle of conversion from third data to fourth data according to an exemplary embodiment of the present disclosure. As shown in Figure 11, taking the third data bit width as an example of 256 bits, the 256-bit third data is converted to 128 bits. In the third data, the remaining bytes other than the bytes constituting the fourth data constitute fifth data, and the principle of the fifth data is the same as that of the fourth data, so a duplicated description will be omitted here.

[0081] Any of the modules and units in this example can be realized by hardware or software, and can be realized using hardware logic circuits to ensure real-time performance.

[0082] In one possible example, in order to ensure the real-time capability of the device, each of the modules, units in each module, and sub-units in each unit of the device of the embodiment of the present disclosure can be realized using hardware logic circuits, thereby effectively reducing hardware overhead and power consumption overhead while maintaining real-time capability.

[0083] Each embodiment and optional example of the present disclosure may be implemented alone or in any combination where no contradiction exists, and may be specifically set according to actual requirements.

[0084] [Exemplary Method] 12 is a diagram showing the flow of a processing method for memory access according to an exemplary embodiment of the present disclosure, which can be realized by the integrated circuit for memory access according to any one of the above embodiments. As shown in FIG. 12, the method of this embodiment can include the following steps 301 to 303.

[0085] In step 301, the original write target data in the first write access signal of the processor is converted into target write target data including two parts of the original write target data according to a first predetermined conversion form, and a converted second write access signal is determined based on the target write target data.

[0086] In one alternative example, this step 301 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the first bit width conversion module.

[0087] In step 302, convert the target write data in the second write access signal into at least one set of first write data that meets a first protocol supported by the memory physical layer interface, and determine a corresponding set of third write access signals based on each set of first write data, where each set of first write data includes two parts of the same first write data from the two parts of original write data, and each set of third write access signals includes two-path third write access signals.

[0088] In one alternative example, this step 302 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the first memory control module.

[0089] In step 303, each set of third write access signals is converted into two fourth write access signals that meet the memory protocol, and each fourth write access signal is transmitted to its corresponding memory module.

[0090] In one alternative example, this step 303 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the memory physical layer interface.

[0091] The specific operations of each step of the method of the embodiment of the present disclosure have already been described in detail in the integrated circuit embodiment described above, and the duplicated description will be omitted here.

[0092] FIG. 13 is a diagram illustrating a flow of a processing method for memory access according to another exemplary embodiment of the present disclosure.

[0093] In an alternative embodiment, the method of the present disclosure may further include steps 401 and 402.

[0094] In step 401, converting target write data in the second write access signal into at least one set of second write data that meets a first protocol supported by the memory physical layer interface, and determining a corresponding set of fifth write access signals based on each set of second write data, where each set of second write data includes two pieces of the same second write data from the two pieces of original write data, and each set of fifth write access signals includes two-path fifth write access signals.

[0095] In one alternative example, this step 401 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the second memory control module.

[0096] In step 402, the third write access signal of each set is compared with the fifth write access signal of each set, and an error signal is output in response to a mismatch between the comparison results.

[0097] In one alternative example, this step 402 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the first comparison module.

[0098] FIG. 14 is a diagram illustrating a flow of data reading for memory access according to an exemplary embodiment of the present disclosure.

[0099] In an alternative embodiment, the method of the present disclosure may further include steps 501 to 504.

[0100] In step 501, at least one set of first data is obtained from the first memory module and the second memory module, respectively, and each set of first data of the at least one set of first data is converted into a set of second data that satisfies a first protocol, where each set of first data includes first read data and second read data, and each set of second data includes third read data corresponding to the first read data and fourth read data corresponding to the second read data.

[0101] In one alternative example, this step 501 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the memory physical layer interface.

[0102] In step 502, each set of second data is converted into third data that satisfies a second protocol.

[0103] In one alternative example, this step 502 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the first memory control module.

[0104] In step 503, perform bit width conversion on the third data according to a second predetermined conversion form to obtain fourth data and fifth data, and transmit the fourth data to the processor.

[0105] In one alternative example, this step 503 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the second bit width conversion module.

[0106] In step 504, the fourth data is compared with the fifth data, and an error signal is output in response to a mismatch between the fourth data and the fifth data.

[0107] In one alternative example, this step 504 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the read data verification module.

[0108] In one alternative embodiment, step 504 of comparing the fourth data with the fifth data and outputting an error signal in response to a mismatch in the comparison result may include a step of comparing the value of the nth bit of the fourth data with the value of the nth bit of the fifth data and outputting an error signal in response to a difference in the comparison result of any bit.

[0109] FIG. 15 is a diagram illustrating a flow of a processing method for memory access according to yet another exemplary embodiment of the present disclosure.

[0110] In an alternative embodiment, the method of the present disclosure may further include steps 610 and 620.

[0111] In step 610, the third write access signal of each set is delayed by a first time before proceeding to the subsequent flow.

[0112] In one alternative example, this step 610 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the first delay module.

[0113] In step 620, the second write access signal is delayed for a first time before proceeding to the subsequent flow.

[0114] In one alternative example, this step 620 may be performed by a processor calling corresponding instructions stored in a memory, or may be performed by the second delay module.

[0115] In one alternative embodiment, step 303 of converting each set of third write access signals into two fourth write access signals that meet the memory protocol and transmitting each fourth write access signal to a corresponding memory module comprises: The method may include transmitting one fourth write access signal corresponding to each set of third write access signals to the first memory module, and transmitting another fourth write access signal corresponding to each set of third write access signals to the second memory module.

[0116] In one alternative embodiment, step 303 of converting each set of third write access signals into two fourth write access signals that meet the memory protocol and transmitting each fourth write access signal to a corresponding memory module comprises: The method may include generating an operating clock to trigger transmitting one fourth write access signal corresponding to each set of third write access signals to the first memory module and transmitting another fourth write access signal corresponding to each set of third write access signals to the second memory module.

[0117] In one alternative embodiment, step 303 of converting each set of third write access signals into two fourth write access signals that meet the memory protocol and transmitting each fourth write access signal to a corresponding memory module comprises: The method may further include generating a reset signal when the first memory module and / or the second memory module needs to be reset, and transmitting the reset signal to the first memory module and / or the second memory module.

[0118] In one alternative embodiment, step 303 of converting each set of third write access signals into two fourth write access signals that meet the memory protocol and transmitting each fourth write access signal to a corresponding memory module comprises: The method may further include the step of monitoring and measuring the operating clock and / or reset signal, and outputting an alarm signal based on the results of the monitoring and measurement.

[0119] In one alternative embodiment, step 301 includes: The method may include the steps of: granulating the original data to be written included in the first write access signal into a first bit width; for a portion of the original data corresponding to each first bit width, duplicating this portion of the original data into two portions of the same data and using these two portions of the same data as two consecutive target data of the first bit width, wherein the first bit width is the same as the bit width of the data supported by the first protocol; determining target data to be written according to the order of the original data of each portion in the original data to be written for target data respectively corresponding to each portion of the original data; converting a signal representing the length of the original data to be written included in the control signal in the first write access signal into a signal representing the length of the target data to be written to obtain a target control signal; and determining a second write access signal based on the target data to be written and the target control signal.

[0120] The beneficial technical effects corresponding to the exemplary embodiments of the present method may refer to the beneficial technical effects corresponding to the exemplary device parts described above, and redundant descriptions will be omitted here.

[0121] The processing method for memory access according to the embodiments of the present disclosure may be executed by any suitable device having a data processing function, including, but not limited to, a terminal device, a server, etc. Alternatively, the processing method for memory access according to the embodiments of the present disclosure may be executed by a processor, for example, the processor may execute the processing method for memory access mentioned in the embodiments of the present disclosure by calling corresponding instructions stored in a memory. Alternatively, any method according to the embodiments of the present disclosure may be executed by a hardware logic circuit device. Hereinafter, redundant description will be omitted.

[0122] As can be understood by those skilled in the art, realizing all or part of the steps of the above method embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer-readable storage medium, and when the program is executed, the steps of the above method embodiments are performed, and the storage medium includes various media that can store program code, such as a ROM, a RAM, a magnetic disk, or an optical disk.

[0123] [Example Electronic Devices] An embodiment of the present disclosure includes a memory for storing a computer program; and a processor for executing a computer program stored in the memory, wherein, when the computer program is executed, a method according to any of the above embodiments of the present disclosure is realized.

[0124] Alternatively, the electronic device includes the device according to any one of the above embodiments (i.e., an integrated circuit for memory access) in order to implement the method according to any one of the above embodiments of the present disclosure.

[0125] Here, at least one module in the apparatus is realized by a hardware logic circuit, or at least one unit in at least one module is realized by a hardware logic circuit.

[0126] To improve real-time performance, each module in the device, each unit in each module, and each subunit in each unit are all realized by hardware logic circuits, that is, the entire device is a hardware logic circuit.

[0127] 16 is a diagram showing the structure of an application example of an electronic device of the present disclosure. In this example, the electronic device 10 includes one or more processors 11 and a memory 12.

[0128] The processor 11 may be a central processing unit (CPU) or other form of processing unit having data processing and / or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

[0129] The memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), a hard disk, and flash memory. The computer-readable storage medium may store one or more computer program instructions, and the processor 11 may execute the program instructions to implement the methods according to the above-described embodiments of the present disclosure and / or other desired functions. The computer-readable storage medium may also store various contents, such as an input signal, a signal component, and a noise component.

[0130] As an example, electronic device 10 may further include input devices 13 and output devices 14 connected to each other via a bus system and / or other form of connection (not shown).

[0131] The input device 13 may include, for example, a keyboard and a mouse.

[0132] The output device 14 can output various types of information to the outside, and can include, for example, a display, a speaker, a printer, a communication network, and remote output devices connected thereto.

[0133] 16 shows only some of the components of the electronic device 10 that are relevant to the present disclosure, and omits components such as a bus, an input / output interface, etc. The electronic device 10 may further include any other appropriate components depending on the specific application.

[0134] In one alternative embodiment, an electronic device may be provided that includes an integrated circuit for memory access according to the above embodiment or example, or that further includes other related devices in addition to the electronic device, and redundant description will be omitted here. At least one module in the integrated circuit is realized by a hardware logic circuit, or at least one unit in at least one module is realized by a hardware logic circuit.

[0135] Exemplary Computer Program Products and Computer-Readable Storage Media In addition to the methods and apparatus described above, embodiments of the present disclosure provide a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods according to various embodiments of the present disclosure described above in the "Exemplary Methods" section of this specification.

[0136] The computer program product may have program code for carrying out operations of embodiments of the present disclosure written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and traditional procedural programming languages ​​such as "C" or similar programming languages. The program code may execute entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on the remote computing device or a server.

[0137] Additionally, embodiments of the present disclosure further provide a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform steps in methods according to various embodiments of the present disclosure described hereinabove in the "Exemplary Method" section.

[0138] The storage medium of the present disclosure may store data that at least one hardware logic circuit of the protection device for the image data processing module described in the "Exemplary Device" section above in the specification of the present disclosure needs to store, so that the hardware logic circuit can realize a corresponding function when it operates. For example, the storage medium may be a register of the hardware logic circuit, storing data for an initial configuration, or storing data that needs to be stored during operation, and is not limited thereto. Here, the at least one hardware logic circuit may be the hardware logic circuit of a module in the device, the hardware logic circuit of a unit in a module, or even the hardware logic circuit of a sub-unit in a unit, and is not limited thereto.

[0139] The computer-readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0140] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, the benefits, advantages, effects, etc. mentioned in the present disclosure are merely illustrative and not limiting, and these benefits, advantages, effects, etc. are not necessarily possessed by each embodiment of the present disclosure. Furthermore, the specific details of the above disclosure are merely illustrative and easy-to-understand functions and are not limiting, and the above details do not necessarily limit the present disclosure to those realized by the above specific details.

[0141] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. 1. An integrated circuit for memory access, comprising: a first bit width conversion module for converting original write target data in a first write access signal of a processor into target write target data including two copies of the original write target data according to a first predetermined conversion form, and determining a converted second write access signal based on the target write target data; a first memory control module connected to the first bit width conversion module, for converting the target write data in the second write access signal into at least one set of first write data that meets a first protocol supported by a memory physical layer interface, and for determining a corresponding set of third write access signals based on each set of the first write data, wherein each set of the first write data includes two portions of the same first write data from the two portions of the original write data, and each set of the third write access signals includes two-path third write access signals; a memory physical layer interface connected to the first memory control module, for converting each set of the third write access signals into a two-path fourth write access signal that satisfies a memory protocol, and for transmitting each of the fourth write access signals to a corresponding memory module.

2. The integrated circuit comprises: a second memory control module connected to the first bit width conversion module, for converting the target write data in the second write access signal into at least one set of second write data that meets a first protocol supported by a memory physical layer interface, and for determining a corresponding set of fifth write access signals based on each set of the second write data, wherein each set of the second write data includes two portions of the same second write data from the two portions of the original write data, and each set of the fifth write access signals includes two-path fifth write access signals; 2. The integrated circuit according to claim 1, further comprising: a first comparison module connected to the first memory control module and the second memory control module, respectively, for comparing each set of the third write access signals with each set of the fifth write access signals, and outputting an error signal in response to a mismatch between the comparison results.

3. the integrated circuit further includes a second bit width conversion module and a read data verification module; the memory physical layer interface further acquires at least one set of first data from the first memory module and the second memory module, respectively, converts each set of first data among the at least one set of first data into a set of second data that satisfies the first protocol, and transmits each set of second data to the first memory control module, wherein each set of first data includes first read data and second read data, and each set of second data includes third read data corresponding to the first read data and fourth read data corresponding to the second read data; The first memory control module further converts each set of the second data into third data that satisfies a second protocol supported by the second bit width conversion module, and transmits the third data to the second bit width conversion module; the second bit width conversion module performs bit width conversion on the third data according to a second predetermined conversion format to obtain fourth data and fifth data, and transmits the fourth data to a processor; 3. The integrated circuit according to claim 2, wherein the read data verification module compares the fourth data with the fifth data and outputs an error signal in response to a mismatch between the fourth data and the fifth data.

4. The read data verification module: a predetermined number of exclusive OR circuits, wherein two inputs of an n-th exclusive OR circuit are the n-th bit value of the fourth data and the n-th bit value of the fifth data, each exclusive OR circuit outputs 1 in response to the two inputs being different in value and outputs 0 in response to the two inputs being the same in value, the predetermined number being the same as the bit width of the fourth data; 4. The integrated circuit according to claim 3, further comprising: a logical OR circuit whose input terminals are respectively connected to the output terminals of the exclusive OR circuits, the logical OR circuit outputting an error signal in response to an output of any of the exclusive OR circuits being 1.

5. The integrated circuit comprises: a first delay module connected to the first memory control module and the first comparison module, respectively, for delaying each set of the third write access signals output from the first memory control module by a first time and then transmitting the third write access signals to the first comparison module; 3. The integrated circuit according to claim 2, further comprising: a second delay module connected to the first bit width conversion module and the second memory control module, respectively, for delaying the second write access signal output from the first bit width conversion module by the first time and then transmitting the second write access signal to the second memory control module.

6. The memory physical layer interface includes: a first channel for transmitting one of the fourth write access signals corresponding to each set of the third write access signals to a first memory module corresponding to the first channel; a second channel for transmitting another fourth write access signal corresponding to each set of the third write access signals to a second memory module corresponding to the second channel; a control unit connected to the first channel and the second channel, respectively, for generating an operation clock and a reset signal for the first channel and the second channel; 2. The integrated circuit according to claim 1, further comprising: a monitor connected to the control unit for monitoring and measuring an operating clock and / or a reset signal and outputting an alarm signal based on the monitoring and measurement result.

7. The first bit width conversion module specifically includes: The original data to be written included in the first write access signal is granulated into a first bit width, and for a portion of the original data corresponding to each first bit width, the original data of this portion is duplicated into two portions of the same data, and the two portions of the same data are used as two consecutive target data of a first bit width, and the first bit width is the same as the bit width of data supported by the first protocol; determining the target data to be written according to the order of the original data of each of the portions in the original data to be written for the target data corresponding to each of the portions of the original data; a signal representing the length of the original data to be written, which is included in the control signal of the first write access signal, is converted into a signal representing the length of the target data to be written, to obtain a target control signal; 2. The integrated circuit according to claim 1, wherein the second write access signal is determined based on the target data to be written and the target control signal.

8. A processing method for memory access, comprising: converting original write target data in a first write access signal of a processor into target write target data including two copies of the original write target data according to a first predetermined conversion form, and determining a converted second write access signal based on the target write target data; converting the target write data in the second write access signal into at least one set of first write data that satisfies a first protocol supported by a memory physical layer interface, and determining a corresponding set of third write access signals based on each set of the first write data, wherein each set of the first write data includes two portions of the same first write data from the two portions of the original write data, and each set of the third write access signals includes two-path third write access signals; converting each set of the third write access signals into two fourth write access signals that satisfy a memory protocol, and transmitting each of the fourth write access signals to a corresponding memory module.

9. A computer-readable storage medium, comprising: The storage medium stores a computer program for executing the processing method for memory access according to claim 8, or A computer-readable storage medium, characterized in that the storage medium stores data that needs to be stored by at least one hardware logic circuit of an integrated circuit for memory access according to any one of claims 1 to 7, thereby enabling the hardware logic circuit to realize a corresponding function when operating.

10. a processor; a memory for storing instructions executable by the processor, The processor reads the executable instructions from the memory and executes the executable instructions to implement the processing method for memory access according to claim 8; or The electronic device includes an integrated circuit for memory access according to any one of claims 1 to 7, 10. An electronic device, wherein at least one module in the integrated circuit for memory access is realized by a hardware logic circuit.

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