Systems and methods for reading out qubit states - Patents.com

Abstract

This paper discusses how to read out the state of a flux qubit after performing a calculation on a quantum processor with the flux qubit represented in an energy basis to obtain the final state of the flux qubit represented in the energy basis. A flux bias is applied to the body loop of the flux qubit to convert the final state of the flux qubit from the energy basis to the flux basis. A control signal is applied to latch the final state of the flux qubit, and the final state of the flux qubit is copied to a shift register. The final state of the flux qubit is then transmitted from the quantum processor to the outside world via the shift register.

Description

[Technical Field]

[0001] Technical Field The present disclosure relates generally to quantum computing, and more particularly to systems and methods for reading out flux qubit states after quantum computing.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority to U.S. Patent Application No. 63 / 448,537, filed February 27, 2023, the entire disclosure of which is incorporated herein by reference for all purposes. [Background technology]

[0003] background quantum computing A quantum computer is a system that directly exploits at least one quantum mechanical phenomenon, such as superposition, tunneling, or entanglement, to perform data manipulations. The building blocks of a quantum computer are qubits. Quantum computers can improve the speed of certain classes of computational problems, such as those that simulate quantum physics. Summary of the Invention [Problem to be solved by the invention]

[0004] overview Hybrid computing systems including quantum processors A hybrid computing system may include a digital computer communicatively connected to an analog computer, in some embodiments, the analog computer is a quantum computer and the digital computer is also referred to as a classical computer.

[0005] A digital computer may include a digital processor that can be used to perform the classical digital processing tasks described in the present systems and methods. A digital computer may include at least one system memory that can be used to store various sets of computer or processor readable instructions, application programs, and / or data.

[0006] A quantum computer may include a quantum processor that includes programmable elements such as qubits, couplers, and other devices. The qubits can be read out via a readout system, and the readout results are transmitted to a digital computer. The qubits and couplers are controlled by a qubit control system and a coupler control system, respectively. In some embodiments, quantum annealing can be implemented in an analog computer using the qubit control system and the coupler control system.

[0007] quantum processor The quantum processor may take the form of a superconducting quantum processor, which may include a number of superconducting qubits and associated local bias elements, and may also include couplers (also known as coupling elements) that selectively provide communicative coupling between the qubits.

[0008] The above examples of related art and their limitations are illustrative and not limiting. Other limitations of the related art will become apparent to those skilled in the art upon reading and understanding this specification and examining the drawings. [Means for solving the problem]

[0009] According to one aspect, there is provided a method for reading out a state of a flux qubit of a quantum processor after performing a computation using the quantum processor having the flux qubit represented in an energy basis, the computation resulting in a final state of the flux qubit represented in the energy basis, the flux qubit including a body loop interrupted by a compound Josephson junction (CJJ), the method including applying a flux bias to the body loop of the flux qubit to transform the final state of the flux qubit from the energy basis to the flux basis; applying a first control signal to latch the final state of the flux qubit represented in the flux basis; copying the final state of the flux qubit represented in the flux basis to a shift register; and transmitting the final state of the flux qubit from the quantum processor externally via the shift register.

[0010] In other aspects, the method of applying a first control signal to latch a final state of a flux qubit represented in a flux basis may include applying the first control signal to a CJJ of the flux qubit; copying the final state of the flux qubit represented in a flux basis to a shift register may include applying a second control signal to raise a tunnel barrier of the CJJ of a first stage of the shift register; the method may further include, after transmitting the final state of the flux qubit externally from the quantum processor via the shift register, removing the flux bias from the body loop of the flux qubit; removing the first control signal from the CJJ of the flux qubit; and removing the second control signal to latch the state of the first stage of the shift register; applying the first control signal to latch the final state of the flux qubit represented in a flux basis may include applying the first control signal via an analog line; and applying the first control signal to latch the final state of the flux qubit may include applying the first control signal to the quantum processor by a control element; and copying the final state of the flux qubit represented in the flux basis into the shift register may include copying the final state of the flux qubit represented in the flux basis into the shift register via a latching quantum flux parametron (QFP), the latching QFP being coupled to the flux qubit by at least one of magnetic and galvanic coupling, wherein applying a first control signal to latch the final state of the flux qubit represented in the flux basis may include applying the first control signal to a CJJ of the latching QFP, and copying the final state of the flux qubit represented in the flux basis into the shift register may include applying a second control signal to raise a tunneling barrier of a first stage of the shift register, and the method may further include, after transmitting the final state of the flux qubit externally from the quantum processor via the shift register, removing the flux bias from the body loop of the flux qubit, removing the first control signal latching the state of the latching QFP, and removing the second control signal latching the state of the first stage of the shift register.

[0011] According to one aspect, there is provided a method for solving a computational problem with a hybrid computing system, the hybrid computing system including a digital processor in communication with a quantum processor, the quantum processor including a flux qubit including a body loop interrupted by a compound Josephson junction (CJJ), the method comprising: programming the quantum processor based on the computational problem by applying one or more programming control signals to the flux qubit, the flux qubit being programmed in an energy basis; instructing the quantum processor to evolve to a processor final state by the digital processor, the processor final state including a qubit final state of the flux qubit expressed in the energy basis; and communicating the digital processor and the quantum processor to each other. applying a first control signal by one of the digital processor and the quantum processor to transmit a flux bias to the body loop of the flux qubit to convert the final qubit state of the flux qubit from the energy basis to the flux basis; applying a second control signal by one of the digital processor and the quantum processor to latch the final qubit state of the flux qubit; applying a third control signal by one of the digital processor and the quantum processor to copy the final qubit state of the flux qubit to the shift register; applying one or more fourth control signals by one of the digital processor and the quantum processor to transmit the final qubit state of the flux qubit through the shift register; and receiving the final qubit state by the digital processor.

[0012] In other aspects, applying a third control signal by one of the digital processor and the quantum processor to copy the final qubit state of the flux qubit into the shift register may include applying the third control signal by one of the digital processor and the quantum processor to copy the final qubit state of the flux qubit into the shift register via a latching quantum flux parametron (QFP) that is magnetically or galvanically coupled to the flux qubit; applying a second control signal by one of the digital processor and the quantum processor to latch the final qubit state of the flux qubit may include applying the second control signal by one of the digital processor and the quantum processor to the CJJ of the flux qubit; and applying a third control signal by one of the digital processor and the quantum processor to copy the final qubit state of the flux qubit into the shift register includes applying the third control signal by one of the digital processor and the quantum processor to raise a tunnel barrier of a first stage of the shift register. and the method may further include releasing a first control signal by one of the digital processor and the quantum processor from the body loop of the flux qubit; releasing a second control signal by one of the digital processor and the quantum processor latching the qubit final state of the flux qubit; releasing a third control signal latching the qubit final state of the first stage of the shift register; and applying the second control signal by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit includes applying the second control signal by one of the digital processor and the quantum processor to a CJJ of a latching QFP coupled to the flux qubit; and applying the third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to the shift register may include applying the third control signal by one of the digital processor and the quantum processor to raise the tunneling barrier of the first stage of the shift register; and the method further includes releasing the first control signal by one of the digital processor and the quantum processor;Releasing the second control signal by one of the digital processor and the quantum processor and releasing the third control signal by one of the digital processor and the quantum processor, applying the second control signal to latch the qubit final state may include applying the second control signal via an analog line, applying the second control signal to latch the qubit final state may include instructing an on-chip control element to apply the second control signal, and applying one or more programming control signals to the flux qubits by the digital processor to program the quantum processor based on the computational problem may include applying one or more programming control signals to the flux qubits by the digital processor to program the quantum processor based on the surface code problem.

[0013] In other aspects, the above-described features can be combined in any reasonable combination, as will be appreciated by those skilled in the art.

[0014] In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve drawing clarity. Furthermore, the particular shapes of elements depicted in the drawings are not intended to convey any information regarding the actual shapes of these particular elements, but have merely been selected for ease of viewing in the drawings. [Brief explanation of the drawings]

[0015] BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] 1 is a schematic diagram of a hybrid computing system including a digital computer connected to an analog computer in accordance with the present systems, apparatus, and methods; [Figure 2] 1 is a schematic diagram of an example of a flux qubit that can be employed in accordance with the present systems, devices, and methods. [Figure 3]1 is a graph of a qubit potential energy landscape illustrating an example of ramping of a qubit potential in accordance with the present systems, apparatus, and methods. [Figure 4A] 1 is a graph of a qubit potential energy landscape illustrating an example of latching of a qubit potential in accordance with the present systems, apparatus, and methods. [Figure 4B] 1 is a graph of a qubit potential energy landscape illustrating an example of latching of a qubit potential in accordance with the present systems, apparatus, and methods. [Figure 5] FIG. 1 is a schematic diagram of an example circuit for reading out a qubit in accordance with the present systems, devices, and methods. [Figure 6] FIG. 1 is a flow diagram of an example method for reading out the state of a flux qubit in a quantum processor that can be employed in accordance with the present systems, apparatus, and methods. [Figure 7] 1 is an example graph of instantaneous eigenspectrum versus time required for tilting and latching by increasing the barrier of a qubit in accordance with the present systems, apparatus, and methods. [Figure 8] 10 is an example plot of instantaneous eigenspectra versus time required for tilting and latching by increasing the barrier of the QFP for a coupled qubit and QFP system in accordance with the present systems, apparatus, and methods. [Figure 9] 1 is an example of a graph of the instantaneous eigenspectrum versus time when reading and resetting a qubit in accordance with the present systems, apparatus, and methods. [Figure 10] FIG. 1 is a flow diagram of an example method for solving a computational problem in a hybrid computing system that may be employed in accordance with the present systems, apparatus, and methods. DETAILED DESCRIPTION OF THE INVENTION

[0016] Detailed Description of the Invention In the following description, specific details are referenced to provide a thorough understanding of the disclosed embodiments. However, it will be understood by those skilled in the art that the embodiments can be practiced without some of these specific details or by using other methods, elements, materials, etc. In other instances, well-known structures associated with computer systems, server computers, and / or communication networks have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0017] Unless the context clearly indicates otherwise, in this specification and the claims that follow, the word "comprising" is synonymous with "including" and is inclusive or open-ended (i.e., does not exclude additional, not yet recited, elements or method acts).

[0018] Throughout this specification, the term "an embodiment" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0019] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include the plural forms unless the context clearly dictates otherwise, and the term "or" is generally used in its sense including "and / or" unless the context clearly dictates otherwise.

[0020] The headings and abstracts provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0021] 1 illustrates a computing system 100 that includes a digital computer 102. The exemplary digital computer 102 includes one or more digital processors 106 used to perform classical digital processing tasks. The digital computer 102 may further include at least one system memory 122 and at least one system bus 120 that couples various system elements, including the system memory 122, to the digital processor 106. The system memory 122 may store one or more sets of processor-executable instructions, also referred to as modules 124.

[0022] Digital processor 106 may be a logic processing device or circuit (e.g., an integrated circuit), such as one or more central processing units ("CPUs"), graphics processing units ("GPUs"), digital signal processors ("DSPs"), application specific integrated circuits ("ASICs"), programmable gate arrays ("FPGAs"), programmable logic controllers ("PLCs"), etc., and / or combinations thereof.

[0023] In some embodiments, computing system 100 includes an analog computer 104 that may include one or more quantum processors 126. Quantum processor 126 may include at least one superconducting integrated circuit. Digital computer 102 may communicate with analog computer 104, for example, via controller 118. As described in more detail below, certain calculations may be performed by analog computer 104 according to instructions from digital computer 102. Because computing system 100 includes a digital computer 102 and an analog computer 104, computing system 100 may be referred to as a hybrid computing system.

[0024] The digital computer 102 may include a user input / output subsystem 108. In some embodiments, the user input / output subsystem includes one or more user input / output elements, such as a display 110, a mouse 112, and / or a keyboard 114.

[0025] The system bus 120 may employ any known bus structure or architecture, including a memory bus with a memory controller, a peripheral bus, and a local bus. The system memory 122 may include read-only memory (ROM), static random access memory (SRAM), non-volatile memory such as flash NAND, and random access memory (RAM) (not shown).

[0026] The digital computer 102 may also include a non-transitory computer- or processor-readable storage medium or non-volatile memory 116. The non-volatile memory 116 may be in various forms, including a hard disk drive that reads from and writes to a hard disk (e.g., a magnetic disk), an optical disk drive that reads from and writes to a removable optical disk, and / or a solid-state drive (SSD) that reads from and writes to solid-state media (e.g., NAND-based flash memory). The non-volatile memory 116 may communicate with the digital processor via a system bus 120, which may include an appropriate interface or controller 118 connected to the system bus 120. The non-volatile memory 116 may serve as long-term storage of processor- or computer-readable instructions, data structures, or other data (also referred to as program modules or modules 124) for the digital computer 102.

[0027] Although the digital computer 102 is described as using hard disk, optical disk, or solid-state storage media, those skilled in the relevant art will appreciate that other types of non-transitory, non-volatile computer-readable media may be used. Those skilled in the relevant art will also appreciate that some computer architectures use a combination of non-transitory, volatile, and non-transitory, non-volatile memory. For example, data in volatile memory may be cached in non-volatile memory or on a solid-state disk with non-volatile memory provided using integrated circuits.

[0028] Various processor- or computer-readable and / or executable instructions, data structures, or other data may be stored in system memory 122. For example, system memory 122 may store instructions for communicating with a remote client to schedule the use of resources, including resources of digital computer 102 and analog computer 104. Also, for example, system memory 122 may store at least one processor-executable instruction or data that, when executed by at least one processor, causes at least one processor to execute various algorithms that implement the instructions. In some embodiments, system memory 122 may store processor- or computer-readable computational instructions and / or data for pre-processing, co-processing, and post-processing by analog computer 104. System memory 122 may store a set of analog computer interface instructions for interacting with analog computer 104. For example, system memory 122 may store processor- or computer-readable instructions, data structures, or other data that, when executed by a processor or computer, cause the processor or computer to perform one, several, or all of the operations of method 600 of FIG. 6 .

[0029] Analog computer 104 may include at least one analog processor, such as quantum processor 126. Analog computer 104 may be provided in an isolated environment, for example, an isolated environment that insulates the internal elements of the quantum computer from heat, magnetic fields, and other external noise. The isolated environment may include a refrigerator, for example, a dilution refrigerator, operable to cool the analog processor to cryogenic temperatures, for example, temperatures below about 1 K.

[0030] Analog computer 104 may include programmable elements such as qubits, couplers, and other elements (also referred to herein as "controllable elements"). Qubits are read out via on-chip readout and readout control system 128. The readout results may be transmitted to another computer or to processor-readable instructions in digital computer 102. Qubits are controlled via qubit control system 130. Qubit control system 130 includes on-chip digital-to-analog converters (DACs) and analog lines operable to bias target elements. Couplers coupling qubits are controlled via coupler control system 132. Coupler control system 132 may include adjustment elements such as on-chip DACs and analog lines. Qubit control system 130 and coupler control system 132 can be used to implement the quantum annealing schedules described herein in quantum processor 126. Programmable elements may be included in quantum processor 126 in the form of integrated circuits. Qubits and couplers may be disposed in layers of the integrated circuit including a first material. Other elements, such as readout control system 128, may be located in other layers of the integrated circuit comprising the second material. According to the present disclosure, quantum processors, such as quantum processor 126, may be designed to perform quantum annealing and / or adiabatic quantum computing, or may be designed to perform gate or circuit model quantum computing. Exemplary embodiments of quantum processors are described in U.S. Patent No. 7,533,068 and U.S. Provisional Patent Application No. 63 / 356,663.

[0031] FIG. 2 is a schematic diagram illustrating an example embodiment of a superconducting qubit 200 usable in accordance with the present systems, apparatus, and methods. In some embodiments, quantum processor 126 of computing system 100 may include multiple superconducting qubits 200. In FIG. 2, solid lines represent superconducting metals, and crosses (X) represent Josephson junctions (see, e.g., U.S. Pat. No. 9,768,371). Superconducting qubit 200 includes Josephson junction structure 201 having Josephson junctions 204 and 205 and superconducting loop 203 having inductor 202. A superconducting material is a material that has a critical temperature below which the superconducting material exhibits superconducting behavior. Examples of superconducting metals include aluminum, niobium, and tantalum. There is a superconducting order parameter phase difference φ across Josephson junction structure 201, as described below with reference to FIGS. 3, 4A, and 4B. The Josephson junction structure 201 may include a single Josephson junction, a Josephson junction pair as shown herein, or other possible combinations of Josephson junctions in series or parallel. A parallel connection of two Josephson junctions is known as a compound Josephson junction (CJJ) (see, e.g., U.S. Pat. No. 8,536,566). Qubits having a layout in which an inductor is connected in parallel with a Josephson junction structure are commonly known as flux qubits (see, e.g., U.S. Pat. No. 8,536,566 and International Patent Application No. PCT / US2022 / 37457).

[0032] A variant of the fluxonium qubit is the fluxonium qubit, characterized by an extremely large body inductance resulting from the series connection of multiple large Josephson junctions. For a discussion of fluxon qubits, see Manucharyan, Vladimir E. et al., Fluxonium: Single Cooper-Pair Circuit Free of Charge Offsets, Science 326.5949 (2009):113-116, and U.S. Provisional Patent Application No. 63 / 223,686. Alternatively, a fluxonium qubit with an extremely large body inductance can be formed using superconducting wire fabricated with a kinetic inductor, such as niobium nitride (NbN), niobium titanium nitride (NbTiN), or titanium nitride (TiN) (see, e.g., International Patent Application No. PCT / US2022 / 37457). As used herein, the term fluxonium qubit refers to any superconducting qubit formed by connecting Josephson junction structures and inductances in parallel, as shown in FIG. 2.

[0033] Electric current flowing through a metallic material principally stores energy in both the magnetic field of the metal and the kinetic energy of the charge carriers (e.g., electrons or Cooper pairs). In non-superconducting metals, charge carriers collide frequently with the lattice, losing their kinetic energy as Joule heating. This is also called scattering, and quickly releases energy. However, in superconducting materials, charge carriers are Cooper pairs that are protected from dissipation by scattering, greatly reducing scattering, allowing the superconducting material to store energy in the form of kinetic inductance. This phenomenon allows kinetic inductance to efficiently store energy within superconducting metals. Kinetic inductance is determined, at least in part, by the inertial mass of the charge carriers in a given material and increases as carrier density decreases. As carrier density decreases, fewer carriers must have proportionally greater velocity to generate the same current. Materials with high kinetic inductance (defined below) per given area are referred to as "kinetic inductors," "kinetic inductance materials," or "high kinetic inductance materials."

[0034] Kinetic inductance materials are materials that have high normal state resistivity and / or a small superconducting energy gap, resulting in a large kinetic inductance per unit area. In general, the total inductance L of a superconducting material is given by L = L K +L G is given by L G is the geometric inductance, L K is the kinetic inductance. The kinetic inductance of a superconducting thin film at near-zero temperatures is given by the effective penetration depth λ eff In particular, for a thin film of a given thickness t, the kinetic inductance of the film is proportional to the ratio of the film's length L to its width W, where the length is in the direction of the current flow and the width is perpendicular to the length (note that both width and length are perpendicular to the dimension in which the thickness is measured). That is, for a superconducting film of a given thickness,

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[0035] Flux qubit 200 passes through a closed inductive loop formed in parallel with Josephson junction structure 201 (also referred to hereinafter as the "qubit body" or "body loop") by inductor 202.

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[0036] When discussing the state of a flux qubit, two different representations of that state can be considered. Figure 3 is a graph 300 illustrating an example of the energy landscape of a flux qubit. Graph 300 includes wave functions 302, 304 of the two lowest energy states of a flux qubit as a function of the superconducting phase drop φ across a Josephson junction structure (e.g., a CJJ) when the qubit is biased such that its potential energy landscape is a symmetric double well 306. In some embodiments, graph 300 can show the energy of flux qubit 200 as a function of the superconducting phase drop φ across Josephson junction structure 201.

[0037] In Figure 300, there is a "degenerate point"

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[0038] The set of states [|0L>,|0R>] defines the flux basis of the qubit. The states in the flux basis correspond to different magnetic moments due to dissipationless current flowing through the closed loop of the flux qubit body, formed by, for example, Josephson junction structure 201 in parallel with inductor 202 of flux qubit 200 of FIG. 2. For example, |0L> may represent the macroscopic amount of magnetic flux penetrating the flux qubit body due to counterclockwise current flow, and |0R> may represent the macroscopic amount of magnetic flux penetrating the flux qubit body due to clockwise current flow.

[0039] While quantum computing can be performed using either a flux basis or an energy basis, the implementation details of a particular model of quantum computing typically favor one choice over the other in practice. For example, quantum annealing (QA) is a quantum computing model suited to solving classical binary optimization problems, and its application to traditional binary optimization problems is easily mapped to the physics of the transverse magnetic field Ising model (Kadowaki, Tadashi, and Hidetoshi Nishimori, Quantum annealing in the transverse Ising model, Physical Review E58.5 (1998): 5355). In this model, qubits have access only to superposition states of the form a|0>+b|1>, where a and b are real numbers. As described in Kaminsky, William M., and Seth Lloyd, "Scalable architecture for adiabatic quantum computing of NP-hard problems," Quantum computing and quantum bits in mesoscopic systems (2004): 229-236, there is a natural mapping of QA to the flux basis of a flux qubit. Gate model quantum computation (GMQC), on the other hand, is suited to solving quantum mechanical problems in which a qubit accesses superposition states where a and b are complex coefficients. Such states are naturally encoded in energy bases within the rotating coordinate system of the flux qubit. Examples of computations include the two-dimensional surface code computations described in U.S. Provisional Patent Applications Nos. 63 / 356,663 and 63 / 390,185, or other forms of gate model computations using flux qubits. Other quantum computing models may similarly be more easily implemented in one basis than another. In the following discussion, we assume that the quantum computations of interest are performed in the energy basis.

[0040] When a computation is performed on a quantum processor, the state of the qubit reflects the result of the computation or some intermediate result, such as a measurement of an error symptom in an error-corrected quantum computation. A readout system is required to move information from the quantum processor to a digital computer or other user interface (also referred to as off-chip). In some embodiments, the readout system may move state information of qubits, such as flux qubit 200, from quantum processor 126 to digital computer 102 based on signals provided by readout control system 128.

[0041] The first category of readout methods suitable for reading out the energy basis states of a flux qubit is distributed readout. To perform distributed readout, the qubit is coupled to a resonator, and the energy eigenstates occupied by the qubit affect the resonator's resonant frequency at the lower photon number limit. Distributed readout can be used to read out a flux qubit represented in an energy basis, as described, for example, in Wallraff, Andreas, et al., Strong coupling of a single photon to a superconducting qubit using circuit quantum electrodynamics, Nature 431.7005 (2004) 162-167, and Manucharyan, Vladimir E. et al., Fluxonium: Single cooper-pair circuit free of charge offsets, Science 326.5949 (2009): 113-116. Distributed readout can achieve high readout fidelity. However, distributed readout is typically slow and difficult to design, fabricate, and operate. Achieving acceptable data rates in distributed readout of large-scale quantum processors would require many high-bandwidth microwave transmission lines. The use of high-bandwidth microwave transmission lines increases the amount of noise in the quantum processor, potentially reducing the fidelity of the computation. Alternative readout methods that combine high fidelity with high data rates while minimizing the bandwidth of control lines would be advantageous.

[0042] As discussed herein, a second category of readout methods suitable for reading out the state of a flux qubit represented in an energy basis involves transferring information from the energy basis to the flux basis and then reading out the state represented in the flux basis. Transferring information from the energy basis to the flux basis involves applying a flux bias to the qubit body.

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[0043] 4A is an example embodiment of a graph 400a of a qubit potential energy landscape after a tilting operation has been performed. That is, a flux bias has been applied to change the energy landscape from that shown in FIG. 3 to that shown in FIG. 4A. Graph 400a includes a ground state 402a, a first excited state 404a, and a potential energy landscape 406a. After tilting, the qubit state can be fully projected onto easily distinguishable states |0L> and |0R> in a process called latching. In some embodiments, a qubit can be latched by coupling the flux generated by the qubit in its flux ground state to a non-hysteretic direct current superconducting quantum interference device (DC SQUID) and then interrogating it with a classical current (see Chiorescu et al., Coherent Quantum Dynamics of a Superconducting Flux Qubit, arXiv:cond-mat / 0305461v1, May 20, 2002, and Ozfidan et al., Demonstration of nonstoquastic Hamiltonian in coupled superconducting flux qubits, arXiv:1903.06139v3, November 8, 2019). Alternatively, latching can be achieved ... CJJ flux bias.

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[0044] Figure 4B shows an example embodiment of a graph 400b of the qubit potential energy landscape after such a latching operation. Graph 400b includes a ground state 402b and a first excited state 404b. In yet another embodiment, described in more detail below, a latching quantum flux parametron (QFP) is magnetically (also referred to as inductively) and / or galvanically coupled to the qubit, and the CJJ flux bias of the latching QFP is ramped to stop quantum tunneling of the coupled qubit and latching QFP system. In this embodiment, the latching QFP has a final classical state, expressed in its flux basis, that can be transferred to a superconducting QFP shift register, as described, for example, in U.S. Patent No. 10,528,886. Readout methods for the QFP approach are described in more detail below. Methods for resetting the combined flux qubit and readout system are also described below.

[0045] FIG. 5 is a schematic diagram of an exemplary circuit 500 including a flux qubit 502 and a QFP readout circuit 504. The exemplary circuit 500 may be formed from one or more superconducting materials. The qubit 502 includes a Josephson junction structure 506 that interrupts a body loop 508. In the exemplary embodiment of FIG. 5, the Josephson junction structure 506 is a CJJ. However, in other embodiments, the Josephson junction structure 506 may be a single Josephson junction or a combination of Josephson junctions in series or parallel. A first control line 510 is communicatively coupled to the flux qubit 502 to apply a flux bias to the Josephson junction structure 506, and a second control line 512 is communicatively coupled to the flux qubit 502 to apply a flux bias to the body loop 508. In some embodiments, the flux qubit 502 may be the flux qubit 200 of FIG. 2.

[0046] QFP readout circuit 504 includes a latching QFP 514 connected to a first shift register stage 516 of a QFP shift register. QFP shift registers for readout of quantum annealing processors are described in detail in U.S. Patent No. 10,528,886. While similar principles described in the referenced patent for transferring data through a QFP shift register are applicable herein, different techniques are required to read out the state of the flux qubit in its energy basis and transfer that state to the QFP shift register, as described below. Flux qubit 502 is inductively coupled to latching QFP 514 at interface 518. In some embodiments, coupling between flux qubit 502 and latching QFP 514 at interface 518 may be fully magnetic / inductive, as shown, or partially galvanic, or interface 518 may be entirely galvanic. Galvanic coupling advantageously reduces the space and wiring used for coupling, but in some embodiments may increase noise and / or crosstalk in the processor-on-chip. Latching QFP 514 has a body loop 520 interrupted by a CJJ 522. CJJ 522 is communicatively coupled to a control line 524 that selectively carries a signal to bias CJJ 522.

[0047] The latching QFP 514 is inductively coupled to a first shift register stage 516 at interface 526. The first shift register stage 516 has a CJJ 528 communicatively coupled to a control line 530 that selectively transmits a flux bias signal to the CJJ 528. The QFP shift register of the QFP readout circuit 504 may also include an additional shift register stage connected to the first shift register stage 516 at 532.

[0048] The coupling structures, such as the inductors shown in FIG. 5, may be separate elements, or the coupling structures may be undifferentiated portions of wiring that function as distributed inductors.

[0049] In some embodiments, the latching of latching QFP 514 is a dynamic part of the read process. Bias line 524 can provide a flux bias signal to body loop 520 that can be used to calibrate the bistability point of latching QFP 514, similar to the calibration of the operating point of a qubit provided by second control line 512 in communication with body loop 508. The flux bias signal can be provided by an off-chip control line or an on-chip control element such as a flux bias DAC.

[0050] FIG. 6 is a flow diagram of an exemplary method 600 for reading out the state of a flux qubit represented in an energy basis that can be employed in accordance with the present systems, apparatus, and methods. Method 600 can, in some embodiments, be followed after performing a calculation on a gate-model quantum processor having the flux qubit represented in an energy basis to obtain a final state of the flux qubit represented in the energy basis. Method 600 can be used, for example, with exemplary circuit 500 of FIG. 5. In some embodiments, method 600 can be performed in a hybrid computing system including at least one digital or classical processor and at least one quantum processor. For example, method 600 can be performed by computing system 100 of FIG. 1. The digital or classical processor can provide control signals or instructions to the quantum processor to perform the method.

[0051] Although method 600 includes even-numbered operations 602-608, those skilled in the art will appreciate that the number of operations shown is exemplary and that in some embodiments, certain operations may be omitted, additional operations may be added, and / or the order of operations may be changed.

[0052] Method 600 may be initiated, for example, in response to a call or invocation from another routine. Method 600 is typically initiated after performing a computation on a quantum processor having flux qubits represented in an energy basis.

[0053] In 602, a flux bias gradient is applied to the body loop of the flux qubit to transform the qubit state from an energy basis to a flux basis. In the exemplary embodiment of Figure 5, the flux bias gradient may be applied to the body loop 508 of the flux qubit 502 via control line 512. Details of the flux bias gradient are described below with reference to Figures 7, 8, and 9.

[0054] At 604, a latch control signal is applied to latch the state of the flux qubit after the energy basis to flux basis conversion. In some embodiments, the latching control signal may be applied to the CJJ of the qubit. In the exemplary embodiment of FIG. 5, the latching control signal may be applied via control line 510. In other embodiments, the combined qubit-latching QFP system can be latched by applying a control signal to CJJ 522 of latching QFP 514 via control line 524. In some embodiments, latching of latching QFP 514 advantageously increases the latching speed of the state of the coupled qubit (i.e., flux qubit 502) and latching QFP system compared to the latching speed of the state of an isolated flux qubit.

[0055] The final state of the flux qubit is copied to the shift register at 606. In the exemplary embodiment of Figure 5, the final state may be copied from the latching QFP 514 to the first shift register stage 516 of the QFP shift register and then copied to additional stages at 532. Data representing qubit state information may be copied through the QFP shift register by, for example, applying a signal to a control line 530 coupled to the CJJ 528.

[0056] At 608, the final state is transmitted externally from the quantum processor. As used herein, "transmitting externally from the quantum processor" refers to transmitting data via signal lines across the quantum processor chip to devices external to the quantum processor. In contrast, "on-chip" refers to devices that form part of the quantum processor. It will be understood that "on-chip" includes devices formed on physically separate chips that are interconnected to form the quantum processor. The final state may be transmitted, for example, to a classical digital processor, and the results displayed to a user. The final state may also be provided to an algorithm executed by the digital computer, such as a classical post-processing algorithm or an error correction algorithm. Referring to FIG. 1, the final state may be transmitted from a shift register located on-chip in quantum processor 126 to digital computer 102 via readout control system 128.

[0057] After step 608, method 600 stops, e.g., until called again. Method 600 may be performed simultaneously or near simultaneously for multiple qubits in a quantum processor and may be repeated iteratively to provide multiple solutions to a computation.

[0058] 5 and method 600. One or more control signals provided to either flux qubit 502 or QFP readout circuit 504 via control lines 510, 512, 524, and 530 as described above with reference to FIG. 5 and method 600 may be provided by analog signal lines, such as microwave lines. The analog lines are controlled by a digital processor to provide the control signals from a device (e.g., controller 118 of FIG. 1) at room temperature. In other embodiments, one or more control signals provided via control lines 510, 512, 524, and 530 may be provided by an on-chip control element. For example, the on-chip control element may be a single flux quantum source, such as the on-chip control element described in U.S. Patent Application Publication No. 2021 / 0248506, or the on-chip control element described in U.S. Provisional Patent Application No. 63 / 265605, which describes pulse sources that can be used to apply the ramp signal (e.g., a signal via second control line 512) or latch signal (e.g., a signal via either control lines 510 and 524) described above. As described in U.S. Provisional Patent Application No. 63 / 265,605, a pulse source may be configured to provide relatively fast control pulses to multiple qubits simultaneously or near-simultaneously. Such pulse sources may be used to simultaneously or near-simultaneously ramp and / or latch all or a portion of the qubits of a quantum processor. In some embodiments, a set of on-chip multiplexed pulse sources may be used to provide control signals to some of the qubits at different times. In some embodiments, control signals via analog control lines, such as from a room temperature source, may not provide sufficiently fast signals or may increase noise in the quantum processor. In these cases, providing an on-chip control source may be advantageous. The latching time scale used for latching readout may utilize either non-adiabatic or adiabatic evolution and may use a variety of time scales.

[0059] FIG. 7 is an exemplary graph 700 illustrating one example of a calculation using flux qubit parameters consistent with a fluxonium element. Graph 700 plots the instantaneous energy spectrum (measured in GHz) of the qubit alone as a function of time (measured in ns) to visualize the tilt and latch readout procedure for latching by ramping the qubit's tunnel barrier. That is, FIG. 7 shows the energy spectrum of a self-latching qubit not coupled to a latching QFP. The qubit starts at the degenerate point at time t=0. The two lowest energy states 702, 704 correspond to |0>=0L+0R and |1>=0L-0R, respectively, as shown in FIG. 3. Additional, higher excited states, e.g., state 706, exist, separated from the qubit's manifold by a large energy gap. These additional states can be represented in higher-order flux bases [|iL>, |iR>], i>1. The ramp is achieved by a Gaussian-smoothed step-edge bias applied to the qubit body, shown at 708 in graph 700, ending at t=4 ns. At that point, states |0> and |1> have smoothly transformed, at least approximately, to |0R> and |0L>, respectively. The latch is instantiated by a Gaussian-smoothed step-edge bias applied to the qubit's CJJ, shown at 710 in graph 710, ending at t=15 ns. This smooth evolution ensures, or at least increases the likelihood, that the lowest states (702, 704) will transform to |0R> and |0L> reliably, or at least with high probability. The two lowest states (702, 704) are well separated from the higher excited state (706) throughout the evolution. Time-domain simulations of the evolution, shown in Figure 7, confirm that a qubit initialized at |0 = |0L + |0R reaches the final state |0R, and a qubit initialized at |1 = |0L - |0R reaches the final state |0L. The tilting and self-latching of the qubit can therefore be described as an adiabatic transformation from the energy basis to the flux basis at the degeneracy point.

[0060] 8 is a graph 800 illustrating an exemplary tilt and latch readout procedure for a qubit coupled to a latching QFP. Graph 800 plots the instantaneous energy spectrum (in GHz) as a function of time (in ns) for a coupled qubit and latching QFP system using realistic example device parameters. The coupled qubit and latching QFP system may be qubit 502 and latching QFP 514 of FIG. 5. In graph 800, the system state is expressed as |qubit state>

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[0061] Once the qubit state is latched, the bit of qubit state information can be moved and / or copied to the readout element. The states of the qubit and latching QFP can then be reset. It is advantageous to reduce local energy dissipation in the region of the qubit as much as possible. In exemplary embodiments described herein, the bit of qubit state information can be copied from the latching QFP to a first shift register stage (SRS). In the example of FIG. 5, the state information from latching QFP 514 can be copied to first shift register stage 516. Once the bit has been copied to the SRS, the qubit and latching QFP can be adiabatically reset. The reset procedure proceeds by first removing the gradient bias, second lowering the tunnel barrier of the QFP, and third lowering the tunnel barrier of the first stage shift register. In embodiments in which the latch bias is applied directly to the qubit, the control signal can be removed from the CJJ of the flux qubit as a second operation of the reset procedure.

[0062] 9 is an exemplary embodiment of instantaneous intrinsic spectra (measured in GHz) versus time (measured in ns) for reading and resetting a qubit. Shown is both an intrinsic spectrum graph 900 and a transition diagram 902 illustrating bit transfer of qubit state information. In graph 900, states are labeled using the compact notation |qubit, QFP, SRS>. In transition diagram 902, solid dots indicate the presence of a bit, and hollow dots represent elements that have been reset.

[0063] The evolution in Figure 9 begins at t = 0, indicated by 904, when the qubit is at the degeneracy point and the tunnel barrier is suppressed by both the latching QFP and the first SRS CJJ. Similar to graph 800 in Figure 8, the qubit is fully tilted at t = 12 ns, indicated by 906, and the QFP is latched at t = 24 ns, indicated by 908. The first SRS is latched at t = 36 ns, indicated by 910. As shown in graph 900, |0,0,0> in the energy basis is mapped to |0R,0L,0R> in the flux basis, and |1,0,0> in the energy basis is mapped to |0L,0R,0L> in the flux basis. Furthermore, as shown in transition diagram 902, at t = 36 ns, the qubit state is copied to all three elements. Bits of information describing the state of a qubit can be copied to a subsequent SRS in a manner similar to that described herein, moving the data any distance away from the qubit. For simplicity, the sequence shown in Figure 9 is limited to a single SRS. All operations from t = 0 to t = 36 ns are considered copy / move operations because no information is erased.

[0064] The act of resetting the system begins at t = 39 ns, indicated at 912, by undoing the ramp and latch procedure in the same time sequence of events. The reset procedure begins with the removal of the ramp applied to the qubit. If the system is in the |0R,0L,0R> or |0L,0R,0L> state at the start of the reset, the system will return to the ground state after the removal of the ramp that resets the qubit state. The removal of the latching QFP tunnel barrier, initiated at t = 45 ns, indicated at 914, introduces two additional states into the low-energy manifold, but these states do not mix with the degenerate ground state and therefore do not move the system away from the ground state. This resets the state of the latching QFP. Because the magnetic moment of the latching QFP is suppressed, the latching QFP is decoupled from the first SRS, and the qubit is again isolated from the readout circuitry. The resulting low-energy spectrum is identical to that found at t = 0, except that it is doubly degenerate due to the two degenerate flux bases of the first SRS.

[0065] Because a copy of the bit remains in the first SRS, the information is not erased until the latching QFP tunnel barrier is lowered. Lowering the tunnel barrier of the first SRS erases the qubit state information, resulting in dissipation according to Landauer's principle. Once the tunnel barrier lowering begins at t = 57 ns, as shown at 916, a noticeable change occurs in the low-energy eigenspectrum. In graph 900, a pair of small-gap anticrossings is observed at t = 58 ns, as shown at 918, due to the lifting of the degeneracy of the low-energy manifold. If the system was in state |0L,0R,0L> before the reset, the system passes through these anticrossings nonadiabatically. Following these anticrossings, the system is found to be in state |0,0,1> with nonzero probability. The energy of this state rises rapidly over time. Eventually, a relaxation event |0,0,1> → |0,0,0> occurs, returning the entire system to the ground state. Provided there is a reservoir near the first SRS from which the first SRS can emit photons, the energy dissipation is localized away from the qubit. Those skilled in the art will appreciate that long chains of QFP shift register stages can be constructed to adiabatically move the bit away from the qubit before erasure. In some embodiments, the energy dissipation by the final SRS can also be shifted elsewhere by applying an appropriate flux bias to the final SRS as its tunnel barrier is suppressed using feedback from a final measurement device.

[0066] In discussing the ramp and latch procedure shown in Figure 8, we noted that the nonadiabatic evolution from the initial state |1,0> to the latched state |0R,0R> does not necessarily result in a read error. However, such nonadiabatic evolution can be problematic at reset, as shown by the location of a state similar to |0R,0R,0L> for the qubit-QFP-SRS system at t = 36 ns (910). Reaching this state involves traversing multiple small-gap anticrossings as the QFP and SRS tunnel barriers rise. As the QFP tunnel barrier is suppressed, additional small-gap anticrossings are encountered. In the best-case scenario, the system reaches a state |1,0,0R> or |1,0,0L> after the QFP barrier is suppressed. The system reaches |1,0,0> after suppressing the SRS tunnel barrier by nonadiabatically traversing a small-gap anticrossing at t = 58 ns (918). In this scenario, the system can only reach the ground state via qubit relaxation |1,0,0>→|0,0,0>. In the worst-case scenario, the qubit will not relax until the next operation, resulting in a reset error. For this reason, it is advantageous for the ramp and latch procedure to be adiabatic. This can be achieved by modifying the time-dependent control sequence as needed. In some embodiments, modifying the time-dependent control sequence may include extending one or more of the periods shown in FIG. 9. For example, in some embodiments, extending the time between 906 and 908 can reduce the likelihood of the system exciting, mitigating the risk later in the evolution.

[0067] FIG. 10 is a flow diagram of an exemplary method 1000 for solving a computational problem in a hybrid computing system that can be employed in accordance with the present systems, apparatus, and methods. Method 1000 may be used, for example, with exemplary circuit 500 of FIG. 5. In some embodiments, method 1000 may be performed in a hybrid computing system that includes at least one digital or classical processor in communication with at least one quantum processor. For example, method 1000 may be performed by computing system 100 of FIG. 1. The quantum processor may include, for example, a flux qubit having a body loop interrupted by a compound Josephson junction (CJJ), such as flux qubit 200 of FIG. 2 and flux qubit 502 of FIG. 5. The digital or classical processor may provide control signals or instructions to the quantum processor to perform the present method.

[0068] Although method 1000 includes even-numbered operations 1002-1014, those skilled in the art will appreciate that the number of operations shown is exemplary and that in some embodiments, certain operations may be omitted, additional operations may be added, and / or the order of operations may be changed.

[0069] The method 1000 may be initiated, for example, in response to a call or invocation from another routine.

[0070] At 1002, one or more programming control signals are applied by a digital processor to a flux qubit, the flux qubit being programmed in an energy basis, to program the quantum processor based on a computational problem. In some embodiments, the computational problem may be, for example, a surface code problem or another gate model computation.

[0071] At 1004, the quantum processor is instructed by the digital processor to evolve to a processor final state, the processor final state including qubit final states of the flux qubits expressed in an energy basis.

[0072] At 1006, a first control signal is applied by one of the digital processor and the quantum processor to transmit a flux bias to the body loop of the flux qubit to transform the qubit final state of the flux qubit from the energy basis to the flux basis.

[0073] At 1008, a second control signal is applied by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit. In some embodiments, the second control signal can be applied to the CJJ of the flux qubit, such as CJJ 506 of qubit 502 in the exemplary embodiment of FIG. 5. In other embodiments, the second control signal can be applied to the CJJ of a latching QFP coupled to the flux qubit, such as latching QFP 514 coupled to qubit 502 as described above. As described above, the control signal may be applied via analog lines at room temperature or by on-chip control elements.

[0074] At 1010, a third control signal is applied by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit into the shift register. In some embodiments, the third control signal may be applied through a latching quantum flux parametron (QFP), which is coupled to the flux qubit by magnetic and / or galvanic coupling, such as in the exemplary embodiment of FIG. 5 showing qubit 502 and latching QFP 514. In some embodiments, the third control signal raises the tunnel barrier of the first stage of the shift register.

[0075] At 1012, one or more fourth control signals are applied by one of the digital processor and the quantum processor to transmit the qubit final states of the flux qubits through the shift register.

[0076] At 1014, the qubit final states are received by the digital processor. The qubit final states may represent values ​​that can be post-processed or transformed to provide values ​​in a solution to a computational problem, such as a solution to a computational problem, a value of one variable in a solution to a computational problem, or a value of a subproblem or clustering problem.

[0077] After performing 1014, method 1000 stops, e.g., until called again. Method 1000 may be performed iteratively or simultaneously on multiple qubits in a quantum processor to provide one or more sample solutions, and may be repeated iteratively to provide multiple sample solutions to a computational problem. In some embodiments, method 1000 may also include excluding control signals.

[0078] The methods, processes, or techniques described above can be implemented by a series of processor-readable instructions stored on one or more non-transitory processor-readable media. Some examples of the methods, processes, or techniques described above can be implemented by a dedicated device, such as an adiabatic quantum computer or quantum annealer, gate, or circuit, a model quantum computer, or a system that programs or otherwise controls the operation of an adiabatic quantum computer, quantum annealer, gate, or circuit, a model quantum computer, e.g., a computer including at least one digital processor. While the methods, processes, or techniques described above may include various operations, those skilled in the art will understand that certain operations may be omitted and / or additional operations may be added in alternative examples. Those skilled in the art will understand that the order of operations depicted is for illustrative purposes and may be altered in alternative examples. Some example operations or operations of the methods, processes, or techniques described above are performed iteratively. Some operations of the methods, processes, or techniques described above can be performed during each iteration, after multiple iterations, or at the end of all iterations.

[0079] The above description of the illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, those skilled in the art will recognize that various equivalent modifications can be made without departing from the spirit and scope of the disclosure. The teachings of the various embodiments described herein are not limited to the exemplary methods of quantum computing generally described above, but may also be applied to other quantum computing methods.

[0080] The various embodiments described above can be combined to provide further embodiments. All co-filed U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications referenced herein and / or listed in Application Data Sheets are incorporated herein by reference in their entirety, including, but not limited to, the following: International Patent Application No. PCT / US2022 / 37457 (Kineon Qubits) U.S. Provisional Patent Application Nos. 63 / 356663 (Surface Code 1), 63 / 390185 (Surface Code 2), and 63 / 265605 (Cold Control) U.S. Patent Application Publication No. 2021 / 0248506 (Projection Source) U.S. Patents Nos. 10,528,886 (QFP shift register), 9,768,371 (Josephson junction fabrication), and 8,536,566 (CCJJ)

[0081] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments to which such claims can pertain and their equivalents. Accordingly, the claims are not limited to the present disclosure.

Claims

1. 1. A method of reading out a state of a flux qubit of a quantum processor after performing a computation using the quantum processor with the flux qubit represented in an energy basis, the computation resulting in a final state of the flux qubit represented in the energy basis, the flux qubit including a body loop interrupted by a Compound Josephson Junction (CJJ), comprising: applying a flux bias to the body loop of the flux qubit to transform the final state of the flux qubit from the energy basis to a flux basis; applying a first control signal to latch the final state of the flux qubit expressed in the flux basis; copying the final state of the flux qubit expressed in the flux basis into a shift register; transmitting the final state of the flux qubit externally from the quantum processor via the shift register; and A method comprising:

2. 2. The method of claim 1 , wherein applying a first control signal to latch the final state of the flux qubit expressed in the flux basis comprises applying the first control signal to the CJJ of the flux qubit.

3. 3. The method of claim 2, wherein copying the final state of the flux qubit expressed in the flux basis to a shift register comprises applying a second control signal to raise a tunnel barrier of a CJJ in a first stage of the shift register.

4. after transmitting the final states of the flux qubits out of the quantum processor via the shift register; removing the flux bias from the body loop of the flux qubit; Releasing the first control signal from the CJJ of the flux qubit; Releasing the second control signal latching the state of the first stage of the shift register; The method of claim 3 further comprising:

5. 5. The method of claim 1, wherein applying a first control signal to latch the final state of the flux qubit expressed in the flux basis comprises applying a first control signal via an analog line.

6. 5. The method of claim 1, wherein applying a first control signal to latch the final state of the flux qubit comprises applying a first control signal to the quantum processor by a controller.

7. 2. The method of claim 1 , wherein copying the final state of the flux qubit represented in the flux basis to the shift register comprises copying the final state of the flux qubit represented in the flux basis to the shift register via a latching quantum flux parametron (QFP), the latching QFP being coupled to the flux qubit by at least one of magnetic coupling and galvanic coupling.

8. 8. The method of claim 7 , wherein applying a first control signal to latch the final state of the flux qubit expressed in the flux basis comprises applying a first control signal to a CJJ of the latching QFP.

9. 9. The method of claim 8 , wherein copying the final state of the flux qubit expressed in the flux basis to a shift register comprises applying a second control signal to raise a tunneling barrier of a first stage of the shift register.

10. after transmitting the final states of the flux qubits out of the quantum processor via the shift register; removing the flux bias from the body loop of the flux qubit; Releasing the first control signal latching the state of the latching QFP; Releasing the second control signal latching the state of the first stage of the shift register; The method of claim 9 further comprising:

11. 1. A method of solving a computational problem in a hybrid computing system, the hybrid computing system including a digital processor in communication with a quantum processor, the quantum processor including a flux qubit having a body loop interrupted by a compound Josephson junction (CJJ), the method comprising: applying, by the digital processor, one or more programming control signals to the flux qubits, the flux qubits being energy-basis programmed, to program the quantum processor based on the computational problem; instructing, by the digital processor, the quantum processor to evolve to a processor final state that includes the flux qubit in a qubit final state expressed in the energy basis; applying a first control signal by one of the digital processor and the quantum processor to transmit a flux bias to the body loop of the flux qubit to transform the qubit final state of the flux qubit from the energy basis to a flux basis; applying a second control signal by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit; applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit into a shift register; applying one or more fourth control signals by one of the digital processor and the quantum processor to transmit the qubit final states of the flux qubits through the shift register; receiving the qubit final states by the digital processor; and A method comprising:

12. 12. The method of claim 11 , wherein applying a third control signal by one of the digital processor and the quantum processor to copy the final qubit state of the flux qubit to a shift register comprises applying a third control signal by one of the digital processor and the quantum processor to copy the final qubit state of the flux qubit to a shift register via a latching quantum flux parametron (QFP), the latching QFP being coupled to the flux qubit by at least one of magnetic coupling and galvanic coupling.

13. 12. The method of claim 11 , wherein applying a second control signal by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit comprises applying a second control signal by one of the digital processor and the quantum processor to the CJJ of the flux qubit.

14. 13. The method of claim 12, wherein applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register comprises applying a third control signal by one of the digital processor and the quantum processor to raise a tunneling barrier of the first stage of the shift register.

15. removing, by one of the digital processor and the quantum processor, the first control signal from the body loop of the flux qubit; releasing the second control signal by one of the digital processor and the quantum processor latching the qubit final state of the flux qubit; Releasing the third control signal latching the qubit final state of the first stage of the shift register; and The method of claim 13 further comprising:

16. 12. The method of claim 11 , wherein applying a second control signal by one of the digital processor and the quantum processor to latch the qubit final state of the flux qubit comprises applying a second control signal by one of the digital processor and the quantum processor to a CJJ of a latching QFP coupled to the flux qubit.

17. 16. The method of claim 15, wherein applying a third control signal by one of the digital processor and the quantum processor to copy the qubit final state of the flux qubit to a shift register comprises applying a third control signal by one of the digital processor and the quantum processor to raise a tunneling barrier of the first stage of the shift register.

18. releasing the first control signal by one of the digital processor and the quantum processor; releasing the second control signal by one of the digital processor and the quantum processor; releasing the third control signal by one of the digital processor and the quantum processor; 17. The method of claim 16, further comprising:

19. 19. The method of any one of claims 11 to 18, wherein applying a second control signal to latch the qubit final state of the flux qubit comprises applying the second control signal via an analog line.

20. 19. The method of any one of claims 11 to 18, wherein applying a second control signal to latch the qubit final state of the flux qubit comprises instructing an on-chip control device to apply the second control signal.

21. 19. The method of any one of claims 11 to 18, wherein applying one or more programming control signals to the flux qubits by the digital processor to program the quantum processor based on the computational problem comprises applying one or more programming control signals to the flux qubits by the digital processor to program the quantum processor based on a surface code problem.

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