Speculative store-to-load forwarding

Abstract

A method for performing predictive store-to-load forwarding on a processor includes receiving a load instruction; obtaining a predicted store queue ID from a prediction table based on an address of the load instruction; and performing a predictive store-to-load forwarding process including retrieving a value from a store queue based on the store queue ID while performing a parallel verification process on the predicted store queue ID, the method further including determining that the parallel verification process is successful; and in response, reading the value for the load instruction from the store queue.

Description

[Background technology]

[0001] In modern computing, loads from and stores to memory are operations that are critical to program performance. Many modern computers support store-to-load forwarding (STLF), which allows data to be forwarded from a store instruction to a load instruction in the processing pipeline, rather than writing data to memory with a store instruction and reading the same data back with a load instruction.

[0002] To support STLFs, a processor may maintain a store queue (SQ) that tracks all pending stores. When a subsequent instruction is executed, the processor can check the store queue to determine if the data to be loaded is in the processor's internal queue; if so, the store-to-load forwarding can be performed by retrieving the data from the internal store rather than from memory. However, as the recent execution window expands, the size of the store queue also increases. For example, a modern processor can have hundreds of pending store instructions in the store queue. Therefore, reading the entire large store queue for an STLF can actually degrade performance. Summary of the Invention

[0003] This specification describes a method and system for providing predictive store-to-load forwarding that can significantly improve the overhead of STLFs with large store queues and execution windows. For example, a large store queue can block instruction execution. The prediction method disclosed herein can achieve an efficient STLF with large store queues by, for example, predicting the location of store instructions within the store queue rather than searching the entire store queue.

[0004] Particular embodiments of the subject matter described in this specification can be implemented to realize one or more of the following advantages.

[0005] The described methods and systems improve the performance of central processing units (CPUs) with large store queues, e.g., large numbers of instructions, that would normally pose challenges to efficient STLFs. For example, the described methods and systems enable STLFs to execute more efficiently, even with very large store queues, e.g., store queues with 100 or 1000 entries, that would traditionally reduce the efficiency of STLFs. In some implementations, the methods and systems can improve CPU performance by approximately 1-2%.

[0006] The details of one or more embodiments of the subject matter herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 2 is a diagram of an exemplary execution window containing instructions. [Figure 1B] FIG. 1 is a diagram of the execution stages of the STLF process for an instruction. [Figure 2] FIG. 1 is a diagram of execution stages of a predictive STLF process. [Figure 3] 1 is an exemplary table that can be used for a predictive STLF process. [Figure 4] 1 is a flowchart illustrating a method for a predictive STLF process. [Figure 5] 1 is an exemplary computing environment in which a predictive STLF process can be implemented. DETAILED DESCRIPTION OF THE INVENTION

[0008] Like reference numbers and designations in the various drawings refer to like elements.

[0009] 1 is a diagram of an exemplary execution window 100 that includes instructions and the execution stages of the STLF process for the instructions. For example, the execution window 100 includes a store instruction 102 that writes data in register R1 to a location in memory, such as given by an address. In the illustrated example, the store instruction 102 writes data into a memory location given by the address value in register R4 plus a 4-byte offset (R4+4).

[0010] Execution window 100 also includes a load instruction 104 that reads data from an address into register R2. In practice, data for loads and stores may be read from or written to one or more caches between the processor and main memory, such as a DRAM device. For simplicity, the examples herein omit details of intermediate caches, so that a write to or read from memory encompasses a write to or read from one or more intermediate caches.

[0011] In the illustrated example, load instruction 104 reads data from the same address (R4+4) as store instruction 102. The execution window also includes add instruction 106, which can only execute after load instruction 104 executes.

[0012] Therefore, the CPU can execute the add instruction 106 using the STLF procedure without waiting for the store instruction 102 and the load instruction 104 to complete. To do so, the CPU can store the data in register R1 in an internal store queue. Then, when the load 104 executes, the CPU can compare the address of the load instruction 104 with the addresses in the store queue. If there is a match, the CPU can transfer the data from the store queue into register R2 without waiting for the store instruction 102 to complete. The add instruction 106 can then execute using the transferred data stored in register R2.

[0013] Without the STLF, a CPU would write data to memory using, for example, a store instruction 102, and after the data is written, read the data from memory using, for example, a load instruction, and then execute an add instruction. Waiting until the data is written to memory before executing the rest of the instruction can degrade CPU performance by approximately 5-10%. However, the STLF stage shown in FIG. 1A can be implemented to transfer data from the store instruction to the load instruction so that the CPU does not have to wait until the data is written to memory.

[0014] 1B is a diagram of execution stages 110 of the STLF process for instructions 102, 104, 106 contained in execution window 102. In the illustrated example, the STLF process executes in five stages, although other implementations may execute more or fewer stages. In a first address generation (AGEN) stage 112, the CPU reads load instruction 104 and determines the address (VA) corresponding to load instruction 104.

[0015] In search stage 114, the CPU searches the store queue. In one example, the CPU may include, for example, a content addressable memory (CAM) structure that holds executing memory instructions and supports concurrent searches. The CPU searches the store queue to determine whether data for the executing store instruction is present. In the illustrated example, store instruction 102 is in the execution window before load instruction 104, so the store queue contains the store instruction that corresponds to load instruction 104. When a large store queue exists, this may take multiple cycles, e.g., many cycles.

[0016] In the third stage 116, the CPU reads data from the store queue after locating the appropriate store instruction. For example, the CPU may read data that is being written to memory by a store instruction. Because the CPU can read this data from the store queue, the CPU does not have to wait for the data to be written to memory in order to use it in, for example, a load instruction.

[0017] In a fourth stage 118, the CPU executes a bypass stage to marshal the data and provide the data retrieved from the store queue to one or more consumer instructions waiting for that data. For example, the CPU may execute the load instruction 104 and the add instruction 106 after reading the corresponding data from the store queue.

[0018] In a fifth stage 120, the CPU writes the data back to the specified memory address, such as, for example, a destination register. Writing the data back includes writing the read data to the specified memory address, such as, for example, a destination register. In some implementations, the CPU can bypass the read data to dependent instructions, such as, for example, an ADD instruction, before the specified memory address is updated, such as, for example, during a bypass stage.

[0019] As mentioned above, efficiently completing the STLF process becomes more difficult for large store queues. For example, a larger store queue has more indices to search, and therefore takes longer to complete the search stage 114. Even with an efficient search algorithm, searching a large store queue, e.g., 100 entries, can take longer than one cycle. This results in longer wait times for the end user.

[0020] FIG. 2 is a diagram of execution stages 200 of a predictive STLF process. Using a predictive STLF can avoid consuming multiple cycles to search a large store queue. The exemplary process can instead provide a predictable and limited number of cycles to determine the store queue index. The illustrated predictive STLF process, similar to the STLF process of FIG. 1, executes two separate processes in parallel over five stages. However, the predictive STLF process can achieve efficient results even with store queues of over 100 entries. In some implementations, more or fewer stages can be executed.

[0021] In the first stage 202, the CPU reads the load instruction and determines the virtual address corresponding to the load instruction. For example, the CPU can read the load instruction because the load instruction is within its execution window. Instead of executing the load instruction, which would require waiting for a store instruction to write data to the memory address before reading it, the CPU executes the remaining stages of the STLF process.

[0022] In a second stage 204, the CPU performs a prediction process to generate a predicted store queue index for the store instruction containing the given address. The index may represent the location of the store instruction in the store queue. For example, the CPU may use a prediction table containing the address and the store queue index to point the CPU to the location of the appropriate store instruction in the store queue. An exemplary prediction table is further described below. Because the prediction table is much smaller than the store queue, predicting the store queue index can be easily accomplished in one cycle.

[0023] In the third stage 206, the CPU reads data from the store queue after generating the predicted location of the store instruction. For example, the CPU may read data that is being written to memory by a store instruction. Because the CPU can read this data from the store queue, the CPU does not need to wait for the data to be written to memory in order to use it in, for example, a load instruction.

[0024] In a fourth stage 208, the CPU aligns the data and, for example, bypasses the data to the user and / or required instructions. For example, the CPU may execute the load instruction 104 and the add instruction 106 after reading the corresponding data from the store queue. In a fifth stage 120, the CPU writes the data back to the specified memory address, such as, for example, a destination register.

[0025] The predictive STLF process includes a parallel verification process 220 that executes concurrently with the predictive STLF process. The parallel verification process 220 verifies whether the predictive STLF process correctly predicted the index of the store instruction in the store queue, for example, during the second stage 204. In the first stage 222, the CPU reads the load instruction and determines the virtual address corresponding to the load instruction. For example, the load instruction is within the execution window, so the CPU can read the load instruction.

[0026] In a second stage 224, the CPU searches the store queue to determine whether a store instruction exists for the given virtual address. In the illustrated example, the store instruction exists in the execution window before the load instruction, so the store queue contains the store instruction that corresponds to the load instruction. During the parallel verification process 220, the search may take two cycles because the speculative STLF process is running simultaneously. This reduces the latency impacted to the end user, for example, during the STLF process of FIG. 1.

[0027] In a third stage 226, the CPU compares the search result with the predicted store queue index. If the search result index is the same as the predicted store queue index, then the parallel verification process 220 succeeds and determines that the predictive STLF process is successful. If the search result index is different from the predicted store queue index, then the parallel verification process determines that the predictive STLF process is unsuccessful. If the predictive STLF process is unsuccessful, the CPU updates the predicted store queue index so that it is the same as the search result index. The CPU may also update other parameters of the predictive STLF process, such as parameters in a prediction table. If the parallel verification process 220 determines that the predictive STLF process is unsuccessful, then the CPU executes a fourth stage 228.

[0028] In a fourth stage 228, the CPU replays the load function according to the search results determined in the third stage 226. For example, if only a few instructions were executed according to an incorrect prediction, then those instructions can be executed again with the correct data determined by the parallel verification process 220. Other instructions that were unrelated to the incorrect prediction can continue to execute unsuppressed. In some implementations, if many instructions were executed according to an incorrect prediction, the CPU can perform a lightweight replay, in which instructions that executed after the incorrect prediction can be executed correctly again. This can be useful, for example, if the incorrect prediction propagates to many other instructions.

[0029] FIG. 3 illustrates an exemplary table 300 that can be used in a predictive STLF process. For example, table 300 can be used as a predictor table for predictive STLF process 200 of FIG. 2. Table 300 can be sized to hold a desired number of indexes. For example, in the illustrated embodiment, table 300 can hold 16 store queue indexes. Storing 16 store queues at a time can allow the predictive STLF process to efficiently transfer data given a large store queue, e.g., with 100 entries. The size of table 300 can be scaled to allow the predictive STLF process to efficiently transfer data given differently sized store queues. For example, a store queue with more than 200 entries can use a larger table. For each index, table 300 can hold a store PC value 302, a load PC value 304, a store queue index 306, and an age value 308.

[0030] When the CPU begins processing instructions from the execution window, the CPU encounters a store instruction as described above. When the CPU encounters the store instruction, the CPU populates table 300 according to the store instruction. Similarly, when the CPU encounters a load instruction, the CPU executes the STLF using table 300 as described above and populates table 300 according to the load instruction. For example, the CPU can populate the table with a store PC value 302, a load PC value 304, a store queue index 306, and an age value 308. The age value 308 represents the order in which store instruction values ​​are maintained in table 300. The age value can be used to determine which entry to replace when a new predicted value needs to be inserted into the table. The CPU can then begin executing the store instruction.

[0031] When the CPU encounters a store instruction, the CPU searches table 300 for a corresponding store PC value 302. For example, store PC value 302 may represent the virtual address received from the store instruction. If table 300 contains the corresponding store PC value, the CPU updates store queue index 306 to correspond to the correct store PC value. For example, the CPU updates store queue index 306 to contain a value that represents the position of the store instruction in the store queue. The CPU also updates age value 308 to indicate that the value is newly stored. If table 300 does not contain store PC value 302, then the CPU updates the table to include store PC value 302. The CPU then updates store queue index 306 to correspond to the correct store PC value. The CPU also updates age value 308 to indicate that the value is newly stored.

[0032] When the CPU encounters a load instruction, the CPU searches table 300 for a corresponding load PC value 304. For example, load PC value 304 may represent the virtual address received from the load instruction. If table 300 contains the corresponding load PC value, the CPU uses the corresponding store queue index 306 to predict where in the store queue the load PC value should be forwarded from. This information can be conveyed to a load store unit (LSU) that uses it to execute the load instruction. The CPU also updates age value 308 to indicate that these values ​​are newly stored. If table 300 does not contain the corresponding load PC value, the CPU determines the store queue index, for example, through a parallel verification process. The CPU updates table 300 with store queue index 306. The CPU also updates age value 308 to indicate that these values ​​are newly stored. If the parallel verification process does not identify a store instruction to which the load instruction should be forwarded, then the load instruction can complete execution with data read from the cache.

[0033] 4 is a flowchart illustrating an example method of predictive STLF process 400. The example process may be performed by one or more processors. The example process is described as being performed by, for example, processor 502 of FIG. 5, configured in accordance with this specification. Processor 502 is described further below.

[0034] The processor may dispatch an instruction, for example, from the execution window (402). For example, the processor may read an instruction from the execution window and dispatch the instruction according to the content of the instruction. If the instruction is a load instruction or a store instruction, the processor may dispatch the instruction according to the method 400.

[0035] The processor determines whether the instruction matches a value stored in a store queue prediction table (SPT) (404). For example, table 300 of FIG. 3 includes a store PC value 302, a load PC value 304, a store queue index 306, and an age value 308. If the contents of the instruction match the store PC value or the load PC value, then the instruction matches a value stored in the prediction table. The processor can also determine when the contents of the instruction do not match a value stored in the prediction table.

[0036] If the instruction does not match a value stored in the prediction table, the processor determines whether the instruction is a load (406). If the instruction is a load, the processor updates the prediction table and continues re-executing the instruction (418), as described further below.

[0037] If the instruction matches a value stored in the prediction table, the processor may then determine whether the instruction is a load instruction or whether the instruction is a store instruction (408).

[0038] If the processor determines that the instruction is a store instruction, then the processor may update the store queue index in the prediction table (410). For example, the processor may update the store queue index to include a value that represents the position of the store instruction in the store queue. The processor may also update the age value in the prediction table to represent that the value is newly stored.

[0039] The processor then executes the store instruction (412). For example, the processor may forward the store instruction to a load-store unit (LSU) for execution. The contents of the store instruction are stored at a virtual address in memory.

[0040] If the processor determines that the instruction is a load instruction, then the processor may perform a predictive STLF process (414). For example, the processor may predict the index of a store instruction that includes the virtual address provided in the load instruction. For example, the processor may use a prediction table that includes the address and the store queue index to point the processor to the location of the appropriate store instruction in the store queue. After the processor finds the location of the appropriate store instruction, it may read data from the store queue. For example, the processor may read data that is being written to memory by the store instruction. The processor may align the data, for example, bypassing the data to the user and / or required instructions.

[0041] The processor may also execute a parallel verification process (416) that executes concurrently with the predictive STLF. The parallel verification process verifies whether the predictive STLF process correctly predicted the index of the store instruction in the store queue. The processor searches the store queue to determine whether a store instruction exists for the virtual address given by the load instruction. The processor compares the result of the search with the predicted store queue index. If the index of the search result is the same as the predicted store queue index, then the parallel verification process is successful and the predictive STLF process is determined to be successful. If the index of the search result is different from the predicted store queue index, then the parallel verification process is determined to be unsuccessful.

[0042] If the prediction is incorrect, e.g., the predictive STLF process fails, then the processor updates the prediction table and re-executes the instruction (418). For example, the processor replays the load function according to the search result determined by the parallel verification process. For example, if only a few instructions were executed according to an incorrect prediction result, then those instructions can be executed again with the correct data determined by the parallel verification process. Other instructions that were unrelated to the incorrect prediction result can continue to execute unsuppressed. In some implementations, if many instructions were executed according to an incorrect prediction result, the CPU can flush all of the instructions that were executed after the incorrect prediction result and re-execute all of the instructions. This can be useful, for example, if the incorrect prediction result propagates to many other instructions. Once the instructions are re-executed using the correct data, the processor can move to the next instruction in the execution window.

[0043] If the prediction is correct, e.g., the predictive STLF process is successful, then the processor updates the prediction table and executes the load instruction (420). For example, the load instruction and store queue index may be forwarded to a load-store unit (LSU) that uses the load instruction and store queue index to execute the load instruction. The processor may also update the age values ​​in the prediction table to indicate that these values ​​are newly stored.

[0044] FIG. 5 illustrates an exemplary computing environment 500 capable of executing a predictive STLF process. The environment includes a processor 502 and a memory 504, such as a cache, random access memory (RAM), or read-only memory (ROM). The processor 502 can execute the predictive STLF process as described above. A load-store unit (LSU) 506 includes a predictive STLF module 508, which includes a prediction table 510 and a store queue 512. The prediction table 510 may be similar to, for example, the prediction table 300 of FIG. 3. The store queue 512 may include a content-addressable memory (CAM) structure that holds executing memory instructions and supports concurrent lookup. The LSU 506 communicates with a main execution logic 514 to send and receive data. For example, communication 516 between the LSU and the main execution logic may include store instructions, load instructions, stored values, etc. The processor 502 communicates with the memory 504 to send and receive data. For example, communications 518 between the processor and memory may include memory addresses, stored values, and the like.

[0045] Embodiments of the subject matter and functional operations described herein can be implemented in digital electronic circuitry, in computer hardware, including the structures disclosed herein and structural equivalents thereof, or in one or more combinations thereof. The processes and logic flows can also be performed by special purpose logic circuitry, such as an FPGA or ASIC, or by a combination of special purpose logic circuitry and one or more programmed computers.

[0046] In addition to the above embodiments, the following embodiments are also innovative.

[0047] Embodiment 1 is a method for performing speculative store-to-load forwarding on a processor, the method comprising: receiving a load instruction; obtaining a predicted store queue ID from a prediction table based on the address of the load instruction; retrieving a value from a store queue based on the store queue ID while performing a parallel verification process on the predicted store queue ID; and performing a speculative store-to-load forwarding process including: determining that the parallel verification process was successful; and in response, reading the value for the load instruction from the store queue; The method includes:

[0048] Embodiment 2 is the method of claim 1, further comprising receiving a store instruction; and populating the prediction table based on the store instruction.

[0049] Embodiment 3 is the method according to any one of embodiments 1 to 2, further comprising reloading some of the load instructions if the verification process fails.

[0050]

[0013] Embodiment 4 is the method according to any one of embodiments 1 to 3, wherein the parallel verification process includes searching the store queue for the address of the load instruction.

[0051] In a fifth embodiment, the parallel verification process includes updating the prediction table upon successful prediction.

[0052]

[0013] Example 6 is the method of example 5, wherein updating the prediction table includes updating a value related to an age of the load instruction.

[0053] Embodiment 7 is the method according to any one of embodiments 1 to 6, wherein the parallel verification process includes updating the prediction table upon failure of a prediction.

[0054] Example 8 is the method of example 7, wherein updating the prediction table includes updating a value related to the store queue ID.

[0055] A ninth embodiment is the method according to any one of the first to eighth embodiments, further comprising receiving a store instruction.

[0056]

[0023] Example 10 is the method of example 9, further comprising updating the predicted store queue ID based on the received store instruction.

[0057]

[0023] Example 11 is the method of example 9, further comprising: executing the store instruction after updating the predicted store queue ID.

[0058]

[0023] Embodiment 12 is a system for performing speculative store-to-load forwarding, the system comprising: a memory configured to store instructions; a processor for executing the instructions to perform an operation; and the operation comprises: receiving a load instruction; obtaining a predicted store queue ID from a prediction table based on the address of the load instruction; retrieving a value from a store queue based on the store queue ID while performing a parallel verification process on the predicted store queue ID; and performing a speculative store-to-load forwarding process including: determining that the parallel verification process was successful; and in response, reading the value for the load instruction from the store queue; The system includes:

[0059]

[0023] Example 13 is the system of example 12, further comprising receiving a store instruction and populating the prediction table based on the store instruction.

[0060] Embodiment 14 is the system according to any one of embodiments 12 to 13, further comprising reloading some of the load instructions if the verification process fails.

[0061] A fifteenth embodiment is the system according to any one of the twelfth to fourteenth embodiments, wherein the parallel verification process includes searching the store queue for the address of the load instruction.

[0062] A sixteenth embodiment is the system according to any one of the twelfth to fifteenth embodiments, wherein the parallel verification process includes updating the prediction table when the prediction is successful.

[0063]

[0023] Embodiment 17 is the system of embodiment 16, wherein updating the prediction table includes updating a value related to an age of the load instruction.

[0064] An eighteenth embodiment is the system according to any one of the twelfth to seventeenth embodiments, wherein the parallel verification process includes updating the prediction table when a prediction fails.

[0065] Example 19 is the system of example 18, wherein updating the prediction table includes updating a value related to the store queue ID.

[0066] A twentieth embodiment is a system according to any one of the twelfth to nineteenth embodiments, further comprising receiving a store instruction.

[0067] Embodiment 21 is the system of embodiment 20, further comprising updating the predicted store queue ID based on the received store instruction.

[0068] Embodiment 22 is the system of embodiment 20, further comprising executing the store instruction after updating the predicted store queue ID.

[0069] While the specification contains many specific implementation details, these should not be construed as limiting the scope of any invention or the scope of patentable subject matter, but rather as descriptions of features that may be unique to particular embodiments of a particular invention. Certain features described herein as separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented in multiple embodiments, either separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and originally claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to subcombinations or variations of the subcombination.

[0070] Similarly, while operations are shown in the figures in a particular order, this should not be understood as requiring such operations to be performed in the particular order or sequential order shown, or that all of the illustrated operations be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the program components and systems described may generally be integrated into a single software product or packaged into multiple software products.

[0071] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims may be performed in a different order and still produce desirable results. By way of example, the processes depicted in the accompanying figures do not necessarily require the particular order shown or sequential order to achieve desirable results. In certain cases, multitasking and parallel processing may be advantageous.

Claims

1. 1. A method for performing speculative store-to-load forwarding on a processor, the method comprising: receiving a load instruction; obtaining a predicted store queue ID from a prediction table based on the address of the load instruction; retrieving a value from a store queue based on the store queue ID while performing a parallel verification process on the predicted store queue ID; and performing a speculative store-to-load forwarding process including: determining that the parallel verification process was successful; and and in response, reading the value for the load instruction from the store queue.

2. 2. The method of claim 1, further comprising receiving a store instruction; and populating the prediction table based on the store instruction.

3. The method of any one of claims 1 to 2, further comprising reloading some load instructions if the verification process fails.

4. The method of any one of claims 1 to 3, wherein the parallel verification process includes searching the store queue for the address of the load instruction.

5. The method of any one of claims 1 to 4, wherein the parallel verification process includes updating the prediction table upon successful prediction.

6. The method of claim 5 , wherein updating the prediction table comprises updating a value related to the age of the load instruction.

7. The method of any one of claims 1 to 6, wherein the parallel verification process includes updating the prediction table upon a failed prediction.

8. The method of claim 7 , wherein updating the prediction table includes updating a value related to the store queue ID.

9. The method of any one of claims 1 to 8, further comprising receiving a store instruction.

10. 10. The method of claim 9, further comprising updating the predicted store queue ID based on the received store instruction.

11. 10. The method of claim 9, further comprising: executing the store instruction after updating the predicted store queue ID.

12. 1. A system for performing speculative store-to-load forwarding, the system comprising: a memory configured to store instructions; a processor for executing the instructions to perform operations, the operations comprising: receiving a load instruction; obtaining a predicted store queue ID from a prediction table based on the address of the load instruction; retrieving a value from a store queue based on the store queue ID while performing a parallel verification process on the predicted store queue ID; and performing a speculative store-to-load forwarding process including: determining that the parallel verification process was successful; and and in response, reading the value for the load instruction from the store queue.

13. 13. The system of claim 12, further comprising: receiving a store instruction; and populating the prediction table based on the store instruction.

14. The system of any one of claims 12 to 13, further comprising reloading some of the load instructions if the verification process fails.

15. The system of any one of claims 12 to 14, wherein the parallel verification process includes searching the store queue for the address of the load instruction.

16. The system of any one of claims 12 to 15, wherein the parallel verification process includes updating the prediction table upon successful prediction.

17. 17. The system of claim 16, wherein updating the prediction table comprises updating a value related to an age of the load instruction.

18. The system of any one of claims 12 to 17, wherein the parallel verification process includes updating the prediction table upon a failed prediction.

19. 20. The system of claim 18, wherein updating the prediction table includes updating a value related to the store queue ID.

20. The system of any one of claims 12 to 19, further comprising receiving a store instruction.

21. 21. The system of claim 20, further comprising updating the predicted store queue ID based on the received store instruction.

22. 21. The system of claim 20, further comprising executing the store instruction after updating the predicted store queue ID.

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