Data transmission method, communication device and storage medium

Abstract

This application discloses a data transmission method, a communication device, and a storage medium in the field of communication technology that can solve the problem of low error correction performance. The method, applied to a first node, includes the steps of error correction encoding a first bit sequence to obtain a second bit sequence, bit selecting the second bit sequence to obtain a third bit sequence, interleaving the third bit sequence based on a target subsequence to obtain an interleaved fourth bit sequence, where the target subsequence is a subsequence within the first bit sequence or a subsequence within the second bit sequence, and the length of the target subsequence is an integer greater than 0, and transmitting the fourth bit sequence.

Description

[Technical Field]

[0001] This disclosure claims priority to Chinese patent application No. 202310151615.3, filed on February 9, 2023, the entire contents of which are incorporated herein by reference.

[0002] [Technical field] The present application relates to the field of communications technology, and in particular to a data transmission method, a communications device, and a storage medium. [Background technology]

[0003] With the development of industries such as intelligent transportation, intelligent industrial control, and intelligent logistics, when transmitting data between different user devices in a wireless communication network, extremely high requirements are being placed on at least one of the performances of data transmission speed, throughput, reliability, and delay, such as ultra-low delay and ultra-high reliability.

[0004] In order to meet the high performance requirements, the transmitting side adds some redundant information to the data to be transmitted through channel coding, so that the receiving side can recover the data to be transmitted using this redundant information, and further remove some of the distortion caused by the data transmission procedure, thereby improving the performance of data transmission. However, the above method has little effect on removing distortion, and cannot better improve the performance of data transmission, which causes the method to have low error correction performance and further reduces the robustness of the wireless communication network. Summary of the Invention [Means for solving the problem]

[0005] The present application provides a data transmission method, a communication device, and a storage medium to solve the problem of low error correction performance.

[0006] A first aspect provides a data transmission method, the method being applied to a first node, comprising: error correction encoding a first bit sequence to obtain a second bit sequence; bit selecting the second bit sequence to obtain a third bit sequence; interleaving the third bit sequence based on a target subsequence to obtain an interleaved fourth bit sequence, where the target subsequence is a subsequence within the first bit sequence or a subsequence within the second bit sequence, and a length of the target subsequence is an integer greater than 0; and transmitting the fourth bit sequence.

[0007] A second aspect provides a data transmission method, applied to a second node, comprising the steps of receiving a fourth bit sequence from a first node, the fourth bit sequence being obtained by interleaving a third bit sequence with a target sub-sequence in the second bit sequence, the second bit sequence being obtained by error correction coding the first bit sequence, and the third bit sequence being obtained by bit selecting the second bit sequence; a target subsequence is a subsequence in the first bit sequence or a subsequence in the second bit sequence; and The method includes the steps of: the length of the target subsequence is an integer greater than 0; and error correction decoding the fourth bit sequence based on information of the target subsequence.

[0008] A third aspect provides a communication apparatus, the apparatus comprising: a communication unit used to transmit a fourth bit sequence; and a processing unit used to error correction encode a first bit sequence to obtain a second bit sequence, bit select the second bit sequence to obtain a third bit sequence, and interleave the third bit sequence based on a target subsequence to obtain an interleaved fourth bit sequence, where the target subsequence is a subsequence within the first bit sequence or a subsequence within the second bit sequence, and a length of the target subsequence is an integer greater than 0.

[0009] A fourth aspect provides a communications apparatus, the apparatus comprising: a communications unit adapted to receive a fourth bit sequence from a first node, the fourth bit sequence being obtained by interleaving a third bit sequence with a target sub-sequence in a second bit sequence, the second bit sequence being obtained by error correction coding the first bit sequence, and the third bit sequence being obtained by bit selecting the second bit sequence; a target subsequence is a subsequence in the first bit sequence or a subsequence in the second bit sequence; and The communication unit includes a length of the target subsequence that is an integer greater than 0, and a processing unit that is used for error correction decoding the fourth bit sequence based on information of the target subsequence.

[0010] A fifth aspect provides a communications device, the device being capable of implementing the functions performed in each of the above aspects or possible designs, the functions may be implemented by hardware, for example, in one possible design, the device may include a processor and a communications interface, the processor may be used to support the device in implementing such functions in any of the possible designs of the first or second aspect, for example, the processor may transmit a fourth bit sequence via the communications interface.

[0011] In yet another possible design, the apparatus may further comprise a memory for storing computer-executable instructions and data required by the apparatus, wherein, when the apparatus is in operation, the processor executes the computer-executable instructions stored in the memory, thereby causing the apparatus to perform the data transmission method of either the first or second possible design.

[0012] According to a sixth aspect, there is provided a computer readable storage medium, which may be a readable non-volatile storage medium, storing computer instructions or a program which, when executed on a computer, causes the computer to perform the data transmission method of the first aspect above or any of the possible designs of the above aspects.

[0013] According to a seventh aspect, there is provided a computer program product comprising instructions which, when executed on a computer, cause the computer to perform the data transmission method of the first aspect above or any possible design of the above aspects. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a schematic diagram illustrating the configuration of a communication system provided by an embodiment of the present application. [Figure 2] 1 is a schematic diagram illustrating the configuration of a communication device provided by an embodiment of the present application. [Figure 3] 1 is a flowchart of a data transmission method provided by an embodiment of the present application; [Figure 4A] FIG. 2 is a diagram illustrating an example of a block interleave column provided by an embodiment of the present application. [Figure 4B] FIG. 2 is a row example diagram of block interleaving provided by an embodiment of the present application; [Figure 5] FIG. 1 is an exemplary diagram of cyclic interleaving provided by an embodiment of the present application. [Figure 6] FIG. 2 is an exemplary diagram of block interleaving provided by an embodiment of the present application. [Figure 7] FIG. 2 is a schematic diagram of a bit sequence provided by an embodiment of the present application. [Figure 8] FIG. 10 is a schematic diagram of another bit sequence provided by an embodiment of the present application. [Figure 9] FIG. 10 is a schematic diagram of another bit sequence provided by an embodiment of the present application. [Figure 10] FIG. 1 is a schematic diagram of performance comparison provided by the examples of the present application. [Figure 11]4 is a flowchart of another data transmission method provided by an embodiment of the present application; [Figure 12] 4 is a flowchart of another data transmission method provided by an embodiment of the present application; [Figure 13] FIG. 10 is a schematic diagram of the configuration of another communication device provided by an embodiment of the present application. [Figure 14] FIG. 10 is a schematic diagram of the configuration of another communication device provided by an embodiment of the present application. [Figure 15] FIG. 2 is a schematic diagram of the configuration of another communication device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0015] The following clearly and completely describes the technical solutions in the embodiments of the present application in combination with the drawings in the embodiments of the present application.

[0016] In the description of this application, unless otherwise specified, " / " means "or", for example, A / B may represent A or B. In this specification, "and / or" is only a relational relationship that describes related objects, and represents that three relations may exist, for example, A and / or B may represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. Letters such as "first", "second", etc. Limited target It does not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean The limited target It is not intended to limit the number of different items. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, "at least one of a, b, or c" may represent a, b, c, ab, ac, bc, or abc, where a, b, and c may be singular or plural.

[0017] It should be noted that, in this application, words such as "exemplary" or "for example" are used to denote an example, instance, or illustration. Any embodiment or design described in this application as "exemplary" or "for example" may be The present disclosure It should not be construed as preferred or advantageous over other embodiments or designs. Where appropriate, use of words such as "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0018] With the rapid development of technologies such as big data, cloud computing, and delay-sensitive networks, the number of user devices in wireless communication networks is increasing explosively, and thus wireless communication networks are carrying many types of applications and large amounts of data. However, with the development of industries such as intelligent transportation, intelligent industrial control, and intelligent logistics, when transmitting data between different user devices in wireless communication networks, extremely high requirements are placed on at least one of data transmission speed, throughput, reliability, and delay, such as ultra-low latency and ultra-high reliability performance requirements.

[0019] Currently, data transmission methods in wireless communication networks mainly involve a transmitter channel-encoding data to be transmitted to obtain a bit sequence, mapping the bit sequence to constellation modulation symbols, and transmitting the resulting sequence to a receiver. The receiver then channel-decodes the received constellation modulation symbols to recover the data to be transmitted. In a data transmission channel, the data to be transmitted is subject to factors such as multipath, noise, and interference, which can lead to errors in the data to be transmitted. The transmitter adds redundant information to the data to be transmitted through channel coding, allowing the receiver to recover the data to be transmitted using the redundant information, and further eliminating some of the distortion caused by the data transmission procedure.

[0020] However, the current data transmission method has only a small effect on distortion removal, and some distortions cannot be removed, which makes it impossible to improve the performance of data transmission, reduces the error correction performance of the method, and further reduces the robustness of the wireless communication network.

[0021] In view of this, an embodiment of the present application provides a data transmission method, in which a first node performs error correction encoding on a first bit sequence to obtain a second bit sequence, selects bits from the second bit sequence to obtain a third bit sequence, and then interleaves the third bit sequence based on a target subsequence (i.e., a subsequence within the first bit sequence or a subsequence within the second bit sequence, where the length of the target subsequence is an integer greater than 0), obtains a fourth interleaved bit sequence, and sends the fourth interleaved bit sequence to a second node. In this way, the first node of the present application can remove data distortion not only by error correction coding but also by adaptively interleaving the third bit sequence (i.e., interleaving the third bit sequence based on an adaptive target subsequence determined from each of the first bit sequence or the second bit sequence), so it can be seen that the data transmission method provided by the present application has a great effect on distortion removal, can better improve the performance of data transmission, and further improve the error correction performance of the data transmission method provided by the present application and improve the robustness of the wireless communication network.

[0022] The technical solutions provided by the embodiments of the present application can be applied to various communication systems, such as New Radio (NR) communication systems employing 5th generation mobile communication technology (5G), Future Evolution systems, or multi-communication convergence systems.

[0023] 1 shows a schematic diagram of a communication system 10 provided by an embodiment of the present application. The communication system 10 may include a first node 101 and a second node 102, and the first node 101 may be communicatively connected to the second node 102.

[0024] Among them, the first node 101 or the second node 102 may be a device having wireless communication capabilities, and may be deployed indoors or outdoors, on land, including handheld or vehicle-mounted; on water (e.g., a steamship); or in the air (e.g., an airplane, balloon, satellite). A terminal device, also called a user equipment (UE), mobile station (MS), mobile terminal (MT), or terminal, is a device that provides voice and / or data connectivity to a user. The terminal device includes, for example, a handheld device, a vehicle-mounted device, etc., having wireless connectivity capabilities. Conventionally, the terminal device may be a mobile phone, a tablet, a laptop, a personal digital assistant, a mobile internet device (MID), a wearable device (e.g., a smart watch, a smart bracelet, a pedometer, etc.), an in-vehicle device (e.g., an automobile, a bicycle, an electric vehicle, an airplane, a ship, a train, a high-speed rail, etc.), a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a smart home device (e.g., a refrigerator, a television, an air conditioner, an electricity meter, etc.), a smart robot, a workshop device, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, or a wireless terminal in a smart home, an aircraft device (e.g., a smart robot, a hot air balloon, an unmanned aerial vehicle, an airplane), etc.

[0025] The first node 101 or the second node 102 may further be a device having a wireless transmission / reception function, or a chip or chip system that may be provided in the device. The first node 101 or the second node 102 includes, but is not limited to, any of a small base station, a wireless access point, a transmission receive point (TRP), a transmission point (TP), a macro base station, a relay base station, and some other access node.

[0026] Note that FIG. 1 is merely an exemplary frame diagram, and the number of nodes included in FIG. 1 and the names of each device are not limited, and the communication system 10 may further include other nodes, such as a third node, in addition to the functional nodes shown in FIG. 1. In some embodiments, The above third node may be a core network device, and the above is only an exemplary description of the third node, and the third node may be other devices, and the present application is not limited thereto.

[0027] The application scenarios of the embodiments of the present application are not limited. The system architectures and business scenarios described in the embodiments of the present application are intended to more clearly explain the technical solutions of the embodiments of the present application, and do not limit the technical solutions provided by the embodiments of the present application. Those skilled in the art will understand that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application can be similarly applied to similar technical problems.

[0028] In specific implementation, any of the devices in Fig. 1 may adopt the configuration structure shown in Fig. 2 or may include the components shown in Fig. 2. Fig. 2 is a schematic configuration diagram of a communication device 200 provided by an embodiment of the present application, which may be the first node 101, or a chip or system-on-chip within the first node 101. Alternatively, the communication device 200 may be the second node 102, or a chip or system-on-chip within the second node 102. As shown in Fig. 2, the communication device 200 includes a processor 201, a communication interface 202, and a communication line 203.

[0029] Furthermore, the communication device 200 may further include a memory 204. The processor 201, the memory 204, and the communication interface 202 may be connected via a communication line 203.

[0030] Among them, the processor 201 may be a CPU, a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 201 may also be, but is not limited to, a circuit, a device, or other apparatus having processing capabilities, such as a software module.

[0031] The communication interface 202 is used to communicate with other devices or other communication networks, such as Ethernet, radio access networks (RAN), wireless local area networks (WLAN), etc. The communication interface 202 may be a module, a circuit, a communication interface, or any device capable of implementing communication.

[0032] The communication line 203 is used to transmit information between the components of the communication device 200 .

[0033] The memory 204 is used to store instructions, among which the instructions may be a computer program.

[0034] Among these, memory 204 may be, but is not limited to, read-only memory (ROM) or other types of static storage devices capable of storing static information and / or instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and / or instructions, electrically erasable programmable read-only memory (EEPROM), read-only compact disc read-only memory (CD-ROM) or other compact disc storage devices, optical disc storage devices (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disc storage media or other magnetic storage devices, etc.

[0035] The memory 204 may exist independently of the processor 201 or may be integrated with the processor 201. The memory 204 may be used to store instructions, program codes, some data, etc. The memory 204 may be located within the communication device 200 or outside the communication device 200, and is not limited thereto. The processor 201 executes the instructions stored in the memory 204 to provide the functions provided in the embodiments described later in this application. Data Transmission Method It is used to achieve this.

[0036] In one example, processor 201 may comprise one or more CPUs, such as CPU0 and CPU1 in FIG.

[0037] In some embodiments, The communication device 200 may include multiple processors, and may further include a processor 207 in addition to the processor 201 in FIG.

[0038] In some embodiments, The communication apparatus 200 further includes an output device 205 and an input device 206. Illustratively, the input device 206 is a device such as a keyboard, a mouse, a microphone, or a lever, and the output device 205 is a device such as a display screen or a speaker.

[0039] Note that communication device 200 may be a desktop computer, a portable computer, a network server, a mobile phone, a tablet terminal, a wireless terminal, an embedded device, a chip system, or a device having a configuration similar to that shown in Figure 2. The configuration shown in Figure 2 does not limit the devices in Figures 1 and 2, and in addition to the components shown in Figure 2, the devices in Figures 1 and 2 may include more or fewer components than those shown, may combine some components, or may be arranged with different components.

[0040] In the embodiments of the present application, the chip system may consist of chips or may include chips and other discrete devices.

[0041] Furthermore, the operations and terms related to the embodiments of the present application may be mutually referenced and are not limited. The names of messages and parameters in messages exchanged between devices in the embodiments of the present application are merely examples, and other names may be used in specific implementations and are not limited.

[0042] The data transmission method provided by the embodiments of the present application will be described below in combination with the communication system shown in Figure 1. Operations and terminology related to the embodiments of the present application may be mutually referenced and are not limited. The names of messages and parameters in messages exchanged between devices in the embodiments of the present application are merely examples, and other names may be used in specific implementations and are not limited. The operations related to the embodiments of the present application are merely examples, and other names may be used in specific implementations. For example, "included" in the embodiments of the present application may be replaced with "mounted" or "carried," etc.

[0043] FIG. 3 is a flowchart of a data transmission method provided in an embodiment of the present application, and as shown in FIG. 3, the method may include the following steps:

[0044] S301: A first node performs error correction coding on a first bit sequence to obtain a second bit sequence.

[0045] In some embodiments, The implementation procedure of the above S301 may be as follows: the first node may obtain a second bit sequence by adding some redundant bits to the first bit sequence, and the method for obtaining the second bit sequence is an error correction coding method (also called a systematic coding method). The redundant bits may be called check bits of the error correction coding.

[0046] In one example, the first bit sequence may be 128 bits, the second bit sequence obtained after the first node performs error correction coding on the first bit sequence may be 200 bits, and the redundant bits include 72 bits.

[0047] In another example, the first bit sequence may be 64 bits, the second bit sequence obtained after the first node performs error correction coding on the first bit sequence may be 128 bits, and the redundant bits include 64 bits.

[0048] In some embodiments,The error correction coding scheme may further include at least one of Low Density Parity Check (LDPC) coding, Turbo coding, Polar coding, and Convolutional coding.

[0049] LDPC code The transformation , defined by a sparse (or low-density) parity-check matrix It is a group , The composition of such a group is Iterative decoding such as belief propagation decoding By permission to use Decoding performance can be improved.

[0050] Polar coding refers to a linear block code proposed based on channel polarization theory. When the length of a first bit sequence is extended infinitely, the first node may use the polar coding to make the second bit sequence obtained after encoding reach the Shannon limit. For example, polar coding is defined by the n-th order Kronecker product of a matrix G, where the matrix G is a 2-by-2 matrix (e.g., [1 0; 1 1]). In some embodiments, Polar coding typically employs a Successive Cancellation List (SCL) decoding algorithm.

[0051] Turbo coding is a parallel concatenated convolutional code that encodes two or more component codes in a parallel manner to obtain a second bit sequence. For example, Turbo coding is a coding method defined in the LTE (Long Term Evolution) system, and may include two component codes and systematic bits, with the parent code having a coding rate of 1 / 3.

[0052] Convolutional coding means dividing a first bit sequence into bit groups of one or more bits, where the coded output bits of each bit group relate not only to the bits of that bit group at the current time, but also to the bits of other bit groups at past times.

[0053] In some implementations, The first bit sequence is determined based on the transport block to be transmitted. The useful information bits are composed of an information sequence and a cyclic redundancy check (CRC) sequence. The first bit sequence is composed of the useful information bits and padding bits. In this, the length of the transport block (transport block size, TBS) is an integer greater than 0, and the length of the CRC sequence is an integer greater than 0.

[0054] In some examples, a CRC check sequence is added to a transport block that needs to be transmitted to obtain a bit sequence awaiting code block division, and when code block division is performed on the bit sequence awaiting code block division, if there is only one code block, the information sequence is the bit sequence awaiting code block division.Also, for example, when code block division is performed on the bit sequence awaiting code block division, if there is one or more code blocks, the information sequence is the sub-block obtained by dividing the code block.In this case, the length of the transport block (transport block size, TBS) is an integer greater than 0, and the length of the CRC check sequence is an integer greater than 0.

[0055] The first bit sequence is an error correction coded Target The first bit sequence may be a bit sequence, the length of the first bit sequence being an integer greater than 0. The second bit sequence may be an error correction coded output bit sequence, the length of the second bit sequence being an integer greater than 0.

[0056] In combination with the above implementation, the length of the transport block waiting for transmission may be less than or equal to a first preset threshold (i.e., T1). In one example, T1 is an integer greater than or equal to 64. In another example, T1 may be other values ​​such as 96, 128, 176, 192, 200, 256, 292, 308, 400, 512, 544, 624, 1024, or 2048. That is, when the transport block size is small, a good data transmission reliability gain can be obtained by adopting and implementing the data processing method.

[0057] In some implementations, The length of the first bit sequence is less than or equal to a second preset threshold (i.e., T2). In one example, T2 is an integer greater than or equal to 64. In another example, T2 may be other values ​​such as 96, 128, 176, 192, 200, 256, 292, 308, 400, 512, 544, 560, 624, 640, 1024, or 2048.

[0058] In some implementations, The length of the effective information bits is less than or equal to a second preset threshold (i.e., T2). In one example, T2 is an integer greater than or equal to 64. In another example, T2 may be other values ​​such as 96, 128, 176, 192, 200, 256, 292, 308, 400, 512, 544, 560, 624, 640, 1024, or 2048.

[0059] For example, take an example where the transport block size is 48 bits, the length of the CRC check sequence is 16 bits, and the length of the useful information bits configured by the first node based on the transport block and the CRC check sequence is 64 bits. Take an example where the length of the useful information bits is 64 bits and the number of padding bits is 2, and the first node can obtain a first bit sequence with a length of 66 bits.

[0060] S302: The first node selects bits from the second bit sequence to obtain a third bit sequence.

[0061] In some embodiments,The above-mentioned step S302 may be implemented as follows: the first node may determine a start position of bit selection, i.e., an index in the second bit sequence of the first bit in the third bit sequence, based on the redundancy version. The first node may determine the number of resources that need to be allocated and determine the length of the third bit sequence based on the number of resources. Next, the first node may determine a third bit sequence from the second bit sequence to be cyclically selected based on the start position and the length of the third bit sequence. The third bit sequence is a bit selection output bit sequence or a rate matching output bit sequence, and the length of the third bit sequence is an integer greater than 0.

[0062] In some embodiments, The above-mentioned S302 may be implemented as follows: the first node may determine a start position of bit selection based on the redundancy version; the first node may determine the number of resources that need to be allocated and determine the length of the third bit sequence based on the number of resources; the first node may then pick elements from the second bit sequence to be cyclically selected based on the start position of the third bit sequence and the length of the third bit sequence, and may determine that the picked elements are elements of the third bit sequence if the picked elements are not elements in the target subsequence; that is, the third bit sequence does not include elements of the target subsequence; the first node determines the third bit sequence based on the picked elements and the picking order.

[0063] As another optional implementation aspect, the implementation procedure of S302 above may be as follows: the first node may first remove the target subsequence from the second bit sequence to obtain a fifth bit sequence, and determine a start position corresponding to the redundancy version as a start position of the third bit sequence. The first node may determine the number of resources to allocate to the first bit sequence, and determine the length of the third bit sequence based on the number of resources. In this way, the first node may determine the third bit sequence from the second bit sequence to be cyclically selected based on the start position of the third bit sequence and the length of the third bit sequence.

[0064] In some embodiments, The first node may repeatedly select elements from the second bit sequence if the length of the third bit sequence is greater than the length of the second bit sequence. For example, if the index sequence of the second bit sequence is {0, 1, 2, 3, 4, 5}, the starting position is 2, and the length of the third bit sequence is 8, the first node may determine based on the above information that the index sequence of the third bit sequence is {2, 3, 4, 5, 0, 1, 2, 3}.

[0065] In some embodiments,A corresponding index in the second bit sequence of an element in the target subsequence may be different from a corresponding index in the second bit sequence of an element in the third bit sequence. For example, if the index sequence of the second bit sequence is {0,1,2,3,4,5,6,7}, the starting position is 2, the corresponding index in the second bit sequence of an element in the target subsequence is {0,1}, and the length of the third bit sequence is 6 bits, the first node may determine based on the above information that the index sequence of the third bit sequence is {2,3,4,5,6,7}. If the length of the third bit sequence is 8 bits, the first node may determine based on the above information that the index sequence of the third bit sequence is {2,3,4,5,6,7,2,3}. If the length of the third bit sequence is 4 bits, the first node may determine based on the above information that the index sequence of the third bit sequence is {2,3,4,5}.

[0066] S303: The first node interleaves the third bit sequence based on the target subsequence to obtain an interleaved fourth bit sequence.

[0067] Wherein, the target subsequence is a subsequence within the first bit sequence or a subsequence within the second bit sequence, the length of the target subsequence is an integer greater than 0, and the length of the fourth bit sequence is an integer greater than 0.

[0068] In some embodiments, the target sub-sequence does not include padding bits. Illustratively, if padding bits are present in the first bit sequence, the target sub-sequence does not include padding bits.

[0069] In some embodiments, the target subsequence does not include systematic puncture bits. In a codeword output by error correction coding, systematic bits that remain untransmitted in the transmitted data may be called systematic puncture bits. In a codeword output by error correction coding, all systematic puncture bits may constitute a systematic puncture sequence.

[0070] In some embodiments, the first node may derive the first bit sequence based on the significant information bits, and the target subsequence includes bits in the significant information bits. The first node may derive the first bit sequence by adding zero or more padding bits to the significant information bits.

[0071] In some embodiments, the interleaving includes circular interleaving and / or block interleaving.

[0072] In some embodiments, The cyclic interleaving process may include at least one of left cyclic shift interleaving, right cyclic shift interleaving, up cyclic shift interleaving, and down cyclic shift interleaving. Typically, the left cyclic shift interleaving and right cyclic shift interleaving are performed on row vector sequences (i.e., sequences in which elements are arranged row by row), and the up cyclic shift interleaving and down cyclic shift interleaving are performed on column vector sequences (i.e., sequences in which elements are arranged column by column).

[0073] The block interleaving process includes at least one of writing row by row and reading column by column, and writing column by column and reading row by row. When the block interleaving process writes row by row and reads column by column, the first node writes in the direction indicated by the arrow in Figure 4B and reads in the direction indicated by the arrow in Figure 4A. When the block interleaving process writes column by column and reads row by row, the first node first writes column by column and then reads row by row.

[0074] In some embodiments, When the length of the third bit sequence (denoted as E) is large, the number of rows or columns of the block interleaving is determined by the length of the third bit sequence. In one example, the difference between the number of rows and the number of columns of the block interleaving is 1 or less.

[0075] In some implementations, The number of rows in the block interleave is r and the number of columns is c, where r and c are positive integers.

[0076] In some embodiments, r is an integer obtained by taking the logarithm of E with base 2 and truncating it, and r satisfies the following formula 1.

number

[0077] c is the smallest integer equal to or greater than the real number obtained by dividing E by r (that is, an integer obtained by rounding up the real number obtained by dividing E by r), and c satisfies the following formula 2.

number

[0078] Also, In some embodiments, r is the smallest integer equal to or greater than the real number obtained by dividing E by c (i.e., the integer obtained by rounding up the real number obtained by dividing E by c). r satisfies the following formula 3.

number

[0079] c is an integer obtained by taking the logarithm of E with base 2 and truncating it. c satisfies the following formula 4.

number

[0080] The procedure for implementing S303 will be explained below by combining the above different interleaving methods.

[0081] If the interleaving process is a cyclic interleaving process, the implementation procedure of S303 above is as follows: the first node determines a decimal value (i.e., the number of shift bits) corresponding to the target subsequence, and may cyclically shift the third bit sequence based on the decimal value corresponding to the target subsequence to obtain a fourth interleaved bit sequence.

[0082] For example, as shown in FIG. 5, the index sequence of the third bit sequence 510 may be {0,1,2,3,4,5,6,7,8,9...,236,237,238,239}, and the data bit sequence of the target subsequence 520 may be {0,0,1,0,1,1,1,1}, and the target subsequence 520 may be used to control the magnitude of the number of cyclic shifts by which the third bit sequence 510 is cyclically shifted. In this example, the first node converts the data bit sequence of the target subsequence 520 into a decimal value (i.e., S=23), and cyclically shifts the third bit sequence 510 left by 23 bits, i.e., assigns the bit with index 23 in the third bit sequence 510 to the bit with index 0 in the fourth interleaved bit sequence 530, and assigns the bit with index 24 in the third bit sequence 510 to the bit with index 1 in the fourth interleaved bit sequence 530, until all indices in the fourth interleaved bit sequence 530 are determined. {23,24,25,26,…,236,237,238,239, ,0,1,2,3,…,19,20,21,22} get.

[0083] If the interleaving process includes cyclic interleaving and block interleaving, the implementation procedure of S303 is as follows: the first node may block interleave the third bit sequence to obtain a fifth bit sequence, and then determine a decimal value corresponding to the target subsequence, and cyclically shift the fifth bit sequence according to the decimal value corresponding to the target subsequence to obtain a fourth interleaved bit sequence.

[0084] Illustratively, as shown in FIG. 6, the data bit sequence of the third bit sequence 610 is {0,1,0,1,1,0,1,0,1,0,1,0,1,1,0,1}; and the number of rows of the third bit sequence 610 is 4 and the number of columns of the third bit sequence 610 is 4, The data bit sequence of the target subsequence 620 is {0,1,1}. However, the number of rows or columns may be other examples, and this disclosure is not limited thereto. In this example, the first node first writes data bits in the third bit sequence 610 in a row format, and then reads data bits from the third bit sequence 610 in a column format to obtain a block-interleaved sixth bit sequence 630 (e.g., the data bit sequence of the sixth bit sequence 630 is {0,1,1,1,1,0,0,1,0,1,1,0,1,0,0,1}). Next, the first node converts the data bit sequence of the target subsequence 620 into a decimal value (i.e., 3), and cyclically shifts the sixth bit sequence 630 left by 3 bits, i.e., sets the bit with index 3 in the sixth bit sequence 630 to the bit with index 0 in the fourth interleaved bit sequence 640, and sets the bit with index 4 in the sixth bit sequence 630 to the bit with index 1 in the fourth interleaved bit sequence 640, until all indices in the fourth interleaved bit sequence 640 are determined, thus obtaining the fourth interleaved bit sequence 640 (e.g., the data bit sequence of the fourth bit sequence 640 is {1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1}).

[0085] In some embodiments, the target subsequence consists of one or more consecutive bits in the second bit sequence.

[0086] In one example (denoted as Example 1), as shown in FIG. 7, the target subsequence 710 may be a subsequence located at the beginning of the second bit sequence 720 (i.e., {0, 1, ..., L-1}, where L is a positive integer).

[0087] As another example (denoted as Example 2), as shown in FIG. 8, the target subsequence 810 may be a subsequence located at the end of the second bit sequence 820 (i.e., {NL, N-L+1, N-L+2, ..., N-1}, where N is a positive integer), where N is the length of the second bit sequence.

[0088] In some embodiments, The third bit sequence may be composed of one or more consecutive bits in the second bit sequence. Combining with Example 1 above, as shown in Figure 7, the third bit sequence 730 may be a subsequence (i.e., {L, ..., E+L-1}) located in the middle of the second bit sequence 720. Combining with Example 2 above, as shown in Figure 8, the third bit sequence 830 may be a subsequence (i.e., {0, ..., E-1}) located at the beginning of the second bit sequence 820.

[0089] In this case, it can be seen that the first node can determine the target subsequence without requiring many addressing operations, and further, the complexity of the first node determining the target subsequence can be reduced, and the procedure for error correction decoding the fourth bit sequence based on the information of the target subsequence can also be simplified, thereby improving the efficiency of the second node processing the fourth bit sequence.

[0090] Alternatively, the target subsequence may consist of one or more discrete bits in the second bit sequence. Illustratively (denoted as Example 3), as shown in Figure 9, the target subsequence 910 may be a subsequence located within the first bit sequence 920 or the second bit sequence 930 (i.e., {0, 1, 20, 21, 40, 41, 42}).

[0091] In some embodiments, The third bit sequence may be composed of one or more discrete bits in the second bit sequence. In combination with Example 3 above, as shown in Figure 9, the third bit sequence 940 may be a subsequence (i.e., {2,...,19,22,...,39,43,...,128}) located within the second bit sequence 930.

[0092] In some embodiments, the corresponding index in the second bit sequence of an element in the target sub-sequence may be different from the corresponding index in the second bit sequence of an element in the third bit sequence.

[0093] That is, the corresponding index in the second bit sequence of each element in the target subsequence constitutes a first set (denoted as A1), and the corresponding index in the second bit sequence of each element in the third bit sequence constitutes a second set (denoted as A0), the intersection of A0 and A1 being the empty set.

[0094] 7, a first set (denoted as A1') of corresponding indices in the second bit sequence for each element of the target subsequence 710 is {0, 1, ..., L-1}. A second set (denoted as A0') of corresponding indices in the second bit sequence for each element of the third bit sequence 730 is {L, ..., E+L-1}. The intersection of A0' and A1' is the empty set.

[0095] In combination with Example 2 above, as shown in FIG. 8, a first set (denoted as A1″) of corresponding indices in the second bit sequence for each element in the target subsequence 810 is {NL, N-L+1, N-L+2, ..., N-1}. A second set (denoted as A0″) of corresponding indices in the second bit sequence for each element in the third bit sequence 830 is {0, 1, ..., E-1}, where E=NL. The intersection of A0″ and A1″ is the empty set.

[0096] In combination with Example 3 above, as shown in FIG. 9, a first set (denoted as A1"') of corresponding indices in the second bit sequence for each element in the target subsequence 910 is {0, 1, 20, 21, 40, 41, 42}. A second set (denoted as A0"') of corresponding indices in the second bit sequence for each element in the third bit sequence 940 is {2, ..., 19, 22, ..., 39, 43, ..., 128}. The intersection of A0"' and A1"' above is the empty set.

[0097] It can be seen that the corresponding indexes in the second bit sequence of elements in the target subsequence are different from the corresponding indexes in the second bit sequence of elements in the third bit sequence, and in this way, the first node transmits to the second node only the data bits that need to be transmitted (i.e., the data bits in the third bit sequence), without occupying transmission resources for transmitting data bits that do not need to be transmitted (i.e., the data bits in the target subsequence), further improving the efficiency of data transmission, improving the reliability performance of data transmission, and improving the robustness of the communication system.

[0098] In some embodiments, the length of the target subsequence is determined according to the length of the useful information bits, or the length of the first bit sequence, or the length of the third bit sequence.

[0099] In some embodiments, The length of the target subsequence is determined according to the length of the useful information bits. In this case, the length of the target subsequence satisfies the following Equation 5.

number

[0100] where L is the length of the target subsequence, K' is the length of the useful information bits, and the function f(x) represents rounding down, up, or rounding the real number x to obtain an integer.

[0101] In some embodiments, The length of the target subsequence is determined according to the length of the first bit sequence, and in this case, the length of the target subsequence satisfies Equation 6 below.

number

[0102] where L is the length of the target subsequence, K is the length of the first bit sequence, and the function f(x) represents rounding down, up, or rounding the real number x to obtain an integer.

[0103] In some implementations, The length of the first bit sequence is less than or equal to a third preset threshold (i.e., T3). In one example, T3 may be an integer greater than 128. In another example, T3 may be other numeric values ​​such as 128, 192, 200, 256, 308, 400, or 512.

[0104] In some implementations, The first node may determine the length of the first bit sequence based on the length of the useful information bits, where the length of the useful information bits is T5 (i.e., the fifth preset threshold) In one example, T5 may be other values ​​such as 64, 96, 128, 176, 192, 200, 256, 292, 308, 400, 512, 544, 624, 1024, or 2048.

[0105] In another optional implementation, the length of the target subsequence is determined according to the length of the third bit sequence, in which case the length of the target subsequence satisfies Equation 7 below.

number

[0106] where E is the length of the third bit sequence. The function f1(x) represents rounding down the real number x to obtain an integer.

[0107] In one example, the length of the target subsequence corresponding to the third bit sequence of length E1 is L1, and the length of the target subsequence corresponding to the third bit sequence of length E2 is L2. If E1 is less than E2, then L1 is less than or equal to L2.

[0108] In another example, the length of the target subsequence corresponding to a first bit sequence of length K1 is L3, and the length of the target subsequence corresponding to a first bit sequence of length K2 is L4. If K1 is less than K2, then L3 is less than or equal to L4.

[0109] In another example, the length of the target subsequence corresponding to useful information bits of length K'1 is L5, and the length of the target subsequence corresponding to useful information bits of length K'2 is L6. If K'1 is less than K'2, then L5 is less than or equal to L6.

[0110] In another optional implementation, the length of the target subsequence is determined according to the length of the transport block. The first bit sequence is obtained by a transport block whose length is the length of the transport block. In this case, the length of the target subsequence satisfies Equation 8 below.

number

[0111] where TBS is the length of the transport block, which is an integer greater than 0. The function f(x) represents rounding down, rounding up, or rounding off the real number x to obtain an integer.

[0112] In some implementations,The length of the transport block is less than or equal to a fourth preset threshold (i.e., T4), and the coding rate is greater than or equal to a first coding rate threshold, where the fourth preset threshold is a positive integer and the first coding rate threshold is a positive real number less than 1. In one example, the coding rate is determined based on a modulation and coding scheme (MCS) index, and the coding rate is a positive real number less than 1. In one example, the first coding rate threshold is equal to at least one of 2 / 3, 0.67, 0.25, 0.5, 0.4, 0.6, 0.75, 0.83, and 5 / 6. In one example, T4 may be an integer greater than or equal to 64. In another example, T4 may be other values ​​such as 64, 96, 128, 176, 192, 200, 256, 292, 308, 400, 512, 544, 624, 1024, or 2048.

[0113] In some implementations, A first node may interleave a third bit sequence based on a target subsequence to obtain an interleaved fourth bit sequence. The first node may interleave only a first subsequence of the third bit sequence based on the target subsequence, and determine a fourth bit sequence consisting of the interleaved sequence and a second subsequence (i.e., the second subsequence includes bits in the third bit sequence other than the first subsequence). The length of the first subsequence is less than or equal to the length of the third bit sequence. In some examples, the index of the first element of the first subsequence in the second bit sequence may be determined by a lift value. In a specific example, the index of the first element of the first subsequence in the second bit sequence may be equal to d*Z, where d is a non-negative integer and Z is the lift value.

[0114] In some examples, the length of the first subsequence is equal to Z, and the index in the second bit sequence of the first element of the first subsequence is equal to d*Z, where d is a non-negative integer and Z is a lift value.

[0115] In some embodiments, the length of the first subsequence is equal to d1*Z, and the index in the second bit sequence of the first element of the first subsequence is equal to d2*Z, where d1 is a positive integer, d2 is a non-negative integer, and Z is a lift value. d1 may be an integer between 1 and 68. d2 may be an integer between 1 and 68. In a specific example, d2 is 2.

[0116] In some implementations, When the first subsequence includes d1 subsequences, the first node interleaves the first subsequence by performing a procedure including the first node interleaving each subcolumn of the d1 subsequences. In one example, the length of each subcolumn in the d1 subsequences is equal to the lift value. When an integer corresponding to the target subsequence is S (e.g., the integer S is obtained by converting the data bit sequence of the target subsequence to a decimal number), the number of bits by which the ith subsequence of the d1 subsequences is cyclically shift interleaved satisfies the following Equation 9:

number

[0117] However, U i is the number of bits by which the i-th subsequence is cyclic shift interleaved, where i is from 0 to d1-1. mod(x1,x2) represents the operation to find the remainder, for example, mod(11,8)=3, floor(x1) represents the operation to round down the real number x, for example, floor(2.6)=2, and x1^x2 represents x1 raised to the power of x2, for example, 7^2=49.

[0118] In some embodiments, the target subsequence is determined depending on one or more of the second bit sequence, the length of the third bit sequence, the length of the first bit sequence, the length of the useful information bits, the modulation order, the coding rate, the number of resources, higher layer signaling, the type of user equipment, and the transport block size.

[0119] In some implementations,The target sub-sequence may be determined according to the second bit sequence and the upper layer signaling, and the implementation procedure is as follows: each third node among the at least one third node may send an upper layer signaling message to the first node; in response, the first node may receive an upper layer signaling message from the at least one third node; and the first node determines the target sub-sequence based on the upper layer signaling message.

[0120] The higher layer signaling message may be used to indicate the length of the target subsequence and the index in the second bit sequence of the first element of the target subsequence, or may be used to indicate the index in the second bit sequence of each element in the target subsequence. In some examples, the higher layer signaling message may include at least one of downlink control information (DCI), radio resource control (RRC) signaling, and medium access control (MAC) signaling.

[0121] In one optional implementation, when the higher layer signaling message includes DCI and RRC signaling, the DCI may be used to indicate the length of the target subsequence, and the RRC signaling may be used to indicate the index in the second bit sequence of the first element of the target subsequence. In this example, the first node determines the index in the second bit sequence of the first element of the target subsequence based on the RRC signaling, and determines the length of the target subsequence based on the DCI. L The first node may then sequentially read L bits from the index position in the second bit sequence of the first element of the target subsequence, where L is a positive integer, to further obtain the target subsequence.

[0122] For example, if the length of the target subsequence that can be indicated by the DCI is 5 bits and the index of the first element of the target subsequence that can be indicated by the RRC signaling is 1 in the second bit sequence, the first node may sequentially read 5 bits of data from index 1 in the second bit sequence and further determine the target subsequence.

[0123] In another possible implementation, if the higher layer signaling message includes MAC signaling, the MAC signaling may be used to indicate an index in the second bit sequence of each element in the target subsequence. In this example, the first node may determine an index in the second bit sequence of each element in the target subsequence based on the MAC signaling, read data bits according to the index, and determine the target subsequence.

[0124] For example, if the indices in the second bit sequence of each element in the target subsequence that can be indicated by the MAC signaling are {0, 2, 5, 25, 40, 47, 48}, the first node may read data with indices 0, 2, 5, 25, 40, 47, 48 from the second bit sequence, and further determine the target subsequence.

[0125] It can be understood that, for the second node, a longer target subsequence requires more attempts to perform error correction decoding on the fourth bit sequence based on the target subsequence information, resulting in increased complexity of the error correction decoding performed by the second node. However, a longer target subsequence length improves the decoding performance of the second node and also reduces transmission power. Therefore, an advantage of the first node determining the target subsequence in response to higher layer signaling is that the at least one third node can flexibly set the length of the target subsequence according to the current state of the user equipment. If the second node is a power-saving device or is in a low-power state, the at least one third node may indicate a short target subsequence. On the other hand, if the second node is a high-end device, the at least one third node may indicate a long target subsequence, which may reduce the transmission power of the first node or improve the decoding performance of the second node, thereby further improving communication flexibility and reliability.

[0126] For example, when the second node (e.g., an access network device) is in a low load state (i.e., idle most of the time), higher layer signaling may instruct the first node (e.g., a user device) to adopt a long target subsequence in order to improve the reception performance of the second node; and when the second node (e.g., an access network device) is in a high load state (i.e., a large amount of data waiting to be processed), higher layer signaling may instruct the first node (e.g., a user device) to adopt a short target subsequence in order to shorten the processing time for error correction decoding of the second node.

[0127] In another possible implementation manner, the target subsequence may be determined according to the second bit sequence, the length of the effective information bits, and upper layer signaling, and the implementation procedure is as follows: the first node determines the index in the second bit sequence of the first element of the target subsequence according to the upper layer signaling, then determines the length of the target subsequence according to the length of the effective information bits, and finally cyclically reads L bits from the second bit sequence from the position of the index in the second bit sequence of the first element of the target subsequence, and further obtains the target subsequence.

[0128] In another possible implementation manner, the target subsequence may be determined according to the second bit sequence, the length of the third bit sequence, and higher layer signaling, and the implementation procedure is as follows: the first node may determine the length of the target subsequence based on the length of the third bit sequence, and how the first node determines the length of the target subsequence based on the length of the third bit sequence may be understood with reference to Equation 2 above and the description related to Equation 2. The first node may determine the index in the second bit sequence of the first element of the target subsequence based on the higher layer signaling, and how the first node determines the index in the second bit sequence of the first element of the target subsequence based on the higher layer signaling may be understood with reference to the description related to the target subsequence being determined according to the second bit sequence and higher layer signaling. Finally, the first node may cyclically read L bits from the second bit sequence from the position of the index in the second bit sequence of the first element of the target subsequence, and further obtain the target subsequence.

[0129] In another possible implementation manner, the target subsequence may be determined according to the second bit sequence, the type of user equipment, and higher layer signaling, and the implementation procedure is as follows: the first node may determine the length of the sequence corresponding to the type of user equipment as the length of the target subsequence; the first node may determine the index in the second bit sequence of the first element of the target subsequence based on the higher layer signaling; and how the first node determines the index in the second bit sequence of the first element of the target subsequence based on the higher layer signaling may be understood by referring to the above description related to the target subsequence being determined according to the second bit sequence and higher layer signaling. Finally, the first node may cyclically read M bits indicated by the length of the target subsequence, starting from the position of the index in the second bit sequence of the first element of the target subsequence, to further obtain the target subsequence.

[0130] In some embodiments,The first node may classify the user equipment according to the uplink and downlink peak rates of the user equipment. For example, as shown in Table 1 below, the first node classifies user equipment having a downlink peak rate of 10 megabits per second (Mbit / s) and an uplink peak rate of 5 Mbit / s as type 1 user equipment, a downlink peak rate of 50 Mbit / s and an uplink peak rate of 25 Mbit / s as type 2 user equipment, a downlink peak rate of 100 Mbit / s and an uplink peak rate of 50 Mbit / s as type 3 user equipment, a downlink peak rate of 150 Mbit / s and an uplink peak rate of 50 Mbit / s as type 4 user equipment, and a downlink peak rate of 300 Mbit / s as type 5 user equipment. A user equipment with a peak downlink rate of 300 Mbit / s and an uplink peak rate of 75 Mbit / s may be determined as type 5 user equipment, a user equipment with a peak downlink rate of 300 Mbit / s and an uplink peak rate of 50 Mbit / s as type 6 user equipment, a user equipment with a peak downlink rate of 300 Mbit / s and an uplink peak rate of 150 Mbit / s as type 7 user equipment, and a user equipment with a peak downlink rate of 3000 Mbit / s and an uplink peak rate of 1500 Mbit / s as type 8 user equipment.

[0131] In some embodiments, The target subsequence may be determined solely according to the type of user equipment.

[0132] [Table 1]

[0133] It can be understood that, for the second node, a longer target subsequence length increases the number of times the second node must attempt error correction decoding when it performs error correction decoding on the fourth bit sequence based on the target subsequence information, resulting in increased complexity of the error correction decoding performed by the second node. However, a longer target subsequence length improves the decoding performance of the second node and also reduces transmission power. Therefore, when the second node is a user equipment, the advantage of the first node determining the target subsequence length according to the type of user equipment is that the first node can flexibly set target subsequence lengths suitable for different user equipment types, thereby improving data transmission efficiency.

[0134] In another possible implementation manner, the target subsequence may be determined according to the second bit sequence, the modulation order, the coding rate, the number of resources, and higher layer signaling, and the implementation procedure is as follows: the first node may determine the length of the target subsequence based on the modulation order, the coding rate, and the number of resources. The first node may determine the index in the second bit sequence of the first element of the target subsequence based on the higher layer signaling. The method in which the first node determines the index in the second bit sequence of the first element of the target subsequence based on the higher layer signaling may be understood by referring to the description related to the target subsequence being determined according to the second bit sequence and higher layer signaling above. Finally, the first node may cyclically read L bits indicated by the length of the target subsequence, starting from the position of the index in the second bit sequence of the first element of the target subsequence, and further obtain the target subsequence.

[0135] In some embodiments, In this implementation, the length of the target subsequence satisfies Equation 10 below.

number

[0136] where Q is the modulation order of the data waiting to be transmitted, R is the coding rate of the data waiting to be transmitted, and Re is the number of resources for the data waiting to be transmitted, which may be determined by the number of resource blocks and the number of antenna layers.

[0137] It can be understood that in this embodiment, the first node can determine a target subsequence based on one or more of the second bit sequence, the length of the third bit sequence, the length of the first bit sequence, the length of the useful information bits, the modulation order, the coding rate, the number of resources, the upper layer signaling, the type of user equipment, and the transport block size, thereby facilitating the first node to determine a target subsequence and interleaving the third bit sequence according to the target subsequence. For the second node, the second node can determine target subsequence information (e.g., the length of the target subsequence or the index in the second bit sequence of the first element of the target subsequence) according to one or more of the second bit sequence, the length of the third bit sequence, the length of the first bit sequence, the length of the useful information bits, the modulation order, the coding rate, the number of resources, the upper layer signaling, the type of user equipment, and the transport block size, further facilitating subsequent operations such as error correction decoding of the second node and improving the processing efficiency of the second node.

[0138] S304: The first node transmits the fourth bit sequence to the arbitrary node, and in response, the arbitrary node receives the fourth bit sequence from the first node.

[0139] Therein, any node includes a second node.

[0140] It can be seen that there is no need for the first node to transmit the target subsequence to the second node, and thus the data transmission efficiency can be improved and the data transmission power consumption can be reduced.

[0141] In some embodiments, The first node may transmit the fourth bit sequence to the second node via a wired communication method (e.g., optical cable), or may transmit the fourth bit sequence to the second node via a wireless communication method (e.g., wireless bearer), and this application does not limit this.

[0142] S305: The second node performs error correction decoding on the fourth bit sequence based on the information of the target subsequence.

[0143] In one optional implementation, the implementation procedure of the above S305 may be as follows: the second node deinterleaves the fourth bit sequence based on the information of the target subsequence to obtain a third bit sequence, performs inverse bit selection on the third bit sequence to obtain a second bit sequence, and then performs error correction decoding on the second bit sequence to obtain a first bit sequence.

[0144] In some embodiments, The second node may deinterleave the fourth bit sequence based on the information of the target subsequence to obtain a third bit sequence as follows: the second node may determine a plurality of bit conversion values ​​based on the length of the target subsequence, and deinterleave the fourth bit sequence based on each of the plurality of bit conversion values ​​to obtain a plurality of candidate third bit sequences. Next, the second node may determine a soft decision value for each of the plurality of candidate third bit sequences, and determine an optimal candidate third bit sequence based on the soft decision value of each candidate third bit sequence, and determine the optimal candidate third bit sequence as the third bit sequence.

[0145] As shown in Figure 10, the abscissa in the coordinate system shown in Figure 10 is used to characterize the signal-to-noise ratio (SNR) of an additive white Gaussian noise channel, and it can be seen that the unit of the signal-to-noise ratio is decibels (dB). The ordinate in the coordinate system shown in Figure 10 is used to characterize the block error rate (BLER). The solid line (denoted as New) in Figure 10 is a performance curve obtained by performing data transmission according to the data transmission method provided by the embodiments of the present application under target conditions, and the dashed line (denoted as Old) in Figure 10 is a performance curve obtained by performing data transmission according to a current data transmission method (e.g., a data transmission method based on LDPC coding) under target conditions.

[0146] Based on Figure 10, it can be seen that when the block error rate is 0.01, the present application has a lower signal-to-noise ratio than the prior art, and the difference between the signal-to-noise ratio of the present application and the signal-to-noise ratio of the prior art is about 1 decibel (dB), that is, the present application can have a performance gain of about 1 dB. When the signal-to-noise ratio is 5.5 dB, the present application has a lower block error rate than the prior art, and the block error rate of the present application can reach 8 / 1000, while the block error rate of the prior art is only 60 / 1000. Therefore, the data transmission method provided by the embodiment of the present invention can improve data transmission performance compared to the data transmission method in the prior art.

[0147] In some embodiments,The data transmission method depicted by the solid line in Figure 10 is a data transmission method in which the length of the target subsequence is 6 bits, the length of the third bit sequence is 86 bits, the lift value of the parity check matrix is ​​11, and the index of the first element of the target subsequence in the second bit sequence is 22. Correspondingly, the length of the useful information bits is 64 bits, and the length of the first bit sequence is 66 bits, including a transport block with a length of 48 bits (i.e., transport block size TBS=48), a CRC check sequence with a length of 16 bits, and padding bits with a length of 2 bits. The parity check matrix is ​​determined by the lift value and the basis matrix.

[0148] In the technical solution provided by the embodiments of the present application, the first node performs error correction coding on the first bit sequence to obtain a second bit sequence, and then bit selects the second bit sequence to obtain a third bit sequence. The first node then interleaves the third bit sequence based on a target subsequence (i.e., a subsequence within the first bit sequence or a subsequence within the second bit sequence) to obtain a fourth interleaved bit sequence, and transmits the fourth bit sequence to the second node. In this way, the first node of the present application can eliminate data distortion not only by error correction coding but also by adaptively interleaving the third bit sequence (i.e., interleaving the third bit sequence based on an adaptive target subsequence determined from each of the first bit sequence or the second bit sequence). Therefore, it can be seen that the data transmission method provided by the present application can effectively eliminate data distortion and improve data transmission performance, thereby improving the error correction performance of the data transmission method provided by the present application and enhancing the robustness of the wireless communication network.

[0149] In some embodiments,As shown in S301, the first node performs error correction encoding on the first bit sequence to obtain a second bit sequence. The embodiment of the present application may provide one possible implementation of S301 based on the embodiment of the method shown in FIG. 3. As shown in FIG. 11, FIG. 11 is one implementation of S301 provided by the present application. Therefore, the implementation procedure in which the first node performs error correction encoding on the first bit sequence to obtain a second bit sequence (i.e., S301) may include the following S1101.

[0150] S1101: A first node performs error correction coding on a first bit sequence based on a parity check matrix to obtain a second bit sequence.

[0151] Therein, the parity check matrix is ​​determined by the lift value and the basis matrix.

[0152] In some implementations, In combination with the above embodiment, the implementation procedure of S1101 above may be as follows: the first node may determine a parity check matrix with a length of 462 rows and 572 columns based on the lift value (e.g., 11) and a basis matrix (e.g., a matrix with 42 rows and 52 columns). Then, the first node performs error correction encoding on the first bit sequence based on the determined parity check matrix to obtain a second bit sequence.

[0153] In some examples, the parity check matrix includes multiple sub-matrix blocks, and each sub-matrix block is an identity matrix or a zero square matrix. Each element of the base matrix corresponds to one sub-matrix block, and the base matrix includes two types of elements: an element representing a cyclic shift of the identity matrix and an element representing a zero square matrix. A lift value is used to indicate the dimension number of the identity matrix and the zero square matrix, and the lift value is a positive integer.

[0154] In some examples, when the lift value is Z, if an element in the basis matrix is ​​less than 0, the sub-matrix block corresponding to this element is a zero square matrix with dimension Z*Z, and if an element in the basis matrix is ​​greater than or equal to 0, the sub-matrix block corresponding to this element is an identity matrix with dimension Z*Z, and the specific numerical value of this element is used to indicate the number of bits of the cyclic shift of the identity matrix.

[0155] In some examples, when the dimension of a base matrix is ​​a*b and the lift value is Z, the dimension of the parity check matrix corresponding to the base matrix is ​​a*Z rows and b*Z columns.In addition, the columns of the parity check matrix include systematic columns and check columns.For example, for a parity check matrix with a dimension of aZ*bZ, suppose the number of columns of this parity check matrix is ​​bZ and the number of rows is aZ.The number of columns of the check columns of this parity check matrix is ​​equal to the number of rows of the parity check matrix aZ, and the number of columns of the systematic columns of this parity check matrix is ​​equal to the difference between the number of columns and the number of rows, that is, bZ-aZ.Accordingly, the length of the second bit sequence obtained by error correction coding the first bit sequence is equal to the number of columns of the parity check matrix. The second bit sequence includes a systematic bit sequence and a check bit sequence. For example, the second bit sequence C=[S;P], where S is the systematic bit sequence, P is the check bit sequence, and the parity check matrix H=[Hs,Hp], where Hs is the matrix of systematic columns and Hp is the matrix of check columns. According to the error correction coding rule, H×C=0, where 0 is a zero vector with length H and number of rows. Therefore, H×C=[Hs,Hp]×[S;P]=Hs×S+Hp×P=0. Thus, the systematic bit sequence in the second bit sequence corresponds to the systematic column in the parity check matrix, and the check bit sequence in the second bit sequence corresponds to the check column in the parity check matrix. The first bit sequence is the systematic bit sequence in the second bit sequence, that is, the length of the first bit sequence is equal to bZ-aZ.

[0156] some ExamplesIn the example shown, the systematic columns of the parity check matrix are composed of the first bZ-aZ columns, and the corresponding systematic column indices may be {0, 1, ..., bZ-aZ-1}, and the check columns are composed of the subsequent aZ columns, and the corresponding check column indices may be {bZ-aZ, bZ-aZ+1, ..., bZ-1}. For example, in a parity check matrix having a length of 462 rows and 572 columns determined based on a lift value (e.g., 11) and a basis matrix (e.g., a 42-row, 52-column matrix), the systematic column indices are {0, 1, ..., 109}, and the check column indices are {110, 111, ..., 571}. Accordingly, in the second bit sequence obtained after error correction coding, the systematic bit sequence indices are {0, 1, ..., 109}, and the check bit sequence indices are {110, 111, ..., 571}.

[0157] In some embodiments, The cyclic shift value of the identity matrix is ​​generally expressed as an integer, and its specific value directly describes the amount of cyclic shift of the identity matrix. The elements of a zero square matrix are generally represented by -1 (or empty or null). For example, if the basis matrix has 4 rows and 16 columns and the lift value is 8, the size of the parity check matrix determined by the first node based on the basis matrix and the lift value is 4*8 rows and 16*8 columns.

[0158] In the scenario shown in Figure 11 above, the target sub-sequence may have the following characteristics:

[0159] In some embodiments, the index in the second bit sequence of the first element of the target subsequence is equal to a non-negative integer multiple of the lift value, for example, the index in the second bit sequence of the first element of the target subsequence is equal to 2*Z, where Z is the lift value.

[0160] Illustratively, taking an example where the lift value is 8, the first node may determine that the index in the second bit sequence of the first element of the target subsequence may be equal to 16 (i.e., 2*8) or 32 (i.e., 4*8).

[0161] In some embodiments, the length of the target subsequence is less than or equal to the lift value.

[0162] In some embodiments, the difference between the index in the second bit sequence of the first element of the target subsequence and the index in the second bit sequence of the last element of the target subsequence is less than the lift value.

[0163] For example, taking an example where the lift value is 8, the indices in the second bit sequence of all elements of the target subsequence are {16, 17, 18, 19, 20}, i.e., the index in the second bit sequence of the first element of the target subsequence is equal to 16, and the index in the second bit sequence of the last element is equal to 20.

[0164] In some embodiments, The target subsequence has at least C elements whose index in the second bit sequence is equal to a non-negative integer multiple of the lift value, where C is an integer greater than one.

[0165] In one example, taking an example where the length is 5 and the lift value is 8, the first node may determine that the index sequence in the coding sequence of the target subsequence is {0, 1, 8, 16, 24}.

[0166] In another example, for a length of 5 and a lift value of 8, the first node may determine that the index sequence in the coded sequence of the target subsequence is {0, 8, 16, 24, 32}, i.e., the index in the second bit sequence of all elements in the target subsequence is equal to a non-negative integer multiple of the lift value.

[0167] In some embodiments, the index in the second bit sequence of an element in the target subsequence is equal to the index in the systematic column of the parity check matrix.

[0168] For example, suppose there are 64 systematic columns in a parity-check matrix, with corresponding indices {0,1,...,63}. It is okay then the indices in the second bit sequence of the elements in the target subsequence are {0,1,2}. It is okay .

[0169] In some embodiments, the indices in the second bit sequence of the L elements in the target subsequence are the indices of the L columns in the parity check matrix with the smallest column weights, where L is the length of the target subsequence and L is a positive integer.

[0170] For example, taking a parity check matrix of size 60 rows and 120 columns as an example, the column indices corresponding to column weight 2 in the parity check matrix are 87 to 119, the column indices corresponding to column weight 3 in the parity check matrix are 64 to 79, the column indices corresponding to column weight 4 in the parity check matrix are 41 to 63, the column indices corresponding to column weight 5 in the parity check matrix are 20 to 40, the column indices corresponding to column weight 6 in the parity check matrix are 0 to 19, and the column indices corresponding to column weight 7 in the parity check matrix are 80 to 86.

[0171] If L is 7, the first node may determine the index sequence in the second bit sequence of the L elements in the target subsequence to be {87, 88, 89, 90, 91, 92, 93}.

[0172] In some embodiments, the first node determines the indices of the L elements in the target subsequence in the second bit sequence according to the column weight of the parity check matrix. For example, if the indices of the L columns with the lightest column weight of the parity check matrix are the indices of the L elements in the target subsequence in the second bit sequence, and L is 4, the first node may determine the index sequence of the L elements in the target subsequence in the second bit sequence as {87, 88, 89, 90}. Alternatively, if the indices of the L columns with the heaviest column weight of the parity check matrix are the indices of the L elements in the target subsequence in the second bit sequence, and L is 5, the first node may determine the index sequence of the L elements in the target subsequence in the second bit sequence as {80, 81, 82, 83, 84}.

[0173] In some implementations, The first node determines a base matrix according to the base graph matrix, determines a parity check matrix based on the base matrix and the lift value, and then performs error correction coding on the first bit sequence based on the parity check matrix to obtain a second bit sequence.

[0174] In some embodiments, The above base graph matrix includes two types of base graph matrices: a first base graph matrix and a second base graph matrix, among which the size of the base matrix corresponding to the first base graph matrix is ​​46 rows and 68 columns, and the size of the base matrix corresponding to the second base graph matrix is ​​42 rows and 52 columns.

[0175] If any of the following conditions is met, the base matrix is ​​determined by the second base graph matrix, and the parity check matrix is ​​determined by this base matrix: Condition 1, the length of the transport block is less than or equal to 292; Condition 2, the length of the transport block is less than or equal to 3824 and the coding rate is less than 0.67; Condition 3, the coding rate is less than 0.25. Otherwise, the base matrix is ​​determined by the first base graph matrix, and the parity check matrix is ​​determined by this base matrix.

[0176] In one embodiment, the number of rows of the basis matrix is ​​less than or equal to a predetermined threshold, or the number of columns of the basis matrix is ​​less than or equal to a predetermined threshold, or the number of systematic columns of the basis matrix is ​​less than or equal to a predetermined threshold, or the number of coded systematic columns is less than or equal to a fifth predetermined threshold, or the lift value is less than or equal to a predetermined lift value threshold, wherein the number of systematic columns of the basis matrix is ​​equal to the difference between the number of columns and the number of rows of the basis matrix, and the number of coded systematic columns is a positive integer less than or equal to the number of systematic columns of the basis matrix, and the number of coded systematic columns may be used to calculate the lift value, for example, the number of systematic columns of the basis matrix is ​​10, and the value of the number of coded systematic columns may be 6, 8, 9, or 10.

[0177] Exemplarily, the preset threshold for the number of rows may be 42, and the preset threshold for the number of columns may be 52. In this case, the basis matrix may be a basis matrix corresponding to the second base graph matrix. The preset threshold for the number of systematic columns may be equal to 10. The fifth preset threshold may be equal to any of 6, 8, 9, and 10. In a specific example, the fifth preset threshold is equal to 6, or the fifth preset threshold is equal to 8, or the fifth preset threshold is equal to 9.

[0178] In one embodiment, the lift value is less than or equal to a preset threshold lift value, where the preset threshold lift value may be equal to 32, 48, 56, 64, 72, 80, 88, 96, 104, or 128.

[0179] Note that the basis matrix corresponding to the first base graph matrix and the basis matrix corresponding to the second base graph matrix are the basis matrices defined in 3GPP (registered trademark) standard protocol 38.212, and will not be described again here.

[0180] In one example, if the base graph matrix is ​​a second base graph matrix, the target Sub If the sequence length is greater than 0 and the base graph matrix is ​​the first base graph matrix, then the target Sub The length of the sequence is equal to 0. Target Sub If the length of the sequence is equal to 0, no interleaving of the third bit sequence is required.

[0181] In the technical solution provided by the embodiments of the present application, the first node performs error correction encoding on the first bit sequence based on a parity check matrix to obtain a second bit sequence, which facilitates the first node to subsequently determine a target subsequence based on the information of the parity check matrix.

[0182] In some embodiments, As shown in S303, the first node interleaves the third bit sequence based on the target subsequence to obtain an interleaved fourth bit sequence. The embodiment of the present application may provide one possible implementation of S303 based on the embodiment of the method shown in FIG. 3. As shown in FIG. 12 in combination with FIG. 11, FIG. 12 is one implementation of S303 provided by the present application. Therefore, the implementation procedure in which the first node interleaves the third bit sequence based on the target subsequence to obtain an interleaved fourth bit sequence (i.e., S303) may include the following S1201:

[0183] S1201: The first node interleaves a third bit sequence based on an interleaving index sequence corresponding to a target subsequence to obtain a fourth bit sequence.

[0184] Among them, the two interleaving index sequences corresponding to any two different target subsequences are different, i.e., if A is an interleaving index sequence, Ai is the i-th element in A, B is another interleaving index sequence, and Bi is the i-th element in B, then Ai ≠ Bi for any i, where i is a natural number.

[0185] When a third bit sequence of length E is cyclically shifted, there are a maximum of E types of cyclic shift methods, i.e., E types of cyclic shift methods with the number of cyclic shift bits ranging from 0 to E-1. Different cyclic shift methods result in different interleaving index sequences. Since the length of a target subsequence is an integer obtained by taking the logarithm of E to base 2 and truncating, the number of interleaving index sequences corresponding to target subsequences of the same length is 2 to the Lth power (2^L), and 2^L is less than or equal to E. Therefore, by employing a cyclic shift interleaving method, it is possible to achieve different interleaving index sequences for any two sequences.

[0186] In some implementations, The fourth bit sequence may satisfy the following equation 11.

number

[0187] Here, F1 is the fourth bit sequence, F0 is the third bit sequence, and A is the interleaving index sequence.

[0188] In some embodiments, two interleaved index sequences corresponding to any two different target subsequences have at most T co-located elements, where T is a positive integer, i.e., if A is an interleaved index sequence, Ai is the i-th element in A, B is another interleaved index sequence, and Bi is the i-th element in B, then there are at most T indexes i such that Ai = Bi.

[0189] Illustratively, T is 1, 2, 3, 4, or 5. The first node can limit T and control T to be equal to or less than a first preset threshold, thereby avoiding the near-codeword problem (i.e., the same fourth bit sequence is output corresponding to a different first bit sequence) from occurring, which can cause the second node to be unable to correctly decode the code or generate an error in the error correction decoding procedure.

[0190] In some embodiments, In two interleaved index sequences corresponding to any two different target subsequences, a maximum percentage W% of elements at the same position have the same value, where W is a real number greater than 0 and less than 20. In some examples, W is equal to 1, 2, 3, 4, or 5. For example, if W is 2 and the length of the interleaved index sequences is 128, then in any two interleaved index sequences, elements at a maximum of two index positions have the same value, i.e., T is 2.

[0191] In the technical solution provided by this application, the first node interleaves a third bit sequence according to an interleaving index sequence corresponding to a target subsequence to obtain a fourth bit sequence, in which two interleaving index sequences corresponding to any two different target subsequences are different, or in which at most T elements at the same position in two interleaving index sequences corresponding to any two different target subsequences are the same, so that the first node adaptively interleaves the third bit sequence, and avoids the fourth bit sequences obtained by interleaving based on different third bit sequences from being the same, and further avoids the near-codeword problem.

[0192] The solutions in the above embodiments of the present application may be combined together as long as they are not contradictory.

[0193] The examples of the present application are as follows: communication equipmentThe above may be divided into functional modules or units. For example, each functional module or functional unit may be divided according to its function, or two or more functions may be integrated into one processing module. The integrated module may be implemented in the form of hardware or in the form of a software functional module or functional unit. In the embodiments of the present application, the division into modules or units is merely a schematic and represents a division of logical functions. In actual implementation, other division methods may be used.

[0194] When dividing each functional module according to each function is adopted, Fig. 13 shows a schematic diagram of the configuration of a communication device 130, and the communication device 130 shown in Fig. 13 may include a communication unit 1301 and a processing unit 1302. Since the communication device for executing the functions related to the second node in the above embodiment is similar to the communication device for executing the functions related to the first node in the above embodiment, this communication device 130 may be used to execute both the functions related to the first node in the above embodiment and the functions related to the second node in the above embodiment.

[0195] When the communication device 130 is used to perform the functions related to the first node in the above embodiment,

[0196] The processing unit 1302 is used to error correction encode the first bit sequence to obtain a second bit sequence, bit select the second bit sequence to obtain a third bit sequence, and interleave the third bit sequence based on a target subsequence to obtain an interleaved fourth bit sequence, where the target subsequence is a subsequence within the first bit sequence or a subsequence within the second bit sequence, and the length of the target subsequence is an integer greater than 0.

[0197] The communication unit 1301 is used to transmit the fourth bit sequence.

[0198] In some implementations,The target subsequence may consist of one or more contiguous bits in the second bit sequence, or the target subsequence may consist of one or more discrete bits in the second bit sequence.

[0199] In some implementations, The corresponding indexes in the second bit sequence of elements in the target subsequence are different from the corresponding indexes in the second bit sequence of elements in the third bit sequence.

[0200] In some implementations, The length of the target subsequence is determined according to the length of the first bit sequence or the length of the third bit sequence.

[0201] In some implementations, The target subsequence is determined according to one or more of the second bit sequence, the length of the third bit sequence, the length of the first bit sequence, the length of the useful information bits, the modulation order, the coding rate, the number of resources, the higher layer signaling, the type of user equipment, and the transport block size.

[0202] In some implementations, Specifically, the processing unit 1302 is used to error-correction-encode the first bit sequence based on a parity check matrix determined by the lift value and the basis matrix to obtain a second bit sequence.

[0203] In some implementations, The index in the second bit sequence of the first element of the target subsequence is equal to a non-negative integer multiple of the lift value.

[0204] In some implementations, The index in the second bit sequence of an element in the target subsequence is equal to the index in the systematic column of the parity check matrix.

[0205] In some implementations,The indices in the second bit sequence of the L elements in the target subsequence are the indices of the L columns with the smallest column weights in the parity check matrix, where L is the length of the target subsequence and L is a positive integer.

[0206] In some implementations, The processing unit 1302 is specifically used to interleave the third bit sequence based on the interleaving index sequence corresponding to the target subsequence to obtain a fourth bit sequence, in which the two interleaving index sequences corresponding to any two different target subsequences are different.

[0207] In some implementations, The processing unit 1302 is specifically used to interleave the third bit sequence based on the interleaving index sequence corresponding to the target subsequence to obtain a fourth bit sequence, in which at most T elements at the same position have the same value in two interleaving index sequences corresponding to any two different target subsequences, respectively, where T is a positive integer.

[0208] In some implementations, Interleaving includes circular interleaving and / or block interleaving.

[0209] In some implementations, The first bit sequence is determined based on a transport block awaiting transmission, the length of the transport block awaiting transmission being less than or equal to a first preset threshold.

[0210] In some implementations, The length of the first bit sequence is less than or equal to a second preset threshold.

[0211] In some implementations,The number of rows of the basis matrix is ​​less than or equal to a predetermined threshold for the number of rows, or the number of columns of the basis matrix is ​​less than or equal to a predetermined threshold for the number of columns, or the number of systematic columns of the basis matrix is ​​less than or equal to a predetermined threshold for the number of systematic columns, or the number of coded systematic columns is less than or equal to a fifth predetermined threshold, wherein the number of systematic columns of the basis matrix is ​​equal to the difference between the number of columns and the number of rows of the basis matrix, the number of coded systematic columns is a positive integer less than or equal to the number of systematic columns of the basis matrix, and the number of coded systematic columns may be used to calculate a lift value, or the lift value is less than or equal to a predetermined threshold for the lift value.

[0212] When the communication device 130 is used to perform the functions related to the second node in the above embodiment,

[0213] The communication unit 1301 is used to receive a fourth bit sequence from a first node, the fourth bit sequence being obtained by interleaving a third bit sequence with a target subsequence in a second bit sequence, the second bit sequence being obtained by error correction coding the first bit sequence, the third bit sequence being obtained by bit selecting the second bit sequence, and the length of the target subsequence being an integer greater than 0.

[0214] The processing unit 1302 is used to error-correction decode the fourth bit sequence based on the information of the target subsequence.

[0215] In some implementations, The target subsequence may consist of one or more contiguous bits in the second bit sequence, or the target subsequence may consist of one or more discrete bits in the second bit sequence.

[0216] In some implementations, The corresponding indexes in the second bit sequence of elements in the target subsequence are different from the corresponding indexes in the second bit sequence of elements in the third bit sequence.

[0217] In some implementations, The length of the target subsequence is determined according to the length of the first bit sequence or the length of the third bit sequence.

[0218] In some implementations, The target subsequence is determined according to one or more of the second bit sequence, the length of the third bit sequence, the length of the first bit sequence, the length of the useful information bits, the modulation order, the coding rate, the number of resources, the higher layer signaling, the type of user equipment, and the transport block size.

[0219] In some implementations, The second bit sequence is obtained by error-correction coding the first bit sequence using a parity check matrix determined by the lift value and the basis matrix.

[0220] In some implementations, The index in the second bit sequence of the first element of the target subsequence is equal to a non-negative integer multiple of the lift value.

[0221] In some implementations, The index in the second bit sequence of an element in the target subsequence is equal to the index in the systematic column of the parity check matrix.

[0222] In some implementations, The indices in the second bit sequence of the L elements in the target subsequence are the indices of the L columns with the smallest column weights in the parity check matrix, where L is the length of the target subsequence and L is a positive integer.

[0223] In some implementations, The fourth bit sequence is obtained by interleaving the third bit sequence with an interleaving index sequence corresponding to the target subsequence, and the two interleaving index sequences corresponding to any two different target subsequences are different.

[0224] In some implementations,The fourth bit sequence is obtained by interleaving the third bit sequence with an interleaving index sequence corresponding to a target subsequence, and at most T elements at the same position in two interleaving index sequences corresponding to any two different target subsequences, respectively, have the same value, where T is a positive integer.

[0225] In some implementations, Interleaving includes circular interleaving and / or block interleaving.

[0226] In some implementations, The first bit sequence is determined based on a transport block awaiting transmission, the length of the transport block awaiting transmission being less than or equal to a first preset threshold.

[0227] In some implementations, The length of the first bit sequence is less than or equal to a second preset threshold.

[0228] In some implementations, The number of rows of the basis matrix is ​​less than or equal to a predetermined threshold for the number of rows, or the number of columns of the basis matrix is ​​less than or equal to a predetermined threshold for the number of columns, or the number of systematic columns of the basis matrix is ​​less than or equal to a predetermined threshold for the number of systematic columns, or the number of coded systematic columns is less than or equal to a fifth predetermined threshold, wherein the number of systematic columns of the basis matrix is ​​equal to the difference between the number of columns and the number of rows of the basis matrix, the number of coded systematic columns is a positive integer less than or equal to the number of systematic columns of the basis matrix, and the number of coded systematic columns may be used to calculate a lift value, or the lift value is less than or equal to a predetermined threshold for the lift value.

[0229] As another possible implementation, the processing unit 1302 of FIG. 13 may be replaced by a processor that may integrate the functionality of the processing unit 1302.

[0230] Furthermore, if the processing unit 1302 is replaced by a processor, the communication device 130 according to the embodiment of the present application may be the communication device shown in FIG.

[0231] When dividing each functional module according to each function, Fig. 14 shows a schematic diagram of a configuration of a communication device 140, which may include a transmitter 1401 and a data processing module 1402. This communication device 140 may be used to execute the functions related to the first node in the above embodiment.

[0232] The data processing module 1402 is used to error correction encode a first bit sequence to obtain a second bit sequence, bit select the second bit sequence to obtain a third bit sequence, and interleave the third bit sequence based on a target subsequence to obtain an interleaved fourth bit sequence, where the target subsequence is a subsequence within the first bit sequence or a subsequence within the second bit sequence, and the length of the target subsequence is an integer greater than 0.

[0233] The transmitter 1401 is used to transmit the fourth bit sequence.

[0234] In some implementations, The target subsequence may consist of one or more contiguous bits in the second bit sequence, or the target subsequence may consist of one or more discrete bits in the second bit sequence.

[0235] In some implementations, The corresponding indexes in the second bit sequence of elements in the target subsequence are different from the corresponding indexes in the second bit sequence of elements in the third bit sequence.

[0236] In some implementations, The length of the target subsequence is determined according to the length of the first bit sequence or the length of the third bit sequence.

[0237] In some implementations, The target subsequence is determined according to one or more of the second bit sequence, the length of the third bit sequence, the length of the first bit sequence, the length of the useful information bits, the modulation order, the coding rate, the number of resources, the higher layer signaling, the type of user equipment, and the transport block size.

[0238] In some implementations, Specifically, the data processing module 14021402 is used to error-correction-encode the first bit sequence based on a parity check matrix determined by the lift value and the basis matrix, to obtain a second bit sequence.

[0239] In some implementations, The index in the second bit sequence of the first element of the target subsequence is equal to a non-negative integer multiple of the lift value.

[0240] In some implementations, The index in the second bit sequence of an element in the target subsequence is equal to the index in the systematic column of the parity check matrix.

[0241] In some implementations, The indices in the second bit sequence of the L elements in the target subsequence are the indices of the L columns with the smallest column weights in the parity check matrix, where L is the length of the target subsequence and L is a positive integer.

[0242] In some implementations, The data processing module 1402 is specifically used to interleave the third bit sequence based on the interleaving index sequence corresponding to the target subsequence to obtain a fourth bit sequence, in which the two interleaving index sequences corresponding to any two different target subsequences are different.

[0243] In some implementations,Specifically, the data processing module 1402 is used to interleave the third bit sequence based on the interleaving index sequence corresponding to the target subsequence to obtain a fourth bit sequence, in which at most T elements at the same position have the same value in two interleaving index sequences corresponding to any two different target subsequences, respectively, where T is a positive integer.

[0244] In some implementations, Interleaving includes circular interleaving and / or block interleaving.

[0245] In some implementations, The first bit sequence is determined based on a transport block awaiting transmission, the length of the transport block awaiting transmission being less than or equal to a first preset threshold.

[0246] In some implementations, The length of the first bit sequence is less than or equal to a second preset threshold.

[0247] In some implementations, The number of rows of the basis matrix is ​​less than or equal to a predetermined threshold for the number of rows, or the number of columns of the basis matrix is ​​less than or equal to a predetermined threshold for the number of columns, or the number of systematic columns of the basis matrix is ​​less than or equal to a predetermined threshold for the number of systematic columns, or the number of coded systematic columns is less than or equal to a fifth predetermined threshold, wherein the number of systematic columns of the basis matrix is ​​equal to the difference between the number of columns and the number of rows of the basis matrix, the number of coded systematic columns is a positive integer less than or equal to the number of systematic columns of the basis matrix, and the number of coded systematic columns may be used to calculate a lift value, or the lift value is less than or equal to a predetermined threshold for the lift value.

[0248] When dividing each functional module according to each function, Fig. 15 shows a schematic diagram of a configuration of a communication device 150, which may include a transmitter 1501, a processor 1502, and a storage medium 1503. This communication device 150 may be used to execute the functions related to the first node or the second node in the above embodiments.

[0249] The processor 1502 is used to error correction encode the first bit sequence to obtain a second bit sequence, bit select the second bit sequence to obtain a third bit sequence, and interleave the third bit sequence based on a target subsequence to obtain an interleaved fourth bit sequence, where the target subsequence is a subsequence within the first bit sequence or a subsequence within the second bit sequence, and the length of the target subsequence is an integer greater than 0.

[0250] The transmitter 1501 is used to transmit the fourth bit sequence.

[0251] In some implementations, The target subsequence may consist of one or more contiguous bits in the second bit sequence, or the target subsequence may consist of one or more discrete bits in the second bit sequence.

[0252] In some implementations, The corresponding indexes in the second bit sequence of elements in the target subsequence are different from the corresponding indexes in the second bit sequence of elements in the third bit sequence.

[0253] In some implementations, The length of the target subsequence is determined according to the length of the first bit sequence or the length of the third bit sequence.

[0254] In some implementations,The target subsequence is determined according to one or more of the second bit sequence, the length of the third bit sequence, the length of the first bit sequence, the length of the useful information bits, the modulation order, the coding rate, the number of resources, the higher layer signaling, the type of user equipment, and the transport block size.

[0255] In some implementations, Specifically, the processor 1502 is used to perform error correction coding on the first bit sequence based on a parity check matrix determined by the lift value and the basis matrix to obtain a second bit sequence.

[0256] In some implementations, The index in the second bit sequence of the first element of the target subsequence is equal to a non-negative integer multiple of the lift value.

[0257] In some implementations, The index in the second bit sequence of an element in the target subsequence is equal to the index in the systematic column of the parity check matrix.

[0258] In some implementations, The indices in the second bit sequence of the L elements in the target subsequence are the indices of the L columns with the smallest column weights in the parity check matrix, where L is the length of the target subsequence and L is a positive integer.

[0259] In some implementations, Specifically, the processor 1502 is used to interleave the third bit sequence based on the interleaving index sequence corresponding to the target subsequence to obtain a fourth bit sequence, in which the two interleaving index sequences corresponding to any two different target subsequences are different.

[0260] In some implementations,Specifically, the processor 1502 is used to interleave the third bit sequence based on the interleaving index sequence corresponding to the target subsequence to obtain a fourth bit sequence, in which at most T elements at the same position have the same value in two interleaving index sequences corresponding to any two different target subsequences, respectively, where T is a positive integer.

[0261] In some implementations, Interleaving includes circular interleaving and / or block interleaving.

[0262] In some implementations, The first bit sequence is determined based on a transport block awaiting transmission, the length of the transport block awaiting transmission being less than or equal to a first preset threshold.

[0263] In some implementations, The length of the first bit sequence is less than or equal to a second preset threshold.

[0264] In some implementations, The number of rows of the basis matrix is ​​less than or equal to a predetermined threshold for the number of rows, or the number of columns of the basis matrix is ​​less than or equal to a predetermined threshold for the number of columns, or the number of systematic columns of the basis matrix is ​​less than or equal to a predetermined threshold for the number of systematic columns, or the number of coded systematic columns is less than or equal to a fifth predetermined threshold, wherein the number of systematic columns of the basis matrix is ​​equal to the difference between the number of columns and the number of rows of the basis matrix, the number of coded systematic columns is a positive integer less than or equal to the number of systematic columns of the basis matrix, and the number of coded systematic columns may be used to calculate a lift value, or the lift value is less than or equal to a predetermined threshold for the lift value.

[0265] In some implementations,The processor 1502 (coupled between the storage medium 1503 and the transmitter 1501) may be any suitable processor capable of executing instructions or scripts of one or more software programs stored within the communication device 200 (e.g., in the memory 204). For example, the processor 1502 may execute processing program instructions 02 to process data 01. The transmitter 1501 may be used to transmit data to a second node. Therein, each software program module in the memory 204 may include instructions that, when executed by the processor 1502, cause the communication device 200 to perform a corresponding function. Thus, the non-transitory computer-readable storage medium of the storage medium 1503 may include instructions for performing all or a portion of the operations described above. It should be noted that, although the processing program instructions 02 are described as software instructions within the storage medium 1503, they may be implemented in software, firmware, or a combination of both.

[0266] In some implementations, The storage medium 1503 may include data 01, which may include a first bit sequence, a length of a target sub-sequence, a corresponding index in the second bit sequence of an element within the target sub-sequence, and other signaling parameters or / and a local cache of the second bit sequence, and processing program instructions 02. The processing program instructions 02 may be used to store data processing software code or instructions, which may include the data processing method shown in any of the above embodiments.

[0267] The embodiments of the present application further provide a computer-readable storage medium. All or part of the flow in the above method embodiments may be accomplished by a computer program that instructs related hardware, and the program may be stored in the computer-readable storage medium. When the program is executed, the program may include the flow of each of the above method embodiments. The computer-readable storage medium may include: communication equipmenta hard disk or memory of any of the above embodiments communication equipment The computer-readable storage medium may be an internal storage unit of the terminal device (including the data sending side and / or the data receiving side). The computer-readable storage medium may also be an external storage device of the terminal device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, or a non-transitory computer-readable storage medium (e.g., one or more non-volatile memory elements, EPROM, EEPROM, flash memory, hard disk drive, etc.). Furthermore, the computer-readable storage medium may be an external storage device of the terminal device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, or a non-transitory computer-readable storage medium (e.g., one or more non-volatile memory elements, EPROM, EEPROM, flash memory, hard disk drive, etc.). communication equipment The computer-readable storage medium may include both an internal storage unit and an external storage unit for storing the computer program and the communication equipment The computer-readable storage medium is for storing other programs and data necessary for the above. The computer-readable storage medium may also be used to temporarily store output data or output data.

[0268] It should be noted that terms such as "first" and "second" in the specification, claims, and drawings of this application are intended to distinguish different objects and not to describe a particular order. Furthermore, the terms "comprise" and "have" and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units. In some embodiments, may optionally include further steps or units not listed, or In some embodiments, Further, other steps or units inherent in these processes, methods, products or apparatuses may be included. Included It can be done.

[0269] From the description of the above embodiments, those skilled in the art will understand that, for convenience and brevity of explanation, only the division of each functional module is taken as an example, and in actual application, the above function allocation can be performed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to achieve all or part of the above-described functions.

[0270] It should be understood that the disclosed devices and methods in some embodiments provided in the present application may be realized in other ways. For example, the device embodiments described above are merely schematic, and the division of modules or units is merely a logical functional division. In actual implementation, other division methods may be used. For example, multiple units or components may be combined or integrated into another device, or some features may be omitted or not implemented. Furthermore, the shown or discussed couplings or direct couplings or communication connections between devices may be indirect couplings or communication connections via some interfaces, devices, or units, and may be in electrical, mechanical, or other forms.

[0271] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, i.e., located in one place or distributed across multiple different locations. Some or all of these units may be selected according to actual needs to achieve the objectives of the embodiments.

[0272] Furthermore, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The integrated unit may be realized in the form of hardware or in the form of a software functional unit.

[0273] The integrated unit may be realized in the form of a software functional unit and stored in a readable storage medium when sold or used as an independent product. Based on this understanding, the technical solutions of the embodiments of the present application may essentially, or the portions that contribute to the prior art, or all or part of the technical solutions may be embodied in the form of a software product stored in a storage medium and including several instructions that cause a device (which may be a one-chip microcomputer or chip) or a processor to perform all or part of the steps of the methods of each embodiment of the present application. The storage medium may include various media capable of storing program code, such as a USB disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or a compact disk.

[0274] The above is merely a specific embodiment of the present application, and the scope of protection of the present application is not limited thereto, and any modifications or substitutions within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be in accordance with the scope of protection of the claims.

Claims

1. A data transmission method applied in a first node, the method comprising: error correction coding the first bit sequence to obtain a second bit sequence; bit-selecting the second bit sequence to obtain a third bit sequence; interleaving the third bit sequence based on a target subsequence to obtain an interleaved fourth bit sequence, wherein the target subsequence is a subsequence within the first bit sequence or a subsequence within the second bit sequence, and the length of the target subsequence is an integer greater than zero; transmitting the fourth bit sequence. Data transmission method.

2. the target subsequence is comprised of one or more contiguous bits in the second bit sequence, or the target subsequence is comprised of one or more discrete bits in the second bit sequence. The method of claim 1.

3. a corresponding index in the second bit sequence of an element in the target subsequence is different from a corresponding index in the second bit sequence of an element in the third bit sequence; The method of claim 1.

4. the length of the target subsequence is determined according to the length of the first bit sequence or the length of the third bit sequence. The method of claim 1.

5. the target subsequence is determined according to one or more of the second bit sequence, the length of the third bit sequence, the length of the first bit sequence, the length of useful information bits, a modulation order, a coding rate, a number of resources, higher layer signaling, a type of user equipment, and a transport block size; The method of claim 1.

6. The step of error correction coding the first bit sequence to obtain a second bit sequence includes: and error-correction-encoding the first bit sequence based on a parity-check matrix determined by the lift value and a basis matrix to obtain the second bit sequence. The method of claim 1.

7. an index in the second bit sequence of the first element of the target subsequence is equal to a non-negative integer multiple of the lift value; The method of claim 6.

8. an index in the second bit sequence of an element in the target subsequence is equal to an index in a systematic column of the parity check matrix; The method of claim 6.

9. indices in the second bit sequence of the L elements in the target subsequence are indices of the L columns in the parity check matrix with the smallest column weights, where L is the length of the target subsequence and L is a positive integer; The method according to any one of claims 6 to 8.

10. interleaving the third bit sequence based on the target subsequence to obtain an interleaved fourth bit sequence, interleaving the third bit sequence based on an interleaving index sequence corresponding to the target subsequence to obtain the fourth bit sequence, wherein two interleaving index sequences corresponding to any two different target subsequences are different. The method of claim 1.

11. interleaving the third bit sequence based on the target subsequence to obtain an interleaved fourth bit sequence, interleaving the third bit sequence based on an interleaving index sequence corresponding to the target subsequence to obtain the fourth bit sequence, wherein at most T elements at the same position in two interleaving index sequences corresponding to any two different target subsequences, respectively, have the same value, where T is a positive integer; The method of claim 1.

12. The interleaving process includes circular interleaving and / or block interleaving.

12. The method of any one of claims 1, 10 and 11.

13. the first bit sequence is determined based on a transport block waiting to be transmitted, and the length of the transport block waiting to be transmitted is equal to or less than a first preset threshold. The method of claim 1.

14. the length of the first bit sequence is equal to or less than a second preset threshold; The method of claim 1.

15. the number of rows of the basis matrix is ​​less than or equal to a predetermined threshold number of rows, or the number of columns of the basis matrix is ​​less than or equal to a predetermined threshold number of columns, or the number of systematic columns of the basis matrix is ​​less than or equal to a predetermined threshold number of systematic columns, or the number of coded systematic columns is less than or equal to a fifth predetermined threshold, and the number of coded systematic columns is used to calculate the lift value, or the lift value is less than or equal to a predetermined threshold value of lift value. The method according to any one of claims 6 to 8.

16. A data transmission method, applied at a second node, comprising: receiving a fourth bit sequence from a first node, the fourth bit sequence being obtained by interleaving a third bit sequence with a target subsequence, the second bit sequence being obtained by error correction coding the first bit sequence, the third bit sequence being obtained by bit selecting the second bit sequence, the target subsequence being a subsequence within the first bit sequence or a subsequence within the second bit sequence, and the length of the target subsequence being an integer greater than 0; and error correction decoding the fourth bit sequence based on information of the target subsequence. Data transmission method.

17. the target subsequence is comprised of one or more contiguous bits in the second bit sequence, or the target subsequence is comprised of one or more discrete bits in the second bit sequence.

17. The method of claim 16.

18. a corresponding index in the second bit sequence of an element in the target subsequence is different from a corresponding index in the second bit sequence of an element in the third bit sequence; 17. The method of claim 16.

19. the length of the target subsequence is determined according to the length of the first bit sequence or the length of the third bit sequence.

17. The method of claim 16.

20. the target subsequence is determined according to one or more of the second bit sequence, the length of the third bit sequence, the length of the first bit sequence, the length of useful information bits, a modulation order, a coding rate, a number of resources, higher layer signaling, a type of user equipment, and a transport block size; 17. The method of claim 16.

21. the second bit sequence is obtained by error correction encoding the first bit sequence using a parity check matrix determined by a lift value and a basis matrix.

17. The method of claim 16.

22. an index in the second bit sequence of the first element of the target subsequence is equal to a non-negative integer multiple of the lift value; 22. The method of claim 21.

23. an index in the second bit sequence of an element in the target subsequence is equal to an index in a systematic column of the parity check matrix; 22. The method of claim 21.

24. indices in the second bit sequence of the L elements in the target subsequence are indices of the L columns in the parity check matrix with the smallest column weights, where L is the length of the target subsequence and L is a positive integer; The method according to any one of claims 21 to 23.

25. the fourth bit sequence is obtained by interleaving the third bit sequence with an interleaving index sequence corresponding to the target subsequence, and two interleaving index sequences corresponding to any two different target subsequences are different from each other; 17. The method of claim 16.

26. the fourth bit sequence is obtained by interleaving the third bit sequence with an interleaving index sequence corresponding to the target subsequence, and at most T elements at the same position in two interleaving index sequences corresponding to any two different target subsequences, respectively, have the same value, where T is a positive integer; 17. The method of claim 16.

27. The interleaving process includes circular interleaving and / or block interleaving.

27. The method of any one of claims 16, 25 and 26.

28. the first bit sequence is determined based on a transport block waiting to be transmitted, and the length of the transport block waiting to be transmitted is equal to or less than a first preset threshold.

17. The method of claim 16.

29. the length of the first bit sequence is equal to or less than a second preset threshold; 17. The method of claim 16.

30. the number of rows of the basis matrix is ​​less than or equal to a predetermined threshold number of rows, or the number of columns of the basis matrix is ​​less than or equal to a predetermined threshold number of columns, or the number of systematic columns of the basis matrix is ​​less than or equal to a predetermined threshold number of systematic columns, or the number of coded systematic columns is less than or equal to a fifth predetermined threshold, and the number of coded systematic columns is used to calculate the lift value, or the lift value is less than or equal to a predetermined threshold value of lift value. The method according to any one of claims 21 to 23.

31. a processor and a memory for storing executable instructions for said processor; The processor is configured to execute the instructions to cause a communication device to perform the method of any one of claims 1 to 15 and / or to perform the method of any one of claims 16 to 30. Communication equipment.

32. storing computer instructions which, when executed on a computer, cause the computer to carry out the method according to any one of claims 1 to 15 and / or the method according to any one of claims 16 to 30; A computer-readable storage medium.

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