Light-emitting element and display device including the same

Abstract

A light emitting device according to an embodiment may include a light emitting stack pattern including a first semiconductor layer, an active layer, and a second semiconductor layer; and an insulating film surrounding an outer periphery of the light emitting stack pattern. The insulating film may include a first layer, a second layer surrounding the first layer, and a third layer surrounding the second layer. The first layer and the third layer may include the same material.

Description

[Technical Field]

[0001] The present invention relates to a light-emitting element and a display device including the same. [Background technology]

[0002] 2. Description of the Related Art In recent years, interest in information displays has increased, and research and development into display devices has been continuously carried out. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention can provide a light-emitting element with improved reliability and a display device including the same. [Means for solving the problem]

[0004] A light emitting device according to an embodiment may include a light emitting stack pattern including a first semiconductor layer, an active layer, and a second semiconductor layer; and an insulating film surrounding an outer periphery of the light emitting stack pattern. The insulating film may include a first layer, a second layer surrounding the first layer, and a third layer surrounding the second layer. The first layer and the third layer may include the same material.

[0005] In an embodiment, the first layer and the third layer are made of ZrOx, SiOx, HfO x ,BeO,Ta x O y , Al x O y , La x O y , Ta x O y , Nb x O y , TiO x , CeO x , MgO, Y x O y , Sr x O y It may include at least one of:

[0006] In an embodiment, the first layer and the third layer are made of AlN, AlGaN, InGaN, SiN x , AlO x N y , HfN, ZrN, HfO x N y , ZrO x N y It may include at least one of:

[0007] In an embodiment, the first layer may have a thickness of 5 nm or less, and the third layer may have a thickness of 10 nm or less.

[0008] In embodiments, the second layer may comprise a different material than the first and third layers.

[0009] In an embodiment, the first layer may be disposed directly on the outer peripheral surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer.

[0010] In an embodiment, the first semiconductor layer may include an n-type semiconductor layer doped with an n-type dopant, and the second semiconductor layer may include a p-type semiconductor layer doped with a p-type dopant.

[0011] In an embodiment, the light emitting stack pattern may further include an electrode layer disposed on the second semiconductor layer, and the insulating film may be disposed directly on outer peripheral surfaces of the first semiconductor layer, the active layer, the second semiconductor layer, and the electrode layer.

[0012] In an embodiment, the insulating film may further include a fourth layer surrounding the third layer, the fourth layer including an inorganic insulating material, and having a thickness greater than the first to third layers.

[0013] In an embodiment, the insulating film may further include a fifth layer surrounding the fourth layer, the fifth layer including an inorganic insulating material, and having a thickness greater than the first to fourth layers.

[0014] A light emitting device according to an embodiment may include a light emitting stack pattern including a first semiconductor layer, an active layer, a second semiconductor layer, and an electrode layer sequentially stacked in one direction; and an insulating film surrounding an outer periphery of the light emitting stack pattern. The insulating film may include a first layer disposed directly on the outer periphery of the light emitting stack pattern and surrounding the light emitting stack pattern; a second layer surrounding the first layer; a third layer surrounding the second layer; a fourth layer surrounding the third layer; and a fifth layer surrounding the fourth layer. The first layer and the third layer may include the same material, and the second layer may include a different material from the first and third layers.

[0015] In an embodiment, the first layer and the third layer are made of ZrO x , SiO x , HfO x ,BeO,Ta x O y , Al x O y , La x O y , Ta x O y , Nb x O y , TiO x , CeO x , MgO, Y x O y , Sr x O y It may include at least one of:

[0016] In an embodiment, the first layer and the third layer are made of AlN, AlGaN, InGaN, SiN x , AlO x N y , HfN, ZrN, HfO x N y , ZrO x N yIt may include at least one of:

[0017] In an embodiment, the first layer may have a thickness of 5 nm or less, and the third layer may have a thickness of 10 nm or less.

[0018] In an embodiment, the fourth layer and the fifth layer may include an inorganic insulating material.

[0019] A display device according to an embodiment may include a substrate; a first electrode and a second electrode spaced apart from each other on the substrate; and a light emitting element positioned on the substrate, the light emitting element including a first end electrically connected to the first electrode and a second end electrically connected to the second electrode. The light emitting element may include a light emitting stack pattern including a first semiconductor layer positioned at the second end, an active layer positioned on the first semiconductor layer, a second semiconductor layer positioned on the active layer, and an electrode layer positioned on the second semiconductor layer and at the first end; and an insulating film surrounding an outer periphery of the light emitting stack pattern. The insulating film may include a first layer directly positioned on the outer periphery of the light emitting stack pattern; a second layer surrounding the first layer; and a third layer surrounding the second layer. The first layer and the third layer may include the same material, and the second layer may include a different material from the first and third layers.

[0020] In an embodiment, the first layer and the third layer are made of ZrO x , SiO x , HfO x ,BeO,Ta x O y , Al x O y , La x O y , Ta x O y , Nb x O y , TiO x , CeO x , MgO, Y x O y , Sr x Oy It may include at least one of:

[0021] In an embodiment, the first layer and the third layer are made of AlN, AlGaN, InGaN, SiN x , AlO x N y , HfN, ZrN, HfO x N y , ZrO x N y It may include at least one of:

[0022] In an embodiment, the first layer may have a thickness of 5 nm or less, and the third layer may have a thickness of 10 nm or less.

[0023] In this embodiment, the display device may further include: an emitting region in which light is emitted from the light-emitting element and a non-emitting region surrounding the emitting region; a first alignment electrode disposed between the substrate and the first electrode and electrically connected to the first electrode; a second alignment electrode disposed between the substrate and the second electrode and electrically connected to the second electrode; a first bank located in the non-emitting region and including an opening corresponding to the emitting region; a second bank located on the first bank; a color conversion layer surrounded by the second bank and located above the light-emitting element; and a color filter disposed on the color conversion layer. [Effects of the Invention]

[0024] According to the embodiment, a multi-layer insulating film including a first layer, a second layer, and a third layer is disposed on the outer peripheral surface of a light-emitting laminated pattern including a first semiconductor layer, an active layer, and a second semiconductor layer, and the first layer and the third layer are made of the same material, thereby effectively controlling surface defects of the light-emitting laminated pattern, improving the protective film properties of the insulating film, and improving the life and efficiency of the light-emitting device.

[0025] According to the embodiment, a display device including the above-described light-emitting element can be provided.

[0026] The effects of the embodiments are not limited to the above-mentioned examples, and various other effects are included in the present specification. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a schematic perspective view of a light-emitting device according to an embodiment; [Figure 2] FIG. 2 is a schematic diagram of the light-emitting element of FIG. 1 as seen from above. [Figure 3] FIG. 2 is a schematic cross-sectional view of the light-emitting device of FIG. [Figure 4] 1 is a schematic perspective view of a light-emitting device according to an embodiment; [Figure 5] 5 is a schematic diagram of the light-emitting element of FIG. 4 as seen from above. [Figure 6] FIG. 4 is a schematic cross-sectional view of the light-emitting device of FIG. [Figure 7] 1 is a schematic perspective view of a light-emitting device according to an embodiment; [Figure 8] 8 is a schematic diagram of the light-emitting element of FIG. 7 as seen from above. [Figure 9] FIG. 6 is a schematic cross-sectional view of the light-emitting device of FIG. [Figure 10] 1 is a schematic plan view of a display device according to an embodiment; [Figure 11] 11 is a schematic circuit diagram showing the electrical connections of components included in each pixel shown in FIG. 10. [Figure 12] FIG. 2 is a schematic plan view showing a pixel according to an embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view taken along line II' in FIG. [Figure 14] FIG. 13 is a schematic cross-sectional view taken along line II' in FIG. [Figure 15] FIG. 14 is a schematic enlarged view showing the EA portion of FIG. [Figure 16] FIG. 13 is a schematic cross-sectional view corresponding to line II' in FIG. [Figure 17] FIG. 13 is a schematic cross-sectional view corresponding to line II' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0028] Although the present invention is susceptible to various modifications and can be embodied in various forms, only specific embodiments are illustrated in the drawings and the present disclosure will be described based on these. However, the present invention is not limited to the specific disclosed embodiments, and it should be understood that all modifications, equivalents, and alternatives falling within the technical scope of the present invention are included in the present invention.

[0029] In the description of each drawing, like reference numerals are used for like elements. In the accompanying drawings, the dimensions of structures are exaggerated for clarity. Terms such as "first" and "second" are used to describe various elements, but the elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be called a "second element," and similarly, a second element can be called a "first element" without departing from the scope of the present invention.

[0030] In this application, the use of terms such as "comprises" or "has" specifies the presence of a specified feature, numeral, step, operation, component, part, or combination thereof, and does not preclude the presence or addition of one or more other features, numerals, steps, operations, components, parts, or combinations thereof. Furthermore, when a layer, film, region, plate, or other portion is described as being "on" another portion, this includes not only the case where it is "directly on" the other portion, but also the case where another portion is located between them. Furthermore, in this specification, when a layer, film, region, plate, or other portion is described as being formed on another portion, this does not mean that it is formed only in an upward direction, but also includes the case where it is formed in a lateral or downward direction. Conversely, when a layer, film, region, plate, or other portion is described as being "under" another portion, this includes not only the case where it is "directly under" the other portion, but also the case where another portion is located between them.

[0031] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, along with other matters necessary for those skilled in the art to easily understand the contents of the present invention. In the following description, the singular expression also includes the plural expression unless the context clearly indicates that only the singular is included.

[0032] FIG. 1 is a schematic perspective view of a light-emitting element LD according to an embodiment, FIG. 2 is a schematic view of the light-emitting element LD of FIG. 1 as seen from above, and FIG. 3 is a schematic cross-sectional view of the light-emitting element LD of FIG.

[0033] 1 to 3, the light emitting element LD may have a shape that extends in one direction. If the extension direction of the light emitting element LD is defined as the length direction, the light emitting element LD may include a first end EP1 and a second end EP2 that face each other along the length direction.

[0034] The light emitting device LD may include a light emitting stacked pattern 10 and an insulating film 14 surrounding the outer periphery of the light emitting stacked pattern 10. As an example, the light emitting device LD may include a light emitting stacked pattern 10 (or a light emitting pattern) in which a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 12 are stacked one on top of the other, and an insulating film 14 surrounding the outer periphery of the light emitting stacked pattern 10.

[0035] The light emitting device LD may be provided in various shapes. For example, the light emitting device LD may have a rod shape, a bar shape, or a column shape that is long in the length direction (for example, an aspect ratio greater than 1). The light emitting device LD may also have a rod shape, a bar shape, or a column shape that is short in the length direction. However, the shape of the light emitting device LD is not limited thereto. The shape of the light emitting device LD may correspond to the shape of the light emitting stack pattern 10. For example, if the light emitting stack pattern 10 has a columnar shape, such as a cylinder, the light emitting device LD may also have a columnar shape.

[0036] Such a light emitting element LD may include, for example, a light emitting diode (LED) that is fabricated to be ultra-small so as to have a diameter D and / or length L on the nanoscale (or nanometer) to microscale (or micrometer) scale.

[0037] When the light emitting device LD is long in the length direction, the diameter D of the light emitting device LD may be about 0.5 μm to 6 μm, and the length L thereof may be about 1 μm to 10 μm. However, the diameter D and length L of the light emitting device LD are not limited thereto, and the size of the light emitting device LD may be changed to meet the requirements (or design conditions) of the lighting device or self-luminous display device to which the light emitting device LD is applied.

[0038] One of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at a first end EP1 of the light emitting element LD, and the other may be located at a second end EP2 of the light emitting element LD. As an example, the second semiconductor layer 13 (or a p-type semiconductor layer) or an electrode layer 15 in ohmic contact with the second semiconductor layer 13 may be located at the first end EP1 of the light emitting element LD, and the first semiconductor layer 11 (or an n-type semiconductor layer) may be located at the second end EP2 of the light emitting element LD.

[0039] For example, the first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may be an n-type semiconductor layer that includes at least one semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a first conductivity dopant (or n-type dopant) such as Si, Ge, or Sn. However, the material constituting the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be made of various other materials.

[0040] The active layer 12 may emit light having a wavelength of about 400 nm to 900 nm and may have a double heterostructure. Light emitted from the active layer 12 may be emitted not only from the outer surface in the longitudinal direction of the light emitting device LD but also from both ends. The directionality of the light emitted from the active layer 12 is not limited to one direction. In an embodiment, a clad layer doped with a conductive dopant may be formed on the upper and / or lower portions of the active layer 12 along the longitudinal direction of the light emitting device LD. The clad layer may include AlGaN or InAlGaN. According to an embodiment, materials such as AlGaN and InAlGaN may be used to form the active layer 12, but various other materials may also be used to form the active layer 12. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0041] When an electric field equal to or greater than a predetermined voltage or a selected voltage is applied to both ends of the light emitting element LD, electron-hole pairs are recombined in the active layer 12, causing the light emitting element LD to emit light. By controlling the light emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source for various light emitting devices, including pixels of display devices.

[0042] The second semiconductor layer 13 is disposed on the active layer 12 and may include a semiconductor layer of a different type from the first semiconductor layer 11. As an example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer that includes at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, or InN and is doped with a dopant of second conductivity (or a p-type dopant) such as Mg, Zn, Ca, Sr, or Ba. However, the material constituting the second semiconductor layer 13 is not limited thereto, and various other materials may also be used to constitute the second semiconductor layer 13.

[0043] The first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses in the length direction of the light emitting device LD. For example, the first semiconductor layer 11 may have a relatively larger thickness than the second semiconductor layer 13 in the length direction of the light emitting device LD. However, this is not limiting, and according to an embodiment, the first semiconductor layer 11 and the second semiconductor layer 13 may have substantially similar or the same thickness in the length direction of the light emitting device LD.

[0044] 3, the first semiconductor layer 11 and the second semiconductor layer 13 are each shown as being composed of a single layer, but are not limited thereto. In an embodiment, depending on the material of the active layer 12, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include at least one layer, for example, a cladding layer and / or a tensile strain barrier reducing (TSBR) layer.

[0045] In an embodiment, the light emitting device LD (or the light emitting stack pattern 10 ) may include an electrode layer 15 disposed on the second semiconductor layer 13 .

[0046] The electrode layer 15 may be, but is not limited to, an ohmic contact electrode. According to an embodiment, the electrode layer 15 may be a Schottky contact electrode. When the light emitting element LD is electrically connected to an alignment electrode or an electrode in a display device (see "DD" in FIG. 10), the electrode layer 15 can reduce the resistance between the light emitting element LD and the alignment electrode or an electrode. The electrode layer 15 may include a conductive material. For example, the electrode layer 15 may include, but is not limited to, an opaque metal such as chromium, titanium, aluminum, gold, nickel, and oxides or alloys thereof, either alone or in combination. According to an embodiment, the electrode layer 15 may be made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or the like. xThe transparent conductive oxide may include transparent conductive oxides such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and the like.

[0047] An insulating film 14 may be disposed on an outer peripheral surface (or external surface) of the light emitting stack pattern 10, which includes the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the electrode layer 15 stacked in one direction (for example, from the second end EP2 to the first end EP1). For example, the insulating film 14 may surround the outer peripheral surface of the light emitting stack pattern 10. According to an embodiment, the insulating film 14 may surround only a portion of the light emitting stack pattern 10.

[0048] The insulating film 14 may expose both ends of the light emitting stack pattern 10 having different polarities. For example, the insulating film 14 may expose a portion of the electrode layer 15 located at a first end EP1 of the light emitting stack pattern 10 and a portion of the first semiconductor layer 11 located at a second end EP2 of the light emitting stack pattern 10.

[0049] The insulating film 14 can prevent electrical short circuits that may occur when the active layer 12 comes into contact with conductive materials other than the first and second semiconductor layers 11 and 13. The insulating film 14 can also minimize surface defects of the light emitting stack pattern 10 to improve the lifespan and light emitting efficiency of the light emitting device LD. When multiple light emitting devices LD are closely arranged, the insulating film 14 can also prevent undesirable short circuits that may occur between adjacent light emitting devices LD.

[0050] The insulating film 14 may be disposed to surround the outer periphery of the light emitting stack pattern 10. The outer periphery of the light emitting stack pattern 10 may be the side surface of the light emitting element LD excluding the first end EP1 and the second end EP2.

[0051] The insulating film 14 may be disposed to surround the outer peripheral surfaces (surfaces or external surfaces) of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the electrode layer 15. The insulating film 14 may be disposed to surround the outer peripheral surfaces of all of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the electrode layer 15, or may be disposed to surround the outer peripheral surfaces of some of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the electrode layer 15. The insulating film 14 is formed in a region of the light emitting stacked pattern 10 having a high concentration of surface defects, thereby effectively controlling the surface defects.

[0052] The insulating film 14 may include a transparent insulating material. Various materials having insulating properties may be used as the material for the insulating film 14.

[0053] The insulating film 14 may be provided in the form of multiple layers, including at least three layers. In an embodiment, the insulating film 14 may include a first layer FRL, a second layer SNL, and a third layer TIL. The first layer FRL may be disposed directly on the outer periphery of the light-emitting stack pattern 10 and surround the light-emitting stack pattern 10. The second layer SNL may be disposed on the first layer FRL and surround the first layer FRL. The third layer TIL may be disposed on the second layer SNL and surround the second layer SNL.

[0054] The third layer TIL may be on the outer circumferential surface (or surface) of the light emitting element LD. For example, the third layer TIL may be located on the outermost side of the light emitting element LD.

[0055] The first layer FRL may include a first surface FRLa and a second surface FRLb facing each other in the longitudinal direction of the light emitting element LD. In a direction perpendicular to the longitudinal direction of the light emitting element LD, the first surface FRLa may be positioned on the same line as the second end EP2 of the light emitting element LD, and the second surface FRLb may be positioned on the same line as the first end EP1 of the light emitting element LD, but is not limited thereto.

[0056] The second layer SNL may include a first surface SNLa and a second surface SNLb facing each other in the length direction of the light emitting element LD. In a direction perpendicular to the length direction of the light emitting element LD, the first surface SNLa may be positioned on the same line as the second end EP2 of the light emitting element LD, and the second surface SNLb may be positioned on the same line as the first end EP1 of the light emitting element LD, but is not limited thereto.

[0057] The third layer TIL may include a first surface TILa and a second surface TILb facing each other in the length direction of the light emitting element LD. In a direction perpendicular to the length direction of the light emitting element LD, the first surface TILa may be positioned on the same line as the second end EP2 of the light emitting element LD, and the second surface TILb may be positioned on the same line as the first end EP1 of the light emitting element LD, but is not limited thereto.

[0058] In an embodiment, the first layer FRL and the third layer TIL may include the same material. For example, the first layer FRL and the third layer TIL may include zirconium oxide (ZrO x ), silicon oxide (SiO x ), hafnium oxide (HfO x ), beryllium oxide (BeO), tantalum oxide (Ta x O y ), aluminum oxide (Al x O y ), lanthanum oxide (La x O y ), niobium oxide (Nb x O y ), titanium oxide (TiO x ), cerium oxide (CeO x ), magnesium oxide (MgO), yttrium oxide (Y x O y ), strontium oxide (Sr x O yThe first layer FRL and the third layer TIL may include at least one of aluminum nitride (AlN), hafnium nitride (HfN), zirconium nitride (ZrN), silicon nitride (SiN x ), aluminum oxynitride (AlO x N y ), hafnium oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y In an embodiment, the first layer FRL and the third layer TIL may include at least one of zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ), hafnium oxynitride (HfO x N y ) may include at least one of:

[0059] The second layer SNL may be made of a material different from that of the first and third layers FRL and TIL. The second layer SNL may be made of a material different from that of the first and third layers FRL and TIL, among the materials exemplified as the materials of the first and third layers FRL and TIL. For example, the first and third layers FRL and TIL may be made of zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ), hafnium oxynitride (HfO x N y ), the second layer SNL contains at least one of aluminum oxide (Al x O y ).

[0060] The first layer FRL may surround the outer periphery of the light emitting stack pattern 10 with a thickness d1 of 5 nm or less. The first layer FRL may have a thickness d1 that is relatively thinner than the second and third layers SNL and TIL. The second layer SNL may have a thickness d2 that is thicker than the first layer FRL and may surround the first layer FRL. The third layer TIL may have a thickness d3 that is relatively thicker than the first and second layers FRL and SNL. However, this is not limited thereto, and according to an embodiment, the third layer TIL may be formed thinner than the first layer FRL.

[0061] The first layer FRL may be coated to entirely surround the side and both ends of the light emitting stack pattern 10 patterned into a desired shape, the second layer SNL may be coated to entirely surround the first layer FRL, and the third layer TIL may be coated to entirely surround the second layer SNL. In a subsequent etching process, portions of the first, second, and third layers FRL, SNL, and TIL may be removed to expose portions of the electrode layer 15 located at the first end EP1 of the light emitting element LD and the first semiconductor layer 11 located at the second end EP2 of the light emitting element LD, respectively, thereby finally forming an insulating film 14 surrounding the outer periphery of the light emitting stack pattern 10 (for example, the side surfaces excluding the first end EP1 and the second end EP2). However, the method of forming the insulating film 14 is not limited thereto.

[0062] An etching process may be generally performed to manufacture the light emitting laminate pattern 10. The etching process partially removes atoms from the outer periphery (or surface) of the light emitting laminate pattern 10, resulting in surface defects of the light emitting laminate pattern 10 due to vacancies or dangling bonds. Furthermore, when the light emitting device LD has a size of nanometers to micrometers, the surface area-to-volume ratio increases, which may further increase the surface defects of the light emitting laminate pattern 10. The first layer FRL may be disposed directly on the outer periphery of the light emitting laminate pattern 10 to reduce surface defects that may occur during the manufacturing process of the light emitting laminate pattern 10. For example, the first layer FRL may be formed of zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ), hafnium oxynitride (HfO x N y ), it is possible to reduce lattice defects that may occur between the first layer FRL and the light emitting laminate pattern 10. In this case, the first layer FRL grows appropriately on the outer peripheral surface of the light emitting laminate pattern 10, protecting the outer peripheral surface of the light emitting laminate pattern 10 and reducing surface defects of the light emitting laminate pattern 10.

[0063] When the thickness d1 of the first layer FRL is 5 nm or less (i.e., when the thickness d1 of the first layer FRL is thinner than that of a typical thin film process), only the interface characteristics between the light emitting stack pattern 10 and the first layer FRL can be controlled. However, when the thickness d1 of the first layer FRL increases (or when another layer containing the same material as the first layer FRL surrounds the first layer FRL), the first layer FRL itself has thin film characteristics, and the characteristics of the insulating film 14 (for example, its characteristics as a protective film that protects the light emitting stack pattern 10) may be degraded. Such a deterioration in the characteristics of the insulating film 14 may reduce the reliability of the light emitting element LD.

[0064] In the embodiment, a second layer SNL made of a different material from the first layer FRL is disposed on the first layer FRL, and a third layer TIL made of a different material from the second layer SNL is disposed on the second layer SNL, so that the insulating film 14 surrounding the outer peripheral surface of the light-emitting stacked pattern 10 has a discontinuous configuration, thereby improving the above-mentioned deterioration in the characteristics of the insulating film 14. This improves the reliability of the light-emitting element LD.

[0065] As described above, when a multi-layer insulating film 14 including a first layer FRL, a second layer SNL, and a third layer TIL is disposed on the outer peripheral surface (or surface) of the light emitting stack pattern 10 to surround the outer peripheral surface of the light emitting stack pattern 10, the interaction between the first layer FRL, the second layer SNL, and the third layer TIL can easily or effectively control surface defects of the light emitting stack pattern 10, improve the protective film properties of the insulating film 14, and thereby improve the reliability (or light emitting efficiency) of the light emitting element LD.

[0066] The light emitting device LD described above can be grown and fabricated on a substrate (not shown) for epitaxial growth.

[0067] The light emitting device LD can be used as a light source for various display devices. The light emitting device LD can be manufactured through a surface treatment process. For example, when a plurality of light emitting devices LD are mixed in a fluid solution (or solvent) and supplied to each pixel region (e.g., a light emitting region of each pixel (or sub-pixel)), the surface of each light emitting device LD can be treated so that the light emitting devices LD are uniformly injected into the solution without being unevenly aggregated.

[0068] The light emitting unit including the light emitting element LD described above can be used in various types of electronic devices that require a light source, including display devices.

[0069] FIG. 4 is a schematic perspective view of the light-emitting element LD according to one embodiment, FIG. 5 is a schematic view of the light-emitting element LD of FIG. 4 as seen from above, and FIG. 6 is a schematic cross-sectional view of the light-emitting element LD of FIG.

[0070] Regarding the embodiment of FIGS. 4 to 6, in order to avoid redundant explanation, differences from the above-described embodiment will be mainly described.

[0071] 4 to 6, the light emitting device LD may include a light emitting laminate pattern 10 and an insulating film 14 surrounding the outer periphery (or surface) of the light emitting laminate pattern 10.

[0072] The light emitting stacked pattern 10 may include a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an electrode layer 15 stacked one on top of the other in the length direction of the light emitting device LD.

[0073] The insulating film 14 may be provided in the form of multiple layers, including at least four layers. In an embodiment, the insulating film 14 may include a first layer FRL, a second layer SNL, a third layer TIL, and a fourth layer FUL. The first layer FRL may be disposed directly on the outer periphery of the light emitting stack pattern 10 and surround the light emitting stack pattern 10. The second layer SNL may be disposed on the first layer FRL and surround the first layer FRL. The third layer TIL may be disposed on the second layer SNL and surround the second layer SNL. The fourth layer FUL may be disposed on the third layer TIL and surround the third layer TIL. The first layer FRL, the second layer SNL, and the third layer TIL may be the first layer FRL, the second layer SNL, and the third layer TIL described with reference to FIGS. 1 to 3.

[0074] The fourth layer FUL may be the outer peripheral surface (or surface) of the light emitting device LD. For example, the fourth layer FUL may be located at the outermost side of the light emitting device LD.

[0075] The fourth layer FUL may include a first surface FULa and a second surface FULb facing each other in the length direction of the light emitting element LD. In a direction perpendicular to the length direction of the light emitting element LD, the first surface FULa may be positioned on the same line as the second end EP2 of the light emitting element LD, and the second surface FULb may be positioned on the same line as the first end EP1 of the light emitting element LD, but is not limited thereto.

[0076] The first layer FRL and the third layer TIL may include the same material. For example, the first layer FRL and the third layer TIL may include zirconium oxide (ZrO x ), silicon oxide (SiO x ), hafnium oxide (HfO x ), beryllium oxide (BeO), tantalum oxide (Ta x O y ), aluminum oxide (Al x O y ), lanthanum oxide (La x O y ), niobium oxide (Nb x O y ), titanium oxide (TiO x ), cerium oxide (CeO x ), magnesium oxide (MgO), yttrium oxide (Y x O y ), strontium oxide (Sr x O y The first layer FRL and the third layer TIL may include at least one of aluminum nitride (AlN), hafnium nitride (HfN), zirconium nitride (ZrN), silicon nitride (SiN x ), aluminum oxynitride (AlO x N y ), hafnium oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y In an embodiment, the first layer FRL and the third layer TIL may include at least one of zirconium oxide (ZrO x), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ), hafnium oxynitride (HfO x N y ) may include at least one of:

[0077] The second layer SNL can be made of a material different from the first and third layers FRL and TIL described above.

[0078] The fourth layer FUL may include an inorganic insulating material. The fourth layer FUL may be made of a material different from that of the first and third layers FRL and TIL. In addition, the fourth layer FUL may be made of the same material as that of the second layer SNL or a material different from that of the second layer SNL. The fourth layer FUL may be made of a material different from that of the first and third layers FRL and TIL, among the materials exemplified as the material of the first and third layers FRL and TIL. For example, the first and third layers FRL and TIL may be made of zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ), hafnium oxynitride (HfO x N y ), the fourth layer FUL is silicon oxide (SiO x ).

[0079] The fourth layer FUL, together with the first, second and third layers FRL, SNL and TIL, can expose a portion of the electrode layer 15 located at the first end EP1 of the light-emitting element LD and a portion of the first semiconductor layer 11 located at the second end EP2 of the light-emitting element LD.

[0080] The fourth layer FUL may have a thickness d4 that is relatively thicker than the first to third layers FRL, SNL, and TIL. As an example, the fourth layer FUL may have a thickness d4 of about 10 nm to 40 nm, but is not limited thereto.

[0081] When the fourth layer FUL is disposed on the third layer TIL and surrounds the third layer TIL, it reduces surface defects of the light emitting stack pattern 10 that occur during the manufacturing process, further reduces lattice defects that exist between the light emitting stack pattern 10 and the first to third layers FRL, SNL, and TIL, and further prevents the active layer 12 (or light emitting layer) from being short-circuited with external conductive materials, thereby improving the reliability of the light emitting device LD.

[0082] 7 is a schematic perspective view of a light-emitting element LD according to one embodiment, FIG. 8 is a schematic view of the light-emitting element LD of FIG. 7 as seen from above, and FIG. 9 is a schematic cross-sectional view of the light-emitting element LD of FIG.

[0083] Regarding the embodiment of FIGS. 7 to 9, in order to avoid redundant explanation, only the differences from the embodiment described above will be explained.

[0084] 7 to 9, the light emitting device LD may include a light emitting laminate pattern 10 and an insulating film 14 surrounding the outer periphery (or surface) of the light emitting laminate pattern 10.

[0085] The light emitting stacked pattern 10 may include a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an electrode layer 15 stacked one on top of the other in the length direction of the light emitting device LD.

[0086] The insulating film 14 may be provided in the form of multiple layers, including at least five layers. In an embodiment, the insulating film 14 may include a first layer FRL, a second layer SNL, a third layer TIL, a fourth layer FUL, and a fifth layer FFL. The first layer FRL may be disposed directly on the outer periphery of the light-emitting stack pattern 10 and surround the light-emitting stack pattern 10. The second layer SNL may be disposed on the first layer FRL and surround the first layer FRL. The third layer TIL may be disposed on the second layer SNL and surround the second layer SNL. The fourth layer FUL may be disposed on the third layer TIL and surround the third layer TIL. The fifth layer FFL may be disposed on the fourth layer FUL and surround the fourth layer FUL. The first layer FRL, the second layer SNL, the third layer TIL, and the fourth layer FUL may be the first layer FRL, the second layer SNL, the third layer TIL, and the fourth layer FUL described with reference to Figures 1 to 6.

[0087] The fifth layer FFL may be the outer peripheral surface (or surface) of the light emitting device LD. For example, the fifth layer FFL may be located at the outermost side of the light emitting device LD.

[0088] The fifth layer FFL may include a first surface FFLa and a second surface FFLb facing each other in the longitudinal direction of the light emitting element LD. In a direction perpendicular to the longitudinal direction of the light emitting element LD, the first surface FFLa may be positioned on the same line as the second end EP2 of the light emitting element LD, and the second surface FFLb may be positioned on the same line as the first end EP1 of the light emitting element LD, but is not limited thereto.

[0089] The first layer FRL and the third layer TIL may include the same material. For example, the first layer FRL and the third layer TIL may include zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y), hafnium oxynitride (HfO x N y ) may include at least one of:

[0090] The second layer SNL can be made of a material different from the first and third layers FRL and TIL described above.

[0091] The fourth layer FUL may include an inorganic insulating material. For example, the fourth layer FUL may include silicon oxide (SiO x ).

[0092] The fifth layer FFL may include an inorganic insulating material. The fifth layer FFL may be made of a material different from that of the first and third layers FRL and TIL. The fifth layer FFL may be made of the same material as the fourth layer FUL or a material different from that of the fourth layer FUL. For example, the fifth layer FFL may be made of aluminum oxide (Al x O y ).

[0093] The fifth layer FFL, together with the first to fourth layers FRL, SNL, TIL, and FUL, can expose a portion of the electrode layer 15 located at the first end EP1 of the light-emitting element LD and a portion of the first semiconductor layer 11 located at the second end EP2 of the light-emitting element LD.

[0094] The fifth layer FFL may have a thickness d5 that is relatively thicker than the first, second, third, and fourth layers FRL, SNL, TIL, and FUL. By way of example, the fifth layer FFL may have a thickness d5 of 40 nm or more, but is not limited thereto. According to an embodiment, the fifth layer FFL may have a thickness d5 that is substantially similar to or the same as that of the fourth layer FUL.

[0095] When the fifth layer FFL is disposed on the fourth layer FUL and surrounds the fourth layer FUL, surface defects of the light emitting stack pattern 10 that occur during the manufacturing process can be further reduced, and lattice defects existing between the light emitting stack pattern 10 and the first to fourth layers FRL, SNL, TIL, and FUL can be further reduced, thereby further preventing the active layer 12 (or light emitting layer) from being short-circuited with external conductive materials, and further improving the reliability of the light emitting device LD.

[0096] An example of a display device using the above-described light emitting element LD as a light source will be described below.

[0097] FIG. 10 is a schematic plan view of a display device DD according to an embodiment.

[0098] For convenience, FIG. 10 shows a simplified structure of the display device DD, for example, a display panel DP provided in the display device DD, with a display area DA where an image is displayed at the center.

[0099] 10, the display device DD can be classified into a passive matrix type display device and an active matrix type display device depending on a method of driving the light emitting element (see "LD" in FIG. 1). For example, when the display device DD is realized as an active matrix type, each of the pixels PXL can include a driving transistor that controls the amount of current supplied to the light emitting element LD, a switching transistor that transmits a data signal to the driving transistor, etc.

[0100] The display panel DP (or display device DD) may include a substrate SUB and pixels PXL arranged on the substrate SUB. Each of the pixels PXL may include at least one light emitting element LD.

[0101] The substrate SUB can include a display area DA and a non-display area NDA.

[0102] The display area DA may be an area where pixels PXL for displaying an image are provided.

[0103] The non-display area NDA may be located adjacent to the display area DA. The non-display area NDA may be provided on at least one side of the display area DA. For example, the non-display area NDA may surround (or surround) the periphery (or edge) of the display area DA. The non-display area NDA may be provided with wiring units electrically connected to each pixel PXL and drivers electrically connected to the wiring units for driving the pixels.

[0104] The wiring unit may electrically connect the driver and each pixel PXL. The wiring unit may include fan-out lines. The fan-out lines may be electrically connected to scan lines and data lines electrically connected to pixel circuits (PXC in FIG. 11) of the pixels PXL. The fan-out lines may also be electrically connected to control lines and sensing lines electrically connected to the pixel circuits PXC in order to compensate for changes in the electrical characteristics of each pixel PXL in real time.

[0105] The substrate SUB may include a transparent insulating material to allow light to pass through, and may be a rigid substrate or a flexible substrate.

[0106] The rigid substrate can be, for example, at least one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate.

[0107] The flexible substrate may be at least one of a film substrate containing a polymer organic material and a plastic substrate, for example, polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.

[0108] One area on the substrate SUB may be provided as a display area DA in which the pixels PXL are arranged, and the remaining area of ​​the substrate SUB may be provided as a non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel area in which the pixels PXL are arranged, and a non-display area NDA arranged around the display area DA (or adjacent to the display area DA).

[0109] Each of the pixels PXL may be provided in a display area DA of a substrate SUB. A plurality of pixels PXL may be provided and arranged in a matrix along pixel rows (or pixel columns) extending in a first direction DR1 and pixel columns (or pixel rows) extending in a second direction DR2 intersecting the first direction DR1, but the arrangement structure of the pixels PXL is not limited thereto.

[0110] Each pixel PXL may include a pixel circuit layer (see "PCL" in FIG. 13) and a display element layer (see "DPL" in FIG. 13) located on a substrate SUB.

[0111] The pixel circuit layer PCL may include a pixel circuit PXC disposed on the substrate SUB, the pixel circuit PXC including a plurality of transistors and signal lines connected to the transistors. For example, each transistor may have a structure in which a semiconductor layer, a gate electrode, a first terminal, and a second terminal are stacked with an insulating layer sandwiched therebetween. The semiconductor layer may include amorphous silicon, polysilicon, low-temperature polysilicon, an organic semiconductor, and / or an oxide semiconductor. The semiconductor layer may include a channel region, a source region, and a drain region. The gate electrode, the first terminal, and the second terminal may include, but are not limited to, one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo). The pixel circuit layer PCL may also include at least one insulating layer.

[0112] A display element layer DPL may be disposed on the pixel circuit layer PCL. A light emitting unit (see "EMU" in FIG. 11) including a light emitting element LD for emitting light may be disposed in the display element layer DPL. Electrodes electrically connected to the light emitting element LD may be disposed in the light emitting unit EMU. The configuration of each pixel PXL will be described in detail below.

[0113] Each pixel PXL may include at least one light emitting element LD driven by corresponding scan signals and data signals. The light emitting element LD may have a small size on the order of nanoscale (or nanometer) to microscale (or micrometer) and may be connected in parallel with adjacent light emitting elements, but is not limited thereto. The light emitting element LD may constitute a light source for each pixel PXL.

[0114] FIG. 11 is a schematic circuit diagram showing the electrical connections of the components included in each pixel PXL shown in FIG.

[0115] 11 shows an example of an electrical connection relationship between components included in a pixel PXL that can be applied to an active matrix display device, but the connection relationship between the components of each pixel PXL is not limited to this example.

[0116] 10 and 11, the pixel PXL may include a light emitting unit EMU that generates light of a brightness corresponding to a data signal, and a pixel circuit PXC for driving the light emitting unit EMU.

[0117] The light emitting unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power supply wiring PL1 connected to a first driving power supply VDD and receiving the voltage of the first driving power supply VDD, and a second power supply wiring PL2 connected to a second driving power supply VSS and receiving the voltage of the second driving power supply VSS. For example, the light emitting unit EMU may include a pixel circuit PXC and a first electrode PE1 (or a first pixel electrode) connected to the first driving power supply VDD via the first power supply wiring PL1, a second electrode PE2 (or a second pixel electrode) connected to the second driving power supply VSS via the second power supply wiring PL2, and a plurality of light emitting elements LD connected in parallel in the same direction between the first and second electrodes PE1 and PE2. In this embodiment, the first electrode PE1 may be an anode, and the second electrode PE2 may be a cathode.

[0118] Each of the light emitting elements LD included in the light emitting unit EMU may include one end (or first end EP1) electrically connected to a first driving power supply VDD via a first electrode PE1 and the other end (or second end EP2) electrically connected to a second driving power supply VSS via a second electrode PE2. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set to a high potential power supply, and the second driving power supply VSS may be set to a low potential power supply. The potential difference between the first and second driving power supplies VDD and VSS may be set to a threshold voltage or higher of the light emitting element LD during the light emitting period of the pixel PXL.

[0119] As described above, each light emitting element LD connected in parallel in the same direction (for example, the forward direction) between the first electrode PE1 and the second electrode PE2 to which different power supply voltages are supplied can constitute a respective effective light source.

[0120] The light emitting element LD of the light emitting unit EMU can emit light at a brightness corresponding to the driving current supplied through the corresponding pixel circuit PXC. For example, during each frame period, a driving current corresponding to the gray scale value of the corresponding frame data of the pixel circuit PXC can be supplied to the light emitting unit EMU. The driving current supplied to the light emitting unit EMU can be divided and flowed to each of the light emitting elements LD. As a result, each light emitting element LD can emit light at a brightness corresponding to the current flowing therethrough, and the light emitting unit EMU can emit light at a brightness corresponding to the driving current.

[0121] Although the embodiment in which both ends of the light emitting element LD are connected in the same direction between the first and second driving power sources VDD and VSS has been described, this is not limiting. According to this embodiment, the light emitting unit EMU may further include at least one backward light emitting element LDr in addition to the light emitting element LD constituting each effective light source. The backward light emitting element LDr is connected in parallel between the first and second electrodes PE1 and PE2 together with the light emitting element LD constituting the effective light source, but may be connected between the first and second electrodes PE1 and PE2 in the opposite direction to the light emitting element LD. The backward light emitting element LDr maintains an inactive state even when a predetermined or selected driving voltage (e.g., a forward driving voltage) is applied between the first and second electrodes PE1 and PE2, so that substantially no current flows through the backward light emitting element LDr.

[0122] The pixel circuit PXC may be electrically connected to the scan line Si and data line Dj of the pixel PXL. The pixel circuit PXC may also be electrically connected to the control line CLi and sensing line SENj of the pixel PXL. For example, if the pixel PXL is arranged in the i-th row and j-th column of the display area DA, the pixel circuit PXC of the pixel PXL may be electrically connected to the i-th scan line Si, the j-th data line Dj, the i-th control line CLi, and the j-th sensing line SENj of the display area DA.

[0123] The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst.

[0124] The first transistor T1 is a driving transistor for controlling a driving current applied to the light emitting unit EMU and may be electrically connected between a first driving power supply VDD and the light emitting unit EMU. Specifically, a first terminal of the first transistor T1 may be electrically connected to the first driving power supply VDD via a first power supply wiring PL1, a second terminal of the first transistor T1 may be electrically connected to a second node N2, and a gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control the amount of driving current applied to the light emitting unit EMU from the first driving power supply VDD via the second node N2 in response to a voltage applied to the first node N1. In the embodiment, the first terminal of the first transistor T1 may be a drain electrode and the second terminal of the first transistor T1 may be a source electrode, but is not limited thereto. According to the embodiment, the first terminal may be a source electrode and the second terminal may be a drain electrode.

[0125] The second transistor T2 is a switching transistor that selects and activates the pixel PXL in response to a scan signal and may be connected between the data line Dj and the first node N1. A first terminal of the second transistor T2 may be electrically connected to the data line Dj, a second terminal of the second transistor T2 may be electrically connected to the first node N1, and a gate electrode of the second transistor T2 may be electrically connected to the scan line Si. The first and second terminals of the second transistor T2 may be different terminals, for example, if the first terminal is a drain electrode, the second terminal may be a source electrode.

[0126] The second transistor T2 may be turned on when a scan signal having a gate-on voltage (e.g., a high-level voltage) is supplied from the scan line Si, thereby electrically connecting the data line Dj to the first node N1. The first node N1 may be a point where the second terminal of the second transistor T2 is connected to the gate electrode of the first transistor T1. The second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0127] The third transistor T3 electrically connects the first transistor T1 to the sensing line SENj, thereby acquiring a sensing signal via the sensing line SENj and detecting characteristics of the pixel PXL, such as the threshold voltage of the first transistor T1, using the sensing signal. Information about the characteristics of the pixel PXL can be used to convert image data so that characteristic deviations between the pixels PXL can be compensated for. A second terminal of the third transistor T3 can be electrically connected to a second terminal of the first transistor T1, a first terminal of the third transistor T3 can be electrically connected to the sensing line SENj, and a gate electrode of the third transistor T3 can be electrically connected to the control line CLi. In addition, a first terminal of the third transistor T3 can be electrically connected to an initialization power source. The third transistor T3 is an initialization transistor that can initialize the second node N2. When a sensing control signal is received from the control line CLi, the third transistor T3 is turned on to transfer the voltage of the initialization power source to the second node N2. This allows the storage capacitor Cst electrically connected to the second node N2 to be initialized.

[0128] The storage capacitor Cst may include a first storage electrode (or lower electrode) and a second storage electrode (or upper electrode). The first storage electrode of the storage capacitor Cst may be electrically connected to a first node N1, and the second storage electrode of the storage capacitor Cst may be electrically connected to a second node N2. The storage capacitor Cst charges a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Thus, the storage capacitor Cst may store a voltage corresponding to the difference between the voltage of the gate electrode of the first transistor T1 and the voltage of the second node N2.

[0129] 11 shows an embodiment in which all the light emitting elements LD constituting the light emitting unit EMU are connected in parallel, but this is not limiting. According to an embodiment, the light emitting unit EMU may be configured to include at least one series stage including a plurality of light emitting elements LD connected in parallel to each other. For example, the light emitting unit EMU may be configured in a series / parallel mixed structure.

[0130] 11 shows an embodiment in which the first, second, and third transistors T1, T2, and T3 included in the pixel circuit PXC are all N-type transistors, but this is not limiting. For example, at least one of the first, second, and third transistors T1, T2, and T3 described above may be changed to a P-type transistor. Also, while FIG. 11 shows an embodiment in which the light-emitting unit EMU is connected between the pixel circuit PXC and the second driving power supply VSS, the light-emitting unit EMU may be connected between the first driving power supply VDD and the pixel circuit PXC.

[0131] The structure of the pixel circuit PXC can be implemented in various ways. For example, the pixel circuit PXC can further include at least one transistor element, such as a transistor element for initializing the first node N1 and / or a transistor element for controlling the light emitting time of the light emitting element LD, and other circuit elements, such as a boost capacitor for boosting the voltage of the first node N1.

[0132] In the following examples, for convenience of explanation, the horizontal direction (or X-axis direction) on the plane will be referred to as the first direction DR1, the vertical direction (or Y-axis direction) on the plane will be referred to as the second direction DR2, and the thickness direction (or vertical direction) of the substrate SUB on the cross section will be referred to as the third direction DR3.

[0133] FIG. 12 is a schematic plan view showing a pixel PXL according to an embodiment.

[0134] 10 to 12, the pixel PXL may be located in a pixel area PXA provided (or provided) in a display area DA of a substrate SUB, which may include a pixel area PXA, a light-emitting area EMA, and a non-light-emitting area NEA.

[0135] The pixel PXL may include a first bank BNK1 located in the non-light-emitting area NEA and a light-emitting element LD located in the light-emitting area EMA.

[0136] The first bank BNK1 is a structure that defines (or partitions) the pixel area PXA (or light-emitting area EMA) of each pixel PXL and its adjacent pixels PXL, and may be, for example, a pixel definition layer.

[0137] In the embodiment, the first bank BNK1 may be a structure that defines each light-emitting area EMA to which the light-emitting element LD should be supplied during the process of supplying (or inputting) the light-emitting element LD to the pixel PXL. For example, the first bank BNK1 partitions the light-emitting area EMA of the pixel PXL, so that a mixture liquid (for example, ink) containing a desired amount and / or type of light-emitting element LD can be supplied to the light-emitting area EMA.

[0138] The first bank BNK1 is configured to include at least one light-blocking material and / or reflective material (or scattering material) to prevent light leakage between the pixel PXL and its adjacent pixel PXL. According to an embodiment, the first bank BNK1 may include a transparent material (or material). Examples of the transparent material include, but are not limited to, polyamide resin, polyimide resin, etc. According to another embodiment, a reflective material layer may be separately provided and / or formed on the first bank BNK1 to further improve the efficiency of light emitted from the pixel PXL.

[0139] The first bank BNK1 may include at least one opening OP exposing the underlying structure in the pixel region PXA. In an embodiment, the light-emitting region EMA of the pixel PXL and the opening OP of the first bank BNK1 may correspond to each other.

[0140] An electrode separation region ESA may be located within the non-emitting region NEA of each pixel PXL. The electrode separation region ESA may be a region in each pixel PXL where the first alignment electrode ALE1 is separated from the first alignment electrode ALE1 provided in the adjacent pixel PXL in the second direction DR2.

[0141] The pixel PXL may include at least an electrode PE provided in the light-emitting region EMA, a light-emitting element LD electrically connected to the electrode PE, an alignment electrode ALE provided at a position corresponding to the electrode PE, and a bank pattern BNP. For example, the pixel PXL may include at least first and second electrodes PE1 and PE2, a light-emitting element LD, first and second alignment electrodes ALE1 and ALE2, and first and second bank patterns BNP1 and BNP2 provided in the light-emitting region EMA. The number, shape, size, and arrangement structure of the electrode PE and / or the alignment electrode ALE may vary depending on the structure of the pixel PXL (or the light-emitting unit EMU).

[0142] In the embodiment, the bank pattern BNP, the alignment electrode ALE, the light emitting element LD, and the electrode PE may be provided in this order based on one surface of the substrate SUB on which the pixel PXL is provided, but this is not limiting. According to the embodiment, the order of the positions and shapes of the electrode patterns constituting the pixel PXL (or the light emitting unit EMU) may be changed in various ways. The stacked structure (or cross-sectional structure) of the pixel PXL will be described later with reference to FIGS. 13 to 15.

[0143] The bank patterns BNP may be provided in at least the light emitting area EMA, spaced apart from each other in a first direction DR1 in the light emitting area EMA, and may extend along a second direction DR2. The bank patterns BNP may include a first bank pattern BNP1 and a second bank pattern BNP2 spaced apart from each other in the first direction DR1.

[0144] Each bank pattern BNP (also referred to as a "wall pattern," "protrusion pattern," "support pattern," or "wall structure") may have a uniform width in the light-emitting area EMA. Each of the first and second bank patterns BNP1 and BNP2 may have a bar shape having a predetermined width along the direction extending in the light-emitting area EMA when viewed in a plan view, but is not limited to this.

[0145] The bank pattern BNP can support each of the first and second alignment electrodes ALE1, ALE2 in order to change the surface profile (or shape) of each of the first and second alignment electrodes ALE1, ALE2 so as to guide the light emitted from the light emitting element LD in the image display direction (or front direction) of the display device DD.

[0146] The bank patterns BNP may have the same or different widths. For example, the first and second bank patterns BNP1 and BNP2 may have the same or different widths in the first direction DR1 at least in the light emitting area EMA.

[0147] Each of the first and second bank patterns BNP1 and BNP2 may at least partially overlap with the corresponding alignment electrode ALE in the light-emitting area EMA. For example, the first bank pattern BNP1 may be positioned below the first alignment electrode ALE1 to overlap with a region of the first alignment electrode ALE1, and the second bank pattern BNP2 may be positioned below the second alignment electrode ALE2 to overlap with a region of the second alignment electrode ALE2. The bank pattern BNP, together with the alignment electrode ALE, may be a structure that accurately defines the alignment position of the light-emitting element LD in the light-emitting area EMA of the pixel PXL.

[0148] The bank patterns BNP are provided under the respective portions of the align electrodes ALE in the light emitting region EMA, so that the respective portions of the align electrodes ALE protrude toward the upper side of the pixels PXL in the regions where the bank patterns BNP are formed. As a result, the bank patterns BNP, which are wall structures, can be formed around the light emitting elements LD. For example, the wall structures can be formed in the light emitting region EMA to face the first and second ends EP1 and EP2 of the light emitting elements LD.

[0149] In an embodiment, if the bank pattern BNP and / or the alignment electrode ALE includes a reflective material, a reflective wall structure may be formed around the light emitting element LD, so that light emitted from the light emitting element LD is directed toward the upper direction (or image display direction) of the pixel PXL, thereby further improving the light output efficiency of the pixel PXL.

[0150] The alignment electrodes ALE may be located at least in the light emitting area EMA, spaced apart from each other in a first direction DR1, and extend in a second direction DR2 in the light emitting area EMA. The alignment electrodes ALE may include a first alignment electrode ALE1 and a second alignment electrode ALE2 spaced apart from each other in the first direction DR1 and extending in the second direction DR2.

[0151] At least one of the first and second alignment electrodes ALE1, ALE2 may be separated from other electrodes (for example, alignment electrodes ALE provided in adjacent pixels PXL adjacent to each pixel PXL in the second direction DR2) after the light-emitting elements LD are provided and aligned in the light-emitting region EMA during the manufacturing process of the display device DD. For example, the first alignment electrode ALE1 may be separated from the first alignment electrode ALE1 provided in the adjacent pixel PXL adjacent to the corresponding pixel PXL during the manufacturing process of the display device DD after the light-emitting elements LD are provided and aligned in the light-emitting region EMA.

[0152] The first align electrode ALE1 may be electrically connected to the storage capacitor Cst of the pixel circuit PXC described with reference to Figure 11 through the first contact portion CNT1. The first contact portion CNT1 may be formed by opening a region of an insulating layer located between the first align electrode ALE1 and the storage capacitor Cst. The second align electrode ALE2 may be electrically connected to a second power line (see "PL2" in Figure 11) electrically connected to the pixel circuit PXC through the second contact portion CNT2. The second contact portion CNT2 may be formed by opening a region of an insulating layer located between the second align electrode ALE2 and the second power line PL2.

[0153] The first contact portion CNT1 and the second contact portion CNT2 may be located in the non-light-emitting area NEA so as to overlap with the first bank BNK1, but are not limited to this. According to an embodiment, both the first contact portion CNT1 and the second contact portion CNT2 may be located in the light-emitting area EMA, or one of the first contact portion CNT1 and the second contact portion CNT2 may be located in the non-light-emitting area NEA and the other may be located in the light-emitting area EMA.

[0154] Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may receive a predetermined or selected alignment signal during the alignment step of the light emitting element LD. For example, the first alignment electrode ALE1 may receive a first alignment signal during the alignment step of the light emitting element LD, and the second alignment electrode ALE2 may receive a second alignment signal during the alignment step of the light emitting element LD. The first and second alignment signals may be signals having a voltage difference and / or phase difference sufficient to align the light emitting element LD between the alignment electrodes ALE. At least one of the first and second alignment signals may be, but is not limited to, an AC signal.

[0155] At least two light emitting elements LD may be aligned and / or provided in the light emitting area EMA (or pixel area PXA).

[0156] The light emitting elements LD may be disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2. When viewed in a plan view, each of the light emitting elements LD may include a first end EP1 and a second end EP2 located at opposite ends (or facing each other) in a length direction thereof, for example, a first direction DR1. In an embodiment, an electrode layer (see "15" in FIG. 3) making ohmic contact with a second semiconductor layer (see "13" in FIG. 3) including a p-type semiconductor layer may be located at the first end EP1 (or p-type end), and a first semiconductor layer (see "11" in FIG. 3) including an n-type semiconductor layer may be located at the second end EP2 (or n-type end).

[0157] The light emitting elements LD may be spaced apart from one another and aligned substantially parallel to one another. The spacing between the light emitting elements LD is not particularly limited. According to an embodiment, a plurality of light emitting elements LD may be arranged adjacent to one another to form a group, and another plurality of light emitting elements LD may be arranged at regular intervals to form a group, and may be aligned in one direction with non-uniform density.

[0158] The light emitting element LD may be provided to the pixel area PXA (or the light emitting area EMA) by inkjet printing, slit coating, or other methods. For example, the light emitting element LD may be mixed with a volatile solvent and provided to the pixel area PXA by inkjet printing or slit coating. When alignment signals corresponding to the first alignment electrode ALE1 and the second alignment electrode ALE2 are applied, an electric field may be formed between the first alignment electrode ALE1 and the second alignment electrode ALE2. As a result, the light emitting element LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. After the light emitting element LD is aligned, the solvent may be volatilized or removed by other methods, thereby stably aligning the light emitting element LD between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0159] The electrodes PE (or pixel electrodes) may be provided at least in the light-emitting area EMA at positions corresponding to at least one alignment electrode ALE and one light-emitting element LD, respectively. For example, each electrode PE may be formed on each alignment electrode ALE and the corresponding light-emitting element LD so as to overlap with the respective alignment electrode ALE and the corresponding light-emitting element LD, and may be electrically connected to at least the light-emitting element LD.

[0160] The electrodes PE may include a first electrode PE1 and a second electrode PE2 that are spaced apart from each other.

[0161] The first electrode PE1 ("first pixel electrode" or "anode") may be formed on the first alignment electrode ALE1 and the first end EP1 of each light emitting element LD and may be electrically connected to the first end EP1 of each light emitting element LD. The first electrode PE1 may be in direct contact with the first alignment electrode ALE1 through a first contact hole CH1 at least in the non-emitting area NEA and may be electrically and / or physically connected to the first alignment electrode ALE1. The first contact hole CH1 may be formed by removing a portion of at least one insulating layer located between the first electrode PE1 and the first alignment electrode ALE1. A portion of the first alignment electrode ALE1 may be exposed through the first contact hole CH1.

[0162] The pixel circuit PXC, the first alignment electrode ALE1, and the first electrode PE1 may be electrically connected to each other through the first contact part CNT1 and the first contact hole CH1.

[0163] In the above-described embodiment, the first alignment electrode ALE1 and the first electrode PE1 are in direct contact with each other and connected to each other through the first contact hole CH1, but the present invention is not limited to this. According to an embodiment, in order to prevent defects due to material characteristics of the first alignment electrode ALE1, the first electrode PE1 may be in direct contact with the pixel circuit PXC and electrically connected to the pixel circuit PXC without being in direct contact with the first alignment electrode ALE1.

[0164] The first electrode PE1 may have a bar shape extending along the second direction DR2, but is not limited thereto. The shape of the first electrode PE1 may be variously changed as long as it is electrically and / or physically stably connected to the first end EP1 of the light emitting element LD. In addition, the shape of the first electrode PE1 may be variously changed in consideration of the arrangement and connection relationship with the first alignment electrode ALE1 arranged thereunder.

[0165] The second electrode PE2 ("second pixel electrode" or "cathode") may be formed on the second alignment electrode ALE2 and the second end EP2 of each of the light emitting elements LD and may be electrically connected to the second end EP2 of each of the light emitting elements LD. In addition, the second electrode PE2 may be in direct contact with the second alignment electrode ALE2 through a second contact hole CH2 and may be electrically and / or physically connected to the second alignment electrode ALE2. The second contact hole CH2 may be formed by removing a portion of at least one insulating layer located between the second electrode PE2 and the second alignment electrode ALE2. A portion of the second alignment electrode ALE2 may be exposed through the second contact hole CH2.

[0166] The second power wiring PL2, the second alignment electrode ALE2, and the second electrode PE2 may be electrically connected to each other through the second contact part CNT2 and the second contact hole CH2.

[0167] In the above-described embodiment, the second alignment electrode ALE2 and the second electrode PE2 are in direct contact with each other and connected to each other through the second contact hole CH2, but the present invention is not limited to this. According to an embodiment, in order to prevent defects due to material characteristics of the second alignment electrode ALE2, the second electrode PE2 may be in direct contact with the second power wiring PL2 and electrically connected to the second power wiring PL2 without being in direct contact with the second alignment electrode ALE2.

[0168] The second electrode PE2 may have a bar shape extending along the second direction DR2, but is not limited thereto. The shape of the second electrode PE2 may be modified in various ways as long as it is electrically and / or physically stably connected to the second end EP2 of the light emitting element LD. In addition, the shape of the second electrode PE2 may be modified in various ways in consideration of the arrangement and connection relationship with the second alignment electrode ALE2 disposed thereunder.

[0169] The stacked structure (or cross-sectional structure) of the pixel PXL according to the above-described embodiment will be described below with reference to FIGS.

[0170] 13 and 14 are schematic cross-sectional views taken along line II' in FIG. 12, and FIG. 15 is a schematic enlarged view showing the EA portion in FIG.

[0171] Fig. 14 shows a modification of the embodiment of Fig. 13 in terms of the formation stages of the first electrode PE1 and the second electrode PE2 and the presence or absence of the third insulating layer INS3. For example, Fig. 14 shows an embodiment in which the first electrode PE1 and the second electrode PE2 are formed in the same process and the third insulating layer INS3 is omitted.

[0172] In the examples of Figures 13 to 15, the layered structure (or cross-sectional structure) of the pixel PXL is shown in a simplified manner, such as each electrode being shown as a single-layer electrode and each insulating layer being shown as a single-layer insulating layer, but this is not limited to this.

[0173] Regarding the embodiment of FIGS. 13 to 15, in order to avoid redundant explanation, differences from the above-described embodiment will be mainly described.

[0174] Referring to FIGS. 10 to 15, the pixel PXL may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

[0175] The pixel circuit layer PCL and the display element layer DPL may be disposed to overlap each other on one surface of the substrate SUB. For example, the display area DA of the substrate SUB may include the pixel circuit layer PCL disposed on one surface of the substrate SUB and the display element layer DPL disposed on the pixel circuit layer PCL. However, the relative positions of the pixel circuit layer PCL and the display element layer DPL on the substrate SUB may vary depending on the embodiment. When the pixel circuit layer PCL and the display element layer DPL are separated into separate layers and overlapped, sufficient layout space for forming the pixel circuits PXC and the light emitting units EMU can be secured on a plane.

[0176] The substrate SUB may include a transparent insulating material to allow light to pass through, and may be a rigid substrate or a flexible substrate.

[0177] In each pixel region PXA of the pixel circuit layer PCL, circuit elements constituting the pixel circuit PXC of the corresponding pixel PXL and predetermined or selected signal wirings electrically connected to the circuit elements may be arranged, and in each pixel region PXA of the display element layer DPL, alignment electrodes AEL, light emitting elements LD, and / or electrodes PE constituting the light emitting units EMU of the corresponding pixel PXL may be arranged.

[0178] The pixel circuit layer PCL may include at least one insulating layer in addition to the circuit elements and signal wiring, such as a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PSV, and a via layer VIA, which are stacked on the substrate SUB along the third direction DR3.

[0179] The buffer layer BFL may be disposed over the entire surface of the substrate SUB. The buffer layer BFL may prevent impurities from diffusing into the transistor T included in the pixel circuit PXC. The buffer layer BFL may be an inorganic insulating film containing an inorganic material. For example, the buffer layer BFL may be formed of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) may include, but is not limited to, at least one of the following. The buffer layer BFL may be provided as a single layer, or may be provided as multiple layers of at least two layers. When the buffer layer BFL is provided as multiple layers, each layer may be formed of the same material or different materials. The buffer layer BFL may be omitted depending on the material of the substrate SUB, process conditions, etc.

[0180] The gate insulating layer GI may be disposed over the entire surface of the buffer layer BFL. The gate insulating layer GI may include the same material as the buffer layer BFL described above, or may include a suitable (or selected) material from the materials exemplified as constituent materials of the buffer layer BFL. For example, the gate insulating layer GI may be an inorganic insulating film containing an inorganic material.

[0181] The interlayer insulating layer ILD may be provided and / or formed on the entire surface of the gate insulating layer GI. The interlayer insulating layer ILD may include the same material as the buffer layer BFL or may include one or more suitable (or selected) materials from the materials exemplified as constituent materials of the buffer layer BFL.

[0182] The passivation layer PSV may be provided and / or formed on the entire interlayer insulating layer ILD. The passivation layer PSV may include the same material as the buffer layer BFL or may include one or more suitable (or selected) materials from the materials exemplified as constituent materials of the buffer layer BFL.

[0183] The via layer VIA can be provided and / or formed entirely on the passivation layer PSV. The via layer VIA can be an inorganic insulating film containing an inorganic material or an organic insulating film containing an organic material. The inorganic insulating film can be, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO xThe organic insulating film can include at least one of, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0184] The via layer VIA can be utilized as a planarization layer that reduces a step that occurs in the pixel circuit layer PCL due to the configuration of the pixel circuit PXC located below it.

[0185] The pixel circuit layer PCL may include at least one conductive layer disposed between the insulating layers. For example, the pixel circuit layer PCL may include a first conductive layer disposed between the substrate SUB and the buffer layer BFL, a second conductive layer disposed on the gate insulating layer GI, a third conductive layer disposed on the interlayer insulating layer ILD, and a fourth conductive layer disposed on the passivation layer PSV. However, the insulating layers and conductive layers are not limited to those in the above-described embodiment. Depending on the embodiment, in addition to the insulating layer and the conductive layer, another insulating layer and another conductive layer may be provided in the pixel circuit layer PCL.

[0186] The first conductive layer may be formed of a single layer of a material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, or a mixture thereof. The first conductive layer may also be formed of a double-layer or multi-layer structure of low-resistance materials such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) to reduce wiring resistance. Each of the second to fourth conductive layers may contain the same material as the first conductive layer, or may contain one or more suitable materials selected from the materials exemplified as the constituent materials of the first conductive layer, but is not limited thereto.

[0187] The pixel circuit PXC arranged in the pixel circuit layer PCL may include at least one transistor T. The transistor T may include one of the first, second, and third transistors T1, T2, and T3 described with reference to Fig. 11. As an example, the transistor T1 may be the first transistor T1 described with reference to Fig. 11.

[0188] The transistor T may include a semiconductor pattern and a gate electrode GE overlapping at least a portion of the semiconductor pattern. The semiconductor pattern may include a channel region ACT, a first contact region SE (or a second terminal), and a second contact region DE (or a first terminal). The first contact region SE may be a source region, and the second contact region DE may be a drain region.

[0189] The gate electrode GE may be provided and / or formed on the gate insulating layer GI to correspond to the channel region ACT of the semiconductor pattern. As an example, the gate electrode GE may be a second conductive layer located between the gate insulating layer GI and the interlayer insulating layer ILD. The gate electrode GE may be provided on the gate insulating layer GI and overlap the channel region ACT of the semiconductor pattern.

[0190] A semiconductor pattern may be provided and / or formed on the buffer layer BFL. The channel region ACT, the first contact region SE, and the second contact region DE may be semiconductor patterns made of polysilicon, amorphous silicon, an oxide semiconductor, or the like. The channel region ACT, the first contact region SE, and the second contact region DE may be formed of a semiconductor layer that is not doped with impurities or that is doped with impurities. For example, the first contact region SE and the second contact region DE may be formed of a semiconductor layer that is doped with impurities, and the channel region ACT may be formed of a semiconductor layer that is not doped with impurities. For example, the impurities may be, but are not limited to, n-type impurities.

[0191] The channel region ACT can overlap with the gate electrode GE of the transistor T.

[0192] A first contact region SE (or a second terminal) of the transistor T may be connected to one end of the channel region ACT and may be electrically connected to the bridge pattern BRP via a first connecting member TE1, and a second contact region DE (or a first terminal) of the transistor T may be connected to the other end of the channel region ACT and may be electrically connected to a second connecting member TE2.

[0193] The first connecting member TE1 may be provided and / or formed on the interlayer insulating layer ILD. For example, the first connecting member TE1 may be formed of a third conductive layer. One end of the first connecting member TE1 may be electrically and / or physically connected to the first contact region SE of the transistor T through a contact hole that sequentially penetrates the interlayer insulating layer ILD and the gate insulating layer GI. In addition, the other end of the first connecting member TE1 may be electrically and / or physically connected to the bridge pattern BRP through a contact hole that penetrates the passivation layer PSV located on the interlayer insulating layer ILD.

[0194] The bridge pattern BRP may be provided and / or formed on the passivation layer PSV. For example, the bridge pattern BRP may be formed of a fourth conductive layer. One end of the bridge pattern BRP may be connected to a first contact region SE of the transistor T via a first connecting member TE1. The other end of the bridge pattern BRP may be electrically and / or physically connected to the lower metal layer BML via a contact hole that sequentially penetrates the passivation layer PSV, the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BFL. The lower metal layer BML and the first contact region SE of the transistor T may be electrically connected to each other via the bridge pattern BRP and the first connecting member TE1.

[0195] According to the embodiment, the bridge pattern BRP may be electrically connected to a portion of the display element layer DPL, for example, the first alignment electrode ALE1, through a contact hole penetrating the via layer VIA.

[0196] The lower metal layer BML may be a first conductive layer provided on the substrate SUB. The lower metal layer BML is electrically connected to the transistor T and may widen the driving range of a predetermined or selected voltage supplied to the gate electrode GE of the transistor T. For example, the lower metal layer BML may be electrically connected to the first contact region SE of the transistor T and may stabilize the channel region ACT of the transistor T. Furthermore, the lower metal layer BML may be electrically connected to the first contact region SE of the transistor T and may prevent the lower metal layer BML from floating.

[0197] The second connection member TE2 may be provided and / or formed on the interlayer insulating layer ILD. For example, the second connection member TE2 may be a third conductive layer. One end of the second connection member TE2 may be electrically and / or physically connected to the second contact region DE of the transistor T through a contact hole that penetrates the interlayer insulating layer ILD and the gate insulating layer GI.

[0198] In the above-described embodiment, the transistor T is a thin film transistor having a top gate structure, but the present invention is not limited to this, and the structure of the transistor T can be modified in various ways.

[0199] A passivation layer PSV may be provided and / or formed on the transistor T and the first and second connecting members TE1 and TE2.

[0200] The pixel circuit layer PCL may include predetermined or selected power supply wiring provided and / or formed on the passivation layer PSV. As an example, the pixel circuit layer PCL may include a second power supply wiring PL2 arranged on the passivation layer PSV. The second power supply wiring PL2 may be formed of a fourth conductive layer. A voltage of the second driving power supply VSS may be applied to the second power supply wiring PL2. Although the second power supply wiring PL2 has been described as being arranged on the passivation layer PSV, this is not limiting. According to an embodiment, the second power supply wiring PL2 may be arranged on an insulating layer different from the passivation layer PSV among insulating layers included in the pixel circuit layer PCL.

[0201] A via layer VIA may be provided and / or formed on the bridge pattern BRP and the second power supply wiring PL2. The via layer VIA may be partially opened to include a first contact portion CNT1 exposing a part of the bridge pattern BRP and a second contact portion CNT2 exposing a part of the second power supply wiring PL2.

[0202] A display element layer DPL may be disposed on the via layer VIA. The display element layer DPL may include a light-emitting element layer LDL including a light-emitting element LD that emits light.

[0203] The light emitting element layer LDL may include first and second bank patterns BNP1, ​​BNP2, first and second alignment electrodes ALE1, ALE2, a first bank BNK1, a light emitting element LD, and first and second electrodes PE1, PE2.

[0204] The first and second bank patterns BNP1 and BNP2 may be located on the via layer VIA. As an example, the first and second bank patterns BNP1 and BNP2 may protrude in the third direction DR3 from one surface of the via layer VIA. In this case, one region of the first and second alignment electrodes ALE1 and ALE2 disposed on the first and second bank patterns BNP1 and BNP2 may protrude in the third direction DR3 (or the thickness direction of the substrate SUB).

[0205] The first and second bank patterns BNP1 and BNP2 may include an inorganic insulating film containing an inorganic material or an organic insulating film containing an organic material. According to an embodiment, the first and second bank patterns BNP1 and BNP2 may include, but are not limited to, a single-layer organic insulating film and / or a single-layer inorganic insulating film. According to an embodiment, the first and second bank patterns BNP1 and BNP2 may be provided in a multi-layer form in which at least one organic insulating film and at least one inorganic insulating film are stacked. However, the material of the first and second bank patterns BNP1 and BNP2 is not limited to the above embodiment, and according to an embodiment, the first and second bank patterns BNP1 and BNP2 may include a conductive material (or material).

[0206] The first bank pattern BNP1 is located below the first alignment electrode ALE1 in the light emitting area EMA and may overlap the first alignment electrode ALE1. The second bank pattern BNP2 is located below the second alignment electrode ALE2 in the light emitting area EMA and may overlap the second alignment electrode ALE2.

[0207] The first and second bank patterns BNP1 and BNP2 may have a trapezoidal cross section that narrows from one surface (for example, the top surface) of the via layer VIA toward the top along the third direction DR3, but is not limited to this.

[0208] The first and second bank patterns BNP1 and BNP2 may be used as reflective members. For example, the first and second bank patterns BNP1 and BNP2, together with the alignment electrodes ALE disposed thereover, may be used as reflective members that guide light emitted from the respective light emitting elements LD in the image display direction of the display device DD, thereby improving the light output efficiency of the pixels PXL.

[0209] First and second alignment electrodes ALE1 and ALE2 may be located on the first and second bank patterns BNP1 and BNP2 and the via layer VIA.

[0210] The first and second alignment electrodes ALE1 and ALE2 may be disposed on the same plane and may have the same thickness in the third direction DR3. The first and second alignment electrodes ALE1 and ALE2 may be formed simultaneously in the same process or successively.

[0211] The first and second alignment electrodes ALE1 and ALE2 may be made of a material having reflectivity so that light emitted from the light emitting element LD is propagated in the image display direction (or forward direction) of the display device DD. As an example, the first and second alignment electrodes ALE1 and ALE2 may be made of a conductive material (or materials). The conductive material may include an opaque metal suitable for reflecting the light emitted from the light emitting element LD in the image display direction of the display device DD.

[0212] Each of the first and second alignment electrodes ALE1 and ALE2 may be formed as a single layer, but is not limited to this. According to an embodiment, each of the first and second alignment electrodes ALE1 and ALE2 may be provided and / or formed as a multi-layer in which at least two or more materials selected from the group consisting of metal, alloy, conductive oxide, and conductive polymer are stacked. Each of the first and second alignment electrodes ALE1 and ALE2 may be formed as a multi-layer, at least two layers, in order to reduce or minimize distortion due to signal delay when transmitting signals to both ends of the light emitting element LD, for example, the first and second ends EP1 and EP2.

[0213] When the first and second alignment electrodes ALE1 and ALE2 are made of a conductive material having reflectivity, the light emitted from the first and second ends EP1 and EP2 of the light emitting element LD can be further propagated in the image display direction of the display device DD.

[0214] A first insulating layer INS1 may be disposed on the first and second alignment electrodes ALE1 and ALE2.

[0215] The first insulating layer INS1 may be disposed on the alignment electrode ALE and the via layer VIA. The first insulating layer INS1 may be partially opened to expose underlying structures in at least the non-emitting area NEA. For example, the first insulating layer INS1 may be partially opened to include a first contact hole CH1 by removing at least a region from the non-emitting area NEA to expose a region of the first alignment electrode ALE1, and a second contact hole CH2 by removing at least another region from the non-emitting area NEA to expose a region of the second alignment electrode ALE2.

[0216] The first insulating layer INS1 may be formed of an inorganic insulating film made of an inorganic material. The first insulating layer INS1 may be provided as a single layer or multiple layers. If the first insulating layer INS1 is provided as multiple layers, the first insulating layer INS1 may be provided as a distributed Bragg reflector structure in which first inorganic films and second inorganic films having different refractive indices are alternately stacked.

[0217] The first insulating layer INS1 may be disposed over the entire light-emitting area EMA and non-light-emitting area NEA of each pixel PXL, but is not limited thereto. According to an embodiment, the first insulating layer INS1 may be located only in a specific area of ​​each pixel PXL, for example, only in the light-emitting area EMA.

[0218] A first bank BNK1 may be located on the first insulating layer INS1.

[0219] The first bank BNK1 may be disposed on the first insulating layer INS1 in the non-light-emitting area NEA. The first bank BNK1 may be a pixel defining layer formed between adjacent pixels PXL to surround the light-emitting area EMA of each pixel PXL and define (or partition) the light-emitting area EMA of the corresponding pixel PXL.

[0220] The first bank BNK1 and the first and second bank patterns BNP1 and BNP2 described above may be formed in different processes and provided in different layers, but are not limited to this. According to an embodiment, the first bank BNK1 and the first and second bank patterns BNP1 and BNP2 may be formed in different processes and provided in the same layer, or may be formed in the same process and provided in the same layer.

[0221] A light emitting element LD may be provided and aligned in the light emitting area EMA of the pixel PXL in which the first insulating layer INS1 and the first bank BNK1 are formed. For example, the light emitting element LD may be provided (or input) in the light emitting area EMA using an inkjet printing method or the like, and the light emitting element LD may be aligned between the alignment electrodes ALE by an electric field formed by a predetermined or selected signal (or alignment signal) applied to each of the alignment electrodes ALE. For example, the light emitting element LD may be aligned on the first insulating layer INS1 between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0222] In an embodiment, each of the light emitting elements LD may include a light emitting stack pattern 10 and an insulating film 14 surrounding the light emitting stack pattern 10 .

[0223] The light-emitting stacked pattern 10 may include a first semiconductor layer 11, an active layer 12 (or a light-emitting layer), a second semiconductor layer 13, and an electrode layer 15, which are sequentially stacked in a direction from the second end EP2 toward the first end EP1 of the light-emitting element LD. The first semiconductor layer 11 includes an n-type semiconductor layer, and the second semiconductor layer 13 includes a p-type semiconductor layer.

[0224] The insulating film 14 may include a first layer FRL surrounding the outer peripheral surface (or surface) of the light-emitting stacked pattern 10, a second layer SNL surrounding the first layer FRL, and a third layer TIL surrounding the second layer SNL. The first, second, and third layers FRL, SNL, and TIL may expose a part of the electrode layer 15 located at the first end EP1 of the light-emitting element LD and a part of the first semiconductor layer 11 located at the second end EP2 of the light-emitting element LD, which have different polarities from each other.

[0225] The first layer FRL and the third layer TIL may contain the same material. The second layer SNL may contain a different material from the first and third layers FRL and TIL. In an embodiment, the first and third layers FRL and TIL are made of zirconium oxide (ZrO x ), hafnium oxide (HfOx ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ), hafnium oxynitride (HfO x N y ), and the second layer SNL may include aluminum oxide (Al2O3).

[0226] The third layer TIL may be configured to have a thickness relatively greater than that of the first and second layers FRL and SNL. In particular, the third layer TIL may be configured to have a thickness greater than that of the first layer FRL. As an example, the first layer FRL may have a thickness of 5 nm or less, and the third layer TIL may have a thickness of 10 nm or less.

[0227] When a multi-layer insulating film 14 including a first layer FRL, a second layer SNL, and a third layer TIL is disposed on the outer peripheral surface (or surface) of the light emitting stack pattern 10 to surround the outer peripheral surface of the light emitting stack pattern 10, the interaction between the first layer FRL, the second layer SNL, and the third layer TIL can easily or effectively control surface defects of the light emitting stack pattern 10, improve the protective film properties of the insulating film 14, and thereby improve the light emitting efficiency of the light emitting element LD.

[0228] A second insulating layer INS2 (or insulating pattern) may be disposed on each of the light emitting elements LD. The second insulating layer INS2 is located on the light emitting elements LD and may partially cover the outer circumferential surface (or surface) of each of the light emitting elements LD, thereby exposing the first end EP1 and the second end EP2 of each of the light emitting elements LD to the outside.

[0229] The second insulating layer INS2 may include an inorganic insulating film containing an inorganic material or an organic insulating film. For example, the second insulating layer INS2 may include an inorganic insulating film suitable for protecting each active layer 12 of the light emitting device LD from external oxygen, moisture, etc. The second insulating layer INS2 may be configured as a single layer or multiple layers.

[0230] By forming the second insulating layer INS2 on the light emitting element LD that has already been aligned in the light emitting region EMA of each pixel PXL, it is possible to prevent the light emitting element LD from moving away from the aligned position.

[0231] An electrode PE may be formed on the first and second ends EP1 and EP2 of the light emitting element LD that are not covered by the second insulating layer INS2. For example, a first electrode PE1 may be formed on the first end EP1 of the light emitting element LD, and a second electrode PE2 may be formed on the second end EP2 of the light emitting element LD.

[0232] The first electrode PE1 may be disposed on top of the first alignment electrode ALE1 so as to overlap with the first alignment electrode ALE1, and the second electrode PE2 may be disposed on top of the second alignment electrode ALE2 so as to overlap with the second alignment electrode ALE2.

[0233] The first electrode PE1 can be electrically connected to the first alignment electrode ALE1 through a first contact hole CH1 in the first insulating layer INS1, and the second electrode PE2 can be electrically connected to the second alignment electrode ALE2 through a second contact hole CH2 in the first insulating layer INS1.

[0234] The first and second electrodes PE1 and PE2 may be made of various transparent conductive materials. For example, the first and second electrodes PE1 and PE2 may include at least one of various transparent conductive materials such as indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide, and may be substantially transparent or semi-transparent to achieve a predetermined transmittance. Thus, light emitted from the first and second ends EP1 and EP2 of the light emitting element LD may pass through the first and second electrodes PE1 and PE2 and be emitted to the outside of the display device DD.

[0235] In some embodiments, the first electrode PE1 and the second electrode PE2 may be formed in different layers or the same layer, and the relative positions and / or formation order of the first electrode PE1 and the second electrode PE2 may vary depending on the embodiment.

[0236] In the embodiment of FIG. 13, the first electrode PE1 disposed adjacent to one side (for example, the left side) of the second insulating layer INS2 may be formed first. Then, the third insulating layer INS3 may be formed to cover the first electrode PE1. The third insulating layer INS3 may be positioned on the first electrode PE1 to cover the first electrode PE1 (or to prevent the first electrode PE1 from being exposed to the outside) and protect the first electrode PE1. The third insulating layer INS3 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. The third insulating layer INS3 may be formed as a single layer or multiple layers. The second electrode PE2 may be formed on the third insulating layer INS3.

[0237] In the above-described embodiment, the second electrode PE2 is formed after the first electrode PE1 and the third insulating layer INS3 are formed, but this is not limiting. According to the embodiment, the second electrode PE2 disposed adjacent to the other side (for example, the right side) of the second insulating layer INS2 may be formed first, the third insulating layer INS3 may be formed on the second electrode PE2, and the first electrode PE1 may be formed on the third insulating layer INS3.

[0238] As in the embodiment of Figure 13, when the electrodes arranged on the first end EP1 and the second end EP2 of each light-emitting element LD are arranged on different layers, the electrodes can be stably separated, thereby ensuring electrical stability between the first and second ends EP1 and EP2 of the light-emitting element LD.

[0239] In the embodiment of FIG. 14, the first electrode PE1 and the second electrode PE2 may be simultaneously formed with the second insulating layer INS2 sandwiched therebetween. For example, the first electrode PE1 may be located adjacent to one side (e.g., the left side) of the second insulating layer INS2, and the second electrode PE2 may be located adjacent to the other side (e.g., the right side) of the second insulating layer INS2. The first electrode PE1 may be in direct contact with the first end EP1 of the light emitting element LD1 and electrically connected to the light emitting element LD. The second electrode PE2 may be in direct contact with the second end EP2 of the light emitting element LD and electrically connected to the light emitting element LD. In the embodiment of FIG. 14, when the first and second electrodes PE1 and PE2 disposed on the first and second ends EP1 and EP2 of the light emitting element LD are disposed in the same layer and simultaneously formed, the manufacturing process of the pixel PXL may be simplified and manufacturing efficiency may be improved.

[0240] According to an embodiment, at least one overcoat layer (for example, a layer that flattens the upper surface of the display element layer DPL) may be further disposed on the first electrode PE1 and the second electrode PE2.

[0241] According to another embodiment, an optical layer including a color conversion layer and a color filter layer for converting light emitted from the light emitting element LD into light having excellent color reproducibility and emitting the light may be selectively provided on the light emitting element layer LDL. The optical layer will be described in detail below with reference to FIGS. 16 and 17.

[0242] 16 and 17 are schematic cross-sectional views taken along line II' in FIG.

[0243] The embodiments of Figures 16 and 17 show different modifications regarding the position of the color conversion layer CCL. For example, Figure 16 discloses an embodiment in which the optical layer LCL including the color conversion layer CCL and the color filter layer CFL is positioned on the light-emitting element layer LDL through a continuous process, while Figure 17 discloses an embodiment in which the optical layer LCL including the color conversion layer CCL and the color filter layer CFL is positioned on the light-emitting element layer LDL through a bonding process using the intermediate layer CTL.

[0244] Regarding the embodiment of FIGS. 16 and 17, in order to avoid redundant explanation, differences from the above-described embodiment will be mainly described.

[0245] 12 and 16, each pixel PXL may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and an encapsulation layer ENC. The display element layer DPL may include a light-emitting element layer LDL and an optical layer LCL.

[0246] The light emitting element layer LDL may include first and second bank patterns BNP1 and BNP2, first and second alignment electrodes ALE1 and ALE2, a first bank BNK1, a light emitting element LD, and first and second electrodes PE1 and PE2.

[0247] The optical layer LCL may include a color conversion layer CCL and a color filter layer CFL, and may also include a second bank BNK2 and a first capping layer CPL1.

[0248] The second bank BNK2 may be disposed on the first bank BNK1 in the non-light-emitting area NEA of the pixel PXL. The second bank BNK2 may be a dam structure that surrounds the light-emitting area EMA of the pixel PXL and defines the position where the color conversion layer CCL should be provided, thereby defining the light-emitting area EMA.

[0249] The second bank BNK2 may include a light-shielding material. For example, the second bank BNK2 may be a black matrix, but is not limited to this. According to an embodiment, the second bank BNK2 may include at least one light-shielding material and / or a reflective material, which may further direct light emitted from the color conversion layer CCL in an image display direction, thereby improving the light output efficiency of the color conversion layer CCL.

[0250] The color conversion layer CCL may include color conversion particles QD corresponding to a specific color, such as color conversion particles QD that convert light emitted from the light emitting element LD into light of a specific color (or light with excellent color reproducibility).

[0251] When the pixel PXL is a red pixel, the color conversion layer CCL of the pixel PXL may include red quantum dot color conversion particles QD that convert the light emitted from the light emitting element LD into red light.

[0252] When the pixel PXL is a green pixel, the color conversion layer CCL of the pixel PXL may include green quantum dot color conversion particles QD that convert the light emitted from the light emitting element LD into green light.

[0253] When the pixel PXL is a blue pixel, the color conversion layer CCL of the pixel PXL may include blue quantum dot color conversion particles QD that convert light emitted from the light-emitting element LD into blue light. When the pixel PXL is a blue pixel, according to an embodiment, a light scattering layer including light scattering particles SCT may be provided instead of the color conversion layer CCL including the color conversion particles QD. For example, when the light-emitting element LD emits blue light, the pixel PXL may include a light scattering layer including the light scattering particles SCT. The above-mentioned light scattering layer may be omitted depending on the embodiment. When the pixel PXL is a blue pixel, according to another embodiment, a transparent polymer may be provided instead of the color conversion layer CCL.

[0254] A first capping layer CPL1 may be disposed on the color conversion layer CCL and the second bank BNK2.

[0255] The first capping layer CPL1 may be provided over the entire display area (see "DA" in FIG. 10) where the pixel PXL is located, so as to cover the second bank BNK2 and the color conversion layer CCL.

[0256] The first capping layer CPL1 may be an inorganic insulating film containing an inorganic material. The first capping layer CPL1 may be made of silicon nitride (SiNx ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x The first capping layer CPL entirely covers the second bank BNK2 and the color conversion layer CCL, and can block moisture or oxygen from entering the color conversion layer CCL from the outside.

[0257] According to the embodiment, the first capping layer CPL1 may have a flat surface by reducing the step caused by the structure disposed thereunder. As an example, the first capping layer CPL1 may include, but is not limited to, an organic insulating film containing an organic material.

[0258] A color filter layer CFL may be disposed on the first capping layer CPL1.

[0259] The color filter layer CFL may include color filters CF corresponding to the light-emitting areas EMA of each pixel PXL. For example, the color filter layer CFL may include a first color filter CF1 disposed on the color conversion layer CCL of one pixel PXL (hereinafter referred to as the "first pixel"), a second color filter CF2 disposed on the color conversion layer of an adjacent pixel (hereinafter referred to as the "second pixel") adjacent to the first pixel PXL1, and a third color filter CF3 disposed on the color conversion layer of an adjacent pixel (hereinafter referred to as the "third pixel") adjacent to the second pixel.

[0260] The first, second, and third color filters CF1, CF2, and CF3 are arranged to overlap each other in the non-light-emitting area NEA and may be used as light-blocking members that block optical interference between adjacent pixels PXL. Each of the first, second, and third color filters CF1, CF2, and CF3 may include a color filter material that selectively transmits light converted by the corresponding color conversion layer CCL. For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter, but are not limited thereto.

[0261] An encapsulation layer ENC can be disposed on the color filter layer CFL.

[0262] The encapsulation layer ENC may include a second capping layer CPL2. The second capping layer CPL2 may be an inorganic insulating film containing an inorganic material or an organic insulating film containing an organic material. The second capping layer CPL2 may entirely cover the underlying structure to prevent external moisture or humidity from entering the color filter layer CFL. According to an embodiment, the encapsulation layer ENC may also be used as a planarization layer to reduce steps caused by the underlying color filter layer CFL.

[0263] The second capping layer CPL2 may be formed as a multi-layer structure. For example, the second capping layer CPL2 may include at least two inorganic insulating layers and at least one organic insulating layer interposed between the at least two inorganic insulating layers. However, the constituent materials and / or structure of the second capping layer CPL2 may be varied. Depending on the embodiment, at least one overcoat layer, filler layer, and / or other substrate may be further disposed on the second capping layer CPL2.

[0264] The pixel PXL according to the above-described embodiment can improve light output efficiency by disposing the color conversion layer CCL and the color filter layer CFL on the light emitting element LD through a continuous process, and emitting light with excellent color reproducibility through the color conversion layer CCL and the color filter layer CFL.

[0265] According to an embodiment, as shown in Fig. 17, the optical layer LCL may be formed in a continuous process on one surface of the base layer BSL to constitute a substrate, for example, an upper substrate, separate from the substrate SUB (for example, a lower substrate) on which the light emitting element layer LDL is disposed. The upper substrate may also be coupled to the light emitting element layer LDL via an intermediate layer CTL. In the process of coupling the light emitting element layer LDL to the upper substrate, an insulating layer may be provided on the first and second electrodes PE1 and PE2 to prevent a portion of the light emitting element layer LDL, for example, the first and second electrodes PE1 and PE2, from being exposed to the outside.

[0266] The intermediate layer CTL may be a transparent adhesive layer (or bonding layer) for strengthening the adhesive force between the light emitting element layer LDL and the upper substrate (or optical layer LCL), for example, an optically clear adhesive layer, but is not limited thereto. According to an embodiment, the intermediate layer CTL may be a refractive index conversion layer for converting the refractive index of light emitted from the light emitting element LD and traveling to the upper substrate to improve the luminance of the pixel PXL. According to an embodiment, the intermediate layer CTL may include a filler made of an insulating material having insulating and adhesive properties.

[0267] The upper substrate may include a base layer BSL and an optical layer LCL, which may include a color filter layer CFL, a fourth insulating layer INS4, a second bank BNK2, a color conversion layer CCL, and a fifth insulating layer INS5.

[0268] The base layer BSL may be a rigid substrate or a flexible substrate, and its material and physical properties are not particularly limited. The base layer BSL may be made of the same material as the substrate SUB, or may be made of a different material from the substrate SUB.

[0269] The color filter layer CFL may be disposed on one surface of the base layer BSL to face the light-emitting element layer LDL. A first color filter CF1 of the color filter layer CFL may be provided on one surface of the base layer BSL to correspond to the color conversion layer CCL in the light-emitting area EMA. The first, second, and third color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed to overlap each other in the non-light-emitting area NEA and may be used as light-blocking members.

[0270] A fourth insulating layer INS4 may be disposed between the color filter layer CFL and the color conversion layer CCL.

[0271] The fourth insulating layer INS4 is located on the color filter layer CFL and covers the color filter layer CFL to protect the color filter layer CFL. The fourth insulating layer INS4 may be an inorganic insulating film containing an inorganic material or an organic insulating film containing an organic material.

[0272] A second bank BNK2 and a color conversion layer CCL may be located on one surface of the fourth insulating layer INS4.

[0273] A fifth insulating layer INS5 may be disposed over the entire surface of the second bank BNK2 and the color conversion layer CCL.

[0274] The fifth insulating layer INS5 is made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or aluminum oxide (AlO x), but is not limited to this. According to an embodiment, the fifth insulating layer INS5 may be formed of an organic film containing an organic material. The fifth insulating layer INS5 is located on the color conversion layer CCL to protect the color conversion layer CCL from external moisture and humidity, thereby further improving the reliability of the color conversion layer CCL.

[0275] Although the present invention has been described above with reference to preferred embodiments, it will be understood that those skilled in the art or those having ordinary knowledge in the art can make various modifications and changes to the present invention without departing from the technical scope of the present invention as defined in the claims below.

[0276] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims

1. a light-emitting stack pattern including a first semiconductor layer, an active layer, and a second semiconductor layer; an insulating film surrounding the outer periphery of the light emitting laminated pattern, The insulating film is a first layer; a second layer surrounding the first layer; a third layer surrounding the second layer; The light-emitting device, wherein the first layer and the third layer contain the same material.

2. 10. The light-emitting device of claim 1, wherein the first layer and the third layer include at least one of ZrOx, SiOx, HfOx, BeO, TaxOy, AlxOy, LaxOy, TaxOy, NbxOy, TiOx, CeOx, MgO, YxOy, and SrxOy.

3. 2. The light-emitting device of claim 1, wherein the first layer and the third layer comprise at least one of AlN, AlGaN, InGaN, SiNx, AlOxNy, HfN, ZrN, HfOxNy, and ZrOxNy.

4. The light-emitting device according to claim 3 , wherein the first layer has a thickness of 5 nm or less, and the third layer has a thickness of 10 nm or less.

5. The light-emitting device of claim 1 , wherein the second layer comprises a different material than the first and third layers.

6. The light-emitting device according to claim 1 , wherein the first layer is disposed directly on the outer peripheral surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer.

7. The light-emitting element according to claim 1 , wherein the first semiconductor layer comprises an n-type semiconductor layer doped with an n-type dopant, and the second semiconductor layer comprises a p-type semiconductor layer doped with a p-type dopant.

8. The light emitting stack pattern further includes an electrode layer disposed on the second semiconductor layer, The light-emitting device according to claim 7 , wherein the insulating film is disposed directly on the outer peripheral surfaces of the first semiconductor layer, the active layer, the second semiconductor layer, and the electrode layer.

9. the insulating film further includes a fourth layer surrounding the third layer; The light emitting device according to claim 1 , wherein the fourth layer includes an inorganic insulating material and has a thickness greater than the first to third layers.

10. the insulating film further includes a fifth layer surrounding the fourth layer; The light emitting device according to claim 9 , wherein the fifth layer includes an inorganic insulating material and has a thickness greater than the first to fourth layers.

11. a light-emitting stacked pattern including a first semiconductor layer, an active layer, a second semiconductor layer, and an electrode layer stacked in sequence along one direction; an insulating film surrounding the outer periphery of the light emitting laminated pattern, The insulating film is a first layer disposed directly on the outer peripheral surface of the light emitting laminated pattern to surround the light emitting laminated pattern; a second layer surrounding the first layer; a third layer surrounding the second layer; a fourth layer surrounding the third layer; a fifth layer surrounding the fourth layer; The light-emitting device, wherein the first layer and the third layer include the same material, and the second layer includes a different material from the first and third layers.

12. 12. The light-emitting device of claim 11, wherein the first layer and the third layer include at least one of ZrOx, SiOx, HfOx, BeO, TaxOy, AlxOy, LaxOy, TaxOy, NbxOy, TiOx, CeOx, MgO, YxOy, SrxOy.

13. 12. The light-emitting device of claim 11, wherein the first layer and the third layer comprise at least one of AlN, AlGaN, InGaN, SiNx, AlOxNy, HfN, ZrN, HfOxNy, and ZrOxNy.

14. The light-emitting device of claim 11 , wherein the first layer has a thickness of 5 nm or less and the third layer has a thickness of 10 nm or less.

15. The light-emitting device of claim 11 , wherein the fourth layer and the fifth layer comprise an inorganic insulating material.

16. a substrate; a first electrode and a second electrode spaced apart from each other on the substrate; a light emitting device disposed on the substrate, the light emitting device including a first end electrically connected to the first electrode and a second end electrically connected to the second electrode; The light-emitting element is a light-emitting stacked pattern including a first semiconductor layer located at the second end, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, and an electrode layer disposed on the second semiconductor layer and located at the first end; an insulating film surrounding the outer periphery of the light emitting laminated pattern, The insulating film is a first layer disposed directly on the outer peripheral surface of the light-emitting stacked pattern; a second layer surrounding the first layer; a third layer surrounding the second layer; A display device, wherein the first layer and the third layer comprise the same material, and the second layer comprises a different material from the first and third layers.

17. 17. The display device of claim 16, wherein the first layer and the third layer comprise at least one of ZrOx, SiOx, HfOx, BeO, TaxOy, AlxOy, LaxOy, TaxOy, NbxOy, TiOx, CeOx, MgO, YxOy, SrxOy.

18. 17. The display device of claim 16, wherein the first layer and the third layer comprise at least one of AlN, AlGaN, InGaN, SiNx, AlOxNy, HfN, ZrN, HfOxNy, and ZrOxNy.

19. 17. The display device of claim 16, wherein the first layer has a thickness of 5 nm or less and the third layer has a thickness of 10 nm or less.

20. a light-emitting region in which light is emitted from the light-emitting element and a non-light-emitting region surrounding the light-emitting region; a first alignment electrode disposed between the substrate and the first electrode and electrically connected to the first electrode; a second alignment electrode disposed between the substrate and the second electrode and electrically connected to the second electrode; a first bank located in the non-light-emitting region and including an opening corresponding to the light-emitting region; a second bank located above the first bank; a color conversion layer surrounded by the second bank and positioned above the light-emitting element; The display device of claim 16 , further comprising a color filter disposed on the color conversion layer.

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