MEMORY DEVICE, MEMORY SYSTEM, AND METHODS FOR DATA COMPUTING USING A MEMORY DEVICE - Patent application

Abstract

A memory device, a memory system, and a method for data computation using the memory device are provided. The memory device includes an array of memory cells, and a peripheral circuit coupled to the memory cells is provided. The peripheral circuit includes a static random access memory (SRAM) configured to acquire first data transmitted from a data interface of the memory device, a page buffer configured to sense second data from the array of memory cells, and at least one processing unit coupled to the SRAM and the page buffer via a data path bus of the peripheral circuit. The at least one processing unit is configured to perform computation based on the first data and the second data. The peripheral circuit further includes control logic configured to program the second data into the array of memory cells.

Description

[Technical Field]

[0001] The present disclosure relates to memory devices, memory systems, and methods for data computation using memory devices. [Background technology]

[0002] Generative artificial intelligence (AI) inference involves AI computation. For example, transformer models typically use tensor processing units (TPUs) and memory for computation. Large transformer models require large amounts of data and computation, which consumes a lot of power and requires sufficient memory. When memory access speeds are slower than the processor's computation speed, the memory bottleneck prevents high-performance processors from operating effectively, becoming a major constraint on high-performance computing (HPC). This problem is known as the memory wall. To further improve the performance of AI systems, it is desirable to break through the memory wall. Summary of the Invention [Means for solving the problem]

[0003] In one aspect, a memory device is provided that includes an array of memory cells and peripheral circuitry coupled to the memory cells. The peripheral circuitry includes a static random access memory (SRAM) configured to acquire first data transmitted from a data interface of the memory device, a page buffer configured to sense second data from the array of memory cells, and at least one processing unit coupled to the SRAM and the page buffer via a data path bus of the peripheral circuitry. The at least one processing unit is configured to perform calculations based on the first data and the second data. The peripheral circuitry further includes control logic configured to program the second data into the array of memory cells.

[0004] In some implementations, the first data includes at least one row, and the control logic is configured to control the SRAM to send each row of the first data to the at least one processing unit based on the first data pattern.

[0005] In some implementations, the first data pattern includes N first data segments of equal data length, where N is a positive integer and N > 2. The sequence of the N first data segments in the first data pattern is the same as the sequence of the first data.

[0006] In some implementations, the data length of each first data segment is less than or equal to the bandwidth of the datapath bus.

[0007] In some implementations, the second data includes M columns, where M is a positive integer and M > 2. The control logic is configured to program each column of the second data into a memory cell based on the second data pattern.

[0008] In some implementations, the control logic is configured to program the second data into the memory cells, and to program each bit of the second data into one of the memory cells as a single-level memory cell (SLC).

[0009] In some implementations, the second data pattern includes N data groups each having M second data segments of equal data length from M columns of the second data, where the first data segments and the second data segments are configured to share the equal data length.

[0010] In some implementations, each second data segment of the M second data segments of each data group of the N data groups is assigned an error checking and correcting (ECC) code.

[0011] In some implementations, the data length of each second data segment is less than or equal to the bandwidth of the data path bus.

[0012] In some implementations, the control logic is configured to control the page buffer to sense second data from the memory cells to the page buffer based on a second data pattern.

[0013] In some implementations, each of the at least one processing unit includes M processing elements configured to perform a convolution operation based on an i-th first data segment of the N first data segments and M second data segments of the i-th data group of the N data groups, where i is a positive integer and N≧i≧1.

[0014] In some implementations, the control logic is configured to control the SRAM to send an i-th first data segment of the first data to each processing element of the M processing elements, and the control logic is further configured to control the page buffer to send M second data segments to the M processing elements.

[0015] In some implementations, each of the at least one processing unit includes a control element configured to assign the M second data segments to the M processing elements one by one based on a sequence of the M second data segments.

[0016] In some implementations, the control logic is configured to obtain the calculation result and output the calculation result to the data interface.

[0017] In some implementations, the array of memory cells is divided into more than one plane of memory cells, the number of the at least one processing unit is equal to the number of planes of memory cells, and the at least one processing unit corresponds to each of the planes of memory cells.

[0018] In some implementations, the array of memory cells is divided into more than one plane of memory cells, and the number of the at least one processing units is less than the number of planes of memory cells.

[0019] In some implementations, the number of the at least one processing units is half the number of planes of memory cells, with one processing unit corresponding to each of two planes of memory cells.

[0020] In some implementations, the number of the at least one processing unit is one-fourth the number of planes of memory cells, one processing unit corresponding to each of the four planes of memory cells.

[0021] In some implementations, the number of the at least one processing unit is one, and one processing unit corresponds to multiple planes of memory cells.

[0022] In some implementations, the memory device includes NAND flash memory.

[0023] In another aspect, a method for data computation using a memory device is provided. The memory device includes an array of memory cells and peripheral circuitry coupled to the memory cells. The method includes obtaining, by a static random access memory (SRAM), first data from a data interface of the memory device. The method further includes sensing, by a page buffer of the peripheral circuitry, second data from the array of memory cells. The method further includes performing, by at least one processing unit of the peripheral circuitry, computation based on the first data and the second data.

[0024] In some implementations, the second data is programmed into the array of memory cells.

[0025] In some implementations, the first data includes at least one row, and acquiring the first data from a data interface of the memory device includes sending each row of the first data to the at least one processing unit based on the first data pattern.

[0026] In some implementations, the first data pattern includes N first data segments of equal data length, where N is a positive integer and N > 2. The sequence of the N first data segments in the first data pattern is the same as the sequence of the first data.

[0027] In some implementations, the data length of each first data segment is less than or equal to the bandwidth of the datapath bus.

[0028] In some implementations, the second data includes M columns, and programming the second data into the array of memory cells includes programming each column of the second data into a memory cell based on the second data pattern.

[0029] In some implementations, the second data is programmed into the memory cells as single-level memory cells (SLC).

[0030] In some implementations, the second data pattern includes N data groups each having M second data segments of equal data length from M columns of the second data, where the first data segments and the second data segments are configured to share the equal data length.

[0031] In some implementations, sensing the second data from the array of memory cells includes assigning an error checking and correcting (ECC) code to each of the M second data segments of each data group of the second data.

[0032] In some implementations, the data length of each second data segment is less than or equal to the bandwidth of the data path bus.

[0033] In some implementations, sensing the second data from the array of memory cells includes sensing the second data from the memory cells to a page buffer based on a second data pattern.

[0034] In some implementations, performing a calculation based on the first data and the second data includes performing, by the M processing elements of each of the at least one processing unit, a convolution operation based on an i-th first data segment of the N first data segments and M second data segments of the i-th data group of the N data groups.

[0035] In some implementations, performing a calculation based on the first data and the second data includes transmitting, by an SRAM, the i-th first data segment to each of the M processing elements; and transmitting, by a page buffer, the M second data segments to the M processing elements one by one.

[0036] In some implementations, the method further includes obtaining a result of the calculation and outputting the result of the calculation to a data interface.

[0037] In yet another aspect, a memory device is provided that includes an array of memory cells and peripheral circuits coupled to the memory cells. The peripheral circuits include a static random access memory (SRAM) configured to acquire first data transmitted from a data interface of the memory device, a page buffer configured to sense second data from the array of memory cells, and at least one processing unit coupled to the SRAM and the page buffer and configured to perform a calculation based on the first data and the second data. The peripheral circuit further includes control logic configured to control the SRAM to subsequently acquire a first portion of the first data, a second portion of the first data, and a third portion of the first data, and to control the page buffer to subsequently sense a first portion of the second data, a second portion of the second data, and a third portion of the second data. The control logic is further configured to control the at least one processing unit to perform a first calculation based on the first portion of the first data and the first portion of the second data while sensing the second portion of the second data, and subsequently perform a second calculation based on the second portion of the first data and the second portion of the second data while sensing the third portion of the second data.

[0038] In some implementations, the control logic is further configured to output a first calculation result for the first portion of the first data and the first portion of the second data to the data interface while detecting the third portion of the second data.

[0039] In some implementations, the control logic is further configured to program the second data into the array of memory cells.

[0040] In some implementations, the first data includes at least one row, and the control logic is configured to control the SRAM to receive each row of the first data based on the first data pattern.

[0041] In some implementations, the first data pattern includes N first data segments of equal data length, where N is a positive integer and N≧2, and the sequence of the N first data segments in the first data pattern is the same as the sequence of the first data.

[0042] In some implementations, the data length of each first data segment is less than or equal to the bandwidth of the datapath bus.

[0043] In some implementations, the second data includes M columns, where M is a positive integer and M > 2. The control logic is configured to program each column of the second data into a memory cell based on the second data pattern.

[0044] In some implementations, the control logic is configured to program the second data into the memory cell as a single-level memory cell (SLC).

[0045] In some implementations, the second data pattern includes N data groups each having M second data segments of equal data length from M columns of the second data, where the first data segments and the second data segments are configured to share the equal data length.

[0046] In some implementations, each of the M second data segments of each data group of the second data is assigned an error checking and correcting (ECC) code.

[0047] In some implementations, the data length of each second data segment is less than or equal to the bandwidth of the data path bus.

[0048] In some implementations, the control logic is configured to control the page buffer to sense second data from the memory cells to the page buffer based on a second data pattern.

[0049] In some implementations, each of the at least one processing unit includes M processing elements configured to perform a convolution operation based on an i-th first data segment of the N first data segments and M second data segments of the i-th data group of the N data groups.

[0050] In some implementations, each of the control logics is configured to control the SRAM to send the i-th first data segment to each processing element of the M processing elements, and to control the page buffer to send the M second data segments to the M processing elements.

[0051] In some implementations, each of the at least one processing unit includes a control element configured to assign the M second data segments to the M processing elements one by one based on a sequence of the M second data segments.

[0052] In some implementations, the array of memory cells is divided into more than one plane of memory cells, the number of the at least one processing unit is equal to the number of planes of memory cells, and the at least one processing unit corresponds to each of the planes of memory cells.

[0053] In some implementations, the array of memory cells is divided into more than one plane of memory cells, and the number of the at least one processing units is less than the number of planes of memory cells.

[0054] In some implementations, the number of the at least one processing units is half the number of planes of memory cells, with one processing unit corresponding to each of two planes of memory cells.

[0055] In some implementations, the number of the at least one processing unit is one-fourth the number of planes of memory cells, one processing unit corresponding to each of the four planes of memory cells.

[0056] In some implementations, the number of the at least one processing unit is one, and one processing unit corresponds to multiple planes of memory cells.

[0057] In some implementations, the memory device is a NAND flash memory.

[0058] In yet another aspect, a system is provided that includes a memory device and a controller coupled to the memory device. The memory device includes an array of memory cells and peripheral circuits coupled to the memory cells. The peripheral circuits include a static random access memory (SRAM) configured to acquire first data transmitted from a data interface of the memory device, a page buffer configured to sense second data from the array of memory cells, and at least one processing unit coupled to the page buffer via a data path bus of the peripheral circuit and configured to perform a calculation based on the first data and the second data. The controller is configured to transmit the first data to the memory device and receive a result of the calculation from the memory device.

[0059] In some implementations, the controller is further configured to transmit the second data to the memory device.

[0060] In some implementations, the memory device is a NAND flash memory.

[0061] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the disclosure and, together with the detailed description, further serve to explain the disclosure and to enable one skilled in the art to make and use the disclosure. [Brief explanation of the drawings]

[0062] [Figure 1A] FIG. 1 is a block diagram of a system having a memory device in accordance with some aspects of the present disclosure. [Figure 1B]FIG. 1 is a diagram of a memory card having a memory device in accordance with some aspects of the present disclosure. [Figure 1C] FIG. 1 is a diagram of a solid-state drive (SSD) having a memory device according to some aspects of the present disclosure. [Figure 1D] FIG. 1 is a schematic diagram of a memory device including peripheral circuitry in accordance with some aspects of the present disclosure. [Figure 1E] FIG. 1 is a block diagram of a memory device including a memory cell array and peripheral circuits in accordance with some aspects of the present disclosure. [Figure 1F] FIG. 1 is a block diagram of a page buffer in accordance with some aspects of the present disclosure. [Figure 2A] FIG. 2 illustrates first and second data processed by a memory device in accordance with some aspects of the present disclosure. [Figure 2B] 2B is a diagram illustrating data shapes of the first data and the second data in FIG. 2A according to some aspects of the present disclosure. [Figure 2C] 2B illustrates a first data pattern and a second data pattern used to process the first data and the second data in FIG. 2A, respectively, in accordance with some aspects of the present disclosure. [Figure 2D] 2C is a diagram illustrating a storage map of the second data in FIG. 2A based on the second data pattern in FIG. 2C in accordance with some aspects of the present disclosure. [Figure 3A] FIG. 2 illustrates a diagram of data flow in a processing unit of a memory device in accordance with some aspects of the present disclosure. [Figure 3B] FIG. 2 illustrates a diagram of data flow in a processing unit of a memory device in accordance with some aspects of the present disclosure. [Figure 4] 2C is a diagram illustrating a process used to process the first data and second data in FIG. 2A based on the first data pattern and second data pattern in FIG. 2C according to some aspects of the disclosure. [Figure 5] FIG. 2 illustrates an operational pipeline of a memory device in accordance with some aspects of the present disclosure. [Figure 6] 1 is a flowchart of a method for data computation using a memory device according to some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0063] In general, terms may be understood, at least in part, from their usage in context. For example, as used herein, the term "one or more" may be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood as conveying a singular meaning or a plural meaning, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exhaustive set of factors, and instead may allow for the existence of additional factors not necessarily expressly described, also depending at least in part on the context.

[0064] Generative artificial intelligence (AI) inference involves AI computation. For example, the transformer model, a common model in AI systems, typically uses a tensor processing unit (TPU) and memory for computation. Large transformer models require large amounts of data and computation, which consumes a lot of power and requires sufficient memory. When the memory access speed is slower than the processor's computation speed, the memory bottleneck prevents high-performance processors from operating effectively, becoming a major constraint on high-performance computing (HPC). This problem is called the memory wall.

[0065] To address one or more of the above-mentioned problems and overcome the memory wall, the present disclosure introduces a solution in which a memory device and a method for computing using the memory device are provided. In the peripheral circuit of the memory device, multiple processing units are provided to perform computations under the control of the control logic of the peripheral circuit. In this way, some of the computational tasks of the AI ​​system, especially tasks requiring a large data width, can be distributed to the memory device of the AI ​​system. Without transferring a large amount of data from the memory device to the processor of the AI ​​system to perform the computation, the computational tasks are completed within the memory device, while the processor can process other computations. Therefore, the computation speed of the AI ​​system is effectively improved by introducing processing units into the memory device.

[0066] FIG. 1A shows a block diagram of a system 10 having a host 20 and a memory system 30 according to some embodiments of the present disclosure. The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, an artificial intelligence (AI) device, or any other suitable electronic device having storage therein. As shown in FIG. 1A, the system 10 may include a host 20 and a memory system 30 having one or more memory devices 34 and a memory controller 32. The host 20 may be a processor of an electronic device, such as a system-on-chip (SoC) such as a tensor processing unit (TPU), a central processing unit (CPU), or an application processor (AP). The host 20 may be configured to send data to and receive data from the memory system 30.

[0067] The memory device 34 can be any memory device disclosed in this disclosure, such as NAND flash memory, vertical NAND flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM®), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.

[0068] According to some implementations, the memory controller 32 is coupled to the memory device 34 and the host 20 and is configured to control the memory device 34. The memory controller 32 can manage data stored in the memory device 34 and communicate with the host 20. In some implementations, the memory controller 32 is designed to operate in low-duty-cycle environments, such as secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 32 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multi-media cards (eMMCs) used for data storage for mobile devices such as smartphones, tablets, and laptop computers, and as enterprise storage arrays. The memory controller 32 can be configured to control operations of the memory device 34, such as read, erase, and program operations. Memory controller 32 may also be configured to manage various functions related to data stored or to be stored in memory device 34, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some implementations, memory controller 32 is further configured to process error correcting codes (ECC) on data read from or written to memory device 34. Any other suitable functions, such as formatting memory device 34, may also be performed by memory controller 32. Memory controller 32 may communicate with external devices (e.g., host 20) according to a particular communication protocol.For example, memory controller 32 may communicate with external devices through at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, and the like.

[0069] The memory controller 32 and one or more memory devices 34 may be integrated into various types of storage devices included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 30 may be implemented and packaged into various types of end electronic products. In one example, as shown in FIG. 1B , the memory controller 32 and a single memory device 34 may be integrated into a memory card 40. The memory card 40 may include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 40 may further include a memory card connector 42 that couples the memory card 40 to a host (e.g., the host 20 of FIG. 1A ). In another example, as shown in FIG. 1C , the memory controller 32 and multiple memory devices 34 may be integrated into an SSD 50. The SSD 50 may further include an SSD connector 52 that couples a host (e.g., the host 20 in FIG. 1A) to the SSD 50. In some implementations, the storage capacity and / or operating speed of the SSD 50 are higher than those of the memory card 40.

[0070] FIG. 1D shows a schematic circuit diagram of a memory device 60 including peripheral circuitry according to some embodiments of the present disclosure. The memory device 60 may be an example of the memory device 34 of FIG. 1A. The memory device 60 may include a memory cell array 62 and peripheral circuitry 64 coupled to the memory cell array 62. The memory cell array 62 may be a NAND flash memory cell array in which memory cells are provided in the form of an array of NAND memory strings 66, each extending vertically above a substrate (not shown). In some implementations, each NAND memory string 66 includes multiple memory cells coupled in series and stacked vertically. Each memory cell can hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the memory cell's region. Each memory cell may be either a floating gate memory cell including a floating gate transistor or a charge trap memory cell including a charge trap transistor.

[0071] In some implementations, each memory cell is a single-level cell (SLC) with two possible memory states, thereby storing one bit of data. For example, a first memory state "0" may correspond to a first range of voltages, and a second memory state "1" may correspond to a second range of voltages. In some implementations, each memory cell is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0072] As shown in FIG. 1D , a schematic circuit diagram of an exemplary memory device 60 includes peripheral circuitry according to some aspects of the present disclosure. Memory device 60 may be an example of memory device 34 of FIG. 1A . Memory device 60 may include a memory cell array 62 and peripheral circuitry 64 coupled to memory cell array 62. Memory cell array 62 may be a NAND flash memory cell array in which memory cells 622 are provided in the form of an array of NAND memory strings 621, each extending vertically above a substrate (not shown). In some implementations, each NAND memory string 621 includes multiple memory cells 622 coupled in series and stacked vertically. Each memory cell 622 can hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the area of ​​memory cell 622.

[0073] In some implementations, each memory cell 622 is a single-level cell (SLC) with two possible memory states and can store one bit of data. For example, a first memory state "0" may correspond to a first range of voltages, and a second memory state "1" may correspond to a second range of voltages. In some implementations, each memory cell 622 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0074] As shown in FIG. 1D , memory cells 622 of adjacent NAND memory strings 621 can be coupled through word lines 629, which select which row of memory cells 622 is affected by read and program operations. Each NAND memory string 621 can include a source select gate (SSG) 623 at its source end and a drain select gate (DSG) 624 at its drain end. The SSG 623 and DSG 624 can be configured to enable a selected NAND memory string 621 (column of the array) during sense, read, and program operations. In some implementations, the sources of the NAND memory strings 621 are coupled through the same source line (SL) 625, e.g., a common SL. In other words, according to some implementations, all NAND memory strings 621 in the same block have an array common source (ACS). According to some implementations, the DSG 624 of each NAND memory string 621 is coupled to a respective bit line 626, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 621 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor comprising the DSG 624) or a deselect voltage (e.g., 0V) to the respective DSG 624 through one or more DSG lines 627, and / or by applying a select voltage (e.g., above the threshold voltage of the transistor comprising the SSG 623) or a deselect voltage (e.g., 0V) to the respective SSG 623 through one or more SSG lines 628.

[0075] 1E, peripheral circuitry 64 includes a page buffer (PB) / sense amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, control logic 75, address registers 76, data registers 77, an SRAM 78, a data interface 79, a processing unit 80, and a data path bus 81. It should be understood that the peripheral circuitry 70 described above may be the same as peripheral circuitry 64 of FIG. 1D, and in some other examples, peripheral circuitry 70 may also include additional peripheral circuitry not shown in FIG. 1E.

[0076] The page buffer / sense amplifier 71 may be configured to sense, read, and program (write) data from and to the memory cell array 62 according to control signals from the control logic 75. In one example, the page buffer / sense amplifier 71 may store one page of program data (write data) to be programmed into one page of the memory cell array 62. In another example, the page buffer / sense amplifier 71 may perform a program verify operation to ensure that data is properly programmed into memory cells coupled to a selected word line. In yet another example, the page buffer / sense amplifier 71 may also sense low-power signals from bit lines representing data bits stored in memory cells and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 72 may be controlled by the control logic 75 and configured to select one or more NAND memory strings 66 by applying bit line voltages generated from a voltage generator 74.

[0077] The row decoder / word line driver 73 is controlled by control logic 75 and may be configured to select / deselect blocks of the memory cell array 62 and select / deselect word lines of the blocks. The row decoder / word line driver 73 may be configured to drive the word lines using word line voltages generated from a voltage generator 74. In some implementations, the row decoder / word line driver 73 may also select / deselect and drive the SSG line 628 and the DSG line 627. As described in more detail below, the row decoder / word line driver 73 is configured to apply a read voltage to a selected word line in a read operation for a memory cell coupled to the selected word line.

[0078] The voltage generator 74 may be controlled by the control logic 75 and configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 62.

[0079] The control logic 75 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The address register 76 and the data register 77 may be coupled to the control logic 75 and configured to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The SRAM 78 may be an on-die SRAM integrated with the memory device or an independent SRAM separate from the memory device. The SRAM 78 may be coupled to the data register 77 for receiving data used for calculations and transmitting the data to the processing unit 80. The data interface 79 is coupled to the control logic 75 through a data path bus 81 and may act as a control buffer, buffering and relaying control commands received from a host (not shown) to the control logic 75 and buffering and relaying status information received from the control logic 75 to the host. The data interface 79 is also coupled to the column decoder / bit line driver 72 and may act as a data input / output (I / O) interface and a data buffer, buffering and relaying data to and from the memory cell array 62.

[0080] 1F , a processing unit 80 is shown. The processing unit 80 includes a plurality of processing elements 82, at least one first register 86, a plurality of second registers 88, and a control element coupled to the first register 86 and the second register 88. The processing unit 80 may be coupled to the SRAM 78 through the at least one first register 86 to receive first data, which may be obtained by the SRAM from a data interface 79. The processing unit 80 may be coupled to the page buffer 71 through the second register 88 to receive second data, which may be sensed by the page buffer 71 from the memory cell array 62 through a data path bus 81. The processing elements 82 are coupled to the first register 86 and the second register 88 and configured to perform convolution calculations based on the first data and the second data. Each processing element 82 may include a result register configured to store a calculation result generated by the corresponding processing element. The number of processing elements 82 is equal to the number of second registers 88 and the number of columns of the second data. In this embodiment, each processing unit includes six processing elements and six second registers 88. The processing unit 80 further includes a control element 84 configured to allocate the first data and the second data to the processing elements 82 according to a predetermined data pattern. In some implementations, the number of the at least one first register 86 is equal to the number of rows of the first data. For example, in this embodiment, each processing unit 80 includes one first register 86. In some implementations, the first register 86 and the second register 88 are first-in-first-out (FIFO) registers.

[0081] AI systems are primarily used in two aspects: training and inference. The present disclosure can be primarily used in AI inference, where data is input to a trained AI module and recognized and analyzed to obtain expected results for the input data. In AI inference, calculations are performed based on the input data and data pre-stored in the AI ​​system to confirm one or more properties of the input data. In AI inference, the input data may be one-dimensional data, and the reference data may often be two-dimensional data, as shown in FIG. 2A, where the first data is a one-dimensional vector and the second data is a two-dimensional matrix. In the AI ​​system, three modules are provided to perform data calculations. The first module performs calculations near the memory device, where the calculations are performed outside the memory device. The second module performs calculations in the memory cell, where the calculations are performed by the memory cell of the memory device. The third module performs processing in the memory cell, where the calculations are performed by an additional processing unit of the memory device. The third module, i.e., the module processing in the memory cell, is utilized in implementations of the present disclosure.

[0082] 2B shows the equivalent shape of the first data and the second data of FIG. 2A. In some implementations, the one-dimensional first data can be considered as a row of data of length a, and the two-dimensional second data, i.e., an a×b matrix, can be considered as b columns, each column having a length of a. In some implementations, the first data may be a two-dimensional matrix including more than one row of equal data length, and dimensionality reduction can be performed on more than one row of the first data to decompose the first data into multiple single rows to which the present disclosure is applicable.

[0083] In some implementations, the first data and the second data may be preprocessed before being processed to perform convolution of the memory device. In some implementations, the first data and the second data may be preprocessed based on first and second data patterns as shown in FIG.

[0084] In some implementations, the first data includes one row, and the control logic 75 is configured to control the SRAM to retrieve and transmit the row of first data to at least one processing unit 80 based on a first data pattern, as shown in FIG. 2C . The first data pattern includes N first data segments of equal length, where N is a positive integer and N≧2. In this implementation, N=4 is used as an example to illustrate the present disclosure. The first data includes four first data segments based on the first data pattern, namely, first data segment S1-0, first data segment S1-1, first data segment S1-2, and first data segment S1-3. The sequence of the four first data segments in the first data pattern is the same as the sequence of the first data. In some implementations, the data length of each first data segment is less than or equal to the bandwidth of the data path bus. In some implementations, an error checking and correcting (ECC) code is assigned to each first data segment to verify the first data segment. The ECC code may also be used as an identifier to identify each first data segment of the first data pattern.

[0085] In some implementations, the second data includes M columns, where M is a positive integer and M≧2. As shown in FIG. 2C , the control logic 75 is configured to program each column of the second data into the memory cells of the memory cell array 62 based on a second data pattern. The second data pattern includes N data groups, each having M second data segments of equal data length from the M columns of the second data, where the first data segment and the second data segment share equal data length. In some implementations, N=4 and M=6 are used as an example to illustrate the present disclosure. As shown in FIG. 2C , the second data includes six columns, namely, column 1, column 2, column 3, column 4, column 5, and column 6. Each of the six columns includes four second data segments, namely, second data segment S2-0, second data segment S2-1, second data segment S2-2, and second data segment S2-3. Referring to FIG. 2C, the six second data segments S2-0 are regrouped as a first data group of the second data pattern, the six second data segments S2-1 are regrouped as a second data group of the second data pattern, the six second data segments S2-2 are regrouped as a third data group of the second data pattern, and the six second data segments S2-3 are regrouped as a fourth data group of the second data pattern.

[0086] 2D , in some implementations, each of the four data groups of the second data pattern is programmed consecutively into the memory cell array, i.e., the logical addresses of the data in each data group are consecutive, so that data of the same data group can be simultaneously sensed into the page buffer 71. For example, in some implementations, the six second data segments S2-0 of the first data group are programmed consecutively in block 0 of the memory cell array 62, the six second data segments S2-1 of the second data group are programmed consecutively in block 1 of the memory cell array 62, the six second data segments S2-2 of the third data group are programmed consecutively in block 2 of the memory cell array 62, and the six second data segments S2-3 of the first data group are programmed consecutively in block 3 of the memory cell array 62. In some implementations, the capacity of each block of the memory cell array 62 is at least twice the data length of each data group, so that two or more data groups can be programmed consecutively within the same block of the memory cell array 62. In some implementations, the capacity of each block of the memory cell array 62 is shorter than the data length of each data group, so that each data group can be programmed in two consecutive blocks of the memory cell array 62. In some implementations, an error checking and correcting (ECC) code is assigned to each second data segment to verify the second data segment. The ECC code can also be used as an identifier to identify each second data segment of the second data pattern.

[0087] 2C to at least one processing unit 80. For example, as shown in FIG. 3A, the first data segment S1-0 is first transmitted to the processing unit 80, and as shown in FIG. 3B, the first data segment S1-1 is transmitted to the processing unit 80 following the first data segment S1-0. The first data segment S1-2 and the first data segment S1-3 are transmitted to the processing unit 80 following the first data segment S1-1 (not shown). Using the first data segment S1-0 as an example, in some implementations, the first data segment S1-0 is transmitted to the first register 86 and buffered therein. In some implementations, as shown in FIG. 3A, each processing unit includes a control element configured to assign the first data segment S1-1 to each processing element 82.

[0088] 2C to at least one processing unit 80. For example, as shown in FIG. 3A, six second data segments S2-0 of the first data group are first transmitted to the processing unit 80, and as shown in FIG. 3B, the first data group is followed by six second data segments S2-1 of the second data group. Following the second data group, six second data segments S2-2 of the third data group of the second data are transmitted to the processing unit 80, and following the third data group, six second data segments S2-3 of the four data groups of the second data are transmitted to the processing unit 80 (not shown). Using the six second data segments S2-0 as an example, in some implementations, the six second data segments S2-1 are transmitted to and buffered in six second registers 88. In some implementations, as shown in FIG. 3A, each processing unit includes a control element configured to assign the six second data segments S2-1 to the six processing elements one by one based on the sequence of the six second data segments S2-1.

[0089] In some implementations, the M processing elements 82 of each processing unit 80 are configured to perform a convolution operation based on an ith first data segment of the N first data segments and M second data segments of the ith data group of the N data groups, where i is a positive integer and N≧i≧1. Referring to FIGS. 3A and 3B , in this implementation, the first data segment S1-0 is sent to each of the six processing elements 82, and the six second data segments S2-0 of the first data group of the second data are sent one by one to the six processing elements 82. The six processing elements 82 then perform a convolution operation based on the first data segment S1-0 and the six second data segments S2-0 to obtain a first calculation result. In some implementations, the first calculation result is then sent to and stored in a corresponding result register of each processing element 82 for further calculation. In some implementations, the first calculation result may then be sent to and stored in a data interface 79 under the control of the control logic 75. In some implementations, the first calculation result is then sent to and stored in the memory cell array 62 under the control of the control logic 75. The first data segment S1-1 and the six second data segments S2-1 are then sent to the six processing elements 82 to perform a convolution operation to generate a second calculation result. The second calculation result is then subsequently sent by the control logic 75 to a corresponding result register, data interface 79, or memory cell array 62.

[0090] 4 , the calculation principle of at least one processing unit is provided, in which an i-th first data segment is multiplied by M second data segments of the i-th data group of N data groups to obtain an i-th result. The N i-th results are accumulated to obtain a convolution result. In some implementations, the peripheral circuit 70 includes one processing unit 80, and the convolution operation between the N first data segments and the convolution operation between the N data groups of the second data are performed consecutively by the one processing unit 80. In some implementations, the peripheral circuit 70 includes more than one processing unit 80, and the convolution operation between the N first data segments and the convolution operation between the N data groups of the second data are each performed simultaneously by different processing units 80.

[0091] The at least one processing unit 80 is independently configured within the peripheral circuit 70 and is a separate module. As the number of the at least one processing unit 80 within the peripheral circuit 70 increases, the calculation speed of the peripheral circuit 70 improves, but a larger area of ​​the peripheral circuit 70 is required, resulting in a trade-off between calculation speed and the area of ​​the peripheral circuit 70. In some implementations, the memory cell array 62 is divided into more than one plane of memory cells, with each plane including multiple memory cells. The number of the at least one processing unit 80 is equal to the number of planes of memory cells, meaning that the at least one processing unit 80 corresponds to each of the multiple planes of memory cells. For example, the memory cell array 62 is divided into 128 planes of memory cells, and the number of the at least one processing unit 80 is also 128. In some implementations, the number of the at least one processing unit 80 is less than the number of planes of memory cells. For example, the memory cell array 62 is divided into 128 planes of memory cells, and the number of the at least one processing unit 80 can be 100, 64, 50, or some other number less than 128. In some implementations, the number of the at least one processing unit 80 is half the number of planes of memory cells, with one processing unit corresponding to two planes of memory cells each. For example, memory cell array 62 is divided into 128 planes of memory cells, and the number of the at least one processing unit 80 is 64. In some implementations, the number of the at least one processing unit 80 is one-quarter the number of planes of memory cells, with one processing unit corresponding to four planes of memory cells each. For example, memory cell array 62 is divided into 128 planes of memory cells, and the number of the at least one processing unit 80 is 32. The number of the at least one processing unit 80 may be set and adjusted based on the needs of the AI ​​system, and the implementations of the present disclosure are intended to illustrate the present disclosure and should not be described as limiting.

[0092] In another aspect of the present disclosure, the control logic 75 of the peripheral circuit 70 is configured to control the SRAM 78 to sequentially acquire a first portion of the first data, a second portion of the first data, and a third portion of the first data. The control logic 75 of the peripheral circuit 70 is further configured to control the page buffer 71 to sequentially sense a first portion of the second data, a second portion of the second data, and a third portion of the second data. The control logic 75 of the peripheral circuit 70 is further configured to perform a first calculation based on the first portion of the first data and the first portion of the second data while sensing the second portion of the second data, and subsequently perform a second calculation based on the second portion of the first data and the second portion of the second data while sensing the third portion of the second data. The control logic 75 of the peripheral circuit 70 is further configured to output the first calculation result for the first portion of the first data and the first portion of the second data to the data interface while sensing the third portion of the second data.

[0093] 5, an operational pipeline of one processing unit 80 is shown. As described above, the first data includes at least one row, and the control logic 75 is configured to control the SRAM 78 to receive each row of the first data based on the first data pattern.

[0094] The first data pattern includes N first data segments of equal data length, where N is a positive integer and N≧2, and the sequence of the N first data segments in the first data pattern is the same as the sequence of the first data. The data length of each first data segment is equal to or less than the bandwidth of the data path bus 81. In this implementation, as shown in FIG. 2C , each portion of the first data includes a first data segment. For example, the first portion of the first data may be first data segment S1-0, the second portion of the first data may be first data segment S1-1, the third portion of the first data may be first data segment S1-2, and the fourth portion of the first data may be first data segment S1-3. In some implementations, the Nth portion of the first data may be first data segment S1-(N−1). In some implementations, each portion of the first data may include a data segment that is longer or shorter than the first data segment based on the bandwidth of the data path bus 81 and other data widths of the peripheral circuit 70.

[0095] The second data includes M columns, where M is a positive integer and M≧2. The control logic 75 is configured to program each column of the second data into a memory cell based on the second data pattern. In some implementations, the control logic 75 is configured to program the second data into the memory cell as a single-level memory cell (SLC). The second data pattern includes N data groups, each having M second data segments of equal data length from the M columns of the second data, where the first data segment and the second data segment are configured to share the same data length. In some implementations, each portion of the second data corresponds to a portion of the first data to be multiplied, e.g., the first portion of the second data may be the six second data segments S2-0 of the first data group of the second data multiplied with the first data segment S1-0, the second portion of the second data may be the six second data segments S2-1 of the second data group multiplied with the first data segment S1-1, the third portion of the second data may be the six second data segments S2-2 of the third data group of the second data multiplied with the first data segment S1-2, and the fourth portion of the second data may be the six second data segments S2-0 of the fourth data group of the second data multiplied with the first data segment S1-3. In some implementations, the Nth portion of the second data may be the six second data segments S2-(N-1) of the Nth data group of the second data multiplied with the first data segment S1-(N-1).

[0096] 5 is performed by at least one processing element 82 of each processing unit 80. The control logic 75 is configured to control the SRAM 78 to send the i-th first data segment to each processing element 82, and to control the page buffer 71 to send M second data segments to the M processing elements 82. Each of the at least one processing unit 80 includes a control element 84 configured to assign the M second data segments to the M processing elements one by one based on the sequence of the M second data segments.

[0097] 5, an initial cycle C0 is configured to prepare the processing unit 80. The operation pipeline begins with a first cycle C1, in which a first portion of first data is obtained by the SRAM 78 and sent to the processing element 82 of the processing unit 80, while a first portion of second data is sensed by the page buffer 71 and sent to the processing element 82 of the processing unit 80.

[0098] In a second cycle C2 subsequent to the first cycle C1, a first calculation is performed by the processing element 82, and a first result is generated based on the first portion of the first data and the first portion of the second data. The first result is copied by the control logic 75 at the end of the second cycle C2. At the same time, a second portion of the first data is retrieved by the SRAM 78 and sent to the processing element 82, while a second portion of the second data is detected by the page buffer 71 and sent to the processing element 82.

[0099] Subsequently, in the third cycle C3, the first result is output to and stored in the corresponding result register of the processing element, the data interface 79, or the memory cell array 62. Because outputting the first result takes much less time than sensing the data or performing the calculation, outputting the first result can be performed at any time during the third cycle C3. During the third cycle C3, a second calculation is performed by the processing element 82, and a second result is generated based on the second portion of the first data and the second portion of the second data. The second result is copied by the control logic 75 at the end of the second cycle C2. Simultaneously, a third portion of the first data is retrieved by the SRAM 78 and sent to the processing element 82, while a third portion of the second data is sensed by the page buffer 71 and sent to the processing element 82.

[0100] Subsequently, in the fourth cycle C4, the second result is output to and stored in the corresponding result register or data interface 79 of the processing element, while the third calculation is performed by the processing element 82, and the third result is generated based on the third portion of the first data and the third portion of the second data. Simultaneously, the fourth portion of the first data is retrieved by the SRAM 78 and sent to the processing element 82, while the fourth portion of the second data is detected by the page buffer 71 and sent to the processing element 82. Similarly, in the ith cycle Ci, the (i-2)th result is sent to and stored in the corresponding result register, data interface 79 of the processing element, while the (i-1)th calculation is performed by the processing element 82, and the (i-1)th result is generated based on the (i-1)th portion of the first data and the (i-1)th portion of the second data. At the same time, the i-th portion of the first data is acquired by the SRAM 78 and sent to the processing element 82, while the i-th portion of the second data is sensed by the page buffer 71 and sent to the processing element 82. By applying the operation pipeline of Figure 5, sensing the first and second data, performing the convolution calculation, and outputting the calculation result can be completed within a single cycle, effectively improving the calculation. In some implementations, only sensing the first data and the second data and performing the convolution calculation are required.

[0101] According to an aspect of the present disclosure, a system is provided that includes a memory device and a memory controller. The memory device includes an array of memory cells and peripheral circuits coupled to the memory cells. The peripheral circuits include a static random access memory (SRAM) configured to acquire first data transmitted from a data interface of the memory device, a page buffer configured to sense second data from the array of memory cells, and at least one processing unit coupled to the page buffer via a data path bus of the peripheral circuit and configured to perform a calculation based on the first data and the second data. The controller is coupled to the memory device and configured to transmit the first data to the memory device and receive a result of the calculation from the memory device.

[0102] In some implementations, the system may be any electronic system to which an AI system is applied, such as a computer, a digital camera, a mobile phone, a smart home appliance, an Internet of Things (IoT), a server, a base station, etc. In the present disclosure, data processing and calculation of the AI ​​system may be performed by a processing unit 80 in the peripheral circuits of the memory device. In some implementations, adding at least one processing unit to the memory device to improve the performance of the AI ​​system may distribute a large number of resource-intensive calculation tasks to the memory device rather than to a TPU or a graphics processing unit (GPU). The number of processing units may be designed based on the needs of the AI ​​system. The more processing units integrated into the memory device, the more effective the AI ​​system will be.

[0103] 6, which shows a flowchart of a method 600 for data computation using a memory device including an array of memory cells 62 and peripheral circuitry 70 coupled to the memory cell array 62, which may be the same as that described above and will not be repeated here. It is understood that the operations shown in method 600 are not exhaustive and that other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a different order than that shown in FIG. 6.

[0104] 6, method 600 may begin at operation 602, where first data is obtained from a data interface of a memory device by a static random access memory (SRAM). Method 600 may begin at operation 604, where second data from an array of memory cells is sensed by a page buffer of a peripheral circuit. Note that there are no constraints on the performance of operation 602 and operation 604. Operation 602 may be performed before, after, or simultaneously with operation 604. In some implementations, operation 602 and operation 604 may be performed in the same period to improve the computational efficiency of the memory device. The order of operations 602 and 604 should not limit the scope of this disclosure.

[0105] In some implementations, as shown in FIG. 2A, the first data may be one-dimensional data, and the second data may often be two-dimensional data, where the first data is a one-dimensional vector and the second data is a two-dimensional matrix. In some implementations, the one-dimensional first data can be equivalent to a row of data of length a, and the two-dimensional second data, i.e., an a×b matrix, can be equivalent to b columns, each column having a length of a. In some implementations, the first data may be a two-dimensional matrix including more than one row of equal data length, and dimensionality reduction can be performed on more than one row of the first data to decompose the first data into multiple single rows to which the present disclosure is applicable.

[0106] In some implementations, the first data and the second data may be preprocessed before operations 602 and 604. In some implementations, the first data and the second data may be preprocessed based on first and second data patterns, as shown in FIG.

[0107] In some implementations, first data is acquired and transmitted to at least one processing unit 80 based on a first data pattern, as shown in FIG. 2C . The first data pattern includes N first data segments of equal length, where N is a positive integer and N≧2. In this implementation, N=4 is used as an example to illustrate the present disclosure. The first data includes four first data segments based on the first data pattern, namely, first data segment S1-0, first data segment S1-1, first data segment S1-2, and first data segment S1-3. The sequence of the four first data segments in the first data pattern is the same as the sequence of the first data. In some implementations, the data length of each first data segment is equal to or less than the bandwidth of the data path bus. In some implementations, an error checking and correcting (ECC) code is assigned to each first data segment to verify the first data segment. The ECC code can also be used as an identifier to identify each first data segment in the first data pattern.

[0108] In some implementations, the second data includes M columns, where M is a positive integer and M≧2. As shown in FIG. 2C , each column of the second data is programmed into a memory cell of memory cell array 62 based on a second data pattern. The second data pattern includes N data groups, each having M second data segments of equal data length from the M columns of the second data, where the first data segments and the second data segments are configured to share the same data length.

[0109] In some implementations, N=4 and M=6 are used as an example to illustrate the present disclosure. As shown in FIG. 2C, the second data includes six columns, namely, column 1, column 2, column 3, column 4, column 5, and column 6. Each of the six columns includes four second data segments, namely, second data segment S2-0, second data segment S2-1, second data segment S2-2, and second data segment S2-3. Referring to FIG. 2C, the six second data segments S2-0 are regrouped as a first data group of the second data pattern, the six second data segments S2-1 are regrouped as a second data group of the second data pattern, the six second data segments S2-2 are regrouped as a third data group of the second data pattern, and the six second data segments S2-3 are regrouped as a fourth data group of the second data pattern. In some implementations, an error checking and correcting (ECC) code is assigned to each second data segment to verify the second data segment, and the ECC code can also be used as an identifier to identify each second data segment of the second data pattern.

[0110] 2D , in some implementations, each of the four data groups of the second data pattern is programmed consecutively into the memory cell array, i.e., the logical addresses of the data in each data group are consecutive, so that data of the same data group can be simultaneously sensed into the page buffer 71. For example, in some implementations, the six second data segments S2-0 of the first data group are programmed consecutively in block 0 of the memory cell array 62, the six second data segments S2-1 of the second data group are programmed consecutively in block 1 of the memory cell array 62, the six second data segments S2-2 of the third data group are programmed consecutively in block 2 of the memory cell array 62, and the six second data segments S2-3 of the first data group are programmed consecutively in block 3 of the memory cell array 62. In some implementations, the capacity of each block of the memory cell array 62 is at least twice the data length of each data group, so that two or more data groups can be programmed consecutively within the same block of the memory cell array 62. In some implementations, the capacity of each block of the memory cell array 62 is smaller than the data length of each data group, so that each data group can be programmed in two consecutive blocks of the memory cell array 62.

[0111] 2C to at least one processing unit 80. For example, as shown in FIG. 3A, the first data segment S1-0 is first transmitted to the processing unit 80, and as shown in FIG. 3B, the first data segment S1-1 is subsequently transmitted to the processing unit 80 after the first data segment S1-0. The first data segment S1-2 and the first data segment S1-3 are subsequently transmitted to the processing unit 80 after the first data segment S1-1 (not shown). Using the first data segment S1-0 as an example, in some implementations, the first data segment S1-0 is transmitted to the first register 86 and buffered therein. In some implementations, each processing unit includes a control element configured to assign the first data segment S1-1 to each processing element 82, as shown in FIG. 3A.

[0112] 2C , the data groups of the second data pattern are detected and transmitted to at least one processing unit 80. For example, as shown in FIG. 3A , six second data segments S2-0 of the first data group are first transmitted to the processing unit 80, and as shown in FIG. 3B , six second data segments S2-1 of the second data group are subsequently transmitted to the processing unit 80 after the first data group. Then, six second data segments S2-2 of the third data group of the second data are subsequently transmitted to the processing unit 80 after the second data group, and six second data segments S2-3 of the fourth data group of the second data are subsequently transmitted to the processing unit 80 after the third data group (not shown). Using the six second data segments S2-0 as an example, in some implementations, the six second data segments S2-1 are transmitted to the six second registers 88 and buffered therein. In some implementations, each processing unit includes a control element configured to assign the six second data segments S2-1 to the six processing elements one by one based on the sequence of the six second data segments S2-1, as shown in FIG. 3A.

[0113] As shown in FIG. 6, method 600 may begin at operation 606, when a calculation is performed by at least one processing unit of a peripheral circuit based on first data and second data.

[0114] In some implementations, operation 606 includes performing a convolution operation by M processing elements 82 of each processing unit 80 based on an ith first data segment of the N first data segments and M second data segments of the ith data group of the N data groups, where i is a positive integer and N≧i≧1. Referring to FIGS. 3A and 3B , in this implementation, the first data segment S1-0 is sent to each of the six processing elements 82, and the six second data segments S2-0 of the first data group of the second data are sent one by one to the six processing elements 82, and convolution operations are performed by the six processing elements 82 based on the first data segment S1-0 and the six second data segments S2-0 to obtain a first calculation result. The first calculation result is then sent by control logic 75 to data interface 79. The first data segment S1-1 and the six second data segments S2-1 are then sent to the six processing elements 82 to perform a convolution operation to generate a second calculation result, which is then subsequently sent by the control logic 75 to the data interface 79.

[0115] 4, in which an i-th first data segment is multiplied by M second data segments of an i-th data group of N data groups to obtain an i-th result. The N i-th results are accumulated to obtain a convolution result. In some implementations, the peripheral circuit 70 includes one processing unit 80, and then the convolution operation between the N first data segments and the convolution operation between the N data groups of the second data are successively performed by the one processing unit 80. In some implementations, the peripheral circuit 70 includes more than one processing unit 80, and the convolution operation between the N first data segments and the convolution operation between the N data groups of the second data are simultaneously performed by different processing units 80.

[0116] The above description of specific implementations may be readily modified and / or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0117] The breadth and scope of the present disclosure should not be limited by any of the above-described implementations, but should be defined only in accordance with the following claims and their equivalents.

[0118] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of the present disclosure. The subject matter as described in this disclosure may also be used in a variety of other applications. The functional and structural features as described in this disclosure may be combined, adjusted, modified, and rearranged in a manner consistent with each other and the scope of the present disclosure. [Explanation of symbols]

[0119] 10 Systems 20 hosts 30 Memory System 32 Memory Controller 34 Memory Devices 40 Memory Card 42 Memory card connector 50 SSD 52 SSD connector 60 Memory Devices 62 Memory Cell Array 64 Peripheral Circuits 70 Peripheral Circuits 71 Page buffer / sense amplifier 72 Column decoder / BL driver 73 Row decoder / WL driver 74 Voltage Generator 75 Control Logic 76 Address Register 77 Data Register 78 SRAM 79 Data Interface 80 processing units 82 Processing Elements 84 Control Elements 86 First Register 621 NAND memory strings 622 memory cells 623 Source Select Gate 624 Drain Select Gate 625 source line 626 bit lines 627 DSG line 628 SSG Line 629 Word Line

Claims

1. an array of memory cells; peripheral circuitry coupled to said array of memory cells; 1. A memory device comprising: a static random access memory (SRAM) configured to receive first data transmitted from a data interface of the memory device; a page buffer configured to sense second data from the array of memory cells; at least one processing unit coupled to the SRAM and the page buffer via a data path bus of the peripheral circuit, the processing unit configured to perform calculations based on the first data and the second data; control logic configured to program the second data into the array of memory cells; A memory device comprising:

2. the first data comprises at least one row; 2. The memory device of claim 1, wherein the control logic is configured to control the SRAM to send each row of the first data to the at least one processing unit based on a first data pattern.

3. the first data pattern comprises N first data segments of equal data length, N is a positive integer, and N≧2; 3. The memory device of claim 2, wherein a sequence of the N first data segments of the first data pattern is the same as a sequence of the first data.

4. The memory device of claim 3 , wherein the data length of each first data segment is less than or equal to a bandwidth of the data path bus.

5. the second data comprises M columns, M is a positive integer, and M≧2; 4. The memory device of claim 3, wherein the control logic is configured to program each column of the second data into the memory cells based on a second data pattern.

6. 6. The memory device of claim 5, wherein the control logic is configured to program the second data into the memory cells, and to program each bit of the second data into one of the memory cells as a single-level memory cell (SLC).

7. the second data pattern comprises N data groups each having M second data segments of equal data length from the M strings of the second data; 6. The memory device of claim 5, wherein the first data segment and the second data segment are configured to share an equal data length.

8. 8. The memory device of claim 7, wherein each second data segment of the M second data segments of each data group of the N data groups is assigned an error checking and correcting (ECC) code.

9. 8. The memory device of claim 7, wherein the data length of each second data segment is less than or equal to a bandwidth of the data path bus.

10. 8. The memory device of claim 7, wherein the control logic is configured to control the page buffer to sense the second data from the memory cells to the page buffer based on the second data pattern.

11. Each of the at least one processing unit:

8. The memory device of claim 7, comprising M processing elements configured to perform a convolution operation based on an i-th first data segment of the N first data segments and the M second data segments of the i-th data group of the N data groups, where i is a positive integer and N≧i≧1.

12. the control logic: controlling the SRAM to transmit the i-th first data segment of the first data to each processing element of the M processing elements; controlling the page buffer to transmit the M second data segments to the M processing elements; The memory device of claim 11 configured to:

13. Each of the at least one processing unit: assigning the M second data segments to the M processing elements one by one based on the sequence of the M second data segments; The memory device of claim 12 , comprising a control element configured to:

14. the control logic: Obtain the calculation results, The calculation result is output to the data interface. The memory device of claim 13 configured to:

15. the array of memory cells is divided into more than one plane of memory cells; the number of said at least one processing unit is equal to the number of said planes of memory cells; 14. The memory device of claim 13, wherein the at least one processing unit corresponds one-by-one to the more than one plane of memory cells.

16. the array of memory cells is divided into more than one plane of memory cells; 14. The memory device of claim 13, wherein the number of the at least one processing unit is less than the number of the planes of memory cells.

17. the number of the at least one processing unit is half the number of the planes of memory cells; 17. The memory device of claim 16, wherein one processing unit corresponds to each of two planes of memory cells.

18. the number of said at least one processing unit is one-fourth of the number of said planes of memory cells; 17. The memory device of claim 16, wherein one processing unit corresponds to each of four planes of memory cells.

19. the number of the at least one processing unit is 1; 17. The memory device of claim 16, wherein one processing unit corresponds to the more than one plane of memory cells.

20. The memory device of claim 1 , wherein the memory device comprises a NAND flash memory.

21. 1. A method for data computation using a memory device comprising an array of memory cells and peripheral circuits coupled to the memory cells, comprising: obtaining, by a static random access memory (SRAM), first data from a data interface of the memory device; sensing second data from the array of memory cells by a page buffer of the peripheral circuitry; performing, by at least one processing unit of the peripheral circuitry, a calculation based on the first data and the second data; A method comprising:

22. 22. The method of claim 21, further comprising programming the second data into the array of memory cells.

23. the first data comprises at least one row; 23. The method of claim 22, wherein obtaining the first data from a data interface of the memory device comprises sending each row of the first data to the at least one processing unit based on a first data pattern.

24. the first data pattern comprises N first data segments of equal data length, N is a positive integer, and N≧2; 24. The method of claim 23, wherein the sequence of the N first data segments of the first data pattern is the same as the sequence of the first data.

25. 25. The method of claim 24, wherein the data length of each first data segment is less than or equal to a bandwidth of a data path bus.

26. the second data comprises M columns; 25. The method of claim 24, wherein programming the second data into the array of memory cells comprises programming each column of the second data into the memory cells based on a second data pattern.

27. 27. The method of claim 26, wherein the second data is programmed into the memory cell as a single-level memory cell (SLC).

28. the second data pattern comprises N data groups each having M second data segments of equal data length from the M strings of the second data; 27. The method of claim 26, wherein the first data segment and the second data segment are configured to share an equal data length.

29. sensing the second data from the array of memory cells; 30. The method of claim 28, comprising assigning an error checking and correcting (ECC) code to each second data segment of the M second data segments of each data group of the second data.

30. 29. The method of claim 28, wherein the data length of each second data segment is less than or equal to a bandwidth of a data path bus.

31. sensing the second data from the array of memory cells; 30. The method of claim 28, comprising sensing the second data from the memory cells to the page buffer based on the second data pattern.

32. performing a calculation based on the first data and the second data, 32. The method of claim 31, comprising: performing, by M processing elements of each of the at least one processing unit, a convolution operation based on an i-th first data segment of the N first data segments and the M second data segments of the i-th data group of the N data groups.

33. performing a calculation based on the first data and the second data, transmitting, by the SRAM, the i-th first data segment to each of the M processing elements; transmitting the M second data segments to the M processing elements one by one by the page buffer; 33. The method of claim 32, comprising:

34. obtaining a calculation result; outputting the calculation result to the data interface; 34. The method of claim 33, further comprising:

35. an array of memory cells; peripheral circuits coupled to the memory cells; 1. A memory device comprising: a static random access memory (SRAM) configured to receive first data transmitted from a data interface of the memory device; a page buffer configured to sense second data from the array of memory cells; at least one processing unit coupled to the SRAM and the page buffer and configured to perform calculations based on the first data and the second data; Control logic comprising: controlling the SRAM to sequentially obtain a first portion of the first data, a second portion of the first data, and a third portion of the first data; Controlling the page buffer to sequentially sense a first portion of the second data, a second portion of the second data, and a third portion of the second data. The control logic is configured as follows: and the control logic further comprises: performing a first calculation based on the first portion of the first data and the first portion of the second data while sensing the second portion of the second data; Then, while detecting the third portion of the second data, a second calculation is performed based on the second portion of the first data and the second portion of the second data. a memory device configured to control the at least one processing unit to:

36. 36. The memory device of claim 35, wherein the control logic is further configured to output a first calculation result for the first portion of the first data and the first portion of the second data to the data interface while sensing the third portion of the second data.

37. 36. The memory device of claim 35, wherein the control logic is further configured to program the second data into the array of memory cells.

38. the first data comprises at least one row; 38. The memory device of claim 37, wherein the control logic is configured to control the SRAM to receive each row of the first data based on a first data pattern.

39. the first data pattern comprises N first data segments of equal data length, N is a positive integer, and N≧2; 39. The memory device of claim 38, wherein a sequence of the N first data segments of the first data pattern is the same as a sequence of the first data.

40. 40. The memory device of claim 39, wherein the data length of each first data segment is less than or equal to a bandwidth of a data path bus.

41. the second data comprises M columns, M is a positive integer, and M≧2; 40. The memory device of claim 39, wherein the control logic is configured to program each column of the second data into the memory cells based on a second data pattern.

42. 42. The memory device of claim 41, wherein the control logic is configured to program the second data into the memory cell as a single-level memory cell (SLC).

43. the second data pattern comprises N data groups each having M second data segments of equal data length from the M strings of the second data; 43. The memory device of claim 42, wherein the first data segment and the second data segment are configured to share an equal data length.

44. 44. The memory device of claim 43, wherein each second data segment of the M second data segments of each data group of the second data is assigned an error checking and correcting (ECC) code.

45. 44. The memory device of claim 43, wherein the data length of each second data segment is less than or equal to a bandwidth of a data path bus.

46. 44. The memory device of claim 43, wherein the control logic is configured to control the page buffer to sense the second data from the memory cells to the page buffer based on the second data pattern.

47. Each of the at least one processing unit:

47. The memory device of claim 46, comprising M processing elements configured to perform a convolution operation based on an i-th first data segment of the N first data segments and the M second data segments of the i-th data group of the N data groups.

48. Each of the control logics controlling the SRAM to transmit the i-th first data segment to each of the M processing elements; controlling the page buffer to transmit the M second data segments to the M processing elements; 46. ​​The memory device of claim 45 configured to:

49. Each of the at least one processing unit: assigning the M second data segments to the M processing elements one by one based on the sequence of the M second data segments; 46. ​​The memory device of claim 45, comprising a control element configured to:

50. the array of memory cells is divided into more than one plane of memory cells; the number of said at least one processing unit is equal to the number of said planes of memory cells; 47. The memory device of claim 46, wherein the at least one processing unit corresponds one-by-one to the more than one plane of memory cells.

51. the array of memory cells is divided into more than one plane of memory cells; 47. The memory device of claim 46, wherein the number of the at least one processing units is less than the number of the planes of memory cells.

52. the number of the at least one processing unit is half the number of the planes of memory cells; 52. The memory device of claim 51, wherein one processing unit corresponds to each of two planes of memory cells.

53. the number of said at least one processing unit is one-fourth of the number of said planes of memory cells; 52. The memory device of claim 51, wherein one processing unit corresponds to each of four planes of memory cells.

54. the number of the at least one processing unit is 1; 52. The memory device of claim 51, wherein one processing unit corresponds to the more than one plane of memory cells.

55. 36. The memory device of claim 35, wherein the memory device is a NAND flash memory.

56. an array of memory cells; peripheral circuits coupled to the memory cells; 1. A memory device comprising: a static random access memory (SRAM) configured to receive first data transmitted from a data interface of the memory device; a page buffer configured to sense second data from the array of memory cells; at least one processing unit coupled to the page buffer via a data path bus of the peripheral circuit and configured to perform calculations based on the first data and the second data; a memory device comprising: a controller coupled to the memory device and configured to send the first data to the memory device and receive results of the calculations from the memory device; A system comprising:

57. 57. The system of claim 56, wherein the controller is further configured to transmit the second data to the memory device.

58. 57. The system of claim 56, wherein the memory device is a NAND flash memory.

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