Electronic device with patch antenna on packaging substrate

Abstract

The electronic device (100) includes a multilevel package substrate (108), a semiconductor die (102), and a package structure (106), the multilevel package substrate having first, second, and third levels (L1-L3) including respective dielectric layers and conductive features, the first level (L1) including a first trace layer (M1) including an antenna (110) and a first via layer (V1) laterally spaced from the antenna (110) and including a portion of a ground wall (GW) surrounding the antenna, the second level (L2) including a second trace layer (M2) having a ground plane (GP) connected to the ground wall, the semiconductor die (102) being attached to the first level (L1) of the multilevel package substrate, and the package structure including a molding compound surrounding the semiconductor die (102) and extending over a side of the antenna, the material and thickness of the package structure molding compound being adjustable for improved performance.

Description

[Technical Field]

[0001] Antennas can be integrated into electronic devices or systems to implement wireless communication capabilities for millimeter wavelengths, terahertz frequencies, and other applications. Integrated antennas can be implemented on-chip, within semiconductor packages, and on host system printed circuit boards (PCBs). However, on-chip antennas operating in the millimeter and terahertz frequency bands suffer from ohmic losses (e.g., I) from the metal layers of the semiconductor die or chip, as well as from the high dielectric loss tangent of the packaging molding compound at these frequency bands. 2 R losses). Antennas on packages can also suffer performance degradation due to dielectric losses in the packaging material, resulting in loss of radiated power for generated higher-order surface wave modes, which further limits the antenna radiation efficiency of planar structures. Also, proximity to off-chip components can cause reflection and absorption of electromagnetic energy, which can reduce the directivity and overall radiation performance of these antennas. Summary of the Invention

[0002] In one aspect, an electronic device includes a multilevel package substrate, a semiconductor die attached to a first level of the multilevel package substrate, and a package structure. The multilevel package substrate has a first level, a second level, and a third level, each including a respective dielectric layer and patterned conductive features, the first, second, and third levels extending in respective first, second, and third planes in a first direction and an orthogonal second direction, the second level being between the first and third levels along a third direction orthogonal to the first and second directions, the first level including a first trace layer including an antenna and a first via layer including a portion of a ground wall spaced laterally from the antenna and surrounding the antenna, and the second level including a second trace layer having a ground plane connected to the ground wall. The package structure includes a molding compound, the molding compound surrounding the semiconductor die and extending over a side of the antenna.

[0003] In another aspect, a system includes a circuit board and an electronic device. The electronic device includes a multilevel package substrate, a semiconductor die attached to a first level of the multilevel package substrate, and a package structure. The multilevel package substrate has a first level, a second level, and a third level, each including a respective dielectric layer and patterned conductive features, the first, second, and third levels extending in respective first, second, and third planes in a first direction and an orthogonal second direction, the second level being between the first and third levels along a third direction orthogonal to the first and second directions, the first level including a first trace layer including an antenna and a first via layer including a portion of a ground wall spaced laterally from the antenna and surrounding the antenna, and the second level including a second trace layer having a ground plane connected to the ground wall. The package structure includes a molding compound, the molding compound surrounding the semiconductor die and extending over a side of the antenna.

[0004] In a further aspect, a method of forming an electronic device includes fabricating a multilevel package substrate including a first level, a second level, and a third level, each including a respective dielectric layer and a respective patterned conductive feature, the second level being between the first level and the third level, the first level including a first trace layer including an antenna and a first via layer including a portion of a ground wall laterally spaced from the antenna and surrounding the antenna, the second level including a second trace layer having a ground plane connected to the ground wall. The method further includes flip-chip attaching a semiconductor die to the first level of the multilevel package substrate and forming a package structure including a molding compound, the molding compound surrounding the die and extending over a side of the antenna. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a top view of an electronic device having a no-lead package, a flip-chip attached semiconductor die, and a multilevel package substrate with an integrated antenna and an epoxy molding compound encapsulation extending above the antenna.

[0006] [Figure 1A] 1A is a cross-sectional side view of the electronic device taken along line 1A-1A of FIG. 1.

[0007] [Figure 1B] 1B is a partial cross-sectional top view of a first metal trace layer in a multi-level package substrate of the electronic device of FIGS. 1 and 1A. FIG.

[0008] [Figure 1C] 2 is a partial cross-sectional top view of a first via layer in the multi-level package substrate of the electronic device of FIGS. 1-1B. FIG.

[0009] [Figure 1D]FIG. 2 is a partial plan view of a second metal trace layer in the multi-level package substrate of the electronic device of FIGS. 1-1C.

[0010] [Figure 1E] FIG. 2 is a partial side view of a system including the electronic device of FIGS. 1-1D mounted on a circuit board.

[0011] [Figure 2] 1 is a flowchart of a method for manufacturing an electronic device.

[0012] [Figure 3] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 4] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 5] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 6] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 7] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 8] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 9] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 10] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 11] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 12] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 13] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 14]3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 15] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 16] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 17] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 18] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 19] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 20] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 21] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2. [Figure 22] 3 is a partial side view of the electronic device of FIG. 1 that has undergone manufacturing processing according to the method of FIG. 2.

[0013] [Figure 23] 1B is a graph containing simulated reflection coefficients and peak gains as a function of frequency for the antennas in the electronic devices of FIGS. 1-1E.

[0014] [Figure 24] 1 is a graph with curves showing simulated radiation efficiency as a function of epoxy molding compound encapsulation thickness for various encapsulation materials. DETAILED DESCRIPTION OF THE INVENTION

[0015] In the drawings, like reference numerals refer to like elements throughout, and various features are not necessarily drawn to scale. Additionally, the term "couple" includes an indirect or direct electrical or mechanical connection, or a combination thereof. For example, when a first device couples to or is coupled to a second device, the connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections. One or more operational characteristics of various circuits, systems, and / or components are described below in some cases in the context of the function that results from the configuration and / or interconnection of the various structures when the circuit elements are powered and operating. Example structures include a layer or material described as being above or on another layer or material, which may be a layer or material immediately above and in contact with the other layer or material, and other materials, such as impurities, artifacts, or residual materials from the manufacturing process, may be present between the layer or material and the other layer or material.

[0016] Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. One or more structures, features, aspects, components, etc. may be referred to herein as first, second, third, etc., such as first and second terminals, first, second, and third wells, for ease of description in connection with certain figures, and should not be construed as limiting with respect to the scope of the claims. Various disclosed structures and methods of the present disclosure can be beneficially applied to the manufacture of electronic devices such as integrated circuits. While such examples may be expected to provide various improvements, no specific result is a requirement of the present disclosure unless expressly recited in a particular claim.

[0017] 1-1E, Figures 1 and 1A show an example electronic device 100 (e.g., an integrated circuit or single-element electronic device) packaged in a QFN (quad flat no-lead) structure with a flip-chip attached semiconductor die 102, providing a flip-chip enhanced QFN (FCeQFN) package with an antenna integrated into a multilevel package substrate and encapsulated by an optional epoxy-based package molding compound for millimeter-wavelength or terahertz-band wireless communications. Figures 1B-1D show portions of an example 300 GHz rectangular patch implementation of the antenna structure on the first and second levels of the multilevel package substrate, and Figure 1E shows a partial side view of a system including the electronic device 100 installed on a host system circuit board 140.

[0018] As best shown in FIGS. 1 and 1A, a semiconductor die 102 has conductive terminals 104 and conductive pads 105 coupled to each of the conductive terminals 104. In one example, the conductive pads 105 are or include aluminum. In this or another implementation, the conductive terminals 104 are or include copper. A molded package structure 106 surrounds the semiconductor die 102 and a portion of a multilevel package substrate 108 (FIG. 1A). The conductive pads 105 are mechanically and electrically connected to conductive features of the multilevel package substrate 108 by solder connections to copper metal studs 107, as shown in FIGS. 1A-1D. Some of the conductive pads 105 and conductive terminals 104 provide RF interconnections from the semiconductor die 102 to an integrated antenna in a ground signal ground (GSG) configuration by conductive features (e.g., lines or traces) within the multilevel package substrate 108. This allows RF signals to flow from semiconductor die 102, through conductive terminals 104, conductive pads 105, and studs 107, to an antenna on multi-level package substrate 108. Electronic device 100 provides an integrated antenna-in-package (AiP) or antenna-on-package (AoP) transmission line in a multi-level package substrate solution for a radio frequency (RF) front-end module for wireless applications with an integrated antenna.

[0019] The multilevel package substrate 108 has a generally rectangular shape with a top or first level L1, a second level L2, and a bottom or third level L3, which includes conductive leads 109 that enable the electronic device 100 to be soldered to a host printed circuit board or other host system structure (e.g., the circuit board 140 shown in FIGS. 1A and 1E). In another implementation (not shown), the multilevel package substrate 108 includes more than three levels, with the conductive leads 109 on the final or lowest level. In one example, the electronic device 100 has leads 109 along four sides (e.g., a QFN configuration). Another exemplary electronic device 100 has leads 109 along fewer or more than four sides. The electronic device 100 in one example provides a compact form factor with single-millimeter length and width dimensions along respective orthogonal first and second directions, X and Y.

[0020] The multilevel package substrate 108 includes a conductive metal antenna 110 having a generally rectangular shape that extends to a first level L1 along a top side of the multilevel package substrate 108. As shown in FIG. 1A , the molded package structure 106 covers a portion of the antenna 110, and the molded package structure 106 has a thickness T along a third direction Z above the antenna 110. In one implementation, the conductive features of each of the levels L1-L3 are or include copper, such as electroplated copper that is formed and patterned during fabrication of the multilevel package substrate 108.

[0021] 1A and 1E, levels L1-L3 each include a respective dielectric layer and a respective patterned conductive feature (e.g., patterned copper trace layer and copper via feature) extending in a first, second, and third plane (e.g., XY plane) in a first direction X and a second direction Y, respectively. Layers L1-L3 are stacked along a third direction Z that is orthogonal to the first and second directions X and Y, and a second level L2 extends between the respective first level L1 and third level L3 along the third direction Z.

[0022] The first level L1 has a first dielectric layer 121 (FIGS. 1A-1C and 1E) in a first XY plane and first patterned conductive features including conductive metal (e.g., copper) features of a first metal trace layer M1 (FIGS. 1A-1B) and a first metal via layer V1 (FIGS. 1A-1C). The first level L1 includes an antenna 110 (FIGS. 1-1B) formed as a conductive metal feature of the first metal trace layer M1.

[0023] The second level L2 extends between the first level L1 and the third level L3 along the third direction Z and includes a second dielectric layer 122 (FIGS. 1A, 1D, and 1E) and second patterned conductive features in a second XY plane, including conductive metal features of a second metal trace layer M2 (FIGS. 1A, 1D, and 1E) and a second metal via layer V2 (FIGS. 1A and 1E). The third level L3 includes a third dielectric layer 123 (FIGS. 1A and 1E) and third patterned conductive features in a third XY plane, including conductive features of a third metal trace layer M3 and a third via layer V3.

[0024] 1A, the first metal trace layer M1 and the features of the first metal trace layer M1 have a thickness 124 along the third direction Z (e.g., 10-30 μm with an etch-back dimension of about 0-5 μm, such as about 20 μm), the conductive metal features of the first via layer V1 have a thickness 125 along the third direction Z that is greater than thickness 124 (e.g., about 45 μm), and the first via layer thickness 125 corresponds to the spacing distance along the third direction Z between the first metal layer M1 and the second metal layer M2. The conductive metal features of the second metal trace layer M2 have a thickness 126 along the third direction Z (e.g., 10-30 μm, such as about 20 μm), and the features of the second via layer V2 have a thickness 127 along the third direction Z (e.g., about 45 μm). The conductive metal features of the third metal trace layer M3 have a thickness 128 along the third direction Z (e.g., 25-45 μm, such as about 35 μm), and the features of the third via layer V3 have a thickness 129 along the third direction Z (e.g., about 35 μm) with an etch-back dimension of about 0-10 μm. The studs 107 of the exemplary multi-level package substrate 108 in one example have a thickness along the third direction Z of 15-45 μm, such as about 30 μm.

[0025] The multi-level packaging substrate provides a ground structure 112 that provides a partial cage or shield with an open top on first and second levels L1 and L2 (FIGS. 1A-1D). As best shown in FIGS. 1A and 1B, the ground structure 112 is spaced apart from, laterally surrounds, and lies below the antenna 110. The ground structure 112 includes a ground wall GW that is spaced apart from and surrounds the antenna 110 in a first plane. In the illustrated example, the first via layer V1 includes a first portion of the ground wall GW, and the first trace layer M1 of the first level L1 includes a second portion of the ground wall GW that is spaced apart from and surrounds the antenna 110 in the first plane. In another example (not shown), the ground wall GW is formed entirely within the first via layer V1 of the first level L1. The ground structure 112 also includes a ground plane GP (FIGS. 1A and 1D) of a second trace layer M2 that is connected to the ground plane GP and is spaced apart from and below the antenna 110 by a spacing distance 130 (FIG. 1A) along a third direction Z (which corresponds to the thickness 125 of the first via layer).

[0026] As best shown in FIGS. 1, 1B, and 1C, the antenna 110 includes a generally rectangular main portion and a microstrip feed portion (FIGS. 1 and 1B) with a lateral spacing distance 131 (e.g., about 25 μm) between the antenna 110 and an upper (e.g., second) portion around the ground plane of the ground structure 112. The rectangular patch antenna 110, in one example, has a length 132 (e.g., about 375 μm) along the first direction X. The microstrip feed portion in the illustrated example forms a 50 ohm microstrip feed line having a width 133 along the second direction Y (e.g., about 72 μm) on an exemplary top or first metal layer M1 of about 20 μm thickness (e.g., thickness 124 along the third direction Z in FIG. 1A). Also in this example, the ground plane GP of the second metal layer M2 has a similar thickness (e.g., about 20 μm) and is spaced apart from the antenna 110 along the third direction Z by a spacing distance 130 (e.g., about 45 μm below the patch antenna 110). The rectangular patch antenna 110 and the example shown has a width 134 along the second direction Y (e.g., about 469.2 μm).

[0027] The semiconductor die 102 is attached to a first level L1 of a multi-level package substrate 108 using, for example, flip-chip surface mount technology soldering, and the package structure 106 includes a molding compound that surrounds the semiconductor die 102 and extends to the top side of the antenna 110. The underside of the semiconductor die 102 is spaced apart along a third direction Z by a spacing distance, for example, about 20-200 μm, set by the height of the conductive terminals 104 and the thickness of the studs 107 following flip-chip solder reflow, and the metal studs 107 on the first trace level M1 provide the antenna as well as a ground wall connection from the semiconductor die 102 to the antenna 110.

[0028] The antenna 110 extends to the top level L1 of the multi-level package substrate and is encapsulated by a molded package structure 106. In one example, a ground wall GW below the epoxy molding compound encapsulation of the package structure 106 helps to suppress higher order surface wave modes. The ground structure 112 in this example also extends laterally around the periphery of the antenna 110 to help isolate the antenna 110 from surrounding metal layers, including those of a host printed circuit board (e.g., FIG. 1A), improving directivity and gain in the operation of the antenna 110 for wireless communications.

[0029] The operation of antenna 110 for wireless communication can be facilitated by the dimensional characteristics of the multi-level package substrate and the material and thickness T of molded package structure 106. In one example, semiconductor die 102 is configured to operate antenna 110 at a wavelength λ, and molding compound thickness T along third direction Z (e.g., FIGS. 1A and 1E ) is 0.125λ or greater above antenna 110. In this or another example, molding compound thickness T is approximately 0.25λ. In a further example, molding compound thickness T is λ / 4 + / −30%. In another example, molding compound thickness T is approximately λ / 4 + nλ / 2, where n is a positive integer. As further described below in connection with FIG. 24 , the radiation efficiency of antenna 110 exhibits a maximum at approximately λ / 4 and at further thickness increments of λ / 2 (e.g., λ / 4 + nλ / 2), which can contribute to the radiation efficiency of electronic device 100.

[0030] The material of the molded package structure 106 (e.g., an epoxy-based molding compound) can be selected to improve the wireless communication performance of the underlying antenna 110. For example, the dielectric loss tangent (e.g., tan δ) of the material affects the dissipation of electrical energy provided by the antenna 110 due to different physical processes, such as dielectric relaxation, dielectric resonance, and losses from nonlinear processes. In one example, the loss tangent value of the molding of the package structure 106 compound is less than 0.02. In this example or another example, the loss tangent value of the molding compound is about 0.001 or greater, and about 0.01 or less. In these or the above examples, the maximum value of radiation efficiency at a molding compound thickness T of λ / 4+nλ / 2 may decrease incrementally with increasing values ​​of n, as the influence of the dielectric loss tangent value increases with the thickness T of the package structure 106 on the top side of the antenna 110.

[0031] 1E shows a partial side view of an example system with the illustrated electronic device 100 soldered to a printed circuit board 140. In this example, the top copper layer of the printed circuit board 140 has conductive (e.g., copper) features that can provide a ground plane that subsequently surrounds the electronic device 100, which can help isolate the antenna 110 to improve antenna directivity and gain in the millimeter wavelength or terahertz bands.

[0032] 2-22, FIG. 2 illustrates a method 200 for manufacturing an electronic device, and FIGS. 3-22 illustrate an electronic device 100 undergoing manufacturing processing according to method 200. At 201 in FIG. 2, wafer processing is performed to fabricate semiconductor die 102 including conductive terminals 104 and conductive pads 105, as described above. The fabricated semiconductor die 102, in one example, includes transmitter circuitry (not shown) that provides a radio frequency signal to antenna 110 relative to a ground or reference voltage of ground structure 112 during powered operation of the semiconductor die 102. Wafer-level processing at 201 also includes die singulation or separation (not shown), which separates individual semiconductor die 102 from the processed wafer.

[0033] 2 also includes fabricating a multi-level package substrate 108 and its levels L1-L3 at 202-232, with conductive leads 109 on the third level L3 and a patch antenna 110 on the first level L1. Levels L1-L3 in one example are constructed one at a time, beginning with the deposition of a seed copper layer on a metal carrier at 202. FIG. 3 shows an example in which a chemical vapor deposition process 300 is performed to deposit a copper seed layer 302 on a metal carrier 301. Process 300, in one example, deposits the copper seed layer on both the top and bottom sides of carrier 301 in the orientation shown.

[0034] Method 200 continues with the deposition and patterning of a first plating mask at 204. FIG. 4 shows an example in which a process 400 is performed to deposit and pattern a first plating mask 402 on the copper seed layer 302 on the top side of the carrier 301. Method 200 continues with electroplating of copper features of a first trace layer at 206 of FIG. 2. FIG. 5 shows an example in which an electroplating process 500 is performed to deposit copper in exposed areas of mask 402 to form copper metal trace features of a first trace layer M1 of a first level L1 on exposed portions of the copper seed layer 302 on the top side of the carrier 301, including the antenna 110 and the upper second portion of the ground wall GW. At 208, the first plating mask is removed and a first via plating mask is deposited and patterned. FIG. 6 illustrates an example process 600 for removing the first plating mask, forming and patterning a second plating mask 602, and electroplating to form a first via layer V1.

[0035] At 210, the method 200 continues with seed layer etching and compression molding for the dielectric of the first level L1. FIG. 7 shows an example in which a compression molding process 700 is performed to compression mold a first dielectric layer 121 of electrically insulating material between and over the patterned conductive features M1 and V1 of the first level L1. At 212, a grinding operation is performed and a second copper seed layer is deposited. FIG. 8 shows an example in which a grinding process 800 is performed to grind and planarize the top side of the structure. The grinding process 800 removes the upper portion of the electrically insulating material of the compression molded dielectric to expose the upper portion of the conductive via feature V1 of the first level L1, and the grinding process 800 can be continued to reduce the thickness of the conductive copper and dielectric features of the first level L1 to a desired final thickness along the third direction Z, as shown in FIG. 8. Next, a second copper seed layer 802 is deposited on the planarized top side of the first level L1, as shown in FIG. 8.

[0036] The same or similar sequence of steps and materials can be used to form the deposition and patterning of second and subsequent levels L2 (FIGS. 9-13) and L3 (FIGS. 14-18) of additional plating masks at 214 of FIG. 2. FIG. 9 shows an example in which a process 900 is performed to deposit and pattern a second plating mask 902 on top of the seed layer 802. The method 200 continues at 216 of FIG. 2 by electroplating copper features of a second metal trace layer M2. FIG. 10 shows an example in which an electroplating process 1000 is performed to deposit copper in the exposed areas of the mask 902 to form copper metal trace layer features M2 on the exposed portions of the first level L1. At 218, the second plating mask is removed, then a second via mask is deposited and patterned, and second via copper features are electroplated. FIG. 11 illustrates an example in which a process 1100 is performed to remove plating mask 902, form and pattern plating mask 1102, and electroplate second via layer feature V2 on second level L2.

[0037] The method 200 continues with etching and compacting the remaining portions of the second seed layer at 220 for the second level. FIG. 12 shows an example in which process 1200 is performed to etch the seed layer and compact a second dielectric layer 122 with an electrically insulating material between and over the patterned conductive features M2 and V2 of the second level L2. At 222, a grinding operation is performed and a third copper seed layer is deposited. FIG. 13 shows an example in which a grinding process 1300 is performed to grind and planarize the top side of the structure. The grinding process 1300 removes the upper portion of the compacted dielectric electrically insulating material to expose the upper portion of the conductive via feature V2 of the second level L2, and the grinding process 1300 can be continued to reduce the thickness of the conductive copper and dielectric features of the second level L2 to a desired final thickness along the third direction Z, as shown in FIG. 13. As further shown in FIG. 13, a third copper seed layer 1302 is then deposited on the planarized top side of the second level L2.

[0038] In the four-level example shown, the third level build begins at 224 with the deposition and patterning of a third plating mask on the third seed layer. FIG. 14 shows an example in which a process 1400 is performed to deposit and pattern a third plating mask 1402 on the top side of the second level L2. The method 200 continues at 226 in FIG. 2 by electroplating copper features of the third trace layer. FIG. 15 shows an example in which an electroplating process 1500 is performed to deposit copper in the exposed areas of the mask 1402 to form copper metal trace layer features M3 of the third level L3 on the exposed portions of the second level L2. At 228, the third plating mask is removed, a third via mask is deposited and patterned, and a third via feature is electroplated. FIG. 16 shows an example where process 1600 is performed to remove the third plating mask, deposit and pattern a third via plating mask 1602, and electroplate third via layer feature V3.

[0039] The method 200 continues with the compression molding of the third level L3 at 230. FIG. 17 shows an example in which a compression molding process 1700 is performed to compression mold the third dielectric layer 123 with an electrically insulating material between and over the patterned conductive features of the third level L3. A grinding operation is performed at 232. FIG. 18 shows an example in which a grinding process 1800 is performed to grind and planarize the top side of the structure. The grinding process 1800 removes upper portions of the compression molded dielectric electrically insulating material to expose upper portions of the conductive via feature V3 of the third level L3. The grinding process 1800 can be continued to reduce the thickness of the conductive copper and dielectric features of the third level L3 to a desired final thickness along the third direction Z, as shown in FIG. 18. In an example, further processing (not shown) can be used to form conductive studs 107 on selected portions of the top side of the first level L1, as shown in FIG. 18.

[0040] At 234 in Figure 2, the semiconductor die 102 is attached to the first level L1 of the multilevel packaging substrate 108. Figure 19 shows an example in which a flip-chip die attach process 1900 is performed to mount the semiconductor die 102 onto the multilevel packaging substrate 108. The method also includes a thermal treatment for solder reflow or adhesive curing at 236. Figure 20 shows an example in which a thermal treatment step 2000 is performed to reflow the solder to complete the flip-chip attachment of the semiconductor die 102, soldering the conductive terminals 104 and electrically coupling the conductive terminals to respective conductive pads (e.g., studs 107) on the first level L1 of the multilevel packaging substrate 108.

[0041] Method 200 includes package molding at 238. Figure 21 illustrates an example in which a molding process 2100 is performed to form a molded package structure 106 to a desired thickness T as described above. The molding process 2100 is illustrated in relation to electronic device 100 and uses engineered materials with the attributes described above, as well as a mold constructed to provide the desired final thickness T according to the embodiments described above.

[0042] Method 200 also includes package separation at 240. Figure 22 shows an example in which a sawing or laser cutting process 2200 is performed to separate individual completed packaged electronic devices 100 from the co-processed panel or array structure along lines 2202. Separation process 2200 forms exposed sides of conductive leads 109 along the co-planar sides of each of the completed packaged electronic devices 100.

[0043] 23 and 24 illustrate simulated antenna performance for the electronic device 100 as described above. Graph 2300 in FIG. 23 illustrates simulated reflection coefficient S-parameters and peak gain performance as a function of frequency for the antenna 110 in an example implementation of the electronic device 100 with and without epoxy molding compound encapsulation of the package structure 106 extending over the antenna 110. Graph 2300 includes a curve 2301 of the simulated reflection coefficient parameter |S| for the antenna without the epoxy molding compound encapsulation and having a bandwidth BW of −10 dB at a resonant frequency λ, and a curve 2302 showing the simulated reflection coefficient parameter |S| for the antenna with an epoxy molding compound encapsulation having a thickness T of approximately 100 μm and a bandwidth BW of BW at a corresponding resonant frequency λ using an epoxy molding compound material with dielectric loss tangent parameters Dk=3.5 and Df=0.013. where the dielectric constant Dk (or relative permittivity εr) indicates the ability of a material to store electrical energy, the dielectric loss represents the energy dissipated as heat in a material when subjected to an electric field, and the loss tangent or tangent δ (or dissipation factor Df) is the ratio of the imaginary part of the dielectric constant to the real part. As an example, one suitable overmolding epoxy-based molding compound used in forming a package structure is HDPE (high density polyethylene), which has a reported dielectric constant of 2.36 and a loss tangent of 0.013 at 500 GHz. The use of an epoxy molding compound encapsulation up to a thickness T of λ / 4 provides a significant increase in -10 dB bandwidth, where BW2 is greater than BW1.

[0044] Graph 2300 also illustrates comparative peak gain performance, including curve 2311 of the peak gain performance of the antenna without an epoxy molding compound encapsulation and curve 2312 showing the improved peak gain performance of the antenna with an epoxy molding compound encapsulation with a T of approximately 100 μm. As shown in graph 2300, the peak gain performance at each resonant frequency is higher for antenna 110 with epoxy molding compound encapsulation (curve 2312), and the simulated results correspond to angles Φ that are not fixed at 0°.

[0045] FIG. 24 shows graph 2400 with curves illustrating simulated radiation efficiency as a function of epoxy molding compound encapsulation thickness for various encapsulation materials. Efficiency at 300 GHz vs. package thickness (μm) for different materials. The effect of package encapsulation thickness on radiation efficiency for five EMC materials. Exemplary radiation efficiency curves 2401, 2402, 2403, 2404, and 2405 show improvements for encapsulation thicknesses T greater than zero, including significant improvements when thickness T is 0.125λ or greater across antenna 110. For example, curve 2402 corresponds to the epoxy molding compound material of package structure 106 having Dk=3.5 and Df=0.013. Significant radiation efficiency improvements are observed when molding compound thickness T is approximately 0.25λ. In other examples, significant efficiency improvements are observed when thickness T is λ / 4 + / - 30%, and a local maximum is observed when molding compound thickness T is approximately λ / 4 + nλ / 2, where n is a positive integer. The simulated radiation efficiency of the antenna 110 exhibits a maximum at approximately λ / 4 and at further thickness increments of λ / 2 (e.g., λ / 4 + nλ / 2), which may provide a benefit to the radiation efficiency of the electronic device 100, with a potentially slight reduction in efficiency gain for larger values ​​of n due to the impact of the loss tangent characteristics of the epoxy molding compound of the package structure 106. The illustrated example provides an approximately 18.4% radiation efficiency improvement (e.g., from 60.8% without epoxy encapsulation to 79.2% efficiency with a molded epoxy encapsulation greater than 140 μm thick) when the encapsulation thickness of the package structure 106 above the patch antenna 110 is ∼λ / 4 for EMC material corresponding to curve 2402. In practice, the actual maximum efficiency peak may vary slightly from the expected encapsulation thickness optimization points of λ / 4 and λ / 4 + λ / 2 due to interactions between the dielectric material of the first dielectric layer 121 of the multilevel package substrate 102 and the epoxy molding compound of the package structure 106. Similar beneficial results are expected for different designed operating frequencies and associated wavelengths λ.In a simulated example, the -10 dB |S11| bandwidth of a 300 GHz patch antenna 110 improves by approximately 2.5 GHz, from 5.85 GHz to 8.55 GHz, when encapsulated in a 100 μm (∼λ / 4) thick epoxy molding compound made from a material corresponding to curve 2402 in Figure 24. Also, the peak gain in this example relative to the molding increases across the entire band of operation.

[0046] Modifications may be made to the described examples and other implementations are possible within the scope of the claims.

Claims

1. 1. An electronic device comprising: a multilevel package substrate having a first level, a second level, and a third level, each of the first, second, and third levels including a respective dielectric layer and patterned conductive features, the first, second, and third levels extending in first, second, and third planes in a first direction and an orthogonal second direction, respectively, the second level being between the first and third levels along a third direction orthogonal to the first and second directions, the first level including a first trace layer including an antenna and a first via layer spaced laterally from the antenna and including a portion of a ground wall surrounding the antenna, and the second level including a second trace layer having a ground plane connected to the ground wall; a semiconductor die attached to the first level of the multi-level package substrate; a package structure including a molding compound surrounding the semiconductor die and extending over sides of the antenna; , an electronic device.

2. 2. The electronic device of claim 1, wherein the first trace layer includes a second portion of the ground wall that is laterally spaced from and surrounds the antenna in the first plane.

3. 10. The electronic device of claim 1, wherein the multi-level package substrate includes metal studs on a first trace level for antenna and ground wall connections.

4. 10. The electronic device of claim 1, wherein the multi-level package substrate includes conductive leads on the third level.

5. 10. The electronic device of claim 1, the semiconductor die is configured to operate the antenna at a wavelength λ; the molding compound has a thickness along the third direction above the antenna of 0.125λ or greater.

6. 6. The electronic device of claim 5, wherein the thickness of the molding compound is about 0.25λ.

7. 6. The electronic device of claim 5, wherein the thickness of the molding compound is about λ / 4+nλ / 2, where n is a positive integer.

8. 6. The electronic device of claim 5, wherein the thickness of the molding compound is λ / 4 + / - 30%.

9. 10. The electronic device of claim 1, wherein the molding compound has a loss tangent value of less than 0.

02.

10. 10. The electronic device of claim 9, wherein the molding compound has a loss tangent value of about 0.001 or greater and about 0.01 or less.

11. 1. A system comprising: a circuit board and an electronic device, The electronic device is a multilevel package substrate having a first level, a second level, and a third level, each of the first, second, and third levels including a respective dielectric layer and a respective patterned conductive feature, the first, second, and third levels extending in first, second, and third planes in a first direction and an orthogonal second direction, respectively, the second level being between the first and third levels along a third direction orthogonal to the first and second directions, the first level including a first trace layer including an antenna and a first via layer including a portion of a ground wall spaced laterally from the antenna and surrounding the antenna, the second level including a second trace layer having a ground plane connected to the ground wall, the multilevel package substrate having conductive leads coupled to the circuit board; a semiconductor die attached to the first level of the multi-level package substrate; a package structure including a molding compound surrounding the semiconductor die and extending over sides of the antenna; Including, the system.

12. 12. The system of claim 11, wherein the first trace layer includes a second portion of the ground wall that is laterally spaced from and surrounds the antenna in the first plane.

13. 12. The system of claim 11, the semiconductor die is configured to operate the antenna at a wavelength λ; the molding compound has a thickness along the third direction above the antenna of 0.125λ or greater.

14. 12. The system of claim 11, wherein the molding compound has a loss tangent value of less than 0.

02.

15. 1. A method of manufacturing an electronic device, the method comprising: manufacturing a multi-level package substrate, the multi-level package substrate comprising: forming a first level, a second level, and a third level, the first, second, and third levels each comprising a respective dielectric layer and a respective patterned conductive feature, the second level being between the first level and the third level, the first level comprising a first trace layer comprising an antenna and a first via layer comprising a portion of a ground wall spaced laterally from the antenna and surrounding the antenna, the second level comprising a second trace layer having a ground plane connected to the ground wall; flip-chip attaching a semiconductor die to the first level of the multi-level package substrate; forming a package structure including a molding compound surrounding the die and extending over sides of the antenna; A method comprising:

16. 16. The method of claim 15, wherein the first trace layer includes a second portion of the ground wall that is laterally spaced from and surrounds the antenna.

17. 16. The method of claim 15, the semiconductor die is configured to operate the antenna at a wavelength λ; The method wherein the molding compound has a thickness above the antenna of 0.125λ or greater.

18. 18. The method of claim 17, wherein the molding compound has a thickness of about 0.25λ.

19. 18. The method of claim 17, wherein the molding compound has a thickness of about λ / 4+nλ / 2, where n is a positive integer.

20. 16. The method of claim 15, wherein the molding compound has a loss tangent value of less than 0.02.

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