Package substrate with embedded integrated devices

Abstract

A package comprising a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnections including a first plurality of interconnections, and a first integrated device at least partially disposed within the substrate. The first integrated device is coupled to the first plurality of interconnections via a first plurality of solder interconnections. The second integrated device is coupled to the first plurality of interconnections via a second plurality of solder interconnections.

Description

Technical Field

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[0001] (Cross - Reference to Related Applications) This application claims the priority and benefit of U.S. Non - Provisional Patent Application No. 18 / 190,019, filed with the United States Patent and Trademark Office on March 24, 2023, and the entire content thereof is incorporated herein by reference as if fully set forth below and for all applicable purposes.

[0002] Various features relate to packages including a substrate.

Background Art

[0003] A package may include a substrate and an integrated device. These components, when joined together, can provide a package that can perform various functions. The performance of the package and its components can depend on many factors. There is a current need to provide packages that offer improved performance. Further, there is a current need to include packages with a more compact form factor so that the package can be implemented within a smaller device.

Summary of the Invention

Means for Solving the Problems

[0004] Various features relate to packages including a substrate.

[0005] One example provides a package including a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects including a first plurality of interconnects, and a first integrated device disposed at least partially within the substrate. The first integrated device is coupled to the first plurality of interconnects via a first plurality of solder interconnects. The second integrated device is coupled to the first plurality of interconnects via a second plurality of solder interconnects.

[0006] Another example provides a device comprising a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects including a first plurality of interconnects, and a first integrated device at least partially disposed within the substrate. The first integrated device is coupled to the first plurality of interconnects via a first plurality of solder interconnects. The second integrated device is coupled to the first plurality of interconnects via a second plurality of solder interconnects.

[0007] Another example is a method for manufacturing a substrate, the method comprising the steps of: coupling a first integrated device to a first plurality of interconnections of a carrier via a first plurality of solder interconnections; forming a first dielectric layer on the carrier and the first integrated device, the first dielectric layer sealing the first integrated device, the first plurality of solder interconnections, and the first plurality of interconnections; forming a second dielectric layer on the surface of the first dielectric layer; forming a first plurality of cavities within the second dielectric layer and the first dielectric layer; forming a second plurality of interconnections within at least the first plurality of cavities; forming a third dielectric layer on the second dielectric layer; forming a second plurality of cavities within the third dielectric layer; and forming a third plurality of interconnections within at least the second plurality of cavities.

[0008] Another example is a method for manufacturing a substrate, the method comprising: coupling a first integrated device to a first plurality of interconnects of a carrier via a first plurality of solder interconnects; forming a first underfill between the first integrated device and the carrier, wherein the first underfill laterally surrounds the first plurality of solder interconnects; forming a first dielectric layer on the carrier; forming a second dielectric layer on the surface of the first integrated device and the first dielectric layer; forming a first plurality of cavities within the second dielectric layer and the first dielectric layer; forming a second plurality of interconnects within at least the first plurality of cavities; forming a third dielectric layer on the second dielectric layer; forming a second plurality of cavities within the third dielectric layer; and forming a third plurality of interconnects within at least the second plurality of cavities.

[0009] By reading the "Modes for Carrying Out the Invention" described below in conjunction with the drawings, in which similar reference numerals identify corresponding elements throughout, various features, properties, and advantages may become apparent. [Brief explanation of the drawing]

[0010] [Figure 1] A cross-sectional side view of an exemplary package, including a substrate with an embedded integrated device, is shown. [Figure 2] A cross-sectional side view of an exemplary package, including a substrate with an embedded integrated device, is shown. [Figure 3] A cross-sectional side view of an exemplary package, including a substrate with an embedded integrated device, is shown. [Figure 4] A cross-sectional side view of an exemplary package, including a substrate with an embedded integrated device, is shown. [Figure 5] An exemplary cross-sectional side view of a deep trench capacitor device is shown. [Figure 6A] This shows an exemplary sequence for fabricating a package including a substrate with an embedded integrated device. [Figure 6B] This shows an exemplary sequence for fabricating a package including a substrate with an embedded integrated device. [Figure 6C] This shows an exemplary sequence for fabricating a package including a substrate with an embedded integrated device. [Figure 6D] This shows an exemplary sequence for fabricating a package including a substrate with an embedded integrated device. [Figure 6E] This shows an exemplary sequence for fabricating a package including a substrate with an embedded integrated device. [Figure 7] This diagram illustrates an exemplary flow chart for fabricating a package that includes a substrate with embedded integrated devices. [Figure 8A] This shows an exemplary sequence for fabricating a package including a substrate with an embedded integrated device. [Figure 8B] This shows an exemplary sequence for fabricating a package including a substrate with an embedded integrated device. [Figure 8C] This shows an exemplary sequence for fabricating a package including a substrate with an embedded integrated device. [Figure 8D] This shows an exemplary sequence for fabricating a package including a substrate with an embedded integrated device. [Figure 8E] This shows an exemplary sequence for fabricating a package including a substrate with an embedded integrated device. [Figure 9] This diagram illustrates an exemplary flow chart for fabricating a package that includes a substrate with embedded integrated devices. [Figure 10] This describes various electronic devices that can integrate dies, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages as described herein. [Modes for carrying out the invention]

[0011] In the following description, specific details are set forth in order to provide a thorough understanding of various aspects of the present disclosure. It will be understood by those skilled in the art, however, that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of the present disclosure.

[0012] The present disclosure describes a package including a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects including a first plurality of interconnects, and a first integrated device at least partially disposed within the substrate. The first integrated device is coupled to the first plurality of interconnects via a first plurality of solder interconnects. The second integrated device is coupled to the first plurality of interconnects via a second plurality of solder interconnects. Embedding the integrated device within the substrate enables the integrated device to be brought closer to the second integrated device, thereby reducing the distance that an electrical signal must propagate between the integrated device and the second integrated device. Thus, positioning the integrated device near the second integrated device, and vice versa, may serve to improve the performance of the second integrated device and the package.

[0013] Exemplary Package Comprising a Substrate with an Embedded Integrated Device FIG. 1 shows a package 100 including a substrate with an embedded integrated device. Package 100 includes substrate 102, integrated device 103, and integrated device 105. In some implementations, integrated device 103 may be configured as a deep trench capacitor device. In some implementations, integrated device 103 may be configured as a bridge. In some implementations, integrated device 103 may be replaced by a bridge including a plurality of bridge interconnects.

[0014] The substrate 102 can be a package substrate. The substrate 102 includes a dielectric layer 104, a dielectric layer 106, a dielectric layer 108, a plurality of interconnects 121, a solder resist layer 122, a solder resist layer 124, and a plurality of solder interconnects 120. The plurality of interconnects 121 can include a plurality of interconnects 142, a plurality of interconnects 162, and a plurality of interconnects 182. The dielectric layer 104, the dielectric layer 106, and / or the dielectric layer 108 can include the same material or different materials. For example, the dielectric layer 104, the dielectric layer 106, and / or the dielectric layer 108 can include prepreg, Ajinomoto Build-Up Film (ABF), and / or underfill. In one example, the dielectric layer 108 includes ABF (or does not include glass reinforced resin), the dielectric layer 106 includes ABF or prepreg, and the dielectric layer 104 can include prepreg. <> <>

[0015] <> The dielectric layer 106 is disposed between the dielectric layer 108 and the dielectric layer 104. The dielectric layer 104 is coupled to the dielectric layer 106. The dielectric layer 108 is coupled to the dielectric layer 106. The plurality of interconnects 142 can be disposed at least within the dielectric layer 104. The plurality of interconnects 162 can be disposed at least within the dielectric layer 106 and the dielectric layer 108. In some implementation forms, the plurality of interconnects 162 can extend through at least a part of the dielectric layer 106 and at least a part of the dielectric layer 108. For example, the plurality of interconnects 162 can include vias (e.g., via interconnects) that extend through at least a part of the dielectric layer 106 and at least a part of the dielectric layer 108. The plurality of interconnects 182 can be disposed at least within the dielectric layer 108. The plurality of interconnects 182 is coupled to the plurality of interconnects 162. The plurality of interconnects 162 is coupled to the plurality of interconnects 142. The plurality of solder interconnects 120 is coupled to the substrate 102. For example, the plurality of solder interconnects 120 is coupled to the plurality of interconnects 142. The solder resist layer 122 can be coupled to the dielectric layer 108. The solder resist layer 124 can be coupled to the dielectric layer 104. <> <>

[0016] <> The integrated device 103 is located at least partially inside the substrate 102. The integrated device 103 is surrounded by a dielectric layer 108. The dielectric layer 108 may be in contact with the front side, back side, and / or sides of the integrated device 103. The integrated device 103 may include a plurality of pillar interconnects 132. A plurality of solder interconnects 130 may be coupled to the plurality of pillar interconnects 132. A plurality of interconnects 184 may be coupled to the plurality of solder interconnects 130. A plurality of interconnects 184 may be considered part of a plurality of interconnects 182 and / or a plurality of interconnects 121. The plurality of pillar interconnects 132, a plurality of solder interconnects 130, and a plurality of interconnects 184 may be located in the dielectric layer 108. Therefore, the integrated device 103, the multiple pillar interconnection parts 132, the multiple solder interconnection parts 130, and the multiple interconnection parts 184 can be embedded in the substrate 102.

[0017] The integrated device 105 is coupled to the substrate 102 via a plurality of solder interconnects 150. The integrated device 105 may include a plurality of pillar interconnects 152. The plurality of solder interconnects 150 may be coupled to the plurality of pillar interconnects 152 and the plurality of interconnects 184. The plurality of solder interconnects 150 may be positioned between the plurality of pillar interconnects 152 and the plurality of interconnects 184. The plurality of solder interconnects 130 may be positioned between the plurality of pillar interconnects 132 and the plurality of interconnects 184. An underfill 110 may be positioned between the integrated device 105 and the substrate 102. The underfill 110 may laterally surround the plurality of pillar interconnects 152 and the plurality of solder interconnects 150.

[0018] The front side of the integrated device 105 may face the substrate 102. The front side of the integrated device 105 may face the integrated device 103. The front side of the integrated device 103 may face the integrated device 105.

[0019] In some implementations, the electrical path 170 between integrated device 105 and integrated device 103 may include at least one pillar interconnect from a plurality of pillar interconnects 152, at least one solder interconnect from a plurality of solder interconnects 150, at least one interconnect from a plurality of interconnects 184, at least one solder interconnect from a plurality of solder interconnects 130, and at least one pillar interconnect from a plurality of pillar interconnects 132. The electrical path 170 may be configured to provide an electrical path for power. The electrical path 170 may be configured to provide an electrical path for signals.

[0020] Package 100 can be coupled to a substrate (not shown), such as a printed circuit board, via a plurality of solder interconnects 120. In some mounting configurations, the electrical path 190 between the integrated device 105 and the substrate (not shown) may include at least one pillar interconnect from a plurality of pillar interconnects 152, at least one solder interconnect from a plurality of solder interconnects 150, at least one interconnect from a plurality of interconnects 182, at least one interconnect from a plurality of interconnects 162, at least one interconnect from a plurality of interconnects 142, and at least one solder interconnect from a plurality of solder interconnects 120. The electrical path 190 may be configured to provide an electrical path for power. The electrical path 190 may be configured to provide an electrical path for signals.

[0021] The structure and / or configuration shown in Figure 1 allows the integrated device 103 to be located and / or positioned close to the integrated device 105, reducing the distance over which current must propagate between the integrated device 103 and the integrated device 105, which may lead to an overall improvement in the performance of the integrated device 103, the integrated device 105, and / or the package 100.

[0022] Figure 2 shows a package 200 including a substrate with an embedded integrated device. The package 200 includes a substrate 202, an integrated device 103, and an integrated device 105. In some implementations, the integrated device 103 may be configured as a deep trench capacitor device. In some implementations, the integrated device 103 may be configured as a bridge. In some implementations, the integrated device 103 may be replaced by a bridge including multiple bridge interconnects.

[0023] The substrate 202 may be a package substrate. The substrate 202 includes a dielectric layer 204, a dielectric layer 206, a dielectric layer 208, an underfill 210, a plurality of interconnection parts 221, a solder resist layer 122, a solder resist layer 124, and a plurality of solder interconnection parts 120. The plurality of interconnection parts 221 may include a plurality of interconnection parts 242, a plurality of interconnection parts 262, and a plurality of interconnection parts 282. The dielectric layers 204, 206, and / or 208 may contain the same material or different materials. For example, the dielectric layers 204, 206, and / or 208 may contain prepreg, Ajinomoto build-up film (ABF), and / or underfill. In one example, the dielectric layer 208 may contain ABF or prepreg, the dielectric layer 206 may contain ABF (or not glass-reinforced resin), and the dielectric layer 204 may contain prepreg.

[0024] Dielectric layer 206 is located between dielectric layer 208 and dielectric layer 204. Dielectric layer 204 is coupled to dielectric layer 206. Dielectric layer 208 is coupled to dielectric layer 206. Multiple interconnects 242 may be located in at least dielectric layer 204. Multiple interconnects 262 may be located in at least dielectric layer 206 and dielectric layer 208. In some implementations, multiple interconnects 262 may extend through at least a portion of dielectric layer 206 and at least a portion of dielectric layer 208. For example, multiple interconnects 262 may include vias (e.g., via interconnects) extending through at least a portion of dielectric layer 206 and at least a portion of dielectric layer 208. Multiple interconnects 282 may be located in at least dielectric layer 208. Multiple interconnects 282 are coupled to multiple interconnects 262. Multiple interconnects 262 are coupled to multiple interconnects 242. Multiple solder interconnects 120 are bonded to the substrate 202. For example, multiple solder interconnects 120 are bonded to multiple interconnects 242. The solder resist layer 122 may be bonded to the dielectric layer 208. The solder resist layer 124 may be bonded to the dielectric layer 204.

[0025] The integrated device 103 is located at least partially inside the substrate 202. The integrated device 103 is surrounded by a dielectric layer 206. The dielectric layer 206 may be in contact with the back side of the integrated device and / or the sides of the integrated device 103. The underfill 210 may be in contact with the front side of the integrated device 103. The integrated device 103 may include a plurality of pillar interconnects 132. A plurality of solder interconnects 130 may be coupled to the plurality of pillar interconnects 132. A plurality of interconnects 284 may be coupled to the plurality of solder interconnects 130. A plurality of interconnects 284 may be considered part of a plurality of interconnects 282 and / or a plurality of interconnects 121. The plurality of pillar interconnects 132, the plurality of solder interconnects 130, and the plurality of interconnects 284 may be located in the underfill 210. Therefore, the integrated device 103, the multiple pillar interconnections 132, the multiple solder interconnections 130, and the multiple interconnections 284 can be embedded within the substrate 202.

[0026] The integrated device 105 is coupled to the substrate 202 via a plurality of solder interconnects 150. The integrated device 105 may include a plurality of pillar interconnects 152. The plurality of solder interconnects 150 may be coupled to the plurality of pillar interconnects 152 and the plurality of interconnects 284. The plurality of solder interconnects 150 may be positioned between the plurality of pillar interconnects 152 and the plurality of interconnects 284. The plurality of solder interconnects 130 may be positioned between the plurality of pillar interconnects 132 and the plurality of interconnects 284. An underfill 110 may be positioned between the integrated device 105 and the substrate 202. The underfill 110 may laterally surround the plurality of pillar interconnects 152 and the plurality of solder interconnects 150. The underfill 110 may be coupled to and in contact with the underfill 210 of the substrate 202.

[0027] The front side of the integrated device 105 may face the substrate 202. The front side of the integrated device 105 may face the integrated device 103. The front side of the integrated device 103 may face the integrated device 105.

[0028] In some implementations, the electrical path 270 between integrated device 105 and integrated device 103 may include at least one pillar interconnect from a plurality of pillar interconnects 152, at least one solder interconnect from a plurality of solder interconnects 150, at least one interconnect from a plurality of interconnects 284, at least one solder interconnect from a plurality of solder interconnects 130, and at least one pillar interconnect from a plurality of pillar interconnects 132. The electrical path 270 may be configured to provide an electrical path for power. The electrical path 270 may be configured to provide an electrical path for signals.

[0029] The package 200 may be coupled to a substrate (not shown), such as a printed circuit board, via a plurality of solder interconnects 120. In some mounting configurations, the electrical path 290 between the integrated device 105 and the substrate (not shown) may include at least one pillar interconnect from a plurality of pillar interconnects 152, at least one solder interconnect from a plurality of solder interconnects 150, at least one interconnect from a plurality of interconnects 282, at least one interconnect from a plurality of interconnects 262, at least one interconnect from a plurality of interconnects 242, and at least one solder interconnect from a plurality of solder interconnects 120. The electrical path 290 may be configured to provide an electrical path for power. The electrical path 290 may be configured to provide an electrical path for signals.

[0030] The structure and / or configuration shown in Figure 2 allows the integrated device 103 to be located and / or positioned close to the integrated device 105, reducing the distance over which current must propagate between the integrated device 103 and the integrated device 105, which may lead to an overall improvement in the performance of the integrated device 103, the integrated device 105, and / or the package 100.

[0031] In some implementations, two or more integrated devices may be coupled to a substrate, and / or two or more integrated devices may be embedded within the substrate (e.g., 102, 202). Figures 3 and 4 show examples of multiple integrated devices coupled to a substrate in a package.

[0032] Figure 3 shows a package 300 including a substrate with embedded integrated devices. Package 300 includes a substrate 102, integrated device 103, integrated device 105, and integrated device 305. In some implementations, integrated device 103 may be configured as a deep trench capacitor device. In some implementations, integrated device 103 may be configured as a bridge. In some implementations, integrated device 103 may be replaced by a bridge including multiple bridge interconnects. Package 300 is similar to package 100 in Figure 1. However, package 300 shows two integrated devices coupled to the substrate 102. Integrated device 105 is coupled to the substrate 102, and integrated device 305 is coupled to the substrate 102. Multiple interconnects 184 include multiple interconnects 184a and multiple interconnects 184b. Multiple pillar interconnects 132 include multiple pillar interconnects 132a and multiple pillar interconnects 132b. The multiple solder interconnection parts 130 include multiple solder interconnection parts 130a and multiple solder interconnection parts 130b.

[0033] The integrated device 105 is coupled to the substrate 102 via a plurality of solder interconnects 150. The integrated device 105 may include a plurality of pillar interconnects 152. The plurality of solder interconnects 150 may be coupled to the plurality of pillar interconnects 152 and the plurality of interconnects 184a. The plurality of solder interconnects 150 may be positioned between the plurality of pillar interconnects 152 and the plurality of interconnects 184a. The plurality of solder interconnects 130a may be positioned between the plurality of pillar interconnects 132a and the plurality of interconnects 184a. An underfill 110 may be positioned between the integrated device 105 and the substrate 102. The underfill 110 may laterally surround the plurality of pillar interconnects 152 and the plurality of solder interconnects 150.

[0034] The front side of the integrated device 105 may face the substrate 102. The front side of the integrated device 105 may face the integrated device 103. The front side of the integrated device 103 may face the integrated device 105.

[0035] The integrated device 305 is coupled to the substrate 102 via a plurality of solder interconnects 350. The integrated device 305 may include a plurality of pillar interconnects 352. The plurality of solder interconnects 350 may be coupled to the plurality of pillar interconnects 352 and the plurality of interconnects 184b. The plurality of solder interconnects 350 may be positioned between the plurality of pillar interconnects 352 and the plurality of interconnects 184b. The plurality of solder interconnects 130b may be positioned between the plurality of pillar interconnects 132b and the plurality of interconnects 184b. An underfill 110 may be positioned between the integrated device 305 and the substrate 102. The underfill 110 may laterally surround the plurality of pillar interconnects 352 and the plurality of solder interconnects 350.

[0036] The front side of the integrated device 305 may face the substrate 102. The front side of the integrated device 305 may face the integrated device 103. The front side of the integrated device 103 may face the integrated device 305.

[0037] In some implementation configurations, the electrical path between the integrated device 105 and the integrated device 103 may include at least one pillar interconnect from a plurality of pillar interconnects 152, at least one solder interconnect from a plurality of solder interconnects 150, at least one interconnect from a plurality of interconnects 184a, at least one solder interconnect from a plurality of solder interconnects 130a, and at least one pillar interconnect from a plurality of pillar interconnects 132a.

[0038] In some implementations, the electrical path between the integrated device 305 and the integrated device 103 may include at least one pillar interconnect from a plurality of pillar interconnects 352, at least one solder interconnect from a plurality of solder interconnects 350, at least one interconnect from a plurality of interconnects 184b, at least one solder interconnect from a plurality of solder interconnects 130b, and at least one pillar interconnect from a plurality of pillar interconnects 132b.

[0039] In some implementation configurations, the electrical path 370 between the integrated device 305 and the integrated device 105 may include at least one pillar interconnect from a plurality of pillar interconnects 352, at least one solder interconnect from a plurality of solder interconnects 350, at least one interconnect from a plurality of interconnects 184b, at least one solder interconnect from a plurality of solder interconnects 130b, at least one pillar interconnect from a plurality of pillar interconnects 132b, the integrated device 103, at least one pillar interconnect from a plurality of pillar interconnects 132a, at least one solder interconnect from a plurality of solder interconnects 130a, at least one interconnect from a plurality of interconnects 184a, at least one solder interconnect from a plurality of solder interconnects 150, and at least one pillar interconnect from a plurality of pillar interconnects 152. The electrical path 370 may be configured to provide an electrical path for signals (e.g., input / output signals) between the integrated device 305 and the integrated device 105.

[0040] In some implementations, the electrical path between integrated device 305 and integrated device 105 may include at least one pillar interconnect from a plurality of pillar interconnects 352, at least one solder interconnect from a plurality of solder interconnects 350, at least one interconnect from a plurality of interconnects 184, at least one solder interconnect from a plurality of solder interconnects 150, and at least one pillar interconnect from a plurality of pillar interconnects 152. Therefore, current and / or signals between integrated device 305 and integrated device 105 may bypass integrated device 103.

[0041] Figure 4 shows a package 400 including a substrate with embedded integrated devices. Package 400 includes a substrate 202, integrated devices 103, 105, and 305. In some configurations, integrated device 103 may be configured as a deep trench capacitor device. In some configurations, integrated device 103 may be configured as a bridge. In some configurations, integrated device 103 may be replaced by a bridge including multiple bridge interconnects. The bridge may include a die substrate. The multiple bridge interconnects may be formed on the surface of the die substrate. Package 400 is similar to package 200 in Figure 2. However, package 400 shows two integrated devices coupled to the substrate 202. Integrated device 105 is coupled to the substrate 202, and integrated device 305 is coupled to the substrate 202. The multiple interconnects 284 include multiple interconnects 284a and multiple interconnects 284b. The multiple pillar interconnection parts 132 include multiple pillar interconnection parts 132a and multiple pillar interconnection parts 132b. The multiple solder interconnection parts 130 include multiple solder interconnection parts 130a and multiple solder interconnection parts 130b.

[0042] The integrated device 105 is coupled to the substrate 202 via a plurality of solder interconnects 150. The integrated device 105 may include a plurality of pillar interconnects 152. The plurality of solder interconnects 150 may be coupled to the plurality of pillar interconnects 152 and the plurality of interconnects 284. The plurality of solder interconnects 150 may be positioned between the plurality of pillar interconnects 152 and the plurality of interconnects 284. The plurality of solder interconnects 130 may be positioned between the plurality of pillar interconnects 132 and the plurality of interconnects 284. An underfill 110 may be positioned between the integrated device 105 and the substrate 202. The underfill 110 may laterally surround the plurality of pillar interconnects 152 and the plurality of solder interconnects 150.

[0043] The front side of the integrated device 105 may face the substrate 202. The front side of the integrated device 105 may face the integrated device 103. The front side of the integrated device 103 may face the integrated device 105.

[0044] The integrated device 305 is coupled to the substrate 202 via a plurality of solder interconnects 350. The integrated device 305 may include a plurality of pillar interconnects 352. The plurality of solder interconnects 350 may be coupled to the plurality of pillar interconnects 352 and the plurality of interconnects 284. The plurality of solder interconnects 350 may be positioned between the plurality of pillar interconnects 352 and the plurality of interconnects 284. The plurality of solder interconnects 130 may be positioned between the plurality of pillar interconnects 132 and the plurality of interconnects 284. An underfill 110 may be positioned between the integrated device 305 and the substrate 202. The underfill 110 may laterally surround the plurality of pillar interconnects 352 and the plurality of solder interconnects 350.

[0045] The front side of the integrated device 305 may face the substrate 202. The front side of the integrated device 305 may face the integrated device 103. The front side of the integrated device 103 may face the integrated device 305.

[0046] In some implementation configurations, the electrical path between the integrated device 105 and the integrated device 103 may include at least one pillar interconnect from a plurality of pillar interconnects 152, at least one solder interconnect from a plurality of solder interconnects 150, at least one interconnect from a plurality of interconnects 284, at least one solder interconnect from a plurality of solder interconnects 130, and at least one pillar interconnect from a plurality of pillar interconnects 132.

[0047] In some implementations, the electrical path between the integrated device 305 and the integrated device 103 may include at least one pillar interconnect from a plurality of pillar interconnects 352, at least one solder interconnect from a plurality of solder interconnects 350, at least one interconnect from a plurality of interconnects 284, at least one solder interconnect from a plurality of solder interconnects 130, and at least one pillar interconnect from a plurality of pillar interconnects 132.

[0048] In some implementation configurations, the electrical path 470 between the integrated device 305 and the integrated device 105 may include at least one pillar interconnect from a plurality of pillar interconnects 352, at least one solder interconnect from a plurality of solder interconnects 350, at least one interconnect from a plurality of interconnects 284b, at least one solder interconnect from a plurality of solder interconnects 130b, at least one pillar interconnect from a plurality of pillar interconnects 132b, the integrated device 103, at least one pillar interconnect from a plurality of pillar interconnects 132a, at least one solder interconnect from a plurality of solder interconnects 130a, at least one interconnect from a plurality of interconnects 284a, at least one solder interconnect from a plurality of solder interconnects 150, and at least one pillar interconnect from a plurality of pillar interconnects 152. The electrical path 470 may be configured to provide an electrical path for signals (e.g., input / output signals) between the integrated device 305 and the integrated device 105.

[0049] In some implementations, the electrical path between integrated device 305 and integrated device 105 may include at least one pillar interconnect from a plurality of pillar interconnects 352, at least one solder interconnect from a plurality of solder interconnects 350, at least one interconnect from a plurality of interconnects 284, at least one solder interconnect from a plurality of solder interconnects 150, and at least one pillar interconnect from a plurality of pillar interconnects 152. Therefore, current and / or signals between integrated device 305 and integrated device 105 may bypass integrated device 103.

[0050] In some implementations, integrated device 103, integrated device 105, and / or integrated device 305 may be chiplets. For example, in some implementations, integrated device 103 may be a first chiplet, integrated device 105 may be a second chiplet, and integrated device 305 may be a third chiplet. In some implementations, one or more of the integrated devices described herein may be fabricated using the same technology node or two or more different technology nodes. For example, a chiplet (e.g., 105) may be fabricated using a first technology node, and another chiplet (e.g., 305) may be fabricated using a second technology node that is less advanced than the first technology node. In such an example, a chiplet (e.g., 105) may include components having a first minimum size (e.g., interconnects, transistors), and the other chiplet (e.g., 305) may include components having a second minimum size (e.g., interconnects, transistors), where the second minimum size is larger than the first minimum size. In some implementations, the package's integrated device 105 and integrated device 305 may be fabricated using the same technology node or different technology nodes. In some implementations, the package's chiplet (e.g., 103) and other chiplets (e.g., 105, 305) may be fabricated using the same technology node or different technology nodes.

[0051] As another example, in some implementations, the integrated device 105 may be a first chiplet, and the integrated device 305 may be a second chiplet. The integrated device 105 may be configured to perform a first set of functions and / or operations. The integrated device 305 may be configured to perform a second set of functions and / or operations. The second set of functions and / or operations includes at least one function and / or operation that is different from the first set of functions and / or operations. In some implementations, the integrated device 105 may be fabricated using a first technology node, and the integrated device 305 may be fabricated using a second technology node that is less advanced than the first technology node. In some implementations, the integrated device 103 may be fabricated using a third technology node that is different from the first and / or second technology nodes.

[0052] As described above, in some implementations, the integrated device 103 may be configured as a deep trench capacitor. Figure 5 shows a cross-sectional side view of the integrated device 500 configured as a trench capacitor device. The integrated device 500 may be an integrated passive device containing multiple trench capacitors (e.g., deep trench capacitors). The integrated device 500 may be a means for trench capacitance. The integrated device 500 may represent the integrated device 103. The integrated device 500 includes a front side and a back side. The front side of the integrated device 500 may contain multiple trench capacitors.

[0053] The integrated device 500 includes a die substrate 502 and a plurality of trench capacitors 505. A plurality of solder interconnects (not shown) may be coupled to the integrated device 500. The die substrate 502 may include silicon (Si). The die substrate 502 may include a plurality of trenches and / or cavities on which capacitors may be formed.

[0054] Multiple trench capacitors 505 include trench capacitors 505a and trench capacitors 505b. Trench capacitors 505a and trench capacitors 505b may be configured to be part of the same capacitor (e.g., a first capacitor, a first trench capacitor). Trench capacitors 505a and trench capacitors 505b may be configured to be coupled to and / or part of a first power distribution network (PDN). Trench capacitors 505a and trench capacitors 505b may be configured to be part of a first electrical path for first power for a package. Trench capacitors 505a and trench capacitors 505b may be configured to be coupled to one or more integrated devices.

[0055] As shown in Figure 5, the integrated device 500 includes a die substrate 502, an oxide layer 504, a first conductive layer 506, a dielectric layer 508, and a second conductive layer 510. The first conductive layer 506 and / or the second conductive layer 510 may contain polysilicon. The oxide layer 504 and / or the dielectric layer 508 may contain SiO2 (e.g., low-pressure chemical vapor deposition (LPCVD) SiO2) or Si3N4 (e.g., LPCVD Si3N4). Parts of the oxide layer 504, the first conductive layer 506, the dielectric layer 508, and the second conductive layer 510 may be located in trenches and / or cavities of the die substrate 502. Note that the die substrate 502 may be considered to have trenches or cavities even if the trenches or cavities are filled with one or more materials.

[0056] A trench capacitor 505a (e.g., a first trench capacitor, a first capacitor, a means for a first trench capacitance) may be defined by (i) a first portion of an oxide layer 504, (ii) a first portion of a first conductive layer 506, (iii) a first portion of a dielectric layer 508, and (iv) a first portion of a second conductive layer 510, which are located within a trench (e.g., a first trench) of a die substrate 502.

[0057] Trench capacitor 505b (e.g., second trench capacitor, second capacitor, means for second trench capacitance) may be defined by (i) a second portion of oxide layer 504, (ii) a second portion of first conductive layer 506, (iii) a second portion of dielectric layer 508, and (iv) a second portion of second conductive layer 510, which are located in a trench (e.g., second trench) of die substrate 502. It should be noted that trench capacitor 505b may be part of the same capacitor as trench capacitor 505a. That is, trench capacitor 505a and trench capacitor 505b may be configured to be electrically coupled together to form a capacitor with a larger capacitance (e.g., first capacitor).

[0058] The integrated device 500 may also include interconnects 509, 592, and 594. Interconnection 509 is coupled to interconnects 592 and 594. Interconnection 509 may be a through-substrate via extending through the die substrate 502. Interconnection 592 may be a pad interconnect. Interconnection 594 may be a pad interconnect. Interconnection 592 may be located on the front side of the integrated device 500. Interconnection 592 may be located on the back side of the integrated device 500. Interconnection 509 may be a through-die substrate interconnect. The integrated device may include at least one through-die substrate interconnect.

[0059] Integrated devices (e.g., 103, 105, 305) may include dies (e.g., bare semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory, power management processors, and / or combinations thereof. Integrated devices (e.g., 103, 105, 305) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Integrated devices may include transistors. An integrated device can be an example of an electrical component and / or electrical device. In some implementations, an integrated device may be a chiplet. Chiplets may be manufactured using processes that yield better results compared to other processes used to manufacture other types of integrated devices, thereby reducing the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect density (e.g., interconnects with different widths and / or spacing). In some implementations, several chiplets may be used to perform the functions of one or more chips (e.g., another integrated device). Therefore, for example, a single integrated device may be divided into several chiplets.As described above, using several chiplets that perform several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some embodiments, one or more of the chiplets and / or one or more of the integrated devices (e.g., 103) described herein may be fabricated using the same technology node or two or more different technology nodes. For example, an integrated device may be fabricated using a first technology node, and a chiplet may be fabricated using a second technology node that is less advanced than the first technology node. In such an example, the integrated device may include components having a first minimum size (e.g., interconnects, transistors), and the chiplet may include components having a second minimum size (e.g., interconnects, transistors), where the second minimum size is larger than the first minimum size. In some implementations, one integrated device and another integrated device in the package may be fabricated using the same technology node or different technology nodes. In some implementations, one chiplet and another chiplet in the package may be fabricated using the same technology node or different technology nodes.

[0060] A technology node can refer to a specific fabrication process and / or technology used to fabricate an integrated device and / or chiplet. A technology node can specify the minimum possible size that can be fabricated (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. A technology node that produces components with finer details (e.g., traces, transistors) may be more expensive and have a higher yield loss than a technology node that produces components with less fine details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and have a higher yield loss than less advanced technology nodes. If all the functionality of a package is implemented within a single integrated device, the entire integrated device will be fabricated using the same technology node, even if some of the functionality of the integrated device does not need to be fabricated using that particular technology node. Therefore, an integrated device is locked into one technology node. To optimize the cost of the package, some of the functions can be implemented in different integrated devices and / or chiplets, and different integrated devices and / or chiplets can be fabricated using different technology nodes to reduce the overall cost. For example, functions that require the use of a state-of-the-art technology node can be implemented in an integrated device, while functions that can be implemented using a less advanced technology node can be implemented in a different integrated device and / or one or more chiplets. One example is an integrated device fabricated using a first technology node (e.g., a state-of-the-art technology node) configured to provide a computing application, and at least one chiplet fabricated using a second technology node configured to provide other functions, where the second technology node is not as expensive as the first technology node, and the second technology node fabricates components with a minimum size greater than the minimum size of components fabricated using the first technology node.Examples of computing applications may include high-performance computing and / or high-performance processing, which can be achieved by fabricating and packing as many transistors as possible in an integrated device, while integrated devices configured for computing applications may be fabricated using the most advanced technology nodes available, while other chiplets may be fabricated using less advanced technology nodes because these chiplets may not require as many transistors to be fabricated in the chiplet. Therefore, the combination of using different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0061] Another advantage of splitting functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without the need to redesign any single integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet the same. Thus, the first chiplet can be reused with an improved and / or different configuration of the first integrated device. This saves costs by eliminating the need to redesign the first chiplet when a package with an improved integrated device is manufactured.

[0062] Exemplary sequence for fabricating a package with a substrate containing an embedded integrated device. In some implementations, creating a package involves several processes. Figures 6A–6E show exemplary sequences for providing or creating a package. In some implementations, the sequences in Figures 6A–6E may be used to provide or create package 100. However, the processes in Figures 6A–6E may be used to create other packages described in this disclosure.

[0063] It should be noted that the sequences in Figures 6A to 6E may be combinations of one or more steps to simplify and / or clarify the sequence for providing or producing a package. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure.

[0064] As shown in Figure 6A, Stage 1 shows the state after the carrier 600 and seed layer 602 have been provided. The seed layer 602 may be placed on the surface of the carrier 600. The seed layer 602 may include a copper layer.

[0065] Stage 2 shows the state after the multiple interconnections 182 have been formed on the carrier 600. The step of forming the multiple interconnections 182 may include the step of forming the multiple interconnections 184. The seed layer 602 may be part of the multiple interconnections 182 and / or the multiple interconnections 184. Masking processes, plating processes, and / or etching processes may be used to form the multiple interconnections 182 and / or the multiple interconnections 184.

[0066] Stage 3 shows the state after the integrated device 103 has been coupled to a plurality of interconnects 184. The integrated device 103 may include a plurality of pillar interconnects 132. The integrated device 103 is coupled to the plurality of interconnects 184 via a plurality of solder interconnects 130. A solder reflow process may be used to couple the integrated device 103 to the plurality of interconnects 184. The plurality of solder interconnects 130 may be coupled to the plurality of pillar interconnects 132 and the plurality of interconnects 184. In some implementations, the integrated device 103 may be configured as a deep trench capacitor. In some implementations, the integrated device 103 may be configured as a bridge. In some implementations, the plurality of pillar interconnects 132 may be optional. In such cases, the plurality of solder interconnects 130 may be coupled to other interconnects of the integrated device 103.

[0067] Stage 4 shows the state after the dielectric layer 108 has been provided. The dielectric layer 108 may be formed on the carrier 600 and the integrated device 103. A vacuum lamination process may be used to form the dielectric layer 108. The dielectric layer 108 may seal the integrated device 103, a plurality of interconnects 182, a plurality of interconnects 184, a plurality of solder interconnects 130, and a plurality of pillar interconnects 132. The dielectric layer 108 may contain ABF (or not contain glass-reinforced resin). The dielectric layer 108 may be the first dielectric layer.

[0068] Stage 5 shows the state after a dielectric layer 106 has been formed on the surface of the dielectric layer 108, as shown in Figure 6B. A deposition process and / or a lamination process may be used to form the dielectric layer 106. In some configurations, the dielectric layer 106 may contain the same material as the dielectric layer 108 or a different material. The dielectric layer 106 is provided such that it has a relatively flat surface. The dielectric layer 106 may be a second dielectric layer. The dielectric layer 106 may include ABF or prepreg.

[0069] Stage 6 shows the state after multiple cavities 662 have been formed within dielectric layers 106 and 108. The multiple cavities 662 may be formed using an etching process (e.g., a photoetching process) and / or a laser process. Masking processes, exposure processes, and / or development processes may be used to form the multiple cavities 662.

[0070] Step 7 shows the state after a plurality of interconnections 162 have been formed within and on the surface of the dielectric layer 106 and / or dielectric layer 108. The plurality of interconnections 162 may be coupled to a plurality of interconnections 182. Masking processes, plating processes, and / or etching processes may be used to form the plurality of interconnections 162.

[0071] Step 8 shows the state after the dielectric layer 104 has been formed on the surface of the dielectric layer 106, as shown in Figure 6C. A deposition process and / or a lamination process may be used to form the dielectric layer 104. In some configurations, the dielectric layer 104 may contain the same material as or a different material from the dielectric layer 108 and / or the dielectric layer 106. The dielectric layer 104 is provided such that the dielectric layer 104 has a relatively flat surface. The dielectric layer 104 may be a third dielectric layer. The dielectric layer 104 may include a prepreg.

[0072] Stage 9 shows the state after multiple cavities 642 have been formed within the dielectric layer 104. The multiple cavities 642 may be formed using an etching process (e.g., a photoetching process) and / or a laser process. Masking processes, exposure processes, and / or development processes may be used to form the multiple cavities 642.

[0073] Step 10 shows the state after multiple interconnections 142 have been formed within and on the surface of the dielectric layer 104. The multiple interconnections 142 can be coupled to multiple interconnections 162. Masking processes, plating processes, and / or etching processes may be used to form the multiple interconnections 142.

[0074] As shown in Figure 6D, step 11 shows the state after the carrier 600 has been disconnected. The carrier 600 may be separated from the dielectric layer 108. In some implementations, at least a portion of the seed layer 602 may be removed and / or separated.

[0075] Step 12 shows the state after the solder resist layers 122 and 124 have been formed. The solder resist layer 122 may be formed on (e.g., above) the dielectric layer 108. The solder resist layer 122 may include openings that expose portions of a plurality of interconnects 182 and / or a plurality of interconnects 184. The solder resist layer 124 may be formed on (e.g., below) the dielectric layer 104. The solder resist layer 124 may include openings that expose portions of a plurality of interconnects 142. Deposition, lamination, masking, exposure, and / or development processes may be used to form the solder resist layers and the openings in the solder resist layers. Steps 1 to 12 may show a sequence for fabricating a substrate (e.g., 102). Once the substrate is fabricated, an assembly process may be used to combine the substrate into one or more integrated devices to form a package. The assembly process for forming the package may be performed by a different factory than the one that fabricated the substrate, or by the same factory that fabricated the substrate.

[0076] Step 13 shows the state after the integrated device 105 has been coupled to the plurality of interconnects 184. The integrated device 105 may include a plurality of pillar interconnects 152. The integrated device 105 is coupled to the plurality of interconnects 184 via a plurality of solder interconnects 150. A solder reflow process may be used to couple the integrated device 105 to the plurality of interconnects 184. The plurality of solder interconnects 150 may be coupled to the plurality of pillar interconnects 152 and the plurality of interconnects 184.

[0077] Step 14 shows the state after the underfill 110 has been provided between the integrated device 105 and the substrate 102, as shown in Figure 6E. The underfill 110 can be formed and / or provided using a deposition process and / or an injection process.

[0078] Stage 15 shows the state after the multiple solder interconnects 120 have been bonded to the substrate 102. A solder reflow process may be used to form and bond the multiple solder interconnects 120. The multiple solder interconnects 120 may be bonded to multiple interconnects 142. Stage 15 may show the package 100.

[0079] Exemplary flowchart of a method for fabricating a package with a substrate containing embedded integrated devices. In some implementations, creating a package involves several processes. Figure 7 shows an exemplary flowchart of a method 700 for providing or creating a package. In some implementations, the method 700 in Figure 7 can be used to provide or create any of the packages in Figures 1 to 4. Figure 7 illustrates the creation of package 100. However, Figure 7 can be used to create any package.

[0080] It should be noted that Method 700 in Figure 7 may combine one or more processes to simplify and / or clarify the method for providing or creating a package. In some implementations, the order of the processes may be changed or modified.

[0081] This method involves providing a carrier having a seed layer (at 705). Step 1 in Figure 6A illustrates and explains an example of a provided carrier 600 and seed layer 602. The seed layer 602 may be placed on the surface of the carrier 600. The seed layer 602 may include a copper layer.

[0082] This method forms interconnects on the carrier and seed layer (at 710). Step 2 in Figure 6A illustrates an example of multiple interconnects 182 formed on the carrier 600. The step of forming multiple interconnects 182 may include the step of forming multiple interconnects 184. The seed layer 602 may be part of the multiple interconnects 182 and / or multiple interconnects 184. Masking processes, plating processes, and / or etching processes may be used to form the multiple interconnects 182 and / or multiple interconnects 184.

[0083] This method connects an integrated device (in 715) to multiple interconnects. Step 3 in Figure 6A illustrates an example of an integrated device 103 connected to multiple interconnects 184. The integrated device 103 may include multiple pillar interconnects 132. The integrated device 103 is connected to the multiple interconnects 184 via multiple solder interconnects 130. A solder reflow process may be used to connect the integrated device 103 to the multiple interconnects 184. The multiple solder interconnects 130 may be connected to the multiple pillar interconnects 132 and the multiple interconnects 184. In some implementations, the integrated device 103 may be configured as a deep trench capacitor. In some implementations, the integrated device 103 may be configured as a bridge. In some implementations, the multiple pillar interconnects 132 may be optional. In such cases, the multiple solder interconnects 130 may be connected to other interconnects of the integrated device 103.

[0084] This method forms a first dielectric layer (at 720). Step 4 in Figure 6A illustrates an example of a provided dielectric layer 108. The dielectric layer 108 may be formed on the carrier 600 and the integrated device 103. A vacuum lamination process may be used to form the dielectric layer 108. The dielectric layer 108 may seal the integrated device 103, a plurality of interconnects 182, a plurality of interconnects 184, a plurality of solder interconnects 130, and a plurality of pillar interconnects 132. The dielectric layer 108 may contain ABF (or not contain glass-reinforced resin). The dielectric layer 108 may be the first dielectric layer.

[0085] This method forms a second dielectric layer (at 725). Step 5 in Figure 6B illustrates an example of a dielectric layer 106 formed on the surface of dielectric layer 108. A deposition process and / or a lamination process may be used to form the dielectric layer 106. In some configurations, the dielectric layer 106 may contain the same material as the dielectric layer 108 or a different material. The dielectric layer 106 is provided such that it has a relatively flat surface. The dielectric layer 106 may be a second dielectric layer. The dielectric layer 106 may include ABF or a prepreg. The step of forming the first and / or second dielectric layers may include the step of forming cavities within the dielectric layer(s). Step 6 in Figure 6B illustrates a plurality of cavities 662 formed within dielectric layer 106 and dielectric layer 108. The plurality of cavities 662 may be formed using an etching process (e.g., a photoetching process) and / or a laser process. A masking process, an exposure process, and / or a development process may be used to form multiple cavities 662.

[0086] This method forms interconnections in the dielectric layer (at 730). Step 7 in Figure 6B illustrates an example of multiple interconnections 162 formed within and on the surface of dielectric layers 106 and 108. Multiple interconnections 162 can be coupled to multiple interconnections 182. Masking, plating, and / or etching processes may be used to form the multiple interconnections 162.

[0087] This method forms a third dielectric layer (at 735). Step 8 in Figure 6C illustrates an example of a dielectric layer 104 formed on the surface of dielectric layer 106. A deposition process and / or a lamination process may be used to form the dielectric layer 104. In some configurations, the dielectric layer 104 may contain the same material as or a different material from dielectric layer 108 and / or dielectric layer 106. The dielectric layer 104 is provided such that the dielectric layer 104 has a relatively flat surface. The dielectric layer 104 may be a third dielectric layer. The dielectric layer 104 may include a prepreg. In some configurations, the step of forming the dielectric layer may include the step of forming cavities within the dielectric layer. Step 9 in Figure 6C illustrates an example of multiple cavities 642 formed within the dielectric layer 104. The multiple cavities 642 may be formed using an etching process (e.g., a photoetching process) and / or a laser process. A masking process, an exposure process, and / or a development process may be used to form multiple cavities 642.

[0088] This method forms interconnections in the third dielectric layer (at 740). Step 10 in Figure 10C illustrates an example of multiple interconnections 142 formed within and on the surface of the dielectric layer 104. The multiple interconnections 142 may be coupled to multiple interconnections 162. Masking, plating, and / or etching processes may be used to form the multiple interconnections 142.

[0089] This method involves decoupling carriers (at 745) and forming a solder resist layer (at 745). Step 11 in Figure 6D illustrates an example of decoupled carriers 600. The carriers 600 may be separated from the dielectric layer 108. In some configurations, at least a portion of the seed layer 602 may be removed and / or separated. Step 12 in Figure 6D illustrates an example of the formation of solder resist layers 122 and 124. The solder resist layer 122 may be formed on (e.g., above) the dielectric layer 108. The solder resist layer 122 may include openings that expose portions of a plurality of interconnects 182 and / or a plurality of interconnects 184. The solder resist layer 124 may be formed on (e.g., below) the dielectric layer 104. The solder resist layer 124 may include openings that expose portions of a plurality of interconnects 142. Deposition, lamination, masking, exposure, and / or development processes may be used to form the solder resist layer and the openings in the solder resist layer. Steps 1 to 12 may represent a sequence for fabricating a substrate (e.g., 102). Once the substrate is fabricated, an assembly process may be used to combine the substrate into one or more integrated devices to form a package. The assembly process for forming the package may be performed by a different factory than the one that fabricated the substrate, or by the same factory that fabricated the substrate.

[0090] This method involves bonding a second integrated device to a substrate (in 750). Step 13 in Figure 6D illustrates an example of an integrated device 105 bonded to a plurality of interconnects 184. The integrated device 105 may include a plurality of pillar interconnects 152. The integrated device 105 is bonded to the plurality of interconnects 184 via a plurality of solder interconnects 150. A solder reflow process may be used to bond the integrated device 105 to the plurality of interconnects 184. The plurality of solder interconnects 150 may be bonded to the plurality of pillar interconnects 152 and the plurality of interconnects 184. This method also allows for the provision of underfill between the second integrated device and the substrate (in 750). Step 14 in Figure 6E illustrates an example of underfill 110 provided between the integrated device 105 and the substrate 102. The underfill 110 may be formed and / or provided using a deposition process and / or an injection process.

[0091] This method involves bonding solder interconnects to a substrate (at 755). Step 15 in Figure 6E illustrates an example of multiple solder interconnects 120 bonded to a substrate 102. A solder reflow process may be used to form and bond the multiple solder interconnects 120. The multiple solder interconnects 120 may be bonded to multiple interconnects 142. Step 15 may show a package 100.

[0092] Exemplary sequence for fabricating a package with a substrate containing an embedded integrated device. In some implementations, creating a package involves several processes. Figures 8A–8E show exemplary sequences for providing or creating a package. In some implementations, the sequences in Figures 8A–8E may be used to provide or create package 200. However, the processes in Figures 8A–8E may be used to create other packages described in this disclosure.

[0093] It should be noted that the sequences in Figures 8A to 8E may be combinations of one or more steps to simplify and / or clarify the sequence for providing or producing a package. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure.

[0094] As shown in Figure 8A, Stage 1 shows the state after the carrier 800 and seed layer 802 have been provided. The seed layer 802 may be placed on the surface of the carrier 800. The seed layer 802 may include a copper layer.

[0095] Stage 2 shows the state after multiple interconnections 282 have been formed on the carrier 800. The step of forming multiple interconnections 282 may include the step of forming multiple interconnections 284. The seed layer 802 may be part of the multiple interconnections 282 and / or multiple interconnections 284. Masking processes, plating processes, and / or etching processes may be used to form the multiple interconnections 282 and / or multiple interconnections 284.

[0096] Stage 3 shows the state after the integrated device 103 has been coupled to the multiple interconnects 284. The integrated device 103 may include multiple pillar interconnects 132. The integrated device 103 is coupled to the multiple interconnects 284 via multiple solder interconnects 130. A solder reflow process may be used to couple the integrated device 103 to the multiple interconnects 284. The multiple solder interconnects 130 may be coupled to the multiple pillar interconnects 132 and the multiple interconnects 284. In some implementations, the integrated device 103 may be configured as a deep trench capacitor. In some implementations, the integrated device 103 may be configured as a bridge. In some implementations, the multiple pillar interconnects 132 may be optional. In such cases, the multiple solder interconnects 130 may be coupled to other interconnects of the integrated device 103. Stage 3 also shows the underfill 210 provided between the integrated device 103 and the carrier 800. The underfill 210 can be formed and / or provided using a deposition process and / or an injection process.

[0097] Stage 4 shows the state after the dielectric layer 208 has been provided. The dielectric layer 208 may be formed on the carrier 800. The dielectric layer 208 may be arranged laterally around the integrated device 103 and the underfill 210. A lamination process may be used to form the dielectric layer 208. The dielectric layer 208 may include a prepreg or ABF. The dielectric layer 208 may be the first dielectric layer.

[0098] Stage 5 shows the state after the dielectric layer 206 has been formed on the dielectric layer 208 and the surface of the integrated device 103, as shown in Figure 8B. The dielectric layer 206 may be bonded to and in contact with the back side of the integrated device 103. A deposition process and / or a lamination process may be used to form the dielectric layer 206. In some configurations, the dielectric layer 206 may contain the same material as the dielectric layer 208 or a different material. The dielectric layer 206 is provided such that it has a relatively flat surface. The dielectric layer 206 may be a second dielectric layer. The dielectric layer 206 may contain ABF (or not contain glass-reinforced resin).

[0099] Stage 6 shows the state after multiple cavities 862 have been formed within dielectric layers 206 and 208. The multiple cavities 862 may be formed using an etching process (e.g., a photoetching process) and / or a laser process. Masking processes, exposure processes, and / or development processes may be used to form the multiple cavities 862.

[0100] Step 7 shows the state after multiple interconnections 262 have been formed within and on the surface of the dielectric layer 206 and / or dielectric layer 208. The multiple interconnections 262 may be coupled to multiple interconnections 282. Masking processes, plating processes, and / or etching processes may be used to form the multiple interconnections 262.

[0101] Step 8 shows the state after the dielectric layer 204 has been formed on the surface of the dielectric layer 206, as shown in Figure 8C. A deposition process and / or a lamination process may be used to form the dielectric layer 204. In some configurations, the dielectric layer 204 may contain the same material as or a different material from the dielectric layer 208 and / or the dielectric layer 206. The dielectric layer 204 is provided such that it has a relatively flat surface. The dielectric layer 204 may be a third dielectric layer. The dielectric layer 204 may include a prepreg.

[0102] Stage 9 shows the state after multiple cavities 842 have been formed within the dielectric layer 204. The multiple cavities 842 may be formed using an etching process (e.g., a photoetching process) and / or a laser process. Masking processes, exposure processes, and / or development processes may be used to form the multiple cavities 842.

[0103] Step 10 shows the state after multiple interconnections 242 have been formed within and on the surface of the dielectric layer 204. The multiple interconnections 242 can be coupled to multiple interconnections 262. Masking processes, plating processes, and / or etching processes may be used to form the multiple interconnections 242.

[0104] As shown in Figure 8D, step 11 shows the state after the carrier 800 has been disconnected. The carrier 800 may be separated from the dielectric layer 208. In some implementations, at least a portion of the seed layer 802 may be removed and / or separated.

[0105] Step 12 shows the state after the solder resist layers 122 and 124 have been formed. The solder resist layer 122 may be formed on (e.g., above) the dielectric layer 208. The solder resist layer 122 may include openings that expose portions of a plurality of interconnects 282 and / or a plurality of interconnects 284. The solder resist layer 124 may be formed on (e.g., below) the dielectric layer 204. The solder resist layer 124 may include openings that expose portions of a plurality of interconnects 242. Deposition, lamination, masking, exposure, and / or development processes may be used to form the solder resist layers and the openings in the solder resist layers. Steps 1 to 12 may show a sequence for fabricating a substrate (e.g., 202). Once the substrate is fabricated, an assembly process may be used to combine the substrate into one or more integrated devices to form a package. The assembly process for forming the package may be performed by a different factory than the one that fabricated the substrate, or by the same factory that fabricated the substrate.

[0106] Step 13 shows the state after the integrated devices 105 and 305 have been bonded to the substrate 202. The integrated device 105 may be bonded to a plurality of interconnects 284. The integrated device 105 may include a plurality of pillar interconnects 152. The integrated device 105 is bonded to a plurality of interconnects 284 via a plurality of solder interconnects 150. A solder reflow process may be used to bond the integrated device 105 to the plurality of interconnects 284. The plurality of solder interconnects 150 may be bonded to a plurality of pillar interconnects 152 and a plurality of interconnects 284. The integrated device 305 may be bonded to a plurality of interconnects 284. The integrated device 305 may include a plurality of pillar interconnects 352. The integrated device 305 is bonded to a plurality of interconnects 284 via a plurality of solder interconnects 350. A solder reflow process may be used to bond the integrated device 305 to a plurality of interconnects 284. Multiple solder interconnections 350 can be connected to multiple pillar interconnections 352 and multiple interconnections 284.

[0107] Step 14 shows the state after the underfill 110 has been provided between the integrated device 105 and the substrate 202, as shown in Figure 8E. The underfill 110 is also provided between the integrated device 305 and the substrate 202. The underfill 110 can be formed and / or provided using a deposition process and / or an injection process.

[0108] Step 15 shows the state after multiple solder interconnects 120 have been bonded to the substrate 202. A solder reflow process may be used to form and bond the multiple solder interconnects 120. The multiple solder interconnects 120 may be bonded to multiple interconnects 242. Step 15 may show the package 400.

[0109] Exemplary flowchart of a method for fabricating a package with a substrate containing embedded integrated devices. In some implementations, creating a package involves several processes. Figure 9 shows an illustrative flowchart of a method 900 for providing or creating a package. In some implementations, the method 900 in Figure 9 can be used to provide or create any of the packages in Figures 1 to 4. Figure 9 illustrates the creation of package 400. However, Figure 9 can be used to create any package.

[0110] It should be noted that Method 900 in Figure 9 may combine one or more processes to simplify and / or clarify the method for providing or creating a package. In some implementations, the order of the processes may be changed or modified.

[0111] This method involves providing a carrier having a seed layer (at 905). Step 1 in Figure 8A illustrates and explains an example of a provided carrier 800 and seed layer 802. The seed layer 802 may be placed on the surface of the carrier 800. The seed layer 802 may include a copper layer.

[0112] This method forms interconnects on the carrier and seed layer (at 910). Step 2 in Figure 8A illustrates an example of multiple interconnects 282 formed on the carrier 800. The step of forming multiple interconnects 282 may include the step of forming multiple interconnects 284. The seed layer 802 may be part of the multiple interconnects 282 and / or multiple interconnects 284. Masking processes, plating processes, and / or etching processes may be used to form the multiple interconnects 282 and / or multiple interconnects 284.

[0113] This method connects an integrated device (at 915) to multiple interconnects. Step 3 in Figure 8A illustrates an example of an integrated device 103 connected to multiple interconnects 284. The integrated device 103 may include multiple pillar interconnects 132. The integrated device 103 is connected to the multiple interconnects 284 via multiple solder interconnects 130. A solder reflow process may be used to connect the integrated device 103 to the multiple interconnects 284. The multiple solder interconnects 130 may be connected to the multiple pillar interconnects 132 and the multiple interconnects 284. In some implementations, the integrated device 103 may be configured as a deep trench capacitor. In some implementations, the integrated device 103 may be configured as a bridge. In some implementations, the multiple pillar interconnects 132 may be optional. In such cases, the multiple solder interconnects 130 may be connected to other interconnects of the integrated device 103. This method also allows for the formation of underfill between the integrated device and multiple interconnections (in 915). Step 3 in Figure 8A illustrates an example of underfill 210 provided between the integrated device 103 and the carrier 800. The underfill 210 may be formed and / or provided using a deposition process and / or an injection process.

[0114] This method forms a first dielectric layer (at 920). Step 4 in Figure 8A illustrates an example in which a dielectric layer 208 is provided. The dielectric layer 208 may be formed on the carrier 800. The dielectric layer 208 may be arranged laterally around the integrated device 103 and the underfill 210. A lamination process may be used to form the dielectric layer 208. The dielectric layer 208 may include a prepreg or ABF. The dielectric layer 208 may be the first dielectric layer.

[0115] This method forms a second dielectric layer (at 925). Step 5 in Figure 8B illustrates an example of a dielectric layer 206 formed on the surface of dielectric layer 208 and integrated device 103. Dielectric layer 206 may be bonded to and in contact with the back side of integrated device 103. Deposition and / or lamination processes may be used to form dielectric layer 206. In some packaging configurations, dielectric layer 206 may contain the same material as dielectric layer 208 or a different material. Dielectric layer 206 may contain ABF (or not contain glass-reinforced resin). Dielectric layer 206 is provided such that dielectric layer 206 has a relatively flat surface. Dielectric layer 206 may be a second dielectric layer. The step of forming the first and / or second dielectric layer may include the step of forming cavities within the dielectric layer(s). Step 6 in Figure 8B illustrates an example of multiple cavities 862 formed within dielectric layer 206 and dielectric layer 208. Multiple cavities 862 may be formed using etching processes (e.g., photoetching processes) and / or laser processes. Masking processes, exposure processes, and / or development processes may be used to form multiple cavities 862.

[0116] This method forms interconnections in the dielectric layer (at 930). Step 7 in Figure 8B illustrates an example of multiple interconnections 262 formed within and on the surface of dielectric layers 206 and 208. Multiple interconnections 262 can be coupled to multiple interconnections 282. Masking, plating, and / or etching processes may be used to form the multiple interconnections 262.

[0117] This method forms a third dielectric layer (at 935). Step 8 in Figure 8C illustrates an example of a dielectric layer 204 formed on the surface of dielectric layer 206. A deposition process and / or a lamination process may be used to form the dielectric layer 204. In some configurations, the dielectric layer 204 may contain the same material as or a different material from dielectric layer 208 and / or dielectric layer 206. The dielectric layer 204 is provided such that it has a relatively flat surface. The dielectric layer 204 may be a third dielectric layer. The dielectric layer 204 may include a prepreg. In some configurations, the step of forming the dielectric layer may include the step of forming cavities within the dielectric layer. Step 9 in Figure 8C illustrates an example of multiple cavities 842 formed within the dielectric layer 204. The multiple cavities 842 may be formed using an etching process (e.g., a photoetching process) and / or a laser process. A masking process, an exposure process, and / or a development process may be used to form multiple cavities 842.

[0118] In this method, a plurality of interconnections are formed in the third dielectric layer (at 940). Step 10 in Figure 8C illustrates an example of a plurality of interconnections 242 formed within and on the surface of the dielectric layer 204. The plurality of interconnections 242 may be coupled to a plurality of interconnections 262. Masking processes, plating processes, and / or etching processes may be used to form the plurality of interconnections 242.

[0119] This method involves decoupling carriers (at 945) and forming a solder resist layer (at 945). Step 11 in Figure 8D illustrates an example of decoupled carriers 800. The carriers 800 may be separated from the dielectric layer 208. In some mounting configurations, at least a portion of the seed layer 802 may be removed and / or separated. Step 12 in Figure 8D illustrates an example of solder resist layers 122 and 124 that are formed. The solder resist layer 122 may be formed on (e.g., above) the dielectric layer 208. The solder resist layer 122 may include openings that expose portions of a plurality of interconnections 282 and / or a plurality of interconnections 284. The solder resist layer 124 may be formed on (e.g., below) the dielectric layer 204. The solder resist layer 124 may include openings that expose portions of a plurality of interconnections 242. Deposition, lamination, masking, exposure, and / or development processes may be used to form the solder resist layer and the openings in the solder resist layer. Steps 1 to 12 may represent a sequence for fabricating a substrate (e.g., 202). Once the substrate is fabricated, an assembly process may be used to combine the substrate into one or more integrated devices to form a package. The assembly process for forming the package may be performed by a different factory than the one that fabricated the substrate, or by the same factory that fabricated the substrate.

[0120] This method involves bonding at least one second integrated device to a substrate (at 950). Step 13 in Figure 8D illustrates an example of integrated devices 105 and 305 bonded to a substrate 202. Integrated device 105 may be bonded to a plurality of interconnects 284. Integrated device 105 may include a plurality of pillar interconnects 152. Integrated device 105 is bonded to a plurality of interconnects 284 via a plurality of solder interconnects 150. A solder reflow process may be used to bond integrated device 105 to a plurality of interconnects 284. The plurality of solder interconnects 150 may be bonded to a plurality of pillar interconnects 152 and a plurality of interconnects 284. Integrated device 305 may be bonded to a plurality of interconnects 284. Integrated device 305 may include a plurality of pillar interconnects 352. Integrated device 305 is bonded to a plurality of interconnects 284 via a plurality of solder interconnects 350. A solder reflow process may be used to connect the integrated device 305 to a plurality of interconnects 284. The plurality of solder interconnects 350 may be connected to a plurality of pillar interconnects 352 and a plurality of interconnects 284. The method may also provide underfill between the integrated device and the substrate (in 950). Step 14 of Figure 8E illustrates an example of underfill 110 provided between the integrated device 105 and the substrate 202. Underfill 110 is also provided between the integrated device 305 and the substrate 202. The underfill 110 may be formed and / or provided using a deposition process and / or an injection process.

[0121] This method involves bonding solder interconnects to a substrate (at 955). Step 15 in Figure 8E illustrates an example of multiple solder interconnects 120 bonded to a substrate 202. A solder reflow process may be used to form and bond the multiple solder interconnects 120. The multiple solder interconnects 120 may be bonded to multiple interconnects 242. Step 15 may show a package 400.

[0122] Exemplary electronic device Figure 10 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1002, a laptop computer device 1004, a fixed-location terminal device 1006, a wearable device 1008, or an automated vehicle 1010 may include device 1000 as described herein. Device 1000 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Devices 1002, 1004, 1006, and 1008, and vehicle 1010 shown in Figure 10 are merely examples. Other electronic devices may also characterize device 1000, and such electronic devices include, but are not limited to, a group of devices (e.g., electronic devices) including mobile devices, hand-held personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-position data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0123] One or more of the components, processes, features, and / or functions shown in Figures 1-5, 6A-6E, 7, 8A-8E, and / or Figures 9-10 may be reconfigured and / or combined into a single component, process, feature, or function, or may be embodied in several components, processes, or functions. Additional components, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that Figures 1-5, 6A-6E, 7, 8A-8E, and / or Figures 9-10, and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 1-5, 6A-6E, 7, 8A-8E, and / or Figures 9-10, and their corresponding descriptions may be used to manufacture, fabricate, provide, and / or produce devices and / or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0124] Note that the figures in this disclosure may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to exact scale. In some cases, not all elements and / or components may be shown for clarity. In some cases, the position, location, size, and / or shape of various components and / or elements in the figures may be illustrative. In some implementations, various components and / or elements in the figures may be optional.

[0125] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” No implementation or aspect described herein as “exemplary” should necessarily be construed as being preferable or advantageous to any other aspect of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the features, advantages, or modes of operation described herein. The term “coupled” is used herein to mean a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C may still be considered coupled to each other, even if they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can propagate between them. Two electrically coupled objects may or may not propagate an electric current between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or any of the fourth) is arbitrary. Any of the components described may be the first, second, third, or fourth component. For example, a component referred to as the second component may be the first, second, third, or fourth component. The term “encapsulating” means that an object can partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be located above a component located at the bottom. A component at the top may be considered a component at the bottom, and vice versa.As described in this disclosure, a first component positioned "over" a second component may mean that the first component is positioned above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, the first component may be positioned above (e.g., above) a first surface of the second component, and the third component may be positioned above (e.g., below) a second surface of the second component, in which case the second surface is opposite to the first surface. It should be further noted that in the context of one component being positioned above another, the term "on" as used in this application may be used to mean a component that is on and / or within another component (e.g., on the surface of the component or embedded within the component). Therefore, for example, a first component on a second component may mean (1) the first component is on the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is inside the second component (e.g., embedded within the second component). A value of about X to XX may mean a value between X and XX, including X and XX. The values ​​(singular or plural) between X and XX may be discrete or continuous. As used in this disclosure, the terms “about ‘value X’” or “approximately value X” mean a range of 10 percent of “value X.” For example, a value of about 1 or approximately 1 means a value in the range of 0.9 to 1.1. “Multiple” components may include all possible components, or only some components from all possible components. For example, if a device contains 10 components, the term "multiple components" could refer to all 10 components or only some of the 10 components.

[0126] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, redistribution metal layers, and / or underbump metallization (UBM) layers. An interconnect may include one or more metal components (e.g., seed layer + metal layer). In some implementations, an interconnect is an electrically conductive material that can be configured to provide an electrical path for current (e.g., data signals, ground, or power). An interconnect may be part of a circuit. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form interconnects. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, interconnects can be formed using a sputtering process, spray coating, and / or an electroplating process or an electroless plating process.

[0127] Furthermore, it should be noted that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, many operations can also be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0128] Further embodiments are described below to facilitate understanding of the present invention.

[0129] Embodiment 1: A package comprising a substrate, the substrate comprising: at least one dielectric layer; a plurality of interconnections including a first plurality of interconnections; and a first integrated device at least partially disposed within the substrate, wherein the first integrated device is coupled to the first plurality of interconnections via a first plurality of solder interconnections. The package further comprises a second integrated device coupled to the first plurality of interconnections via a second plurality of solder interconnections.

[0130] Embodiment 2: The package according to Embodiment 1, wherein the first integrated device includes a deep trench capacitor.

[0131] Embodiment 3: The package according to Embodiment 1 or 2, wherein the electrical path between the first integrated device and the second integrated device includes (i) solder interconnects from a first plurality of solder interconnects, (ii) interconnects from the first plurality of interconnects, and (iii) solder interconnects from the second plurality of solder interconnects.

[0132] Embodiment 4: The package according to Embodiments 1 to 3, wherein a first integrated device is coupled to a first plurality of interconnections via a first plurality of pad interconnections and a first plurality of solder interconnections, and a second integrated device is coupled to the first plurality of interconnections via a second plurality of pillar interconnections and a second plurality of solder interconnections.

[0133] Embodiment 5: The package according to Embodiment 4, wherein the electrical path between the first integrated device and the second integrated device includes (i) pad interconnects from a plurality of first pad interconnects, (ii) solder interconnects from a plurality of first solder interconnects, (iii) interconnects from a plurality of first interconnects, (iv) solder interconnects from a plurality of second solder interconnects, and (v) pillar interconnects from a plurality of second solder interconnects.

[0134] Embodiment 6: The package according to Embodiments 1 to 3, wherein a first integrated device is coupled to a first plurality of interconnections via a first plurality of pillar interconnections and a first plurality of solder interconnections, and a second integrated device is coupled to the first plurality of interconnections via a second plurality of pillar interconnections and a second plurality of solder interconnections.

[0135] Embodiment 7: The package according to Embodiment 6, wherein the electrical path between the first integrated device and the second integrated device includes (i) pillar interconnects from a first plurality of pillar interconnects, (ii) solder interconnects from a first plurality of solder interconnects, (iii) interconnects from a first plurality of interconnects, (iv) solder interconnects from a second plurality of solder interconnects, and (v) pillar interconnects from a second plurality of solder interconnects.

[0136] Embodiment 8: The package according to embodiments 1 to 7, further comprising an underfill disposed between a second integrated device and a substrate.

[0137] Embodiment 9: The package according to Embodiments 1 to 7, further comprising a first plurality of interconnects and a first plurality of solder interconnects arranged laterally around the first plurality of solder interconnects, and a second underfill arranged between a second integrated device and a substrate, wherein the second underfill is in contact with the first underfill.

[0138] Embodiment 10: The package according to Embodiment 9, wherein the first underfill comprises a material different from at least one dielectric layer.

[0139] Embodiment 11: The package according to Embodiments 1 to 10, wherein at least one dielectric layer comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer.

[0140] Embodiment 12: The package according to Embodiment 11, wherein a plurality of interconnections include vias extending through a first dielectric layer and a second dielectric layer, and the first dielectric layer is coupled to the back surface and the side surface of the first integrated device.

[0141] Embodiment 13: The package according to embodiments 1 to 12, further comprising a third integrated device coupled to a first plurality of interconnects via a third plurality of solder interconnects, wherein the first integrated device includes a bridge, the electrical path between the second integrated device and the third integrated device includes a bridge, the second integrated device includes a first chiplet, and the third integrated device includes a second chiplet.

[0142] Embodiment 14: The package according to Embodiments 1 to 13, wherein the first integrated device includes a first front side and a first back side, and the second integrated device includes a second front side and a second back side, the first front side of the first integrated device faces a first direction, and the second front side of the second integrated device faces a second direction opposite to the first direction.

[0143] Embodiment 15: A device comprising a substrate, the substrate comprising: at least one dielectric layer; a plurality of interconnections including a first plurality of interconnections; and a first integrated device at least partially disposed within the substrate, wherein the first integrated device is coupled to the first plurality of interconnections via a first plurality of solder interconnections. The device further comprises a second integrated device coupled to the first plurality of interconnections via a second plurality of solder interconnections.

[0144] Embodiment 16: The device according to Embodiment 15, wherein the first integrated device includes a deep trench capacitor.

[0145] Embodiment 17: The device according to Embodiment 15 or 16, wherein the electrical path between the first integrated device and the second integrated device includes (i) solder interconnects from a first plurality of solder interconnects, (ii) interconnects from the first plurality of interconnects, and (iii) solder interconnects from the second plurality of solder interconnects.

[0146] Embodiment 18: The device according to embodiments 15 to 17, further comprising an underfill disposed between a second integrated device and a substrate.

[0147] Embodiment 19: The device according to embodiments 15 to 17, further comprising a first plurality of interconnects and a first underfill arranged laterally around the first plurality of solder interconnects, and a second underfill arranged between a second integrated device and a substrate, wherein the second underfill is in contact with the first underfill.

[0148] Embodiment 20: The device according to Embodiment 19, wherein the first underfill comprises a material different from at least one dielectric layer.

[0149] Embodiment 21: The device according to Embodiments 15 to 20, wherein at least one dielectric layer comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer.

[0150] Embodiment 22: The device according to Embodiment 21, wherein a plurality of interconnections include vias extending through a first dielectric layer and a second dielectric layer.

[0151] Embodiment 23: The device according to Embodiment 21 or 22, wherein the first dielectric layer is bonded to the back surface and the side surface of the first integrated device.

[0152] Embodiment 24: The device according to Embodiments 15 to 23, wherein the first integrated device includes a first front side and a first back side, and the second integrated device includes a second front side and a second back side, the first front side of the first integrated device faces a first direction, and the second front side of the second integrated device faces a second direction opposite to the first direction.

[0153] Embodiment 25: A method for manufacturing a substrate, comprising the steps of: coupling a first integrated device to a first plurality of interconnections of a carrier via a first plurality of solder interconnections; forming a first dielectric layer on the carrier and the first integrated device, wherein the first dielectric layer seals the first integrated device, the first plurality of solder interconnections, and the first plurality of interconnections; forming a second dielectric layer on the surface of the first dielectric layer; forming a first plurality of cavities within the second dielectric layer and the first dielectric layer; forming a second plurality of interconnections within at least the first plurality of cavities; forming a third dielectric layer on the second dielectric layer; forming a second plurality of cavities within the third dielectric layer; and forming a third plurality of interconnections within at least the second plurality of cavities.

[0154] Embodiment 26: The method of Embodiment 25, wherein, after forming a substrate, the method further comprises the step of coupling a second integrated device to a first plurality of interconnections via a second plurality of solder interconnections.

[0155] Embodiment 27: The method according to Embodiment 26, further comprising the step of forming an underfill between the second integrated device and the first dielectric layer after coupling the second integrated device.

[0156] Embodiment 28: The method according to Embodiment 25 or 26, wherein the first dielectric layer includes ABF and the third dielectric layer includes a prepreg.

[0157] Embodiment 29: The method according to Embodiments 25 to 27, wherein the first integrated device and the first plurality of solder interconnects are arranged in a substrate.

[0158] Embodiment 30: A method for manufacturing a substrate, comprising the steps of: coupling a first integrated device to a first plurality of interconnections of a carrier via a first plurality of solder interconnections; forming a first underfill between the first integrated device and the carrier, wherein the first underfill laterally surrounds the first plurality of solder interconnections; forming a first dielectric layer on the carrier; forming a second dielectric layer on the surface of the first integrated device and the first dielectric layer; forming a first plurality of cavities within the second dielectric layer and the first dielectric layer; forming a second plurality of interconnections within at least the first plurality of cavities; forming a third dielectric layer on the second dielectric layer; forming a second plurality of cavities within the third dielectric layer; and forming a third plurality of interconnections within at least the second plurality of cavities.

[0159] Embodiment 31: The method according to Embodiment 30, wherein, after forming a substrate, the method further comprises the step of coupling a second integrated device to a first plurality of interconnections via a second plurality of solder interconnections.

[0160] Embodiment 32: The method according to Embodiment 31, further comprising the step of forming a second underfill between the second integrated device and the first underfill after coupling the second integrated device.

[0161] Embodiment 33: The method according to Embodiments 30 to 32, wherein the first dielectric layer comprises ABF or prepreg, the second dielectric layer comprises ABF, and the third dielectric layer comprises prepreg.

[0162] Embodiment 34: The method according to Embodiments 30 to 33, wherein a first integrated device, a first plurality of solder interconnects, and a first underfill are located within the substrate.

[0163] Various features of the Disclosure described herein can be implemented in various systems without departing from the Disclosure. It should be noted that the above-described aspects of the Disclosure are merely examples and should not be construed as limiting the Disclosure. The descriptions of the aspects of the Disclosure are intended to be illustrative and not to limit the scope of the aspects. Therefore, the teachings can be readily applied to other types of devices, and many alternative, modified, and variant forms will be apparent to those skilled in the art. [Explanation of symbols]

[0164] 100 packages 102 circuit boards 103, 105 Integrated devices 104, 106, 108 Dielectric layers 120, 130, 150 Multiple solder interconnections 121, 142, 162, 182, 184 Multiple interconnection parts

Claims

1. It is a package, It is a substrate, At least one dielectric layer, Multiple interconnection parts including a first set of multiple interconnection parts, A first integrated device, at least partially disposed within the substrate, wherein the first integrated device is coupled to the first plurality of interconnections via a first plurality of solder interconnections, A second integrated device coupled to the first plurality of interconnections via a second plurality of solder interconnections, Including substrates, A package equipped with the following features.

2. The package according to claim 1, wherein the first integrated device includes a deep trench capacitor.

3. The package according to claim 1, wherein the electrical path between the first integrated device and the second integrated device includes (i) solder interconnects from the first plurality of solder interconnects, (ii) interconnects from the first plurality of interconnects, and (iii) solder interconnects from the second plurality of solder interconnects.

4. The first integrated device is coupled to the first plurality of interconnections via the first plurality of pad interconnections and the first plurality of solder interconnections, The second integrated device is coupled to the first plurality of interconnections via a second plurality of pillar interconnections and a second plurality of solder interconnections. The package according to claim 1.

5. The package according to claim 4, wherein the electrical path between the first integrated device and the second integrated device includes (i) pad interconnects from the first plurality of pad interconnects, (ii) solder interconnects from the first plurality of solder interconnects, (iii) interconnects from the first plurality of interconnects, (iv) solder interconnects from the second plurality of solder interconnects, and (v) pillar interconnects from the second plurality of solder interconnects.

6. The first integrated device is coupled to the first plurality of interconnections via the first plurality of pillar interconnections and the first plurality of solder interconnections, The second integrated device is coupled to the first plurality of interconnections via a second plurality of pillar interconnections and a second plurality of solder interconnections. The package according to claim 1.

7. The package according to claim 6, wherein the electrical path between the first integrated device and the second integrated device includes (i) pillar interconnects from the first plurality of pillar interconnects, (ii) solder interconnects from the first plurality of solder interconnects, (iii) interconnects from the first plurality of interconnects, (iv) solder interconnects from the second plurality of solder interconnects, and (v) pillar interconnects from the second plurality of solder interconnects.

8. The package according to claim 1, further comprising an underfill disposed between the second integrated device and the substrate.

9. The first plurality of interconnections and the first underfill arranged laterally around the first plurality of solder interconnections, The present invention further comprises a second underfill disposed between the second integrated device and the substrate, wherein the second underfill is in contact with the first underfill. The package according to claim 1.

10. The package according to claim 9, wherein the first underfill comprises a material different from the at least one dielectric layer.

11. The package according to claim 1, wherein the at least one dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer.

12. The plurality of interconnection portions include vias extending through the first dielectric layer and the second dielectric layer, The first dielectric layer is bonded to the back surface and the side surface of the first integrated device. The package according to claim 11.

13. The third integrated device is further connected to the first plurality of interconnections via a third plurality of solder interconnections, The first integrated device includes a bridge, The electrical path between the second integrated device and the third integrated device includes the bridge, The second integrated device includes the first chiplet, The third integrated device includes a second chiplet. The package according to claim 1.

14. The first integrated device includes a first front side and a first back side, The second integrated device includes a second front side and a second back side, The first front side of the first integrated device faces the first direction, The second front side of the second integrated device faces a second direction opposite to the first direction. The package according to claim 1.

15. It is a device, It is a substrate, At least one dielectric layer, Multiple interconnection parts including a first set of multiple interconnection parts, A first integrated device, at least partially disposed within the substrate, wherein the first integrated device is coupled to the first plurality of interconnections via a first plurality of solder interconnections, A second integrated device coupled to the first plurality of interconnections via a second plurality of solder interconnections, Including substrates, A device equipped with the following features.

16. The device according to claim 15, wherein the first integrated device includes a deep trench capacitor.

17. The device according to claim 15, wherein the electrical path between the first integrated device and the second integrated device includes (i) solder interconnects from the first plurality of solder interconnects, (ii) interconnects from the first plurality of interconnects, and (iii) solder interconnects from the second plurality of solder interconnects.

18. The device according to claim 15, further comprising an underfill disposed between the second integrated device and the substrate.

19. The first plurality of interconnections and the first underfill arranged laterally around the first plurality of solder interconnections, The present invention further comprises a second underfill disposed between the second integrated device and the substrate, wherein the second underfill is in contact with the first underfill. The device according to claim 15.

20. The device according to claim 19, wherein the first underfill comprises a material different from the at least one dielectric layer.

21. The device according to claim 15, wherein the at least one dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer.

22. The device according to claim 21, wherein the plurality of interconnections include vias extending through the first dielectric layer and the second dielectric layer.

23. The device according to claim 21, wherein the first dielectric layer is bonded to the back surface and the side surface of the first integrated device.

24. The first integrated device includes a first front side and a first back side, The second integrated device includes a second front side and a second back side, The first front side of the first integrated device faces the first direction, The second front side of the second integrated device faces a second direction opposite to the first direction. The device according to claim 15.

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