Upper via interconnect

Abstract

The semiconductor structure comprises a first metal wire embedded in a first dielectric layer, a second metal wire embedded in a second dielectric layer, the second metal wire having an upper via arranged on the first metal wire and extending between one of the first metal wires and one of the second metal wires, the upper via being self-aligned to one of the first metal wires, and at least one air gap located between the first and second metal wires adjacent to the upper via.

Description

Background Art

[0001] The present invention generally relates to semiconductor structures, and more specifically to a backend-of-line interconnect structure with self-aligned upper via interconnects.

[0002] Integrated circuit processing can generally be divided into front-end-of-line (FEOL), middle-end-of-line (MOL), and backend-of-line (BEOL) processes. FEOL and MOL processing generally form many layers of logic and functional devices. As an example, a typical FEOL process includes wafer preparation, isolation, well formation, gate patterning, spacers, extension and source / drain implantation, silicide formation, and dual stress liner formation. MOL is mainly gate contact formation. Interconnect layers are formed over these logic and functional layers during BEOL processing to complete the integrated circuit structure. Thus, BEOL processing generally involves the formation of insulators and conductive wiring. In the industry, typically, copper is used as the conductive metal for interconnect structures, and the dual damascene process is most often used to form metal wire / via interconnect structures.

[0003] As the size of integrated circuits continues to decrease, it has become more difficult to implement effective isolation of the operating components in these devices. Particularly in the case of transistor structures, the design requirements call for effective isolation of the operating components in order to reduce negative effects such as parasitic capacitance coupling and undesirable high power consumption.

Summary of the Invention

[0004] According to embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure may comprise a first metal wire embedded in a first dielectric layer, a second metal wire embedded in a second dielectric layer, the second metal wire having upper vias arranged on the first metal wires and extending between one of the first metal wires and one of the second metal wires, the upper vias being self-aligned to one of the first metal wires, and at least one air gap disposed between the first and second metal wires adjacent to the upper vias.

[0005] According to embodiments of the present invention, the semiconductor structure further comprises a dielectric liner surrounding the sides and bottom of at least one air gap.

[0006] According to embodiments of the present invention, the dielectric liner is in direct contact with all of the uppermost surfaces of the first metal wire directly below the second metal wire, except where the upper vias are located.

[0007] According to embodiments of the present invention, the semiconductor structure further includes a mask that is on and in direct contact with the uppermost surface of the first metal wire, except where the first metal wire is directly beneath the second metal wire, the lowermost surface of the mask being substantially coplanar with the lowermost surface of the upper via.

[0008] According to embodiments of the present invention, the lowest surface of the second metal wire is located below the uppermost surface of the first dielectric layer.

[0009] According to embodiments of the present invention, the first metal wire is in direct contact with the first dielectric layer without a barrier liner, where the upper via is in direct contact with the first dielectric layer without a barrier liner, and the second metal wire is in direct contact with both the first and second dielectric layers without a barrier liner.

[0010] According to embodiments of the present invention, the first metal wire and the second metal wire contain ruthenium.

[0011] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may comprise a first metal wire embedded in a first dielectric layer, a second metal wire embedded in a second dielectric layer, the second metal wire being arranged on top of the first metal wire, an upper via extending between one of the first metal wires and one of the second metal wires, the upper via being self-aligned to one of the first metal wires, and at least one air gap positioned between the first and second metal wires adjacent to the upper via, the at least one air gap being at the same level as the upper via.

[0012] According to embodiments of the present invention, the semiconductor structure further comprises a dielectric liner surrounding the sides and bottom of at least one air gap.

[0013] According to embodiments of the present invention, the dielectric liner is in direct contact with all of the uppermost surfaces of the first metal wire directly below the second metal wire, except where the upper vias are located.

[0014] According to embodiments of the present invention, the semiconductor structure further includes a mask that is on and in direct contact with the uppermost surface of the first metal wire, except where the first metal wire is directly beneath the second metal wire, the lowermost surface of the mask being substantially coplanar with the lowermost surface of the upper via.

[0015] According to embodiments of the present invention, the lowest surface of the second metal wire is located below the uppermost surface of the first dielectric layer.

[0016] According to embodiments of the present invention, the first metal wire is in direct contact with the first dielectric layer without a barrier liner, where the upper via is in direct contact with the first dielectric layer without a barrier liner, and the second metal wire is in direct contact with both the first and second dielectric layers without a barrier liner.

[0017] According to embodiments of the present invention, the first metal wire and the second metal wire contain ruthenium.

[0018] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may comprise: a first metal wire embedded in a first dielectric layer; a second metal wire embedded in a second dielectric layer, the second metal wire being arranged on top of the first metal wire; an upper via extending between one of the first metal wires and one of the second metal wires, the upper via being self-aligned with one of the first metal wires; and at least one air gap positioned at the same level as the upper via, the at least one air gap being arranged at the intersection between the first and second metal wires.

[0019] According to embodiments of the present invention, the semiconductor structure further comprises a dielectric liner surrounding the sides and bottom of at least one air gap.

[0020] According to embodiments of the present invention, the dielectric liner is in direct contact with all of the uppermost surfaces of the first metal wire directly below the second metal wire, except where the upper vias are located.

[0021] According to embodiments of the present invention, the semiconductor structure further includes a mask that is on and in direct contact with the uppermost surface of the first metal wire, except where the first metal wire is directly beneath the second metal wire, the lowermost surface of the mask being substantially coplanar with the lowermost surface of the upper via.

[0022] According to embodiments of the present invention, the lowest surface of the second metal wire is located below the uppermost surface of the first dielectric layer.

[0023] According to embodiments of the present invention, the first metal wire is in direct contact with the first dielectric layer without a barrier liner, where the upper via is in direct contact with the first dielectric layer without a barrier liner, and the second metal wire is in direct contact with both the first and second dielectric layers without a barrier liner.

[0024] According to embodiments of the present invention, the first metal wire and the second metal wire contain ruthenium.

[0025] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first metal wire embedded in a first dielectric layer, a second metal wire embedded in a second dielectric layer, where the second metal wire is arranged above the first metal wire, an upper via extending between one of the first metal wires and one of the second metal wires, where the upper via is self-aligned with one of the first metal wires, at least one air gap disposed at the same level as the upper via, where the at least one air gap is arranged at an intersection between the first metal wire and the second metal wire, a dielectric liner surrounding the sides and bottom of the at least one air gap, and a mask directly contacting and above the uppermost surface of the first metal wire except where the first metal wire is directly below the second metal wire, where the lowermost surface of the mask is substantially in the same plane as the lowermost surface of the upper via.

[0026] According to an embodiment of the present invention, the dielectric liner directly contacts the uppermost surfaces of all of the first metal wires directly below the second metal wire, except where the upper via is located.

[0027] According to an embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first metal wire embedded in a first dielectric layer, a second metal wire embedded in a second dielectric layer, where the second metal wire is arranged above the first metal wire, an upper via extending between one of the first metal wires and one of the second metal wires, where the upper via is self-aligned with one of the first metal wires, a dielectric plug disposed at the same level as the upper via and directly above all of the first metal wires except where the upper via is located, and at least one air gap disposed within at least one of the dielectric plugs separating both the first dielectric layer and the second dielectric layer.

[0028] According to an embodiment of the present invention, each of the dielectric plugs is self-aligned with each of the first metal wires, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The following detailed description is provided by way of example and is not intended to limit the present invention thereto, and is best understood in conjunction with the following accompanying drawings.

[0030] [Figure 1] FIG. Cross-sectional view of a first semiconductor structure in an intermediate step of a method of manufacturing an interconnect structure according to an exemplary embodiment.

[0031] [Figure 2] FIG. Cross-sectional view of a first semiconductor structure after patterning an opening in a first metal layer to expose a lower level, according to an exemplary embodiment.

[0032] [Figure 3] FIG. Cross-sectional view of a first semiconductor structure after forming a first dielectric layer, according to an exemplary embodiment.

[0033] [Figure 4] FIG. Cross-sectional view of a first semiconductor structure after an etch stop layer, a second dielectric layer, and a sacrificial mask, according to an exemplary embodiment.

[0034] [Figure 5] FIG. Cross-sectional view of a first semiconductor structure after removing a portion of an etch stop layer, according to an exemplary embodiment.

[0035] [Figure 6] FIG. Cross-sectional view of a first semiconductor structure after forming a planarization layer and a second hard mask layer, according to an exemplary embodiment.

[0036] [Figure 7] FIG. Cross-sectional view of a first semiconductor structure after removing a single individual mask exposed at the bottom of an opening and removing a second hard mask layer, according to an exemplary embodiment.

[0037] [Figure 8]This is a cross-sectional view of the first semiconductor structure after the planarization layer has been removed and self-aligned upper vias have been formed, according to an exemplary embodiment.

[0038] [Figure 9] This is a cross-sectional view of the first semiconductor structure after removing additional individual masks exposed in the trench, according to an exemplary embodiment.

[0039] [Figure 10] This is a cross-sectional view of the first semiconductor structure after the liner and third dielectric layer have been formed, according to an exemplary embodiment.

[0040] [Figure 11] This is a cross-sectional view of the first semiconductor structure after the third dielectric layer has been removed, according to an exemplary embodiment.

[0041] [Figure 12] This is a cross-sectional view of the first semiconductor structure after the liner has been removed, according to an exemplary embodiment.

[0042] [Figure 13] This is a cross-sectional view of the first semiconductor structure after the second metal wire has been formed, according to an exemplary embodiment. [Figure 14] This is a cross-sectional view of the first semiconductor structure after the second metal wire has been formed, according to an exemplary embodiment. [Figure 15] This is a cross-sectional view of the first semiconductor structure after the second metal wire has been formed, according to an exemplary embodiment.

[0043] [Figure 16] This is a cross-sectional view of a second semiconductor structure in an intermediate step of a method for manufacturing an interconnect structure according to an exemplary embodiment.

[0044] [Figure 17] This is a cross-sectional view of a second semiconductor structure after patterning an opening in the first metal layer and exposing the lower level, according to an exemplary embodiment.

[0045] [Figure 18] This is a cross-sectional view of a second semiconductor structure after the formation of a first dielectric layer, according to an exemplary embodiment.

[0046] [Figure 19] This is a cross-sectional view of a second semiconductor structure after forming a planarization layer and a second hard mask layer according to an exemplary embodiment.

[0047] [Figure 20] This is a cross-sectional view of the second semiconductor structure after removing a single individual mask exposed at the bottom of the opening and removing the second hard mask layer, according to an exemplary embodiment.

[0048] [Figure 21] This is a cross-sectional view of the second semiconductor structure after forming self-aligned upper vias and removing the planarization layer, according to an exemplary embodiment.

[0049] [Figure 22] This is a cross-sectional view of the second semiconductor structure after the remaining individual masks have been removed, according to an exemplary embodiment.

[0050] [Figure 23] This is a cross-sectional view of a second semiconductor structure after the formation of a second dielectric layer, according to an exemplary embodiment.

[0051] [Figure 24] This is a cross-sectional view of a second semiconductor structure after forming a second metal wire and a third dielectric layer according to an exemplary embodiment. [Figure 25] This is a cross-sectional view of a second semiconductor structure after forming a second metal wire and a third dielectric layer according to an exemplary embodiment. [Figure 26] This is a cross-sectional view of a second semiconductor structure after forming a second metal wire and a third dielectric layer according to an exemplary embodiment.

[0052] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to represent specific parameters of the invention. For clarity and ease of illustration, the scale of elements may be shown larger than they actually are. The drawings are intended to illustrate only typical embodiments of the invention. In the drawings, similar reference numerals represent similar elements.

[0053] Additionally, XYZ Cartesian coordinates may also be shown in each of the drawings to provide further spatial context. As used herein, the terms “vertical,” “vertical direction,” or “vertical height” refer to the Z direction of the Cartesian coordinates shown in the drawings, and as used herein, the terms “horizontal,” “horizontal direction,” or “lateral direction” refer to the X and / or Y directions of the Cartesian coordinates shown in the drawings. [Modes for carrying out the invention]

[0054] Detailed embodiments of the claimed structure and method are disclosed herein; however, it should be understood that the disclosed embodiments are merely illustrative of the claimed structure and method, which may be embodied in various forms. The present invention may, however, be embodied in many different forms and should not be considered limited to the exemplary embodiments described herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0055] References in the specification such as "one embodiment," "embodiment," and "exemplary embodiment" indicate that the embodiments described may include certain features, structures, or characteristics, but not all embodiments may necessarily include such features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, if certain features, structures, or characteristics are described in relation to an embodiment, it is considered within the knowledge of those skilled in the art that such features, structures, or characteristics may be affected in relation to other embodiments, whether or not they are explicitly described.

[0056] For the purposes of the following explanation, the terms “upper,” “downward,” “right,” “left,” “vertical,” “horizontal,” “top,” and “bottom,” and their derivatives, shall be those of the structure and method disclosed as oriented in the drawings. When an element, such as a layer, region, or substrate, is said to be "on" or "over" another element, it will be understood that it may be directly on the other element, or there may be an intervening element. In contrast, when an element is said to be "directly on" or "directly over" another element, there is no intervening element. When an element is said to be "connected" or "coupled" to another element, it will also be understood that it may be directly connected or coupled to the other element, or there may be an intervening element. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there is no intervening element. Furthermore, the term "sublithography" may refer to dimensions or sizes smaller than the current dimensions achievable by the photolithography process, and the term "lithography" may refer to dimensions or sizes equal to or larger than the current dimensions achievable by the photolithography process. Sublithography and lithography dimensions may be determined by a person skilled in the art at the time this application is filed.

[0057] The terms substantially, substantially similar, approximately, or any other terms indicating functionally equivalent similarity refer to cases where differences in length, height, or orientation do not result in actual differences between a clear enumeration (e.g., a phrase without the term substantially similar) and substantially similar derivatives. In one embodiment, substantial (and its derivatives) differs by generally acceptable engineering or manufacturing tolerances for similar devices, such as a deviation of up to 10% in value or a deviation of 10% in angle.

[0058] To avoid ambiguity in the presentation of embodiments of the present invention, some processing steps or operations known in the art may be combined together for presentation and illustrative purposes in the following detailed description, and in some cases may not be described in detail. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the specific features or elements of various embodiments of the present invention.

[0059] As the pitch of BEOL metal features decreases, the metal wires themselves become narrower, making it increasingly difficult to maintain proper isolation and insulation between adjacent metal features. Subtractive metal patterning schemes, such as top via schemes, are an attractive solution for producing narrow metal features with relatively tight pitches because they do not require a metal liner and allow for larger volumes of conductors, thereby reducing resistance. One drawback of subtractive top via schemes is that it remains difficult to form subtractive "top vias" that also self-align with the metal level directly above them. This is especially true when the top metal wires have a relatively loose pitch and can be formed by conventional damascene processes. Finally, it is highly desirable that top via schemes be compatible with perfectly aligned vias.

[0060] The present invention generally relates to semiconductor structures, and more specifically to back-end obline interconnect structures with self-aligning upper via interconnects. More specifically, the interconnect structures and related methods disclosed herein enable a novel solution for reducing residual masking material and capacitance between a metal level formed directly above the upper via interconnect structure. According to embodiments of the present invention, the upper via scheme disclosed herein refers to a subtractively formed metal level having self-aligning vias subsequently formed thereon. Exemplary embodiments of the interconnect structures are described in detail below by reference to the accompanying drawings in Figures 1 to 26. Those skilled in the art will readily understand that the present invention extends beyond these limiting embodiments, and therefore the detailed description provided herein with respect to these figures is for illustrative purposes only.

[0061] Referring here to Figure 1, an explanatory diagram of the first structure 100 (hereinafter referred to as structure 100) in an intermediate step of a method for manufacturing an interconnect structure according to an embodiment of the invention is shown. More specifically, as disclosed herein, the method may begin with a lower level 102 having a first metal layer 104 and a first hard mask layer 106 formed on top of it.

[0062] For the purposes of this description, lower level 102 represents one of the front-end obline device layer, middle obline metal layer, or back-end obline metal layer. In at least one example, lower level 102 may include one or more contacts or contact vias present in the front-end obline device layer or back-end obline metal layer. In yet another example, lower level 102 may include one or more metal wires, vias, or other conductors present in the middle obline metal layer or back-end obline metal layer.

[0063] The first metal layer 104 of this embodiment is formed directly on top of the lower level 102 according to known techniques. The first metal layer 104 may contain any suitable interconnect metal that can be readily removed by subtractive etching. For example, the first metal layer 104 may contain aluminum, copper, ruthenium, cobalt, rhodium, iridium, nickel or alloys thereof or similar, as desired for the application. In at least one embodiment, the first metal layer 104 is made from ruthenium for low electrical resistance and high resistance to electromigration. The first metal layer 104 may be deposited using known techniques such as CVD, sputtering, electrochemical deposition or similar processes. In embodiments, the thickness of the first metal layer 104 may be in the range of approximately 20 nm to approximately 100 nm; however, other thicknesses less than 20 nm and greater than 100 nm are explicitly intended. In some embodiments, an adhesive layer (not shown) is provided between the lower level 102 and the first metal layer 104; however, this is not essential. In such cases, the adhesive layer may be a relatively thin layer of titanium nitride.

[0064] Finally, the first hard mask layer 106 of this embodiment is formed directly on top of the first conductive layer 104 according to known techniques, as illustrated. The first hard mask layer 106 may include any known dielectric hard mask material suitable for facilitating subsequent patterning and etching techniques. In all cases, the first hard mask layer 106 is preferably made from a dielectric material that can be selectively etched or patterned with respect to the first dielectric layer (Figure 3) and the metal wire (110). For example, the first hard mask layer 106 may include nitrides such as silicon nitride, titanium nitride, tantalum nitride, aluminum nitride, or silicon carbon nitride. In at least one embodiment, for example, the first hard mask layer 106 is a layer of silicon nitride. In another embodiment, the first hard mask layer 106 is a layer of silicon carbon nitride. Finally, the first hard mask layer 106 is essentially sacrificial, as some or all of it is removed in a subsequent process and no longer exists in the final structure. The first hard mask layer 106 can be formed by any deposition technique, including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition.

[0065] The cumulative thickness of the first metal layer 104 and the first hard mask layer 106 is approximately equal to the desired thickness of a typical metallization level that extends over the lower level 102 and is subsequently formed. Specifically, the relative thickness of the first metal layer 104 corresponds to the desired height or thickness of a typical metal level (e.g., Mx-1), and the relative thickness of the first hard mask layer 106 corresponds to the desired height or thickness of a typical via level (e.g., Vx-1). In some embodiments, the thickness of the first hard mask layer 106 is substantially equal to the thickness of the first metal layer 104. In other embodiments, the first hard mask layer 106 may be thicker than the first metal layer 104. In yet another embodiment, the first hard mask layer 106 may be thinner than the first metal layer 104. It should be noted that the final heights of the subsequently formed metal wires and upper vias do not depend solely on the relative height or thickness of either the first metal layer 104 or the first hard mask layer 106, respectively.

[0066] Referring now to Figure 2, the structure 100 according to an embodiment of the invention is shown after the opening 108 has been patterned in the first metal layer 104 and the lower level 102 has been exposed.

[0067] The opening 108 in this embodiment is patterned in the structure 100 according to known techniques. The opening 108 can be patterned by applying a photoresist (not shown), exposing the photoresist to a desired pattern of radiation, and developing the exposed photoresist using a conventional resist developer. The pattern in the photoresist can then be transferred to the first hard mask layer 106 and the first metal layer 104 according to known techniques. For example, one or more preferred etching techniques, such as dry etching, wet etching, or a combination of both, can be used to pattern the opening 108.

[0068] After patterning, as illustrated, the remaining portion of the first hard mask layer 106 becomes a plurality of individual masks 112, and the remaining portion of the first metal layer 104 becomes the first metal wire 110. The first metal wire 110 formed according to the process described herein is formed according to a conventional subtractive technique.

[0069] Generally, the apertures 108 and, similarly, the first metal wire 110 may be separated according to lithography limitations, ground rules, or both. In some embodiments, the apertures 108 are separated by equal distances, however, this is not mandatory. Finally, for illustrative purposes only, only three apertures 108 are shown in Figure 2. As is also known to those skilled in the art, any typical semiconductor structure has multiple back-end ob-line interconnect structures, and the structure 100 of the present invention also explicitly includes multiple apertures 108, although not shown in the figure.

[0070] Referring now to Figure 3, the structure 100 after the formation of the first dielectric layer 114 according to an embodiment of the invention is shown.

[0071] In this embodiment, the first dielectric layer 114 is blanket-deposited on top of the structure 100, and more specifically, the opening 108 is filled according to known techniques, as illustrated. Thus, the first metal wire 110 is embedded in the first dielectric layer 114.

[0072] The first dielectric layer 114 may include any suitable dielectric material, such as oxides, nitrides, silicon oxide (SiO2), silicon nitride (Si3N4), silicon hydride carbon oxide (SiCOH), carbon-rich silicon carbon nitride (SiCN), silicon-based low-κ dielectrics, porous dielectrics, or some combination thereof. As used herein, the term "low-κ" refers to a material having a dielectric constant κ lower than that of silicon dioxide. In embodiments, the first dielectric layer 114 may be formed using deposition techniques including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vapor deposition, spin-on coating, or sputtering.

[0073] For example, in one embodiment, the first dielectric layer 114 is made from silicon hydride carbon oxide (SiCOH). In another embodiment, the first dielectric layer 114 is made from carbon-rich silicon carbonitride (SiCN). In all cases, the first dielectric layer 114 should be made from a dielectric material having appropriate etching selectivity to the surrounding dielectric, e.g., the individual mask 112, and other materials subsequently formed as discussed below.

[0074] Finally, a chemical mechanical polishing technique is used to remove any unwanted excess dielectric material from the top surface of the structure 100. As a result, the top surface of the first dielectric layer 114 is coplanar or substantially coplanar with the top surface of the individual mask 112.

[0075] Referring now to Figure 4, the structure 100 after the etching stop layer 116, the second dielectric layer 118, and the sacrificial mask 120 have been formed according to an embodiment of the invention is shown.

[0076] The etching stop layer 116 of this embodiment is blanket-deposited on top of the structure 100 according to a known technique, as illustrated. Specifically, the etching stop layer 116 covers the exposed portions of the individual mask 112 and the first dielectric layer 114. The etching stop layer 116 may contain any known etching stop material. In this embodiment, the etching stop layer 104 needs to protect the individual mask 112 and the first dielectric layer 114 during subsequent processing. For example, the etching stop layer 116 may be made from aluminum nitride. In this embodiment, the thickness of the etching stop layer 116 may be in the range of approximately 1 nm to approximately 10 nm, however other thicknesses greater than 10 nm are explicitly intended.

[0077] Next, the second dielectric layer 118 of this embodiment is blanket-deposited on top of the structure 100 according to known techniques, as illustrated. Similar to the first dielectric layer 114, the second dielectric layer 118 may include any suitable dielectric material, such as oxides, nitrides, silicon oxide (SiO2), silicon nitride (Si3N4), silicon hydride carbon oxide (SiCOH), carbon-rich silicon carbon nitride (SiCN), silicon-based low-κ dielectrics, porous dielectrics, or some combination thereof. In embodiments, the second dielectric layer 118 may be formed using deposition techniques including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vapor deposition, spin-on coating, or sputtering.

[0078] For example, in one embodiment, the second dielectric layer 118 is made from silicon hydride carbon oxide (SiCOH). In another embodiment, the second dielectric layer 118 is made from carbon-rich silicon carbonitride (SiCN). In all cases, the second dielectric layer 118 should be formed from a dielectric material suitable for subsequent damascene treatment. According to at least one embodiment, the second dielectric layer 118 is made from the same dielectric material as the first dielectric layer 114. In at least another embodiment, the second dielectric layer 118 is made from a different material than the first dielectric layer 114.

[0079] The relative thickness of the second dielectric layer 118 is approximately equal to the desired thickness of a typical metallization level formed on and after the lower Mx-1 and Vx-1 levels. Specifically, the relative thickness of the second dielectric layer 118 corresponds to the desired height or thickness of a typical metal level (e.g., Mx).

[0080] Next, as illustrated, a sacrificial masking layer (not shown) is formed directly on top of the second dielectric layer 118 according to known techniques. The sacrificial masking layer may include any known dielectric hard mask material suitable for facilitating subsequent patterning and etching techniques. For example, the sacrificial masking layer may include nitrides such as silicon nitride, titanium nitride, tantalum nitride, aluminum nitride, or silicon carbon nitride. In at least one embodiment, for example, the sacrificial masking layer is a relatively thin layer of silicon nitride. In another embodiment, the sacrificial masking layer is a relatively thin layer of silicon carbon nitride. Finally, the sacrificial masking layer is sacrificial in nature, as it is removed in a subsequent process and no longer exists in the final structure.

[0081] Finally, as illustrated, the trench 122 is patterned in the structure 100 according to known techniques. Although only a single trench is illustrated in Figure 4, embodiments of the present invention explicitly intend to pattern multiple trenches. The trench 122 may be patterned by applying a photoresist (not shown), exposing the photoresist to a desired pattern of radiation, and developing the exposed photoresist using a conventional resist developer. The pattern in the photoresist may then be transferred to a sacrificial masking layer and a second dielectric layer 118 according to known techniques. One or more preferred etching techniques, such as dry etching, wet etching, or a combination of both, may be used to pattern the trench 122. In all cases, the patterning or etching is designed to stop on an etching stop layer 116. In other words, the etching stop layer 116 protects the underlying material during etching of the trench 122. After patterning, the remainder of the sacrificial masking layer becomes the sacrificial mask 120.

[0082] Referring now to Figure 5, the structure 100 after the etching stop layer 116 has been removed according to an embodiment of the present invention is shown.

[0083] As illustrated, the exposed portion of the etching stop layer 116 is removed using the same pattern that occurs during the formation of the trench 122, according to known techniques. The exposed portion of the etching stop layer 116 is selectively removed relative to the sacrificial mask 120 and the rest of the second dielectric layer 118. In other words, the etching stop layer 116 is removed from the bottom of the trench 122, as illustrated. The portion of the etching stop layer 116 beneath the second dielectric layer 118 remains.

[0084] One or more suitable etching techniques may be applied to etch the exposed portion of the etching stop layer 116. Suitable dry etching techniques may include, but are not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation. Such etching techniques should be designed to selectively remove portions of the etching stop layer 116 relative to the sacrificial mask 120 and the rest of the second dielectric layer 118.

[0085] Referring now to Figure 6, the structure 100 after the formation of the planarization layer 124 and the second hard mask layer 126 according to an embodiment of the present invention is shown.

[0086] The planarization layer 124 in this embodiment is blanket-deposited directly onto the exposed surface of the structure 100 according to a known technique, as illustrated, to fill the trench 122 (Figure 5). The planarization layer 124 may be an organic planarization layer or a layer of material that can be planarized or etched by a known technique. In this embodiment, for example, the planarization layer 124 may be an amorphous carbon layer that can withstand the high temperatures of subsequent processing steps. The planarization layer 124 may preferably have a thickness sufficient to cover the existing structure. For example, the planarization layer 124 is typically deposited to cover both the second dielectric layer 118 and the sacrificial mask 120.

[0087] Next, as illustrated, the second hard mask layer 126 of this embodiment is deposited directly onto the planarization layer 124 according to known techniques. The second hard mask layer 126 may include any known hard mask material suitable for facilitating subsequent patterning and etching techniques. In all cases, the second hard mask layer 126 is preferably made from a material that can be selectively etched or patterned with respect to the planarization layer 124 and other surrounding metallic features. The second hard mask layer 126 may include known anti-reflective coatings such as SiARC, TiARC, TiOx, LTO, and SiON. Finally, the second hard mask layer 126 is essentially sacrificial, as it is removed in subsequent processes and no longer exists in the final structure. The second hard mask layer 126 may be formed by any deposition technique, including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. Finally, as illustrated, both the second hard mask layer 126 and the planarization layer 124 of this embodiment are patterned according to known techniques to form an opening 128. The opening 128 is arranged to expose a single individual mask 112, as illustrated. Similarly, the opening 128 is arranged directly over a single first metal wire 110, also as illustrated.

[0088] Referring now to Figure 7, the structure 100 according to an embodiment of the present invention is shown after removing the single individual mask 112 exposed at the bottom of the opening 128 and the second hard mask layer 126.

[0089] A single individual mask 112 and a second hard mask layer 126 exposed at the bottom of the opening 128 are selectively removed from the underlying structures according to known techniques, as exemplified. For example, in at least one embodiment, the single individual mask 112 is selectively removed from the first dielectric layer 114 and the first metal wire 110, and the second hard mask layer 126 is selectively removed from the planarization layer 124. One or more preferred etching techniques, such as dry etching, wet etching, or a combination thereof, may be used to remove the single individual mask 112 and the second hard mask layer 126. For example, preferred dry etching techniques may include, but are not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation. The primary objective of this etching is to remove the single individual mask 112, and the removal of the second hard mask layer 126 is a result when a similar hard mask material is used. Embodiments of the present invention explicitly intend to use a single individual mask 112 and a second hard mask layer 126 made of different hard mask materials, and therefore require an additional etching step to remove the second hard mask layer 126, although this is inefficient.

[0090] Referring now to Figure 8, the structure 100 according to an embodiment of the present invention is shown after the planarization layer 124 has been removed and the self-aligned upper via 130 has been formed.

[0091] First, the planarization layer 124 is selectively removed from all underlying structures according to known techniques, as illustrated. For example, in at least one embodiment, the planarization layer 124 is removed by ashing.

[0092] Next, the self-aligned upper via 130 (hereinafter, upper via 130) of this embodiment is formed directly on top of a single first metal wire 110 according to known techniques, as illustrated. Specifically, the gap formed by removing a single individual mask 112 exposed at the bottom of the opening 128 (Figure 7) is filled with a conductive material to form the upper via 130. For example, known CVD or ALD techniques may be used to selectively deposit metals such as tungsten, ruthenium, aluminum, copper, ruthenium, cobalt, rhodium, iridium, nickel, or alloys thereof. In at least one embodiment, the upper via 130 is made of ruthenium for low electrical resistance and high resistance to electromigration. Thus, the upper via 130 is formed only in the gap formed by removing a single individual mask 112 exposed at the bottom of the opening 128 (Figure 7). As shown in Figure 8, the selective metal deposition technique used to form the upper via 130 may overfill the opening, resulting in a small portion of the conductive material extending above the upper surface of the first dielectric layer 114. This prevents unwanted air gaps in the upper via 130.

[0093] Additionally, combinations of the same or different materials may be used to produce the desired electrical resistance characteristics. For example, according to at least one embodiment, both the first metal wire 110 and the aligned upper vias 130 are made of ruthenium. According to another embodiment, the first metal wire 110 is made of ruthenium, and the upper vias 130 are made of ruthenium, cobalt, or tungsten. According to yet another embodiment, the first metal wire 110 is made of tungsten, cobalt, or copper, and the upper vias 130 are made of ruthenium. Ruthenium is particularly advantageous due to its excellent electromigration properties, thus eliminating the need for a barrier layer or liner layer. The resulting conductive structure, in this case the first metal wire 110 and upper vias 130, has a larger volume compared to a similar structure made of copper.

[0094] Additionally, the upper vias 130 are considered to be self-aligned with a single first metal wire 110. This is possible because the single first metal wire 110 is patterned based on a single individual mask 112, which then replaces the entire upper via 130. Additionally, the width of each upper via 130 is defined in the y direction by the individual mask 112, and the length of each upper via 130 is defined in the x direction by the flattening player 124.

[0095] Referring now to Figure 9, the structure 100 according to an embodiment of the present invention is shown after the removal of the additional individual mask 112 exposed in the trench 122.

[0096] The additional individual mask 112 exposed at the bottom of the trench 122 is selectively removed from the underlying structure according to known techniques, as illustrated, thereby forming an additional opening 132. For example, in at least one embodiment, the additional individual mask 112 is selectively removed from the first dielectric layer 114 and the first metal wire 110, as illustrated. One or more preferred etching techniques, such as dry etching, wet etching, or a combination of both, may be used to remove the additional individual mask 112. For example, preferred dry etching techniques may include, but are not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation. In doing so, the sacrificial mask 120 is reset. It is important that the sacrificial mask 120 is sufficiently thick so that at least a portion remains after the removal of the additional individual mask 112, as illustrated in Figure 9. Additionally, it should be noted that only the additional individual mask 112 exposed within the trench 122 is removed. In other words, as illustrated, one or more individual masks 112 and the first metal wire 110 remain protected beneath the etching stop layer 116, the second dielectric layer 118, and the rest of the sacrificial mask 120.

[0097] Referring now to Figure 10, the structure 100 after the formation of the liner 134 and the third dielectric layer 136 according to an embodiment of the invention is shown. The liner 134 may alternatively be referred to as the dielectric liner 134.

[0098] First, the liner 134 of this embodiment is conformally deposited directly onto the exposed surface of the structure 100 according to known techniques, as illustrated. As used herein, “conformal” means that the material layer has a substantially continuous thickness. For example, substantially continuous thickness generally means a first thickness measured from the bottom to the top, which is identical to a second thickness measured from the inner sidewall to the outer sidewall. In another embodiment, the liner 134 may be a non-conformal layer.

[0099] The liner 134 is composed of a dielectric material suitable for providing suitable protection of the underlying structure during subsequent processing. More specifically, the liner 134 can be any dielectric material having some etching selectivity for the third dielectric layer 136 that is subsequently deposited, as will be described in more detail just below. In at least one embodiment, the liner 134 is fabricated from SiOC.

[0100] Next, the third dielectric layer 136 of this embodiment is blanket-deposited directly onto the top of the structure 100 and onto the top of the liner 134, as illustrated, according to known techniques. More specifically, the third dielectric layer 136 is deposited to fill an additional opening 132 (Figure 9). The deposition thickness of the third dielectric layer 136 is not critical, as long as the additional opening 132 is completely filled with the third dielectric material.

[0101] The third dielectric layer 136 may include any suitable dielectric material, such as oxides, nitrides, silicon oxide (SiO2), silicon nitride (Si3N4), silicon hydride carbon oxide (SiCOH), carbon-rich silicon carbon nitride (SiCN), silicon-based low-κ dielectrics, porous dielectrics, or some combination thereof. In embodiments, the third dielectric layer 136 may be formed using deposition techniques including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vapor deposition, spin-on coating, or sputtering.

[0102] For example, in one embodiment, the third dielectric layer 136 is made from silicon hydride carbon oxide (SiCOH). In another embodiment, the third dielectric layer 136 is made from carbon-rich silicon carbonitride (SiCN). In all cases, the third dielectric layer 136 should be formed from a dielectric material having appropriate etching selectivity for the liner 134, as described above. According to at least one embodiment, both the third dielectric layer 136 and the first dielectric layer 114 are made from the same low-κ dielectric. In at least another embodiment, both the third dielectric layer 136 and the first dielectric layer 114 are made from different low-κ dielectrics.

[0103] As illustrated, during the deposition of the third dielectric layer 136, an air gap 138 is formed within an additional opening 132. More specifically, a pinch-off occurs at the relatively narrow “mouth” of the additional opening 132, thus forming the air gap 138. While the formation of the air gap 138 is highly probable, it is also possible, and therefore explicitly intended, that the air gap 138 may not form at all, or may form only in a portion of the opening 132.

[0104] Referring now to Figure 11, the structure 100 after the third dielectric layer 136 has been removed, according to an embodiment of the invention, is shown.

[0105] The third dielectric layer 136 of this embodiment is reset according to known techniques, as illustrated. Specifically, one or more preferred etching techniques, such as dry etching, wet etching, or a combination of both, may be used to reset the third dielectric layer 136. As illustrated, after etching, a portion of the third dielectric layer 136 remains in an additional opening 132 (Figure 9).

[0106] In all cases, the selected etching technique is selective to the liner 134. The liner 134, on the other hand, protects the underlying structures from etching. Specifically, the selectivity of the liner 134 protects the sacrificial mask 120, the second dielectric layer 118, the etching stop layer 116, and the first dielectric layer 114, as exemplified. Etching continues until a large portion of the liner 134 at the bottom of the trench 122 is exposed. Doing so makes it more likely that etching will continue until a small recess 140 is formed in or in the additional opening 132, as exemplified. The small recess 140 is neither important nor necessary, but it is merely a consequence of exposing the liner 134 at the bottom of the trench 122.

[0107] Referring now to Figure 12, the structure 100 after the liner 134 has been reset according to an embodiment of the present invention is shown.

[0108] The liner 134 of this embodiment is reset according to known techniques, as illustrated. Specifically, one or more preferred etching techniques, such as dry etching, wet etching, or a combination of both, may be used to reset the exposed portions of the liner 134. In all cases, the selected etching technique shall be selective to the underlying structures, such as the sacrificial mask 120, the second dielectric layer 118, the etching stop layer 116, the aligned upper vias 130, and the first dielectric layer 114, as illustrated.

[0109] Etching continues until most of the liner 134 is removed, leaving only a portion within the additional opening 132. Specifically, after etching, a portion of the liner 134 remains covered by the rest of the third dielectric layer 136. In all cases, etching of the liner 134 needs to expose the upper surface of the upper via 130. Doing so increases the likelihood that etching will continue until a small recess 140 is formed in or within the additional opening 132, as illustrated. The small recess 140 is neither important nor necessary, but it simply results in exposing the liner 134 at the bottom of the trench 122.

[0110] Referring now to Figures 13, 14, and 15, the structure 100 after the formation of the second metal wire 142 according to an embodiment of the present invention is shown. Figure 13 illustrates a cross-sectional view of the structure 100 shown in Figure 15, obtained along line XX. Figure 14 illustrates a cross-sectional view of the structure 100 shown in Figure 15, obtained along line YY. Figure 15 illustrates a cross-sectional view of the structure 100 shown in Figures 13 and 14, obtained along line ZZ. For clarity and understanding, some elements, such as the surrounding dielectric layer, are omitted in Figure 15.

[0111] The second metal wire 142 in this embodiment is formed in the trench 122 according to known techniques, as illustrated. Thus, the second metal wire 110 is embedded in the second dielectric layer 118. Although only a single second metal wire is illustrated in Figure 13, embodiments of the present invention explicitly intend to form multiple second metal wires, as shown in Figure 14.

[0112] The second metal wire 142 may include any suitable interconnect metal that can be readily deposited within a single damascene trench. For example, the second metal wire 142 may include aluminum, copper, ruthenium, cobalt, rhodium, iridium, nickel or alloys thereof, or similar, as desired for the application. In at least one embodiment, the second metal wire 142 is made from copper using a damascene method. The second metal wire 142 may be deposited using known techniques such as CVD, sputtering, electrochemical deposition, or similar processes. The thickness of the second metal wire 142 corresponds to the relative thickness of the second dielectric layer 118, which is approximately equal to the desired thickness of a typical metallization level, as previously described. In some embodiments, an adhesive layer (not shown) is first deposited within the trench 122 before the second metal wire 142 is deposited. In such cases, the adhesive layer may be a relatively thin layer of titanium nitride.

[0113] Generally, the second metal wire 142 is manufactured using a known damascene technique. Thus, the upper via 130 is also self-aligned with a single second metal wire 142. In other words, the upper via 130 is self-aligned with a single first metal wire 110 in the y direction and with a single second metal wire 142 in the x direction.

[0114] In summary, for the purposes of this description, the structure 100 illustrated in the figures and described herein includes a plurality of interconnect levels that are arranged to overlap each other and manufactured in a process flow. Embodiments of the present invention and the detailed description provided above primarily relate to the formation of upper vias 130 with improved performance characteristics (i.e., lower capacitance between metal levels).

[0115] As illustrated in Figures 13-15, the interconnect structure represented by structure 100 has several notable features. Unlike conventional structures, the masking material (e.g., mask 112) does not remain directly beneath the second metal wire 142 and between the first metal wire 110 and the second metal wire 142. After the formation of the upper via 130, the masks 112 in positions that would otherwise not be occupied by the upper via 130 typically remain in conventional structures. The presence of “residual” masks 112 directly between the first metal wire 110 and the second metal wire 142 results in an unwanted increase in capacitance between the metal levels. This unwanted capacitance between the metal levels is caused by the relatively high κ value of the “residual” masks 112. It should be noted that embodiments of the present invention specifically aim to remove any “residual” masks 112, as illustrated in the figures. Thus, by removing the “residual masks 112,” as described with reference to Figure 9, the unwanted capacitance between the metal levels is effectively reduced.

[0116] Additionally, the removed portion of the mask 112 is replaced with dielectric material, which in some cases results in an air gap 138. Such air gaps 138 exist in those locations where the “residual” mask 112 was removed. The formation of the air gaps 138 is highly process-dependent, and therefore, it is further intended to be explicitly intended that in some embodiments, the air gaps 138 may not exist at all. In some embodiments, it is further intended to be explicitly intended that the air gaps 138 may exist in only some areas and not in others.

[0117] Continuing to refer to Figures 13-15, according to the embodiment, the structure 100 includes a first metal wire 110 embedded in a first dielectric layer 114, a second metal wire 142 embedded in a second dielectric layer 118, where the second metal wire 142 is arranged on top of the first metal wire 110, an upper via 130 extending between one of the first metal wires (110) and one of the second metal wires (142), where the upper via 130 is self-aligned with one of the first metal wires (110), and at least one air gap 138 positioned between the first metal wire 110 and the second metal wire 242 adjacent to the upper via 130.

[0118] Continuing to refer to Figures 13-15, according to the embodiment, the structure 100 further includes a dielectric liner 134 surrounding the sides and bottom of at least one air gap 138.

[0119] Continuing to refer to Figures 13-15, according to this embodiment, the dielectric liner 134 is in direct contact with all of the uppermost surfaces of the first metal wire directly below the second metal wire 142, except where the upper via 130 is located.

[0120] Continuing to refer to Figures 13-15, according to the embodiment, the structure 100 further includes a mask 112 that is on and in direct contact with the uppermost surface of the first metal wire 110, except where the first metal wire 110 is directly below the second metal wire 142, where the lowermost surface of the mask 112 is substantially coplanar with the lowermost surface of the upper via 130.

[0121] Continuing to refer to Figures 13-15, according to this embodiment, the lowest surface of the second metal wire 142 is below the uppermost surface of the first dielectric layer 114.

[0122] Referring again to Figures 13-15, according to the embodiment, the first metal wire 110 is in direct contact with the first dielectric layer 114 without a barrier liner, the upper via 130 is in direct contact with the first dielectric layer 114 without a barrier liner, and the second metal wire 142 is in direct contact with both the first dielectric layer 114 and the second dielectric layer 118 without a barrier liner.

[0123] Continuing to refer to Figures 13-15, according to this embodiment, the first metal wire 110 and the second metal wire 142 contain ruthenium.

[0124] Continuing to refer to Figures 13-15, according to the embodiment, the structure 100 includes a first metal wire 110 embedded in a first dielectric layer 114, a second metal wire 142 embedded in a second dielectric layer 118, where the second metal wire 142 is arranged on top of the first metal wire 110, an upper via 130 extending between one of the first metal wires (110) and one of the second metal wires (142), where the upper via 130 is self-aligned with one of the first metal wires (110), and at least one air gap 138 positioned between the first metal wire 110 and the second metal wire 142 adjacent to the upper via 130, where the at least one air gap 138 is at the same level as the upper via 130.

[0125] Continuing to refer to Figures 13-15, according to the embodiment, the structure 100 includes a first metal wire 110 embedded in a first dielectric layer 114, a second metal wire 142 embedded in a second dielectric layer 118, where the second metal wire 142 is aligned on top of the first metal wire 110, an upper via 130 extending between one of the first metal wires (110) and one of the second metal wires (142), where the upper via 130 is self-aligned with one of the first metal wires (110), and at least one air gap 138 positioned at the same level as the upper via 130, where the at least one air gap 138 is aligned at the intersection between the first metal wire 110 and the second metal wire 142 (see Figure 15).

[0126] Referring again to Figures 13-15, according to the embodiment, the structure 100 includes a first metal wire 110 embedded in a first dielectric layer 114, a second metal wire 142 embedded in a second dielectric layer 118, where the second metal wire 142 is arranged on top of the first metal wire 110, an upper via 130 extending between one of the first metal wires (110) and one of the second metal wires (142), where the upper via 130 is self-aligned with one of the first metal wires (110) and positioned at the same level as the upper via 130. The configuration includes at least one air gap 138, where the at least one air gap 138 is arranged at the intersection between the first and second metal wires (see Figure 15), a dielectric liner 134 surrounding the sides and bottom of the at least one air gap 138, a mask 112 that is on and in direct contact with the uppermost surface of the first metal wire 110, except where the first metal wire 110 is directly beneath the second metal wire 142, where the lowest surface of the mask 112 is substantially coplanar with the lowest surface of the upper via 130.

[0127] Referring here to Figure 16, an explanatory diagram of the second structure 200 (hereinafter referred to as structure 200) in an intermediate step of a method for manufacturing an interconnect structure according to an embodiment of the invention is shown. More specifically, as disclosed herein, the method may begin with a lower level 202 having a first metal layer 204 and a first hard mask layer 206 formed on top of it.

[0128] For the purposes of this description, lower level 202 represents one of the front-end obline device layer, middle obline metal layer, or back-end obline metal layer. In at least one example, lower level 202 may include one or more contacts or contact vias present in the front-end obline device layer or back-end obline metal layer. In yet another example, lower level 202 may include one or more metal wires, vias, or other conductors present in the middle obline metal layer or back-end obline metal layer.

[0129] The first metal layer 204 of this embodiment is formed directly on top of the lower level 202 according to known techniques. The first metal layer 204 may contain any suitable interconnect metal that can be readily removed by subtractive etching. For example, the first metal layer 204 may contain aluminum, copper, ruthenium, cobalt, rhodium, iridium, nickel or alloys thereof or similar, as desired for the application. In at least one embodiment, the first metal layer 204 is made from ruthenium for low electrical resistance and high resistance to electromigration. The first metal layer 204 may be deposited using known techniques such as CVD, sputtering, electrochemical deposition or similar processes. In embodiments, the thickness of the first metal layer 204 may be in the range of approximately 20 nm to approximately 100 nm; however, other thicknesses less than 20 nm and greater than 100 nm are explicitly intended. In some embodiments, an adhesive layer (not shown) is provided between the lower level 202 and the first metal layer 204. In such cases, the adhesive layer may be a relatively thin layer of titanium nitride.

[0130] Finally, the first hard mask layer 206 of this embodiment is formed directly on top of the first conductive layer 204 according to known techniques, as illustrated. The first hard mask layer 206 may include any known dielectric hard mask material suitable for facilitating subsequent patterning and etching techniques. In all cases, the first hard mask layer 206 is preferably made from a dielectric material that can be selectively etched or patterned with respect to the first dielectric layer (Figure 18) and the metal wire (210). For example, the first hard mask layer 206 may include nitrides such as silicon nitride, titanium nitride, tantalum nitride, aluminum nitride, or silicon carbon nitride. In at least one embodiment, for example, the first hard mask layer 206 is a layer of silicon nitride. In another embodiment, the first hard mask layer 206 is a layer of silicon carbon nitride. Finally, the first hard mask layer 206 is essentially sacrificial, as some or all of it is removed in a subsequent process and no longer exists in the final structure. The first hard mask layer 206 can be formed by any deposition technique, including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition.

[0131] The cumulative thickness of the first metal layer 204 and the first hard mask layer 206 is approximately equal to the desired thickness of a typical metallization level that extends over the lower level 202 and is subsequently formed. Specifically, the relative thickness of the first metal layer 204 corresponds to the desired height or thickness of a typical metal level (e.g., Mx-1), and the relative thickness of the first hard mask layer 206 corresponds to the desired height or thickness of a typical via level (e.g., Vx-1). In some embodiments, the thickness of the first hard mask layer 206 is substantially equal to the thickness of the first metal layer 204. In other embodiments, the first hard mask layer 206 may be thicker than the first metal layer 204. In yet another embodiment, the first hard mask layer 206 may be thinner than the first metal layer 204. It should be noted that the final heights of the subsequently formed metal wires and upper vias do not depend solely on the relative height or thickness of either the first metal layer 204 or the first hard mask layer 206, respectively.

[0132] Referring now to Figure 17, the structure 200 according to an embodiment of the invention is shown after the opening 208 has been patterned in the first metal layer 204 and the lower level 202 has been exposed.

[0133] The opening 208 in this embodiment is patterned in the structure 200 according to known techniques. The opening 208 can be patterned by applying a photoresist (not shown), exposing the photoresist to a desired pattern of radiation, and developing the exposed photoresist using a conventional resist developer. The pattern in the photoresist can then be transferred to the first hard mask layer 206 and the first metal layer 204 according to known techniques. For example, one or more preferred etching techniques, such as dry etching, wet etching, or a combination of both, can be used to pattern the opening 208.

[0134] After patterning, as illustrated, the remaining portion of the first hard mask layer 206 becomes a plurality of individual masks 212, and the remaining portion of the first metal layer 204 becomes the first metal wire 210. The first metal wire 210 formed according to the process described herein is formed according to a conventional subtractive technique.

[0135] Generally, the apertures 208 and, similarly, the first metal wire 210 may be separated according to lithography limitations, ground rules, or both. In some embodiments, the apertures 208 are separated by equal distances, however, this is not mandatory. Finally, for illustrative purposes only, only three apertures 208 are shown in Figure 17. As is also known to those skilled in the art, any typical semiconductor structure has multiple back-end ob-line interconnect structures, and the structure 200 of the present invention also explicitly includes multiple apertures 208, although not shown in the figures.

[0136] Referring now to Figure 18, the structure 200 after the formation of the first dielectric layer 214 according to an embodiment of the invention is shown.

[0137] The first dielectric layer 214 of this embodiment is blanket-deposited on top of the structure 200, and more specifically, fills the opening 208 according to known techniques, as illustrated.

[0138] The first dielectric layer 214 may include any suitable dielectric material, such as oxides, nitrides, silicon oxide (SiO2), silicon nitride (Si3N4), silicon hydride carbon oxide (SiCOH), carbon-rich silicon carbon nitride (SiCN), silicon-based low-κ dielectrics, porous dielectrics, or some combination thereof. As used herein, the term "low-κ" refers to a material having a dielectric constant κ lower than that of silicon dioxide. In embodiments, the first dielectric layer 214 may be formed using deposition techniques including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vapor deposition, spin-on coating, or sputtering.

[0139] For example, in one embodiment, the first dielectric layer 214 is made from silicon carbon hydride (SiCOH). In another embodiment, the first dielectric layer 214 is made from carbon-rich silicon carbonitride (SiCN). In all cases, the first dielectric layer 214 should be made from a dielectric material having appropriate etching selectivity to the surrounding dielectric, e.g., the individual mask 212, and other materials subsequently formed as discussed below.

[0140] Finally, a chemical mechanical polishing technique is used to remove any unwanted excess dielectric material from the top surface of the structure 200. As a result, the top surface of the first dielectric layer 214 is coplanar or substantially coplanar with the top surface of the individual mask 212.

[0141] Referring now to Figure 19, the structure 200 after the formation of the planarization layer 224 and the second hard mask layer 226 according to an embodiment of the present invention is shown.

[0142] The planarization layer 224 of this embodiment is blanket-deposited directly onto the exposed surface of the structure 200 according to known techniques, as illustrated. The planarization layer 224 may be an organic planarization layer or a layer of material that can be planarized or etched by known techniques. In this embodiment, for example, the planarization layer 224 may be an amorphous carbon layer that can withstand the high temperatures of subsequent processing steps. The planarization layer 224 may preferably have a thickness sufficient to cover the existing structure.

[0143] Next, as illustrated, the second hard mask layer 226 of this embodiment is deposited directly onto the planarization layer 224 according to known techniques. The second hard mask layer 226 may include any known hard mask material suitable for facilitating subsequent patterning and etching techniques. In all cases, the second hard mask layer 226 is preferably made from a material that can be selectively etched or patterned with respect to the planarization layer 224 and other surrounding metallic features. Similar to the first hard mask layer 206, the second hard mask layer 126 may include, for example, a known anti-reflective coating such as SiARC, TiARC, TiOx, LTO, or SiON. Finally, the second hard mask layer 226 is essentially sacrificial, as it is removed in subsequent processes and no longer exists in the final structure. The second hard mask layer 226 may be formed by any deposition technique, including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. Finally, as illustrated, both the second hard mask layer 226 and the planarization layer 224 of this embodiment are patterned according to known techniques to form an opening 228. The opening 228 is arranged to expose a single individual mask 212, as illustrated. Similarly, the opening 228 is arranged directly over a single first metal wire 210, also as illustrated.

[0144] Referring now to Figure 20, the structure 200 according to an embodiment of the present invention is shown after removing the single individual mask 212 exposed at the bottom of the opening 228 and the second hard mask layer 226.

[0145] A single individual mask 212 and a second hard mask layer 226 exposed at the bottom of the opening 228 are selectively removed from the underlying structures according to known techniques, as exemplified. For example, in at least one embodiment, the single individual mask 212 is selectively removed from the first dielectric layer 214 and the first metal wire 210, and the second hard mask layer 226 is selectively removed from the planarization layer 224. One or more preferred etching techniques, such as dry etching, wet etching, or a combination thereof, may be used to remove the single individual mask 212 and the second hard mask layer 226. For example, preferred dry etching techniques may include, but are not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation. The primary objective of this etching is to remove the single individual mask 212, and the removal of the second hard mask layer 226 is a result when a similar hard mask material is used. Embodiments of the present invention explicitly intend to use a single individual mask 212 and a second hard mask layer 226 made of different hard mask materials, and therefore require an additional etching step to remove the second hard mask layer 226, although this is inefficient.

[0146] Referring now to Figure 21, the structure 200 according to an embodiment of the present invention is shown after the formation of the self-aligned upper via 230 and the removal of the planarization layer 224.

[0147] First, the self-aligned upper via 230 (hereinafter, upper via 230) of this embodiment is formed directly on top of a single first metal wire 210 according to known techniques, as illustrated. Specifically, the gap formed by removing a single individual mask 212 exposed at the bottom of the opening 228 (Figure 20) is filled with a conductive material to form the upper via 230. For example, known CVD or ALD techniques may be used to selectively deposit metals such as tungsten, ruthenium, aluminum, copper, ruthenium, cobalt, rhodium, iridium, nickel, or alloys thereof. In at least one embodiment, the upper via 230 is made from ruthenium for low electrical resistance and high resistance to electromigration. Thus, the upper via 230 is formed only in the gap formed by removing a single individual mask 212 exposed at the bottom of the opening 228 (Figure 20). Chemical mechanical polishing techniques are used to remove excess unwanted conductive material from the top surface of the structure 200. As a result, the uppermost surface of the first dielectric layer 114 is coplanar or substantially coplanar with the uppermost surface of the individual mask 212 and the uppermost surface of the first dielectric layer 214.

[0148] Additionally, combinations of the same or different materials may be used to produce the desired electrical resistance characteristics. For example, according to at least one embodiment, both the first metal wire 210 and the upper via 230 are made of ruthenium. According to another embodiment, the first metal wire 210 is made of ruthenium, and the upper via 230 is made of ruthenium, cobalt, or tungsten. According to yet another embodiment, the first metal wire 210 is made of tungsten, cobalt, or copper, and the upper via 230 is made of ruthenium. Ruthenium is particularly advantageous due to its excellent electromigration properties, thus eliminating the need for a barrier layer or liner layer. The resulting conductive structure, in this case the first metal wire 210 and the upper via 230, has a larger volume compared to a similar structure made of copper.

[0149] Additionally, the upper vias 230 are considered to be self-aligned with a single first metal wire 210. This is possible because the single first metal wire 210 is patterned based on a single individual mask 212, which then replaces the entire upper via 230. Additionally, the width of each upper via 230 is defined in the y direction by the individual mask 212, and the length of each upper via 230 is defined in the x direction by the flattening player 224.

[0150] Next, the planarization layer 224 is selectively removed from all underlying structures according to known techniques, as illustrated. For example, in at least one embodiment, the planarization layer 224 is removed by ashing.

[0151] Referring now to Figure 22, the structure 200 according to an embodiment of the present invention is shown after the remaining individual masks 212 have been removed.

[0152] The remaining individual masks 212 are selectively removed from the underlying structures according to known techniques, as illustrated, thereby forming additional openings 232. For example, in at least one embodiment, the remaining individual masks 212 are selectively removed from the first dielectric layer 214 and the first metal wire 210, as illustrated. One or more preferred etching techniques, such as dry etching, wet etching, or a combination of both, may be used to remove the remaining individual masks 212. For example, preferred dry etching techniques may include, but are not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation.

[0153] Referring now to Figure 23, the structure 200 after the formation of the second dielectric layer 218 according to an embodiment of the invention is shown.

[0154] First, the second dielectric layer 218 of this embodiment is blanket-deposited on top of the structure 200 according to known techniques, as illustrated. More specifically, the second dielectric layer 218 is deposited to fill an additional opening 232 (Figure 22). The deposition thickness of the second dielectric layer 218 is not critical, as long as the additional opening 232 is completely filled with the third dielectric material.

[0155] The second dielectric layer 218 may include any suitable dielectric material, such as oxides, nitrides, silicon oxide (SiO2), silicon nitride (Si3N4), silicon hydride carbon oxide (SiCOH), carbon-rich silicon carbon nitride (SiCN), silicon-based low-κ dielectrics, porous dielectrics, or some combination thereof. In embodiments, the second dielectric layer 218 may be formed using deposition techniques including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vapor deposition, spin-on coating, or sputtering.

[0156] For example, in one embodiment, the second dielectric layer 218 is made from silicon hydride carbon oxide (SiCOH). In another embodiment, the second dielectric layer 218 is made from carbon-rich silicon carbonitride (SiCN). According to at least one embodiment, both the second dielectric layer 218 and the first dielectric layer 214 are made from the same low-κ dielectric. In at least another embodiment, both the second dielectric layer 218 and the first dielectric layer 214 are made from different low-κ dielectrics.

[0157] As illustrated, during the deposition of the second dielectric layer 218, an air gap 238 is formed within an additional opening 232. More specifically, a pinch-off occurs at the relatively narrow “mouth” of the additional opening 232, thus forming the air gap 238. While the formation of an air gap 238 is highly probable, it is possible, and therefore explicitly intended, that an air gap 238 may not form at all, or may form only in a portion of the opening 232.

[0158] Referring now to Figures 24, 25, and 26, the structure 200 shown according to an embodiment of the invention after the formation of the second metal wire 242 and the third dielectric layer 236 is illustrated. Figure 24 illustrates a cross-sectional view of the structure 100 shown in Figure 26, obtained along line XX. Figure 25 illustrates a cross-sectional view of the structure 100 shown in Figure 26, obtained along line YY. Figure 26 illustrates a cross-sectional view of the structure 100 shown in Figures 24 and 25, obtained along line ZZ. For clarity and understanding, some elements, such as the surrounding dielectric layer, are omitted in Figure 26.

[0159] The second metal wire 242 in this embodiment is formed according to known techniques, as illustrated. Although only a single second metal wire is illustrated in Figure 24, embodiments of the present invention explicitly intend to form multiple second metal wires, as shown in Figures 25 and 26.

[0160] The second metal wire 242 may include any suitable interconnect metal that can be readily formed by conventional damascene or subtractive techniques. For example, the second metal wire 242 may include aluminum, copper, ruthenium, cobalt, rhodium, iridium, nickel or alloys thereof or similar, as desired for the application. In at least one embodiment, the second metal wire 242 is formed according to a known damascene technique. In at least another embodiment (not shown), the second metal wire 242 is formed subtractively from ruthenium for low electrical resistance and high resistance to electromigration. In the first subtractive scheme, the conductive material selected for the second metal wire 242 is blanket-deposited using a known technique such as CVD, sputtering, electrochemical deposition or a similar process. The thickness of the selected conductive material is approximately equal to the desired thickness at a typical metallization level, as previously described. In embodiments, the thickness of the blanket layer may be in the range of approximately 20 nm to approximately 100 nm; however, other thicknesses less than 20 nm and greater than 100 nm are explicitly intended. In some embodiments, an adhesive layer (not shown) is deposited first before the second metal wire 242 is deposited; however, this is not mandatory. In such cases, the adhesive layer may be a relatively thin layer of titanium nitride.

[0161] Generally, according to the illustrated embodiments, the second metal wire 242 is manufactured using a known subtractive technique. Thus, the upper via 230 is also not self-aligned with a single second metal wire 242. In other words, the upper via 230 is self-aligned with a single first metal wire 110 in the y direction, but not with a single second metal wire 142 in any direction. In an alternative embodiment, the second metal wire 242 was formed using a known damascene technique.

[0162] Finally, the second dielectric layer 236 of this embodiment is blanket-deposited on top of the structure 100 according to known techniques, as illustrated. Similar to the first dielectric layer 214, the second dielectric layer 236 may include any suitable dielectric material, e.g., oxides, nitrides, silicon oxide (SiO2), silicon nitride (Si3N4), silicon hydride carbon oxide (SiCOH), carbon-rich silicon carbon nitride (SiCN), silicon-based low-κ dielectrics, porous dielectrics, or some combination thereof. In embodiments, the second dielectric layer 236 may be formed using deposition techniques including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vapor deposition, spin-on coating, or sputtering.

[0163] For example, in one embodiment, the second dielectric layer 236 is made from silicon hydride carbon oxide (SiCOH). In another embodiment, the second dielectric layer 236 is made from carbon-rich silicon carbonitride (SiCN). According to at least one embodiment, the second dielectric layer 236 is made from the same dielectric material as the first dielectric layer 214. In at least another embodiment, the second dielectric layer 236 is made from a different material than the first dielectric layer 214.

[0164] The relative thickness of the second dielectric layer 236 is approximately equal to the desired thickness of a typical metallization level formed on and after the lower Mx-1 and Vx-1 levels. Specifically, the relative thickness of the second dielectric layer 236 corresponds to the desired height or thickness of a typical metal level (e.g., Mx).

[0165] In summary, for the purposes of this description, the structure 200 illustrated in the figures and described herein includes a plurality of interconnect levels that are arranged to overlap each other and manufactured in a process flow. Embodiments of the present invention and the detailed description provided above primarily relate to the subsequent formation of self-aligned upper vias 230 with improved performance characteristics (i.e., lower capacitance between metal levels).

[0166] As illustrated in Figures 24-26, the interconnect structure represented by structure 200 has several notable features. Unlike conventional structures, the masking material (e.g., mask 212) does not remain directly beneath the second metal wire 242 and between the first and second metal wires 210 and 242. After the formation of the upper via 230, the masks 212 in positions that would otherwise not be occupied by the upper via 230 typically remain in conventional structures. The presence of “residual” masks 112 directly between the first and second metal wires 210 and 242 results in an unwanted increase in capacitance between the metal levels. This unwanted capacitance between the metal levels is caused by the relatively high κ value of the “residual” masks 212. It should be noted that embodiments of the present invention specifically aim to remove any “residual” masks 212, as illustrated in the figures. Thus, by removing the “residual masks 212,” as described with reference to Figure 22, the unwanted capacitance between the metal levels is effectively reduced. As further illustrated in Figure 26, all remaining portions of the mask 212 are removed except where the upper via 230 is present. Additionally, the removed portions of the mask 212 are replaced with dielectric material, which in some cases results in an air gap 238. Such air gaps 238 are present in those locations where the “residual” mask 212 was removed. The formation of the air gaps 238 is highly process-dependent, and therefore, it is further intended to be explicitly intended that in some embodiments, there may be no air gaps 238 at all. It is further intended to be explicitly intended that in some embodiments, the air gaps 238 may be present in only some areas and not in others.

[0167] Continuing to refer to Figures 24-26, according to the embodiment, the structure 200 includes a first metal wire 210 embedded in a first dielectric layer 214, a second metal wire 242 embedded in a second dielectric layer 236, where the second metal wire 242 is arranged on top of the first metal wire 210, an upper via 230 extending between one of the first metal wires (210) and one of the second metal wires (242), where the upper via 130 is self-aligned with one of the first metal wires (210), and at least one air gap 238 positioned between the first metal wire 210 and the second metal wire 242 adjacent to the upper via 230.

[0168] Referring again to Figures 24-26, according to the embodiment, the first metal wire 210 is in direct contact with the first dielectric layer 214 without a barrier liner, the upper via 230 is in direct contact with the first dielectric layer 214 without a barrier liner, and the second metal wire 242 is in direct contact with both the first dielectric layer 214 and the second dielectric layer 236 without a barrier liner.

[0169] Continuing to refer to Figures 24-26, according to the embodiment, the structure 200 includes a first metal wire 210 embedded in a first dielectric layer 214, a second metal wire 242 embedded in a second dielectric layer 236, where the second metal wire 242 is arranged on top of the first metal wire 210, an upper via 230 extending between one of the first metal wires (210) and one of the second metal wires (242), where the upper via 230 is self-aligned with one of the first metal wires (210), and at least one air gap 238 positioned between the first metal wire 210 and the second metal wire 242, adjacent to the upper via 230, where the at least one air gap 238 is at the same level as the upper via 230.

[0170] Continuing to refer to Figures 24-26, according to the embodiment, the structure 200 includes a first metal wire 210 embedded in a first dielectric layer 214, a second metal wire 242 embedded in a second dielectric layer 236, where the second metal wire 242 is arranged on top of the first metal wire 210, an upper via 230 extending between one of the first metal wires (210) and one of the second metal wires (242), where the upper via 230 is self-aligned with one of the first metal wires (210), and at least one air gap 238 positioned at the same level as the upper via 230, where the at least one air gap 238 is arranged at the intersection between the first metal wire 210 and the second metal wire 242 (see Figure 26).

[0171] Continuing to refer to Figures 24-26, according to the embodiment, the structure 200 comprises a first metal wire 210 embedded in a first dielectric layer 214, a second metal wire 242 embedded in a second dielectric layer 236, where the second metal wire 242 is arranged on top of the first metal wire 210, an upper via 230 extending between one of the first metal wires (210) and one of the second metal wires (242), where the upper via 230 is self-aligned with one of the first metal wires (210), a dielectric plug 218 positioned at the same level as the upper via 230 and directly above all of the first metal wires 110 except where the upper via 230 is located, and at least one air gap 238 located within at least one of the dielectric plugs 218 that is separated from both the first dielectric layer 214 and the second dielectric layer 236.

[0172] Continuing to refer to Figures 24-26, according to this embodiment, each dielectric plug 218 is self-aligned with each of the first metal wires 210.

[0173] For reference purposes, the measurement result obtained in the x-direction parallel to the first metal wires 110 and 210 is referred to herein as "length," while the measurement result obtained in the y-direction perpendicular to the first metal wires 110 and 210 is referred to herein as "width."

[0174] The descriptions of various embodiments of the present invention have been presented for illustrative purposes only and are not intended to be comprehensive or limitful to the embodiments disclosed. Many modifications and variations will become apparent to those skilled in the art without departing from the scope and spirit of the invention. The terms used herein have been selected to best describe the principles, practical applications, or technical improvements to the technologies available on the market of the embodiments, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A first metal wire embedded in the first dielectric layer; A second metal wire is embedded in the second dielectric layer, where the second metal wire is arranged on top of the first metal wire; An upper via extending between one of the first metal wires and one of the second metal wires, wherein the upper via is self-aligned with the one of the first metal wires; and at least one air gap positioned between the first and second metal wires, adjacent to the upper via. A semiconductor structure comprising the features described above.

2. Dielectric liner surrounding the sides and bottom of at least one air gap The semiconductor structure according to claim 1, further comprising the above.

3. The semiconductor structure according to claim 2, wherein the dielectric liner is in direct contact with all of the uppermost surfaces of the first metal wire that are directly below the second metal wire, except where the upper via is located.

4. A mask (112) that is on the uppermost surface of the first metal wire and in direct contact with it, except where the first metal wire is directly below the second metal wire, wherein the lowest surface of the mask is substantially coplanar with the lowest surface of the upper via. The semiconductor structure according to claim 1, further comprising the above.

5. The semiconductor structure according to claim 1, wherein the lowest surface of the second metal wire is below the uppermost surface of the first dielectric layer.

6. The semiconductor structure according to claim 1, wherein the first metal wire is in direct contact with the first dielectric layer (114) without a barrier liner, the upper via is in direct contact with the first dielectric layer (114) without a barrier liner, and the second metal wire is in direct contact with both the first dielectric layer (114) and the second dielectric layer (118) without a barrier liner.

7. The semiconductor structure according to claim 1, wherein the first metal wire and the second metal wire contain ruthenium.

8. A first metal wire embedded in the first dielectric layer; A second metal wire is embedded in the second dielectric layer, where the second metal wire is arranged on top of the first metal wire; An upper via extending between one of the first metal wires and one of the second metal wires, wherein the upper via is self-aligned with the one of the first metal wires; and At least one air gap is disposed between the first metal wire and the second metal wire adjacent to the upper via, wherein the at least one air gap is at the same level as the upper via. A semiconductor structure comprising the features described above.

9. Dielectric liner surrounding the sides and bottom of at least one air gap The semiconductor structure according to claim 8, further comprising the above.

10. The semiconductor structure according to claim 9, wherein the dielectric liner is in direct contact with all of the uppermost surfaces of the first metal wire that are directly below the second metal wire, except where the upper via is located.

11. A mask (112) that is on the uppermost surface of the first metal wire and in direct contact with it, except where the first metal wire is directly below the second metal wire, wherein the lowest surface of the mask is substantially coplanar with the lowest surface of the upper via. The semiconductor structure according to claim 8, further comprising the above.

12. The semiconductor structure according to claim 8, wherein the lowest surface of the second metal wire is below the uppermost surface of the first dielectric layer.

13. The semiconductor structure according to claim 8, wherein the first metal wire is in direct contact with the first dielectric layer without a barrier liner, the upper via is in direct contact with the first dielectric layer without a barrier liner, and the second metal wire is in direct contact with both the first dielectric layer and the second dielectric layer without a barrier liner.

14. The semiconductor structure according to claim 8, wherein the first metal wire and the second metal wire contain ruthenium.

15. A first metal wire embedded in the first dielectric layer; A second metal wire is embedded in the second dielectric layer, where the second metal wire is arranged on top of the first metal wire; An upper via extending between one of the first metal wires and one of the second metal wires, wherein the upper via is self-aligned with the one of the first metal wires; and At least one air gap located at the same level as the upper via, wherein the at least one air gap is arranged at the intersection between the first metal wire and the second metal wire. A semiconductor structure comprising the features described above.

16. Dielectric liner surrounding the sides and bottom of at least one air gap The semiconductor structure according to claim 15, further comprising the above.

17. The semiconductor structure according to claim 16, wherein the dielectric liner is in direct contact with all of the uppermost surfaces of the first metal wire that are directly below the second metal wire, except where the upper via is located.

18. A mask (112) that is on the uppermost surface of the first metal wire and in direct contact with it, except where the first metal wire is directly below the second metal wire, wherein the lowest surface of the mask is substantially coplanar with the lowest surface of the upper via. The semiconductor structure according to claim 15, further comprising the above.

19. The semiconductor structure according to claim 15, wherein the lowest surface of the second metal wire is below the uppermost surface of the first dielectric layer.

20. The semiconductor structure according to claim 15, wherein the first metal wire is in direct contact with the first dielectric layer without a barrier liner, the upper via is in direct contact with the first dielectric layer without a barrier liner, and the second metal wire is in direct contact with both the first dielectric layer and the second dielectric layer without a barrier liner.

21. The semiconductor structure according to claim 15, wherein the first metal wire and the second metal wire contain ruthenium.

22. A first metal wire embedded in the first dielectric layer; A second metal wire is embedded in the second dielectric layer, where the second metal wire is arranged on top of the first metal wire; An upper via extending between one of the first metal wires and one of the second metal wires, wherein the upper via is self-aligned with the one of the first metal wires; At least one air gap positioned at the same level as the upper via, wherein the at least one air gap is located at the intersection of the first metal wire and the second metal wire; A dielectric liner surrounding the sides and bottom of the at least one air gap; and A mask (112) is located on the uppermost surface of the first metal wire and in direct contact with it, except where the first metal wire is directly beneath the second metal wire, where the lowest surface of the mask is substantially coplanar with the lowest surface of the upper via. A semiconductor structure comprising the features described above.

23. The semiconductor structure according to claim 22, wherein the dielectric liner is in direct contact with all of the uppermost surfaces of the first metal wire that are directly below the second metal wire, except where the upper via is located.

24. A first metal wire embedded in the first dielectric layer; A second metal wire is embedded in the second dielectric layer, where the second metal wire is arranged on top of the first metal wire; An upper via extending between one of the first metal wires and one of the second metal wires, wherein the upper via is self-aligned with the one of the first metal wires; A dielectric plug positioned at the same level as the upper via and directly above all of the first metal wires except where the upper via is located; and at least one air gap located within at least one of the dielectric plugs, which is separated from both the first dielectric layer and the second dielectric layer. A semiconductor structure comprising the features described above.

25. The semiconductor structure according to claim 24, wherein each of the dielectric plugs is self-aligned with each of the first metal wires.

Images