Light-emitting element and display device containing the same

Abstract

A light-emitting element according to one embodiment includes a first semiconductor layer, an active layer, and a second semiconductor layer arranged sequentially along one direction, and M1 surrounding the outer periphery of the first semiconductor layer, the active layer, and the second semiconductor layer. x O y A first insulating film containing a type oxide, and surrounding the first insulating film, M2 2x O (2y-1) A second insulating film containing a type oxide, and surrounding the second insulating film, M3 x O y The material comprises a third insulating film containing a type oxide and a fourth insulating film surrounding the third insulating film, wherein M1, M2, and M3 are each metallic substances, and x and y can each be natural numbers.

Description

Technical Field

[0001] Embodiments of the present invention relate to a light-emitting element and a display device including the same.

Background Art

[0002] With the development of multimedia, display devices have become increasingly important. Accordingly, various display devices such as liquid crystal display devices and organic light-emitting display devices are being developed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved by the present invention is to provide a light-emitting element with improved reliability and a display device including the same.

[0004] The problems of the present invention are not limited to the above-described technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0005] A light-emitting element according to an embodiment includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially arranged along one direction, and a first insulating film surrounding outer peripheral surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer and including an M1 x O y type oxide, a second insulating film surrounding the first insulating film and including an M2 2x O (2y-1) type oxide, a third insulating film surrounding the second insulating film and including an M3 x O y type oxide, and a fourth insulating film surrounding the third insulating film. The M1, M2, and M3 are each a metallic substance, and the x and y can each be a natural number.

[0006] The sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film may be 10 nm or less.

[0007] The fourth insulating film may have a thickness greater than the sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film.

[0008] The thickness of the first insulating film may be greater than the thickness of the second insulating film.

[0009] The thickness of the third insulating film may be greater than or equal to the thickness of the second insulating film.

[0010] The first insulating film may contain an M1O2 type oxide, the second insulating film may contain an M22O3 type oxide, and the third insulating film may contain an M3O2 type oxide.

[0011] The first insulating film contains at least one oxide from among SiO2, ZrO2, HfO2, GeO2, TiO2, and TeO2, and the second insulating film may contain at least one oxide from among Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3, and Yb2O3.

[0012] The third insulating film may contain at least one oxide from among SiO2, ZrO2, HfO2, GeO2, TiO2, and TeO2.

[0013] The first insulating film may contain ZrO2, the second insulating film may contain Al2O3, and the third insulating film may contain ZrO2.

[0014] The light-emitting element may further include a fifth insulating film that surrounds the fourth insulating film and has a thickness greater than the thickness of the fourth insulating film.

[0015] The fourth insulating film is an inorganic film containing an oxide, and the fifth insulating film may be an inorganic film containing an oxide different from the material of the fourth insulating film.

[0016] The light-emitting device according to one embodiment includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially arranged along one direction, and surrounds the outer peripheral surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer, and M1 x O y a first insulating film containing an oxide of type M1; surrounds the first insulating film, and M2 2x O (2y-1) a second insulating film containing an oxide of type M2; surrounds the second insulating film, and M3 x O y It may include a third insulating film containing an oxide of type M3. The M1, M2, and M3 are each a metallic substance, and the x and y may each be natural numbers. The thickness of the first insulating film is greater than the thickness of the second insulating film, and the thickness of the third insulating film may be greater than or equal to the thickness of the second insulating film.

[0017] The total thickness of the first insulating film, the second insulating film, and the third insulating film may be 10 nm or less.

[0018] The first insulating film contains an M1O2-type oxide, the second insulating film contains an M22O3-type oxide, and the third insulating film may contain an M3O2-type oxide.

[0019] The first insulating film contains at least one oxide of SiO2, ZrO2, HfO2, GeO2, TiO2, TeO2, and the second insulating film may contain at least one oxide of Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3, Yb2O3.

[0020] The third insulating film may contain at least one oxide of SiO2, ZrO2, HfO2, GeO2, TiO2, TeO2.

[0021] The first insulating film contains ZrO2, the second insulating film contains Al2O3, and the third insulating film may contain ZrO2.

[0022] The light-emitting device may further include a fourth insulating film that surrounds the third insulating film and has a thickness greater than the total thickness of the first insulating film, the second insulating film, and the third insulating film.

[0023] The light-emitting element may further include a fifth insulating film that surrounds the fourth insulating film and has a thickness greater than the thickness of the fourth insulating film.

[0024] A display device according to one embodiment may include a pixel comprising a first electrode and a second electrode spaced apart from each other, and a light-emitting element electrically connected between the first electrode and the second electrode. The light-emitting element comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged sequentially along one direction, and M1 surrounding the outer periphery of the first semiconductor layer, the active layer and the second semiconductor layer. x O y A first insulating film containing a type oxide, and surrounding the first insulating film, M2 2x O (2y-1) A second insulating film containing a type oxide, and surrounding the second insulating film, M3 x O y The material may include a third insulating film containing a type oxide and a fourth insulating film surrounding the third insulating film. M1, M2, and M3 are each metallic substances, and x and y can each be natural numbers.

[0025] The sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film may be 10 nm or less.

[0026] The fourth insulating film may have a thickness greater than the sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film.

[0027] The thickness of the first insulating film may be greater than the thickness of the second insulating film, and the thickness of the third insulating film may be greater than or equal to the thickness of the second insulating film.

[0028] The first insulating film may contain an M1O2 type oxide, the second insulating film may contain an M22O3 type oxide, and the third insulating film may contain an M3O2 type oxide.

[0029] The first insulating film contains at least one oxide from among SiO2, ZrO2, HfO2, GeO2, TiO2, and TeO2, and the second insulating film may contain at least one oxide from among Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3, and Yb2O3.

[0030] The third insulating film may contain at least one oxide from among SiO2, ZrO2, HfO2, GeO2, TiO2, and TeO2.

[0031] The first insulating film may contain ZrO2, the second insulating film may contain Al2O3, and the third insulating film may contain ZrO2.

[0032] The light-emitting element may further include a fifth insulating film that surrounds the fourth insulating film and has a thickness greater than the thickness of the fourth insulating film.

[0033] The fourth insulating film is an inorganic film containing an oxide, and the fifth insulating film may be an inorganic film containing an oxide different from the material of the fourth insulating film.

[0034] The pixel may further include a first alignment electrode and a second alignment electrode, which are located below the light-emitting element and spaced apart from each other.

[0035] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0036] The light-emitting element according to the embodiment may include a multilayer oxide insulating film surrounding a first semiconductor layer, an active layer, and a second semiconductor layer. The multilayer oxide insulating film is M1 x O y First insulating film containing type oxide, M2 2x O (2y-1) A second insulating film containing a type oxide, and M3 x O y It may include a third insulating film containing a type oxide.

[0037] According to the embodiment, oxygen flowing into the light-emitting element can be captured by oxygen vacancies formed at the interfaces of the first, second, and third insulating films. This can improve the reliability of the light-emitting element.

[0038] The display device according to this embodiment may include pixels containing the light-emitting element. This can improve the reliability of the display device.

[0039] The effects of the embodiments are not limited to those exemplified above, and a wider variety of effects are included herein. [Brief explanation of the drawing]

[0040] [Figure 1] This is a schematic perspective view showing a light-emitting element according to one embodiment. [Figure 2] This is a schematic cross-sectional view showing a light-emitting element according to one embodiment. [Figure 3] This is a cross-sectional view showing a light-emitting element according to one embodiment. [Figure 4] This is a cross-sectional view showing a light-emitting element according to one embodiment. [Figure 5] This figure shows the interfacial reaction occurring in a multilayer oxide insulating film according to one embodiment, and the oxygen vacancies formed thereby. [Figure 6] This graph shows the brightness maintenance rate of a light-emitting element according to the materials that make up the multilayer oxide insulating film. [Figure 7] This graph shows the brightness maintenance rate of the light-emitting element according to the thickness of the first insulating film. [Figure 8] This graph shows the brightness maintenance rate of the light-emitting element according to the thickness of the second insulating film. [Figure 9] This graph shows the brightness maintenance rate of the light-emitting element according to the thickness of the third insulating film. [Figure 10] This is a plan view showing a display device according to an embodiment. [Figure 11] This is a circuit diagram showing a pixel according to one embodiment. [Figure 12] This is a circuit diagram showing a pixel according to one embodiment. [Figure 13] This is a plan view showing pixels according to one embodiment. [Figure 14] This is a cross-sectional view showing a display device according to one embodiment. [Figure 15] This figure shows a magnified view of a region of the pixels shown in Figure 14. [Figure 16] This figure shows a magnified view of a region of the light-emitting element shown in Figure 15. [Figure 17] This figure shows a magnified view of a region of the light-emitting element shown in Figure 15. [Modes for carrying out the invention]

[0041] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the embodiments described below in detail, along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be realized in a variety of different forms, and these embodiments are provided merely to complete the disclosure of the present invention and to fully inform those who are ordinary skill in the art to which the invention pertains, of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0042] When elements or layers are referred to as "on" other elements or layers, this includes all cases where other layers or elements are interposed immediately above or between other elements. Reference numerals identical throughout the specification refer to the same component. The shapes, sizes, proportions, angles, numbers, etc., shown in the drawings illustrating embodiments are illustrative and the invention is not limited to those shown.

[0043] The features of each of the various embodiments of the present invention can be combined or linked together, either partially or entirely, allowing for a wide range of technically diverse interlocking and driving mechanisms. Each embodiment can be implemented independently of the others or in conjunction with them.

[0044] The following describes specific embodiments with reference to the attached drawings.

[0045] Figure 1 is a schematic perspective view showing a light-emitting element LD according to one embodiment. Figure 2 is a schematic cross-sectional view showing a light-emitting element LD according to one embodiment. For example, Figure 2 schematically shows a cross-section of the light-emitting element LD of Figure 1.

[0046] Referring to Figures 1 and 2, the light-emitting element LD may include a light-emitting laminate LES, a multilayer oxide insulating film MLO, and a protective film PRL. In one embodiment, the light-emitting element LD may be provided in a rod shape. For the purposes of describing the embodiment, the rod shape may include various forms of rod-like shapes or bar-like shapes, such as cylindrical or polygonal prism shapes, and its cross-sectional shape is not particularly limited. In one embodiment, the length L of the light-emitting element LD may be greater than its diameter D (or the width of its cross-section).

[0047] A light-emitting laminate (LES), also called a "light-emitting element" or "light-emitting structure," may include semiconductor layers of different conductivity types and an active layer disposed between the semiconductor layers. The light-emitting laminate LES may further selectively include at least one electrode layer.

[0048] The multilayer oxide insulating film MLO may surround the outer circumferential surface of the light-emitting laminate LES (e.g., the sides of a rod-shaped light-emitting laminate LES). The multilayer oxide insulating film MLO may expose both ends of the light-emitting laminate LES (e.g., the two bottom surfaces of a rod-shaped light-emitting laminate LES). The multilayer oxide insulating film MLO may include at least two insulating films containing different oxides. The at least two insulating films may be thin films. As an example, the multilayer oxide insulating film MLO may include insulating films whose total thickness is 10 nm or less. Limiting the thickness of the multilayer oxide insulating film MLO to 10 nm or less can prevent or reduce the influence of the multilayer oxide insulating film MLO on the properties of the light-emitting laminate LES.

[0049] The protective film PRL may surround the multilayer oxide insulating film MLO and expose both ends of the light-emitting laminate LES (for example, both bottom surfaces of a rod-shaped light-emitting laminate LES). The protective film PRL may consist of a single insulating film or may include two or more insulating films.

[0050] The protective film PRL can be formed to stably protect the light-emitting laminate LES and the multilayer oxide insulating film MLO during the manufacturing process of the light-emitting element LD and / or other subsequent processes (e.g., the pixel process for forming pixels of a display device using the light-emitting element LD). For example, the protective film PRL can be formed to a thickness sufficient to allow the light-emitting element LD to remain even if some of its thickness is etched away by over-etching that may occur during the manufacturing process of the light-emitting element LD, such as the etching of the multilayer oxide insulating film MLO and the upper surface of the protective film PRL, and / or the pixel process for forming pixels of a display device using the light-emitting element LD (e.g., the etching process for forming pixel electrodes connected to both ends of the light-emitting element LD).

[0051] For example, the protective film PRL may be formed with a thickness sufficient to stably surround the light-emitting laminate LES and the multilayer oxide insulating film MLO, including any over-etching margins that may occur in subsequent processes. In one embodiment, the protective film PRL may include at least one insulating film having a thickness greater than or equal to the thickness of the multilayer oxide insulating film MLO (for example, a thickness of approximately 10 nm or more).

[0052] In one embodiment, the light-emitting diode (LD) may have a small size in the range of nanometers to micrometers. For example, each light-emitting diode (LD) may have a diameter D (or cross-sectional width) and / or length L in the range of nanometers to micrometers. As an example, the light-emitting diode (LD) may have a diameter D and / or length L in the range of approximately tens of nanometers to tens of micrometers.

[0053] The structure, shape, size, and / or type of the light-emitting diode (LD) can be modified depending on the embodiment. For example, the structure, shape, size, and / or type of the light-emitting diode (LD) can be varied depending on the design conditions of the light-emitting device using the LD and the light-emitting characteristics to be secured.

[0054] Light-emitting devices including light-emitting diodes (LDs) can be used in various devices that require a light source. For example, light-emitting diodes (LDs) can be placed in the pixels of a display device and used as the light source for the pixels. Light-emitting diodes (LDs) can also be used in other types of devices that require a light source, such as lighting devices.

[0055] In one embodiment, the light-emitting element LD can be surface-treated using a hydrophobic material. This prevents the light-emitting element LD from aggregating when it is supplied to each light-emitting region (for example, the light-emitting region of each pixel and / or subpixel) by an inkjet method or the like.

[0056] Figure 3 is a cross-sectional view showing a light-emitting element LD according to one embodiment. For example, Figure 3 shows one embodiment of a cross-section (e.g., a longitudinal section) of a light-emitting element LD corresponding to the line I-I' in Figure 1.

[0057] Figure 4 is a cross-sectional view showing a light-emitting element LD according to one embodiment. For example, Figure 4 shows another embodiment of the cross-section of the light-emitting element LD corresponding to the line I-I' in Figure 1. Compared with the embodiment in Figure 3, the embodiment in Figure 4 further includes a fifth insulating film INF5 in the light-emitting element LD.

[0058] Referring to Figures 1 and 2, as well as Figures 3 and 4, the light-emitting element LD may include a light-emitting laminate LES comprising a first semiconductor layer SCL1, an active layer ACT (also called the “light-emitting layer”), and a second semiconductor layer SCL2, which are sequentially arranged and / or stacked along one direction (e.g., longitudinal or height). The light-emitting laminate LES may further selectively include an electrode layer ETL. The light-emitting element LD may further include a multilayer oxide insulating film MLO and a protective film PRL surrounding the light-emitting laminate LES.

[0059] The light-emitting element LD may include a first end EP1 and a second end EP2. In one embodiment, the first end EP1 and the second end EP2 may face each other. For example, the light-emitting element LD may include a first end EP1 and a second end EP2 at both ends in the longitudinal (or height) direction. The first end EP1 of the light-emitting element LD may include the first bottom surface (e.g., the top surface) and / or its surrounding area. The second end EP2 of the light-emitting element LD may include the second bottom surface (e.g., the bottom surface) and / or its surrounding area.

[0060] In one embodiment, the first semiconductor layer SCL1, the active layer ACT, the second semiconductor layer SCL2, and the electrode layer ETL may be arranged sequentially from the second end EP2 to the first end EP1 of the light-emitting element LD. For example, the electrode layer ETL (or the second semiconductor layer SCL2) may be arranged at the first end EP1 of the light-emitting element LD, and the first semiconductor layer SCL1 (or another electrode layer adjacent to the first semiconductor layer SCL1 and electrically connected to the first semiconductor layer SCL1) may be arranged at the second end EP2 of the light-emitting element LD.

[0061] In the embodiment shown in Figure 3, the electrode layer ETL is described as being included in the light-emitting laminate LES, but the embodiments are not limited to this. For example, the electrode layer ETL may be formed separately from the light-emitting laminate LES and placed on the light-emitting laminate LES.

[0062] In one embodiment, the light-emitting laminate LES (or light-emitting element LD comprising the light-emitting laminate LES) may further include at least one other semiconductor layer (e.g., at least one other semiconductor layer disposed above and / or below the active layer ACT) and / or at least one other electrode layer (e.g., an additional electrode layer disposed around the first semiconductor layer SCL1).

[0063] The first semiconductor layer SCL1 may include a semiconductor layer of a first conductivity type containing a dopant of a first conductivity type. For example, the first semiconductor layer SCL1 may be an N-type semiconductor layer containing an N-type dopant.

[0064] In one embodiment, the first semiconductor layer SCL1 may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the first semiconductor layer SCL1 may include a nitride-based semiconductor material containing at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material containing at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The first semiconductor layer SCL1 may also contain other materials.

[0065] In one embodiment, the first semiconductor layer SCL1 may contain an N-type dopant such as Si, Ge, or Sn. The first semiconductor layer SCL1 may also contain other dopants.

[0066] The active layer ACT (also called the "emissive layer") may be placed on the first semiconductor layer SCL1. The active layer ACT may include a single or multiple quantum well (QW) structure. When a voltage above a threshold voltage is applied across the light-emitting element LD, electron-hole pairs may recombine in the active layer ACT, thereby causing light to be emitted from the light-emitting element LD.

[0067] In one embodiment, the active layer ACT can emit light in the visible light wavelength range, for example, light in the wavelength range of approximately 400 nm to 900 nm. For example, the active layer ACT can emit blue light with a peak wavelength in the range of approximately 440 nm to 480 nm, green light with a peak wavelength in the range of approximately 510 nm to 550 nm, or red light with a peak wavelength in the range of approximately 610 nm to 650 nm. The active layer ACT can also emit light of other colors and / or wavelength ranges other than those exemplified above.

[0068] In one embodiment, the active layer ACT may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the active layer ACT may include a nitride-based semiconductor material containing at least one of GaN, AlGaN, InGaN, InGaAlN, AlN, InN, and AlInN, or a phosphide-based semiconductor material containing at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The active layer ACT may also contain other materials.

[0069] The second semiconductor layer SCL2 may be placed on the active layer ACT. The second semiconductor layer SCL2 may include a semiconductor layer of the second conductivity type containing a dopant of the second conductivity type. For example, the second semiconductor layer SCL2 may be a P-type semiconductor layer containing a P-type dopant.

[0070] In one embodiment, the second semiconductor layer SCL2 may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the second semiconductor layer SCL2 may include a nitride-based semiconductor material containing at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material containing at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The second semiconductor layer SCL2 may also contain other materials.

[0071] In one embodiment, the second semiconductor layer SCL2 may contain a P-type dopant such as Mg. The second semiconductor layer SCL2 may also contain other dopants.

[0072] In one embodiment, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 may contain the same semiconductor material (e.g., the same nitride-based semiconductor material) but may contain dopants of different conductivity types. In another embodiment, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 may contain different semiconductor materials and dopants of different conductivity types.

[0073] In one embodiment, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 may have different lengths (or thicknesses) in the longitudinal direction of the light-emitting element LD. For example, the first semiconductor layer SCL1 may have a longer length (or greater thickness) than the second semiconductor layer SCL2 along the longitudinal direction of the light-emitting element LD. This allows the active layer ACT to be located closer to the first end EP1 (e.g., the P-type end) than to the second end EP2 (e.g., the N-type end).

[0074] The electrode layer ETL may be placed on the second semiconductor layer SCL2. The electrode layer ETL may be an electrode that protects the second semiconductor layer SCL2 and smoothly connects the second semiconductor layer SCL2 to at least one circuit element, electrode and / or wiring. For example, the electrode layer ETL may be an ohmic contact electrode or a Schottky contact electrode.

[0075] Depending on the embodiment, the electrode layer ETL may contain a metal or a metal oxide. For example, the electrode layer ETL may be formed by metals such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), or copper (Cu), their oxides or alloys, or transparent conductive materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), or In2O3 (Indium Oxide), either alone or in mixtures. The electrode layer ETL may also be formed from other materials.

[0076] In one embodiment, the electrode layer ETL may be substantially transparent. This allows light generated by the light-emitting element LD to pass through the electrode layer ETL.

[0077] A multilayer oxide insulating film MLO can surround the light-emitting laminate LES. For example, the multilayer oxide insulating film MLO can surround at least the outer periphery (e.g., sides) of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2. In embodiments in which the light-emitting element LD further includes an electrode layer ETL, the multilayer oxide insulating film MLO can selectively surround the electrode layer ETL. For example, the multilayer oxide insulating film MLO may partially or completely surround the outer periphery (e.g., sides) of the electrode layer ETL, or it may not surround the electrode layer ETL at all.

[0078] The multilayer oxide insulating film MLO can expose the electrode layer ETL (or second semiconductor layer SCL2) and the first semiconductor layer SCL1 (or other electrode layer provided at the second end EP2 of the light-emitting element LD) at the first end EP1 and the second end EP2, respectively. For example, the multilayer oxide insulating film MLO does not need to be provided at the two bottom surfaces corresponding to the first and second ends EP1 and EP2 of the light-emitting element LD (e.g., the top and bottom surfaces of the light-emitting element LD). This allows electrical signals (e.g., drive signals and / or power supply voltages) to be applied to the light-emitting element LD via the first end EP1 and the second end EP2.

[0079] The multilayer oxide insulating film MLO is provided on the surface of the light-emitting laminate LES, ensuring the electrical stability of the light-emitting element LD. Furthermore, the multilayer oxide insulating film MLO can block or reduce the inflow of oxygen into the light-emitting laminate LES, thereby delaying the degradation of the light-emitting element LD and improving its reliability. For example, the multilayer oxide insulating film MLO has oxygen vacancies (e.g., oxygen vacancies (V) in Figure 5) formed at the interfaces of insulating films containing different oxides. O )) may include. By capturing oxygen with the oxygen vacancies, the inflow of oxygen into the light-emitting laminate LES can be blocked or reduced.

[0080] The multilayer oxide insulating film MLO may include a first insulating film INF1, a second insulating film INF2, and a third insulating film INF3.

[0081] The first insulating film INF1 may surround the light-emitting laminate LES. For example, the first insulating film INF1 may surround the outer periphery (e.g., the sides) of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2. In one embodiment, the first insulating film INF1 may further surround at least a portion (e.g., at least a portion of the sides) of the electrode layer ETL.

[0082] The second insulating film INF2 may surround the first insulating film INF1. For example, the second insulating film INF2 may surround the outer surface (e.g., the side) of the first insulating film INF1.

[0083] The third insulating film INF3 may surround the second insulating film INF2. For example, the third insulating film INF3 may surround the outer surface (e.g., the side) of the second insulating film INF2.

[0084] The first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 may contain oxides that can reduce or minimize defects in the light-emitting element LD while generating oxygen vacancies at their interfaces that can improve the degradation of the light-emitting element LD. For example, the first insulating film INF1 is M1 x O y Type (or M x O y (Type) Oxide (e.g., M1 x O y It may contain (type metal oxide), and the third insulating film INF3 is M3 x O y Type (or M x O y (Type) Oxide (e.g., M3) x O y It may contain (type metal oxide), and the second insulating film INF2 is M2 2x O (2y-1) Type (or M 2x O (2y-1) (Type) Oxide (e.g., M2 2x O (2y-1)It may include a metal oxide. Here, M or M1, M2 and M3 are substances that bond with oxygen (or oxygen ions), and for example, each may be a metallic substance (or metal ion), and x and y may each be natural numbers. At least two of M1, M2 and M3 may be the same substance, or M1, M2 and M3 may be different substances. For example, M1 and M3 may be the same substance, and M2 may be a different substance from M1 and M3, but the embodiments are not limited thereto.

[0085] In one embodiment, the oxides used to form the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 may be materials selected such that defects in the light-emitting element LD are reduced or minimized while generating oxygen vacancies at their interfaces that can improve the degradation of the light-emitting element LD. For example, the first insulating film INF1 and the third insulating film INF3 may contain M1O2 type oxide and M3O2 type oxide, respectively, and the second insulating film INF2 may contain M22O3 type oxide.

[0086] In one embodiment, each of the first insulating film INF1 and the third insulating film INF3 may contain at least one oxide from among silicon oxide, zirconium oxide, hafnium oxide, germanium oxide, titanium oxide, and tellurium oxide. For example, each of the first insulating film INF1 and the third insulating film INF3 may contain at least one oxide from among SiO2, ZrO2, HfO2, GeO2, TiO2, and TeO2. The first insulating film INF1 and the third insulating film INF3 may contain the same oxide or different oxides.

[0087] In one embodiment, the second insulating film INF2 may contain at least one oxide from among aluminum oxide, yttrium oxide, lanthanum oxide, cerium oxide, ruthenium oxide, scandium oxide, and ytterbium oxide. For example, the second insulating film INF2 may contain at least one oxide from among Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3, and Yb2O3.

[0088] In one embodiment, the first insulating film INF1 may be an oxide insulating film containing ZrO2, the second insulating film INF2 may be an oxide insulating film containing Al2O3, and the third insulating film INF3 may be an oxide insulating film containing ZrO2. In this case, defects in the light-emitting diode (LD) can be reduced or minimized while ensuring oxygen vacancies for degradation improvement. The oxides used to form the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 are not limited to these and can be changed depending on the embodiment.

[0089] In one embodiment, the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 may be formed as thin films such that their influence on the light-emitting laminate LES can be reduced or minimized. For example, the sum of the thicknesses of the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 may be 10 nm or less. Furthermore, the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 may be formed with a thickness limited so as to reduce or minimize defects in the light-emitting element LD, while smoothly inducing interfacial reactions that generate oxygen vacancies at their interfaces to the extent that the degradation of the light-emitting element LD can be improved.

[0090] For example, the second insulating film INF2 is formed with a thickness of 2 nm or less (for example, a thickness in the range of approximately 1 nm to 2 nm) in order to smoothly induce interfacial reactions, but is not limited thereto. The first insulating film INF1 is formed with a thickness greater than that of the second insulating film INF2 so that defects do not occur in regions excessively adjacent to the light-emitting laminate LES (for example, so that a distance of a certain amount or more is secured between the interface of the first insulating film INF1 and the second insulating film INF2 and the light-emitting laminate LES), but it may be formed with a thickness limited so as to reduce or minimize the impact on the light-emitting laminate LES. For example, the first insulating film INF1 is formed with a thickness of 3 nm or less (for example, a thickness in the range of approximately 2 nm to 3 nm), but is not limited thereto. The third insulating film INF3 can be formed to a thickness greater than or equal to that of the second insulating film INF2 so that relatively uniform interfacial reactions can occur at the interface between the first insulating film INF1 and the second insulating film INF2, and at the interface between the second insulating film INF2 and the third insulating film INF3 (for example, so that interfacial reactions do not concentrate at the interface between the first insulating film INF1 and the second insulating film INF2). For example, the third insulating film INF3 is formed to a thickness of 2 nm or 3 nm or less (for example, a thickness in the range of approximately 1 nm to 3 nm), but is not limited thereto. This can reduce or minimize defects in the light-emitting element LD and improve the degradation characteristics of the light-emitting element LD, thereby increasing the reliability of the light-emitting element LD.

[0091] The protective film PRL may surround the multilayer oxide insulating film MLO. For example, the protective film PRL may surround the third insulating film INF3, exposing the first end EP1 and the second end EP2 of the light-emitting element LD.

[0092] The protective film PRL may include at least one insulating film. For example, the protective film PRL may include a fourth insulating film INF4 (or a first protective film).

[0093] The fourth insulating film INF4 may surround the multilayer oxide insulating film MLO. For example, the fourth insulating film INF4 may surround the outer surface (e.g., the side) of the third insulating film INF3.

[0094] In one embodiment, the protective film PRL consists only of the fourth insulating film INF4, similar to the embodiment in Figure 3. The fourth insulating film INF4 may be formed of a material and / or thickness that can stably protect the light-emitting laminate LES and the multilayer oxide insulating film MLO in the process of manufacturing the light-emitting element LD and / or other subsequent processes (e.g., the etching process included in the pixel process of a display device using the light-emitting element LD). For example, the fourth insulating film INF4 may be an inorganic film containing an oxide (e.g., an inorganic film containing silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide) and may have a thickness greater than the sum of the thicknesses of the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 (e.g., a thickness of approximately 10 nm or more). As an example, the fourth insulating film INF4 may be an inorganic film containing SiO2 or other oxides and may have a thickness in the range of approximately 10 nm to 200 nm, but is not limited thereto.

[0095] In one embodiment, the protective film PRL consists of a double-layer insulating film including a fourth insulating film INF4 and a fifth insulating film INF5 (or a second protective film), similar to the embodiment in Figure 4.

[0096] The fifth insulating film INF5 may surround the fourth insulating film INF4. For example, the fifth insulating film INF5 may surround the outer surface (e.g., the side) of the fourth insulating film INF4.

[0097] The fifth insulating film INF5, together with the fourth insulating film INF4, can protect the light-emitting laminate LES and the multilayer oxide insulating film MLO. For example, the fifth insulating film INF5 may be formed with a material and / or thickness that can stably protect the light-emitting laminate LES and the multilayer oxide insulating film MLO in the process of manufacturing the light-emitting element LD and / or other subsequent processes (e.g., an etching process for forming pixel electrodes on the light-emitting element LD). For example, the fifth insulating film INF5 may be an inorganic film containing a different oxide than the material of the fourth insulating film INF4 (e.g., an inorganic film containing silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide), and may have a greater thickness than the fourth insulating film INF4. As an example, the fifth insulating film INF5 may be an inorganic film containing Al2O3 or other oxides, and may have a thickness in the range of approximately 10 nm to 200 nm, but is not limited thereto.

[0098] The structure, material, and / or thickness of the protective film PRL are not limited to the embodiments described above. For example, the protective film PRL consists of three or more insulating films, further comprising one or more additional insulating films along with the fourth insulating film INF4 and the fifth insulating film INF5.

[0099] When forming a protective film PRL using at least two insulating films, including a fourth insulating film INF4 and a fifth insulating film INF5, the thickness of each insulating film constituting the protective film PRL can be reduced. This shortens the process time required for forming the protective film PRL and improves process efficiency. For example, when forming a protective film PRL using ALD (Atomic Layer Deposition) process technology, the ALD process time can be shortened by reducing the thickness of each insulating film constituting the protective film PRL.

[0100] Figure 5 shows the interfacial reaction occurring in a multilayer oxide insulating film MLO according to one embodiment, and the oxygen vacancies (V) formed thereby. OThis figure shows the interfacial reaction that occurs in a multilayer oxide insulating film MLO containing a first insulating film INF1 containing ZrO2, a second insulating film INF2 containing Al2O3, and a third insulating film INF3 containing ZrO2, and the oxygen vacancies (V) formed thereby. For example, Figure 5 shows the interfacial reaction that occurs in a multilayer oxide insulating film MLO containing a first insulating film INF1 containing ZrO2, a second insulating film INF2 containing Al2O3, and a third insulating film INF3 containing ZrO2, and the oxygen vacancies (V) formed thereby. O This indicates that...

[0101] Referring to Figures 1 through 4, and also to Figure 5, at the interface where the second insulating film INF2 contacts the first insulating film INF1 and the third insulating film INF3, an interfacial reaction occurs, creating oxygen vacancies (V O ) may be formed. For example, at the interface, Al2O3 of the second insulating film INF2 reacts with ZrO2 of the first insulating film INF1 and ZrO2 of the third insulating film INF3 to form oxygen vacancies (V O ) can be formed.

[0102] For example, at the interface, aluminum (Al) and zirconium (Zr) may be substituted for each other, and oxygen (O) may be substituted for each other. As an example, at the interface where the second insulating film INF2 is in contact with the first insulating film INF1 and the third insulating film INF3, as shown in the chemical formula in Figure 5, Al2O3 of the second insulating film INF2 reacts with 2ZrO2 of the first and third insulating films INF1 and INF3 (ZrO2 of the first insulating film INF1 and ZrO2 of the third insulating film INF3), so that zirconium (Zr) is located in the place of aluminum (Al) and oxygen (O) may be substituted for each other.

[0103] The chemical formulas shown in Figure 5 represent defects occurring at the interface according to Kroger-Vink notation, where subscripts indicate the location of the defect and superscripts indicate the amount of charge. For example, chemical formula 1 below represents a zirconium (Zr) ion with a +1 charge (single positive charge) located at the lattice site of aluminum (Al). [ka]

[0104] The following chemical formula 2 represents an oxygen vacancy (V) located at the oxygen (O) position, which carries a double negative charge (-2). O ) indicates. [ka]

[0105] Three oxygen (O) ions occupy three of the four oxygen (O) positions, leaving one oxygen (O) position empty, thus creating an oxygen vacancy (V). O ) The superscript X in the following chemical formula 3 indicates that the relative charge is 0. [ka]

[0106] For example, at the interface where the second insulating film INF2 contacts the first and third insulating films INF1 and INF3, the ratio of oxygen (O) ions in the first and third insulating films INF1 and INF3 to the oxygen (O) ions in the second insulating film INF2 is 4:3, and therefore, oxygen vacancies (V) are present at the interface. O ) may be formed. Oxygen vacancies (V) formed by interfacial reactions O A defect is fixed to an adjacent atom and may not move even while the light-emitting diode (LD) is being driven.

[0107] Oxygen vacancies (V) formed at the interface O The ) functions as a capture site that captures oxygen (O) flowing into the light-emitting diode (LD), thereby suppressing oxygen diffusion. This reduces or minimizes the degradation of the light-emitting diode (LD) and improves its reliability.

[0108] Figure 6 is a graph showing the brightness maintenance rate of a light-emitting diode (LD) depending on the material constituting the multilayer oxide insulating film MLO. For example, Figure 6 shows the brightness maintenance rate of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO containing a first insulating film INF1 containing ZrO2, a second insulating film INF2 containing Al2O3, and a third insulating film INF3 containing ZrO2, and the brightness maintenance rate of a light-emitting diode (LD) equipped with multilayer oxide insulating films MLO_R1, MLO_R2 in which the material of the second insulating film INF2 is changed to an oxide other than M2O3 type oxide.

[0109] Referring to Figures 1 through 5, and also to Figure 6, a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO containing a first insulating film INF1 containing ZrO2, a second insulating film INF2 containing Al2O3, and a third insulating film INF3 containing ZrO2 exhibits the characteristic of maintaining a high brightness retention rate even over time. On the other hand, a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_R1 in which the second insulating film INF2 is changed to an insulating film containing an MO2 type (where M is a metallic substance) oxide (e.g., SiO2) exhibits the characteristic of slightly reduced brightness retention rate. Furthermore, if the second insulating film INF2 is changed to an M2O5 type oxide (e.g., Ta2O 5) A light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_R2, which has been modified to include the insulating film, exhibits a significantly reduced brightness maintenance rate.

[0110] As mentioned above, the brightness maintenance rate of the light-emitting element LD can change depending on the forming material of the multilayer oxide insulating film MLO. In this embodiment, the first insulating film INF1 and the third insulating film INF3 are each M x O y Formed with type oxides (for example, M1O2 type oxide and M3O2 type oxide, respectively), and the second insulating film INF2 is M 2x O (2y-1) By forming the element with a specific type oxide (for example, M22O3 type oxide), the degradation characteristics of the light-emitting diode (LD) can be improved, and its reliability can be ensured.

[0111] Figure 7 is a graph showing the brightness maintenance rate of a light-emitting diode (LD) according to the thickness of the first insulating film INF1. For example, Figure 7 shows the brightness maintenance rate of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_1a containing a first insulating film INF1 with a thickness of 2 nm containing ZrO2, a second insulating film INF2 with a thickness of 1 nm containing Al2O3, and a third insulating film INF3 with a thickness of 1 nm containing ZrO2, and the brightness maintenance rate of a light-emitting diode (LD) equipped with multilayer oxide insulating films MLO_2 and MLO_3 with varying thicknesses of the first insulating film INF1.

[0112] Referring to Figures 1 to 5, and also to Figure 7, the brightness maintenance rate of the light-emitting diode (LD) can change depending on the thickness of the first insulating film INF1. For example, the brightness maintenance rate of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_1a containing a 2nm thick first insulating film INF1 (ZrO2 insulating film) may differ from that of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_2 containing a 3nm thick first insulating film INF1 (ZrO2 insulating film) and a multilayer oxide insulating film MLO_3 containing a 2.5nm thick first insulating film INF1 (ZrO2 insulating film). Therefore, the brightness maintenance rate of the light-emitting diode (LD) can be controlled or improved by appropriately adjusting the thickness of the first insulating film INF1.

[0113] Figure 8 is a graph showing the brightness maintenance rate of a light-emitting diode (LD) according to the thickness of the second insulating film INF2. For example, Figure 8 shows the brightness maintenance rate of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_1b containing a first insulating film INF1 with a thickness of 2 nm containing ZrO2, a second insulating film INF2 with a thickness of 1 nm containing Al2O3, and a third insulating film INF3 with a thickness of 1 nm containing ZrO2, and the brightness maintenance rate of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_4 with a changed thickness of the second insulating film INF2.

[0114] Referring to Figures 1 to 5, and also to Figure 8, the brightness maintenance rate of the light-emitting diode (LD) can change depending on the thickness of the second insulating film INF2. For example, the brightness maintenance rate of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_1b containing a 1 nm thick second insulating film INF2 (Al2O3 insulating film) may differ from that of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_4 containing a 2 nm thick second insulating film INF2 (Al2O3 insulating film). Therefore, the brightness maintenance rate of the light-emitting diode (LD) can be controlled or improved by appropriately adjusting the thickness of the second insulating film INF2.

[0115] Figure 9 is a graph showing the brightness maintenance rate of a light-emitting diode (LD) according to the thickness of the third insulating film INF3. Figure 9 shows the brightness maintenance rate of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_1c containing a first insulating film INF1 with a thickness of 2 nm containing ZrO2, a second insulating film INF2 with a thickness of 1 nm containing Al2O3, and a third insulating film INF3 with a thickness of 1 nm containing ZrO2, and the brightness maintenance rate of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_5 with a different thickness of the third insulating film INF3.

[0116] Referring to Figures 1 through 5, and also to Figure 9, the brightness maintenance rate of the light-emitting diode (LD) can change depending on the thickness of the third insulating film INF3. For example, the brightness maintenance rate of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_1c containing a 1 nm thick third insulating film INF3 (ZrO2 insulating film) may differ from that of a light-emitting diode (LD) equipped with a multilayer oxide insulating film MLO_5 containing a 2 nm thick third insulating film INF3 (ZrO2 insulating film). Therefore, the brightness maintenance rate of the light-emitting diode (LD) can be controlled or improved by appropriately adjusting the thickness of the third insulating film INF3.

[0117] As mentioned above, the light-emitting diode (LD) may exhibit different characteristics (e.g., different brightness maintenance rates) depending on the thickness of the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3. Therefore, the thicknesses of the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 can be appropriately adjusted considering the characteristics exhibited by the light-emitting diode (LD).

[0118] In Figures 7 to 9, the light-emitting diodes (LDs) used in each experiment to confirm the brightness maintenance rate of the light-emitting diodes (LDs) according to the thickness of the first insulating film INF, the second insulating film INF2, and the third insulating film INF3 may be different light-emitting diodes (LDs). For example, even in the case of a light-emitting diode (LD) equipped with multiple layers of oxide insulating films MLO_1a, MLO_1b, and MLO_1c under the same thickness conditions, the experimental values ​​may differ due to differences in the characteristics of the light-emitting diodes (LDs).

[0119] Figure 10 is a plan view showing a display device DD according to one embodiment. Figure 10 shows a simplified structure of the display device DD, centering on the display panel DP which includes the display area DA. The display device DD may further include drive circuits for driving pixels PXL (e.g., a scanning drive unit, a data drive unit, and a timing control unit).

[0120] Referring to Figure 10, the display device DD may include a base layer BSL and pixels PXL arranged on the base layer BSL. The shape of the base layer BSL and the display device DD including it can vary. For example, the base layer BSL and the display device DD may be provided as a plate having a substantially rectangular shape in plan view, and may include angular or rounded corners. The shape of the base layer BSL and the display device DD can be changed. As an example, the base layer BSL and the display device DD may have other polygonal shapes, such as hexagons or octagons, or shapes that include curved outer perimeters, such as circles or ellipses, in plan view. In Figure 10, the display device DD is shown as having a rectangular plate shape.

[0121] Figure 10 shows the first direction DR1, the second direction DR2, and the third direction DR3. In one embodiment, the first direction DR1 may be the lateral direction of the display device DD (e.g., the row direction or horizontal direction), and the second direction DR2 may be the vertical direction of the display device DD (e.g., the column direction or vertical direction). The third direction DR3 is a direction that intersects the first direction DR1 and the second direction DR2, and may, for example, be the thickness direction or height direction of the display device DD.

[0122] The base layer BSL can be a base member for constructing a display device DD. For example, the base layer BSL can constitute the base surface of the display device DD. The base layer BSL and the display device DD containing it may include a display area DA and a non-display area NA.

[0123] The display area DA is the area where pixels PXL are arranged and may be the area where an image is displayed. In one embodiment, the display area DA may be located in the central area of ​​the base layer BSL and the display device DD.

[0124] The display area DA can have a variety of shapes. For example, the display area DA can have a variety of shapes including rectangles, circles, or ellipses. In one embodiment, the display area DA may have a shape corresponding to the shape of the base layer BSL, but is not limited thereto.

[0125] The non-display area NA is the remaining area excluding the display area DA, and may be located around the display area DA. In one embodiment, the non-display area NA may be located in the edge area of ​​the base layer BSL and the display device DD so as to surround the display area DA. The non-display area NA may include the pad area where the pad P is placed.

[0126] Pixels PXL may be placed in the display area DA. For example, the display area DA may contain pixel areas in which each pixel PXL is placed.

[0127] In one embodiment, the display area DA may contain at least two types of pixels PXL to emit light of different colors (or light of different wavelength bands). For example, the display area DA may contain a first-color pixel PXL1, a second-color pixel PXL2, and a third-color pixel PXL3. At least one first-color pixel PXL1, at least one second-color pixel PXL2, and at least one third-color pixel PXL3, arranged adjacent to each other, constitute a pixel group PXG. By individually controlling the brightness of the first, second, and third-color pixels PXL1, PXL2, and PXL3, various colors of light can be emitted from each pixel group PXG.

[0128] In the embodiment shown in Figure 10, a first-color pixel PXL1, a second-color pixel PXL2, and a third-color pixel PXL3, arranged continuously along the first direction DR1, constitute a single pixel group PXG. However, the number, type, and / or relative arrangement structure of the pixels PXL constituting each pixel group PXG can be varied in various ways depending on the embodiment.

[0129] In one embodiment, the first color pixel PXL1 may be a red pixel for emitting red light, and the second color pixel PXL2 may be a green pixel for emitting green light. Furthermore, the third color pixel PXL3 may be a blue pixel for emitting blue light. The color of the light emitted from each pixel PXL can also be varied in various ways.

[0130] In one embodiment, each pixel PXL may include at least one light-emitting element LD. For example, a pixel PXL may include a light-emitting element LD according to at least one embodiment of the embodiments described with reference to Figures 1 to 9. As an example, a pixel PXL may include a light-emitting element LD, which may include a light-emitting laminate LES comprising at least a first semiconductor layer SCL1, an active layer ACT and a second semiconductor layer SCL2, a multilayer oxide insulating film MLO comprising first, second and third insulating films INF1, INF2, and INF3, and a protective film PRL comprising at least a fourth insulating film INF4. The number, type, structure, and / or size of the light-emitting elements LDs provided to each pixel PXL can be changed according to the embodiment.

[0131] In one embodiment, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may each be equipped with first, second, and third color light-emitting diodes (LDs) as light sources. As a result, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 can emit light of the first color, the second color, and the third color, respectively.

[0132] In other embodiments, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may include light-emitting elements (LDs) that emit light of the same color to each other, and the light-emitting regions of the first color pixel PXL1, the second color pixel PXL2, and / or the third color pixel PXL3 may be arranged with a light-conversion layer containing wavelength-converting particles (also called "wavelength shifters") that convert the color and / or wavelength of light, such as quantum dots, quantum rods, or phosphors. This allows the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 to emit light of the first color, the second color, and the third color, respectively.

[0133] For example, the first-color pixel PXL1, the second-color pixel PXL2, and the third-color pixel PXL3 may include a blue light-emitting element. In this case, the light-emitting region of the first-color pixel PXL1 may contain a light conversion layer containing wavelength-converting particles of the first color (e.g., quantum dots that convert incident light to red light), and the light-emitting region of the second-color pixel PXL2 may contain a light conversion layer containing wavelength-converting particles of the second color (e.g., quantum dots that convert incident light to green light). As a result, the first-color pixel PXL1 can emit light of the first color (e.g., red light), and the second-color pixel PXL2 can emit light of the second color (e.g., green light).

[0134] A pixel PXL may have a structure according to at least one embodiment of the embodiments described below. For example, a pixel PXL may have a structure to which one of the embodiments described later is applied, or a structure to which at least two embodiments are applied in combination. However, the structure and type of pixel PXL are not limited to the embodiments disclosed below.

[0135] In one embodiment, the pixel PXL may be an active pixel, but is not limited thereto. For example, the pixel PXL may be a passive pixel.

[0136] The non-display area NA may contain wiring and / or internal circuitry connected to the pixels PXL of the display area DA. Additionally, a pad P may be located within a portion of the non-display area NA (e.g., a pad area). The pad P may include a signal pad and a power pad to which the drive signals and power supply voltages necessary for driving the pixels PXL are applied.

[0137] Figure 11 is a circuit diagram showing a pixel PXL according to one embodiment. Figure 12 is a circuit diagram showing a pixel PXL according to one embodiment. For example, Figures 11 and 12 show respective pixel PXLs, each including a light-emitting unit EMU with a different structure.

[0138] Each pixel PXL shown in Figures 11 and 12 could be any one of the pixel PXLs located in the display area DA of Figure 6. The pixel PXLs in the display area DA may have substantially the same or similar structures.

[0139] Referring to Figures 1 through 10, as well as Figures 11 and 12, a pixel PXL may be connected to the scan line SL (also known as the "first scan line"), the data line DL, the first power line PL1, and the second power line PL2. Furthermore, a pixel PXL may be further connected to at least one different power line and / or signal line. For example, a pixel PXL may be further connected to the sensing line SENL (also known as the "initialization power line") and / or the control line SSL (also known as the "second scan line").

[0140] A pixel PXL may include an EMU (Emitting Magnet Unit) for generating light with a brightness corresponding to each data signal. The pixel PXL may further include a pixel circuit PXC (Picture Circuit) for driving the EMU.

[0141] The pixel circuit PXC may be connected to the scan line SL and the data line DL, and may be connected between the first power line PL1 and the light-emitting unit EMU. For example, the pixel circuit PXC may be electrically connected to the scan line SL to which the first scan signal is supplied, the data line DL to which the data signal is supplied, the first power line PL1 to which the voltage of the first power supply VDD is applied, and the light-emitting unit EMU.

[0142] The pixel circuit PXC may be selectively further connected to a control line SSL to which a second scan signal is supplied, and to a sensing line SENL connected to a reference power supply (or initialization power supply) or a sensing circuit, corresponding to the display period or sensing period. In one embodiment, the second scan signal may be the same as or different from the first scan signal. If the second scan signal is the same as the first scan signal, the control line SSL may also be integrated with the scan line SL.

[0143] The pixel circuit PXC may include at least one transistor M and a capacitor Cst. For example, the pixel circuit PXC may include a first transistor M1, a second transistor M2, a third transistor M3, and a capacitor Cst.

[0144] The first transistor M1 may be connected between the first power line PL1 and the second node N2. The second node N2 may be a node to which the pixel circuit PXC and the light-emitting unit EMU are connected. For example, the second node N2 may be a node to which one electrode of the first transistor M1 (e.g., the source electrode) and one electrode of the light-emitting unit EMU (e.g., the first pixel electrode ELT1) are electrically connected to each other. The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may be a drive transistor that controls the drive current supplied to the light-emitting unit EMU in response to the voltage at the first node N1.

[0145] In one embodiment, the first transistor M1 may further include a bottom metal layer (BML) (also referred to as a "back gate electrode" or "second gate electrode"). In one embodiment, the bottom metal layer BML may be connected to one electrode of the first transistor M1 (e.g., a source electrode).

[0146] The lower metal layer BML may be placed beneath the semiconductor pattern (for example, the semiconductor pattern SCP in Figure 14) that constitutes the channel of the first transistor M1. In this case, the light incident on the semiconductor pattern can be blocked, thereby stabilizing the operating characteristics of the first transistor M1.

[0147] A second transistor M2 may be connected between the data line DL and the first node N1. The gate electrode of the second transistor M2 may be connected to the scan line SL. The second transistor M2 may be turned on when a first scan signal of gate-on voltage (e.g., logic high voltage or high level voltage) is supplied from the scan line SL, and may connect the data line DL and the first node N1.

[0148] For each frame period of the display period, the data line DL may be supplied with the data signal for that frame. The data signal may be transmitted to the first node N1 via the second transistor M2 for the duration of the period during which the first scan signal of the gate-on voltage is supplied.

[0149] Capacitor Cst may be connected between the first node N1 and the second node N2. Capacitor Cst may be charged with a voltage corresponding to the data signal supplied to the first node N1.

[0150] A third transistor M3 may be connected between the second node N2 and the sensing line SENL. The gate electrode of the third transistor M3 may also be connected to the control line SSL (or scan line SL). When a second scan signal (or first scan signal) of gate-on voltage (e.g., logic high voltage or high-level voltage) is supplied from the control line SSL, the third transistor M3 is turned on and can transmit a reference voltage or initialization voltage supplied to the sensing line SENL to the second node N2, or transmit the voltage of the second node N2 to the sensing line SENL. In one embodiment, the voltage of the second node N2 may be transmitted to a sensing circuit via the sensing line SENL and provided to a drive circuit (e.g., a timing control unit) to compensate for characteristic deviations of the pixel PXL, etc.

[0151] In Figures 11 and 12, all transistors M included in the pixel circuit PXC are shown as N-type transistors, but the embodiments are not limited to this. For example, at least one of the first, second, and third transistors M1, M2, and M3 can be changed to a P-type transistor. In addition, the structure and driving method of the pixel PXL can be varied in various ways depending on the embodiment.

[0152] The light-emitting unit EMU may include at least one light-emitting element LD connected between a first power supply VDD and a second power supply VSS (for example, connected in the forward direction). The at least one light-emitting element LD may be the light source for a pixel PXL.

[0153] In one embodiment, the light-emitting unit EMU may include a single light-emitting element LD connected in the forward direction between a first power supply VDD and a second power supply VSS. In another embodiment, the light-emitting unit EMU may include at least two light-emitting elements LD connected in the forward direction between the first power supply VDD and the second power supply VSS.

[0154] In one embodiment, the light-emitting unit EMU may include light-emitting elements LD connected in parallel to each other between the pixel circuit PXC and the second power line PL2, similar to the embodiment in Figure 11. The first end EP1 of the light-emitting element LD may be electrically connected to the pixel circuit PXC via the first pixel electrode ELT1 and to the first power line PL1 via the pixel circuit PXC. The second end EP2 of the light-emitting element LD may be electrically connected to the second power line PL2 via the second pixel electrode ELT2. The voltage of the second power supply VSS may be applied to the second power line PL2.

[0155] The type, number, and / or structure of the light-emitting elements (LDs) constituting the light-emitting EMU of the pixel PXL can be changed according to the embodiment. Furthermore, the arrangement and / or connection structure of the light-emitting elements (LDs) can also be changed according to the embodiment.

[0156] In one embodiment, the light-emitting unit EMU may include light-emitting elements LDs connected in series-parallel between the pixel circuit PXC and the second power line PL2, similar to the embodiment in Figure 12. For example, the light-emitting elements LDs may be arranged and / or connected to at least two series terminals between the pixel circuit PXC and the second power line PL2, with each series terminal including at least one light-emitting element LD forward-connected between the first power supply VDD and the second power supply VSS. For example, the light-emitting unit EMU may include at least one light-emitting element LD connected between the first pixel electrode ELT1 and the third pixel electrode ELT3 (e.g., at least one light-emitting element LD forward-connected to the first series terminal), and at least one light-emitting element LD connected between the third pixel electrode ELT3 and the second pixel electrode ELT2 (e.g., at least one light-emitting element LD forward-connected to the second series terminal). The third pixel electrode ELT3 may be an intermediate electrode connecting the first and second series terminals.

[0157] The first power supply VDD and the second power supply VSS may have different potentials. For example, the first power supply VDD may be a high-potential pixel power supply, and the second power supply VSS may be a low-potential pixel power supply.

[0158] The light-emitting element LD can emit light at a brightness corresponding to the drive current supplied via the pixel circuit PXC. During each frame period of the display period, the pixel circuit PXC can supply a drive current corresponding to the data signal to the light-emitting unit EMU. The light-emitting element LD can emit light at a brightness corresponding to the drive current.

[0159] Figure 13 is a plan view showing a pixel PXL according to one embodiment. For example, Figure 13 shows the structure of a pixel PXL centered on the light-emitting unit EMU, and, similar to the embodiment in Figure 12, shows one embodiment of the light-emitting unit EMU that includes light-emitting elements LDs connected in series and parallel to each other.

[0160] Referring to Figures 1 to 12, and also to Figure 13, a pixel PXL may include a light-emitting region EA on which at least one light-emitting element LD is located. In one embodiment, the light-emitting region EA may include at least two light-emitting elements LD and electrodes electrically connected to the light-emitting elements LD. In one embodiment, the electrodes may include an alignment electrode ALE and a pixel electrode ELT (also referred to as a "contact electrode"). The pixel PXL may further include a bank pattern BNP located below the alignment electrode ALE.

[0161] Alignment electrodes ALE can have a variety of shapes and can be spaced apart from one another. In one embodiment, the alignment electrodes ALE may be spaced apart from one another along a first direction DR1, and each may have a shape (e.g., bar shape) extending along a second direction DR2.

[0162] The shape, size, number, position, and / or relative arrangement structure of the alignment electrodes (ALEs) can be modified according to the embodiment. Furthermore, the alignment electrodes (ALEs) may have similar or identical shapes and / or sizes, or they may have different shapes and sizes.

[0163] Aligned electrode ALE may include at least two electrodes spaced apart from each other. For example, the aligned electrode ALE may include a first aligned electrode ALE1, a second aligned electrode ALE2, and a third aligned electrode ALE3.

[0164] In one embodiment, the first alignment electrode ALE1 may be located in the center of the light-emitting region EA, and the second alignment electrode ALE2 and the third alignment electrode ALE3 may be located on either side of the first alignment electrode ALE1. For example, the second alignment electrode ALE2 may be located to the right of the first alignment electrode ALE1, and the third alignment electrode ALE3 may be located to the left of the first alignment electrode ALE1.

[0165] Alignment electrodes ALE (or alignment wiring before being separated into each alignment electrode ALE of a pixel PXL) can receive the necessary alignment signals for the alignment of the light-emitting element LDs during the alignment stage of the light-emitting element LDs. This allows the light-emitting element LDs to be aligned and / or arranged between the alignment electrode ALEs. Alignment and / or arrangement of light-emitting element LDs between alignment electrode ALEs means that at least a portion of each light-emitting element LD is positioned between the alignment electrode ALEs.

[0166] For example, the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 (or the first alignment wiring connected to the first alignment electrode ALE1 of the pixel PXL, the second alignment wiring connected to the second alignment electrode ALE2 of the pixel PXL, and the third alignment wiring connected to the third alignment electrode ALE3 of the pixel PXL) can receive the first alignment signal, the second alignment signal, and the third alignment signal, respectively, during the alignment stage of the light-emitting element LD. The first and second alignment signals may have different waveforms, potentials, and / or phases, and the first and third alignment signals may have different waveforms, potentials, and / or phases. The third alignment signal may be the same as or different from the second alignment signal. This allows the light-emitting element LD to be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2, and between the first alignment electrode ALE1 and the third alignment electrode ALE3.

[0167] Alignment electrodes ALEs may be located in the light-emitting region EA of each pixel PXL. In one embodiment, the alignment electrodes ALEs may extend through the non-light-emitting region NEA surrounding the light-emitting region EA to a separation region SPA. The separation region SPA may be the region where, after the alignment of the light-emitting element LDs is complete, each alignment wiring (e.g., first alignment wiring, second alignment wiring, or third alignment wiring) is separated to the alignment electrodes ALEs of the pixel PXL (e.g., first alignment electrode ALE1, second alignment electrode ALE2, or third alignment electrode ALE3 of the pixel PXL), and may be located on at least one side of each light-emitting region EA.

[0168] For example, each pixel PXL may include at least one isolated region SPA located around the light-emitting region EA (e.g., two isolated regions SPA located above and below each light-emitting region EA). Each isolated region SPA may have the end of at least one electrode constituting the light-emitting unit EMU (e.g., the end of an aligned electrode ALE).

[0169] In one embodiment, each alignment electrode ALE may have a pattern separated for each pixel PXL. For example, the first, second, and third alignment electrodes ALE1, ALE2, and ALE3 of each pixel PXL may each have individually separated patterns. However, the embodiment is not limited thereto. For example, the alignment electrodes ALE connected to the second power line PL2 (e.g., the third alignment electrode ALE3 of the pixel PXL) may be formed integrally with each other.

[0170] In one embodiment, the first alignment electrode ALE1 may be electrically connected via a first contact portion CNT1 to a pixel circuit PXC (e.g., the pixel circuit PXC of the pixel PXL in Figure 14) and / or a first power line PL1 located in a circuit layer (e.g., circuit layer PCL in Figure 14). In this case, a first alignment signal may be supplied to the first alignment electrode ALE1 (or the first alignment wiring) via at least one wiring located in the circuit layer (e.g., the first power line PL1).

[0171] The first contact portion CNT1 may include at least one contact hole and / or via hole. In one embodiment, the first contact portion CNT1 may be located in a non-emitting region NEA located around each emitting region EA, but the position of the first contact portion CNT1 can be changed.

[0172] In one embodiment, the second alignment electrode ALE2 may be electrically connected to a second power line PL2 located in the circuit layer via a second contact portion CNT2. In this case, a second alignment signal may be supplied to the second alignment electrode ALE2 (or second alignment wiring) via the second power line PL2.

[0173] The third alignment electrode ALE3 can be electrically connected to the second power line PL2 located in the circuit layer via the third contact portion CNT3. In this case, the second alignment signal can also be supplied to the third alignment electrode ALE3 (or the third alignment wiring) via the second power line PL2.

[0174] The second contact portion CNT2 and the third contact portion CNT3 may each include at least one contact hole and / or via hole. In one embodiment, the second contact portion CNT2 and the third contact portion CNT3 may be located in the non-luminescent area (NEA), but the positions of the second contact portion CNT2 and the third contact portion CNT3 can be changed.

[0175] At least one first light-emitting element LD1 may be positioned between the first alignment electrode ALE1 and the second alignment electrode ALE2. For example, multiple first light-emitting elements LD1 may be arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0176] Each first light-emitting element LD1 may or may not be superimposed on the first alignment electrode ALE1 and / or the second alignment electrode ALE2. The first end EP1 of the first light-emitting element LD1 may be adjacent to the first alignment electrode ALE1, and the second end EP2 of the first light-emitting element LD1 may be adjacent to the second alignment electrode ALE2.

[0177] The first end EP1 of the first light-emitting element LD1 may be electrically connected to the first pixel electrode ELT1 (also referred to as the "first electrode"). In one embodiment, the first end EP1 of the first light-emitting element LD1 may be electrically connected to the first alignment electrode ALE1 via the first pixel electrode ELT1, and may be electrically connected to the pixel circuit PXC and / or the first power line PL1 via the first alignment electrode ALE1. In other embodiments, the first end EP1 of the first light-emitting element LD1 and the first pixel electrode ELT1 may be electrically connected to the pixel circuit PXC and / or the first power line PL1 without going through the first alignment electrode ALE1.

[0178] The second end EP2 of the first light-emitting element LD1 may be electrically connected to the third pixel electrode ELT3 (also referred to as the "third electrode") and / or the second pixel electrode ELT2 (also referred to as the "second electrode"). In one embodiment, the second end EP2 of the first light-emitting element LD1 may be electrically connected to the third pixel electrode ELT3. Alternatively, the second end EP2 of the first light-emitting element LD1 may be electrically connected to the second power line PL2 via the third pixel electrode ELT3, at least one second light-emitting element LD2, the second pixel electrode ELT2, and the third alignment electrode ALE3 in that order.

[0179] At least one second light-emitting element LD2 may be positioned between the first alignment electrode ALE1 and the third alignment electrode ALE3. For example, multiple second light-emitting elements LD2 may be arranged between the first alignment electrode ALE1 and the third alignment electrode ALE3.

[0180] Each second light-emitting element LD2 may or may not be superimposed on the first alignment electrode ALE1 and / or the third alignment electrode ALE3. The first end EP1 of the second light-emitting element LD2 may be adjacent to the first alignment electrode ALE1, and the second end EP2 of the second light-emitting element LD2 may be adjacent to the third alignment electrode ALE3.

[0181] The first end EP1 of the second light-emitting element LD2 may be electrically connected to the third pixel electrode ELT3. The second end EP2 of the second light-emitting element LD2 may be electrically connected to the second pixel electrode ELT2. In one embodiment, the second end EP2 of the second light-emitting element LD2 may be electrically connected to the third alignment electrode ALE3 via the second pixel electrode ELT2, and to the second power line PL2 via the third alignment electrode ALE3. In another embodiment, the second end EP2 and the second pixel electrode ELT2 of the second light-emitting element LD2 may also be electrically connected to the second power line PL2 without going through the third alignment electrode ALE3.

[0182] For example, each light-emitting element LD (e.g., each first light-emitting element LD1 or second light-emitting element LD2) may include a first end EP1 electrically connected to a first pixel electrode ELT1 and a second end EP2 electrically connected to a second pixel electrode ELT2. In one embodiment, each light-emitting element LD may be an ultra-miniature (e.g., having a small size in the range of nanometers to micrometers) inorganic light-emitting element made of an inorganic crystalline material. As an example, each light-emitting element LD may be a light-emitting element LD according to at least one embodiment of the embodiments described with reference to Figures 1 to 9.

[0183] The light-emitting element LDs can be supplied to each light-emitting region EA by methods such as inkjet or slit coating. The light-emitting element LDs can be aligned between alignment electrodes ALEs (or alignment wiring) by an alignment signal applied to the alignment electrodes ALEs, and then fixed in the aligned position.

[0184] The first pixel electrode ELT1 may be positioned on the first end EP1 of the first light-emitting element LD1 and may be electrically connected to the first end EP1 of the first light-emitting element LD1. For example, the first pixel electrode ELT1 may be positioned directly on the first end EP1 of the first light-emitting element LD1 so as to be in contact with the first end EP1 of the first light-emitting element LD1.

[0185] In one embodiment, the first pixel electrode ELT1 may be superimposed on the first alignment electrode ALE1 and may be electrically connected to the first alignment electrode ALE1 via the fourth contact portion CNT4. Alternatively, the first pixel electrode ELT1 may be electrically connected to the pixel circuit PXC and / or the first power line PL1 via the first alignment electrode ALE1. In another embodiment, the first pixel electrode ELT1 may be electrically connected to the pixel circuit PXC and / or the first power line PL1 without going through the first alignment electrode ALE1.

[0186] The third pixel electrode ELT3 may be positioned on the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2, and may be electrically connected to the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2. For example, the third pixel electrode ELT3 may be positioned directly on the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2 so as to be in contact with the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2. The third pixel electrode ELT3 may electrically connect the first light-emitting element LD1 and the second light-emitting element LD2. In one embodiment, the third pixel electrode ELT3 may be superimposed on a portion of the first and second alignment electrodes ALE1 and ALE2, respectively.

[0187] The second pixel electrode ELT2 (also referred to as the "second electrode") may be positioned on the second end EP2 of the second light-emitting element LD2 and may be electrically connected to the second end EP2 of the second light-emitting element LD2. For example, the second pixel electrode ELT2 may be positioned directly on the second end EP2 of the second light-emitting element LD2 so as to be in contact with the second end EP2 of the second light-emitting element LD2.

[0188] In one embodiment, the second pixel electrode ELT2 may be superimposed on the third alignment electrode ALE3 and electrically connected to the third alignment electrode ALE3 via the fifth contact portion CNT5. Alternatively, the second pixel electrode ELT2 may be electrically connected to the second power line PL2 via the third alignment electrode ALE3. In another embodiment, the second pixel electrode ELT2 may be electrically connected to the second power line PL2 without going through the third alignment electrode ALE3.

[0189] Pixel electrode ELTs may be formed in each light-emitting region EA, separated from each other. In one embodiment, at least one pixel electrode ELT may extend from each light-emitting region EA to the non-light-emitting region NEA and / or the separation region SPA. For example, the first pixel electrode ELT1 and the second pixel electrode ELT2 may extend from each light-emitting region EA to the non-light-emitting region NEA and the separation region SPA, and may be electrically connected to the first alignment electrode ALE1 and the third alignment electrode ALE3, respectively, in the separation region SPA. The third pixel electrode ELT3 may be formed only in each light-emitting region EA, or a portion of it may be located in the non-light-emitting region NEA. The position, size, shape, relative arrangement structure of the pixel electrode ELTs, and / or the positions of the fourth and fifth contact portions CNT4, CNT5, etc., can be changed according to the embodiment.

[0190] A bank pattern BNP (also called a “pattern” or “wall pattern”) may be positioned below the alignment electrode ALE so as to overlap with a portion of the alignment electrode ALE. For example, a bank pattern BNP may include a first bank pattern BNP1, ​​a second bank pattern BNP2, and a third bank pattern BNP3, which overlap with portions of the first, second, and third alignment electrodes ALE1, ALE2, and ALE3, respectively.

[0191] The bank pattern BNP allows a portion of the alignment electrode ALE to protrude upwards from the pixel PXL (e.g., in the third direction DR3). This allows for easy control of the region where the light-emitting element LD is aligned, and the light emitted from the light-emitting element LD that is emitted at a low angle toward the bank pattern BNP is reflected upwards from the pixel PXL, thereby increasing the optical efficiency of the pixel PXL.

[0192] In one embodiment, at least two adjacent pixels PXL may share at least one bank pattern BNP. For example, a second bank pattern BNP2 may be formed integrally with a third bank pattern BNP3 of an adjacent pixel PXL in the first direction DR1 (e.g., a right-side adjacent pixel). The third bank pattern BNP3 may be formed integrally with a second bank pattern BNP2 of another adjacent pixel in the first direction DR1 (e.g., a left-side adjacent pixel). The position, structure, number, size, and / or shape of the bank patterns BNP can be modified according to the embodiment.

[0193] A non-emitting region NEA may be located around each emitting region EA and / or each isolation region SPA. The first bank BNK1 may be located in the non-emitting region NEA.

[0194] The first bank BNK1 may include a first aperture OPA1 corresponding to each light-emitting region EA, and may surround the light-emitting region EA. In one embodiment, the first bank BNK1 may further include a second aperture OPA2 corresponding to a separation region SPA, and may surround the separation region SPA. For example, the first bank BNK1 may include an aperture OPA corresponding to each light-emitting region EA and each separation region SPA. The first bank BNK1 can define each light-emitting region EA to which a light-emitting element LD should be supplied when supplying a light-emitting element LD to each pixel PXL.

[0195] In one embodiment, the first bank BNK1 may include a hydrophobic surface. For example, the first bank BNK1 itself can be formed as a hydrophobic pattern using a hydrophobic material, or a hydrophobic coating made of a hydrophobic material can be formed on the first bank BNK1. As an example, the first bank BNK1 can be formed using a hydrophobic organic insulating material with a large contact angle, such as polyacrylate. This allows for smooth supply of light-emitting elements (LDs) to the light-emitting region EA.

[0196] Figure 14 is a cross-sectional view showing a display device DD according to one embodiment. For example, Figure 14 is a cross-sectional view showing a part of the display device DD, and shows a cross-section of a pixel PXL corresponding to lines II to II' in Figure 13.

[0197] Referring to Figures 1 through 13, and also to Figure 14, the display device DD may include a base layer (BSL), a circuit layer (PCL), and a display layer (DPL). The circuit layer (PCL) and the display layer (DPL) may be arranged superimposed on each other on the base layer (BSL). As an example, the circuit layer (PCL) and the display layer (DPL) may be arranged sequentially on one surface of the base layer (BSL).

[0198] The display device DD may further include a color filter layer CFL and / or a sealing layer ENC (or protective layer) disposed on the display layer DPL. In one embodiment, the color filter layer CFL and / or sealing layer ENC are formed directly on one surface of the base layer BSL on which the circuit layer PCL and the display layer DPL are formed, but the embodiments are not limited thereto.

[0199] The base layer (BSL) can be a substrate or film made of a rigid or flexible material. In one embodiment, the base layer (BSL) can be an insulating substrate and may have a single-layer or multi-layer structure.

[0200] The circuit layer PCL may be provided on one surface of the base layer BSL. The circuit layer PCL may include circuit elements that constitute the pixel circuit PXC of each pixel PXL. For example, multiple circuit elements (e.g., transistors M and capacitors Cst that constitute each pixel circuit PXC) may be formed in each pixel region of the circuit layer PCL.

[0201] Figure 14 illustrates an example of a circuit element that may be placed in the circuit layer PCL, specifically one transistor M (for example, the first transistor M1 including the lower metal layer BML) provided in each pixel circuit PXC.

[0202] The circuit layer PCL may further include signal lines and power lines connected to the pixel PXL. For example, the circuit layer PCL may include scan lines SL, control lines SSL, data lines DL, sensing lines SENL, and / or first and second power lines PL1, PL2 connected to the pixel PXL. Figure 14 illustrates an example of wiring that may be arranged in the circuit layer PCL, with wiring LI located on the same layer as the lower metal layer BML (e.g., the first conductive layer). Each wiring LI may be one of the signal lines and / or power lines connected to the pixel PXL. In one embodiment, at least one signal line and / or power line may also be arranged in other layers of the circuit layer PCL.

[0203] The circuit layer PCL may further include insulating layers. For example, the circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and / or a passivation layer PSV, arranged sequentially on one surface of the base layer BSL.

[0204] The circuit layer PCL is located on the base layer BSL and may include a first conductive layer containing the lower metal layer BML of the first transistor M1. For example, the first conductive layer may be located between the base layer BSL and the buffer layer BFL and may include the lower metal layer BML of the first transistor M1 provided in each pixel circuit PXC. The lower metal layer BML of the first transistor M1 may be superimposed on the semiconductor pattern SCP of the first transistor M1.

[0205] The first conductive layer may further include at least one wiring LI (or a portion of at least one wiring LI). For example, the first conductive layer may include at least a portion of the wiring LI that extends in the second direction DR2 in the display area DA.

[0206] A buffer layer BFL may be placed on one surface of the base layer BSL containing the first conductive layer. The buffer layer BFL can prevent impurities from diffusing to each circuit element.

[0207] A semiconductor layer may be placed on the buffer layer BFL. The semiconductor layer may include a semiconductor pattern SCP for each transistor M. The semiconductor pattern SCP may include a channel region that overlaps with the gate electrode GE of the transistor M, and first and second conductive regions (e.g., source and drain regions) located on both sides of the channel region. The semiconductor pattern SCP may be a semiconductor pattern made of polysilicon, amorphous silicon, or an oxide semiconductor.

[0208] A gate insulating layer GI may be placed on the semiconductor layer. A second conductive layer may be placed on the gate insulating layer GI.

[0209] The second conductive layer may include the gate electrode GE of each transistor M. The second conductive layer may further include one electrode and / or a bridge pattern of a capacitor Cst provided in the pixel circuit PXC. Additionally, if at least one power line and / or signal line located in the display area DA is composed of multiple layers, the second conductive layer may further include at least one wiring (or a portion of said at least one wiring).

[0210] An interlayer insulating layer (ILD) may be placed on the second conductive layer. A third conductive layer may be placed on the interlayer insulating layer (ILD).

[0211] The third conductive layer may include a source electrode SE and a drain electrode DE for each transistor M. The source electrode SE may be connected to a region of the semiconductor pattern SCP included in the transistor M (e.g., the source region) via at least one contact hole CH, and the drain electrode DE may be connected to another region of the semiconductor pattern SCP included in the transistor M (e.g., the drain region) via at least one other contact hole CH. In other embodiments, the source electrode SE and / or drain electrode DE of at least one transistor M may not be located in the third conductive layer but may be realized as the source region and / or drain region of the semiconductor pattern SCP.

[0212] In one embodiment, the third conductive layer may further include another electrode of the capacitor Cst provided in the pixel circuit PXC, at least one wiring and / or bridge pattern, etc. For example, the third conductive layer may include at least a portion of the wiring extending in the first direction DR1 in the display area DA.

[0213] Each electrode, conductive pattern (e.g., bridge pattern), and / or wiring constituting the first to third conductive layers can be conductive by containing a conductive material, and the constituent material is not particularly limited. For example, each electrode, conductive pattern, and / or wiring constituting the first to third conductive layers may contain one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), or other conductive material.

[0214] A passivation layer PSV may be placed on the third conductive layer. Each of the buffer layer BFL, gate insulating layer GI, interlayer insulating layer ILD, and passivation layer PSV may consist of a single layer or multiple layers and may contain inorganic and / or organic insulating materials. In one embodiment, each of the buffer layer BFL, gate insulating layer GI, and interlayer insulating layer ILD may contain silicon nitride, silicon oxide, silicon oxynitride, or other inorganic materials. In one embodiment, the passivation layer PSV may include at least one organic insulating layer containing an organic insulating material. In one embodiment, the passivation layer PSV can planarize the surface of the circuit layer PCL.

[0215] A display layer (DPL) may be placed on top of the passivation layer (PSV).

[0216] The display layer DPL may include the light-emitting unit EMU of each pixel PXL. For example, the display layer DPL may include an alignment electrode ALE, at least one light-emitting element LD, and a pixel electrode ELT, all located in the light-emitting region EA of each pixel PXL. In one embodiment, each light-emitting unit EMU may include multiple light-emitting elements LD.

[0217] The indicator layer DPL may further include insulating patterns and / or insulating layers sequentially arranged on one surface of the base layer BSL on which the circuit layer PCL is formed. For example, the indicator layer DPL may include a bank pattern BNP, a first insulating layer INS1, a first bank BNK1, a second insulating layer INS2, a third insulating layer INS3, a second bank BNK2, a fourth insulating layer INS4, a fifth insulating layer INS5, and / or a sixth insulating layer INS6. The indicator layer DPL may further selectively include an optical conversion layer CCL.

[0218] The bank pattern BNP may be placed on the passivation layer PSV. The bank pattern BNP may be placed beneath the alignment electrode ALE so as to overlap with a portion of each of the alignment electrode ALEs.

[0219] The bank pattern BNP allows the alignment electrode ALE to protrude upward (e.g., in the third direction DR3) around the light-emitting element LD. The bank pattern BNP and the alignment electrode ALE above it can form a reflective protruding pattern around the light-emitting element LD. This can improve the optical efficiency of the pixel PXL.

[0220] The bank pattern BNP may be a single-layer or multi-layer insulating pattern containing inorganic and / or organic insulating materials. Aligned electrodes ALE may be placed on the bank pattern BNP.

[0221] Aligned electrodes (ALEs) may contain conductive material. As an example, each aligned electrode ALE may contain at least one conductive material from a diverse range of metallic substances including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc., or an alloy containing such a metal; conductive oxides such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), AZO (Aluminum doped Zinc Oxide), GZO (Gallium doped Zinc Oxide), ZTO (Zinc Tin Oxide), GTO (Gallium Tin Oxide), and FTO (Fluorine doped Tin Oxide); and conductive polymers such as PEDOT; or other conductive materials. Aligned electrodes (ALEs) may contain the same or different conductive materials.

[0222] Each alignment electrode ALE may consist of a single layer or multiple layers. In one embodiment, each alignment electrode ALE may include a reflective electrode layer containing a reflective conductive material (e.g., a metal).

[0223] A first insulating layer INS1 may be placed on the alignment electrode ALE. In one embodiment, the first insulating layer INS1 may include contact holes for connecting at least one of the alignment electrode ALEs to one of the pixel electrodes ELT. For example, the first insulating layer INS1 may include contact holes for forming the fourth and fifth contact portions CNT4 and CNT5 in Figure 13. In other embodiments, the first insulating layer INS1 may be more widely open in the light-emitting region EA to expose at least one of the alignment electrode ALEs, and each pixel electrode ELT may be directly placed on each exposed alignment electrode ALE.

[0224] The first insulating layer INS1 may be a single layer or multiple layers. The first insulating layer INS1 may contain silicon nitride, silicon oxide, silicon oxynitride, or other insulating material.

[0225] A first bank BNK1 may be arranged in the display region DA where the alignment electrode ALE and the first insulating layer INS1 are formed. The first bank BNK1 may be arranged in the non-emitting region NEA so as to surround the light-emitting region EA of each pixel PXL.

[0226] A light-emitting element LD may be placed in each light-emitting region EA enclosed by the first bank BNK1. The light-emitting elements LD may be aligned between alignment electrodes ALE. For example, at least one first light-emitting element LD1 may be aligned or placed between the first alignment electrode ALE1 and the second alignment electrode ALE2, and at least one second light-emitting element LD2 may be aligned or placed between the first alignment electrode ALE1 and the third alignment electrode ALE3.

[0227] A second insulating layer INS2 may be placed on a portion of the light-emitting element LD. In one embodiment, the second insulating layer INS2 may be locally placed on a portion of the light-emitting element LD, including the central portion, so as to expose the first and second ends EP1 and EP2 of the light-emitting element LD. In other embodiments, the second insulating layer INS2 may be formed over the entire display area DA, which includes a number of pixel areas, and may include contact holes that expose the first and second ends EP1 and EP2 of the light-emitting element LD. The second insulating layer INS2 can stably fix the light-emitting element LD.

[0228] The second insulating layer INS2 may be a single layer or multiple layers. The second insulating layer INS2 may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, photoresist material, or other insulating material.

[0229] Different pixel electrodes ELTs may be arranged and / or formed on the first and second ends EP1 and EP2 of the light-emitting element LD. For example, a first pixel electrode ELT1 may be arranged on the first end EP1 of the first light-emitting element LD1, and a portion of a third pixel electrode ELT3 may be arranged on the second end EP2 of the first light-emitting element LD1. The other portion of the third pixel electrode ELT3 may be arranged on the first end EP1 of the second light-emitting element LD2, and a second pixel electrode ELT2 may be arranged on the second end EP2 of the second light-emitting element LD2.

[0230] In one embodiment, the first pixel electrode ELT1 may be electrically connected to the first alignment electrode ALE1 via at least one contact portion (for example, the fourth contact portion CNT4 in Figure 13). The second pixel electrode ELT2 may be electrically connected to the third alignment electrode ALE3 via at least one contact portion (for example, the fifth contact portion CNT5 in Figure 13). The third pixel electrode ELT3 may electrically connect at least one first light-emitting element LD1 and at least one second light-emitting element LD2 to each other.

[0231] In one embodiment, the first alignment electrode ALE1 of each pixel PXL may be electrically connected to the first transistor M1 of the corresponding pixel PXL via at least one contact portion (e.g., the first contact portion CNT1 in Figure 13). Similarly, the second and third alignment electrodes ALE2 and ALE3 may each be electrically connected to the second power line PL2 via at least one contact portion (e.g., the second contact portion CNT2 and the third contact portion CNT3 in Figure 13).

[0232] The first pixel electrode ELT1 may overlap with a portion of the first alignment electrode ALE1, and the second pixel electrode ELT2 may overlap with a portion of the third alignment electrode ALE3. The third pixel electrode ELT3 may overlap with the remaining portion of the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0233] The first pixel electrode ELT1 may be electrically connected to the first end EP1 of the first light-emitting element LD1, and the second pixel electrode ELT2 may be electrically connected to the second end EP2 of the second light-emitting element LD2. The third pixel electrode ELT3 may be electrically connected to the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2.

[0234] In one embodiment, the first pixel electrode ELT1, the second pixel electrode ELT2, and the third pixel electrode ELT3 may be arranged on the same layer as shown in Figure 14. In another embodiment, some of the pixel electrode ELTs (e.g., the first pixel electrode ELT1 and the second pixel electrode ELT2) and the remainder may be arranged on different layers. In this case, an insulating layer may be placed between the pixel electrode ELTs that are arranged on different layers.

[0235] Similar to the embodiment shown in Figure 11, if each pixel PXL includes a parallel-structured light-emitting unit EMU, or if each pixel PXL includes a single light-emitting element LD, the pixel PXL does not need to include a third pixel electrode ELT3. In this case, the first pixel electrode ELT1 may be placed on the first end EP1 of the light-emitting element LD, and the second pixel electrode ELT2 may be placed on the second end EP2 of the light-emitting element LD.

[0236] The pixel electrode ELT may include at least one conductive material. In one embodiment, the pixel electrode ELT may include a transparent conductive material that allows light emitted from the light-emitting element LD to pass through.

[0237] A third insulating layer INS3 may be placed on the pixel electrode ELT. The third insulating layer INS3 may be a single layer or multiple layers. The third insulating layer INS3 may contain silicon nitride, silicon oxide, silicon oxynitride, or other insulating material.

[0238] In one embodiment, the display device DD may include an optical conversion layer CCL disposed on the light-emitting part EMU of each pixel PXL. For example, the optical conversion layer CCL may be provided in each light-emitting region EA so as to be located above the light-emitting element LD of each pixel PXL.

[0239] The display device DD may further include a second bank BNK2 positioned in a non-emitting region NEA so as to overlap with the first bank BNK1. The second bank BNK2 may define (or partition) each emitting region EA in which a photoconversion layer CCL is formed. The second bank BNK2 may be integrated with the first bank BNK1.

[0240] The second bank, BNK2, may contain light-shielding and / or reflective materials, including black matrix materials. The second bank, BNK2, may contain the same or different materials as the first bank, BNK1.

[0241] The optical conversion layer CCL may include at least one of wavelength conversion particles (or color conversion particles) for converting the color and / or wavelength of light emitted from the light-emitting element LD, and light scattering particles SCT for scattering the light emitted from the light-emitting element LD to increase the light emission efficiency of the pixel PXL. As an example, each optical conversion layer CCL may be placed on each light-emitting unit EMU. Each optical conversion layer CCL may include at least one type of wavelength conversion particle WS (e.g., quantum dots corresponding to red, green, and / or blue) that converts incident light into light of a specific color, and / or light scattering particles SCT. The wavelength conversion particles WS and / or light scattering particles SCT may be dispersed in the base resin BS of the optical conversion layer CCL.

[0242] For example, if any one pixel PXL is set as a red (or green) pixel, and a blue light-emitting element LD is provided in the light-emitting unit EMU of the pixel PXL, then a photoconversion layer CCL containing red (or green) wavelength conversion particles WS for converting blue light to red (or green) light may be arranged on the light-emitting unit EMU of the pixel PXL. The photoconversion layer CCL may further include light scattering particles SCT. In one embodiment, if any one pixel PXL is set as a blue pixel, and a blue light-emitting element LD is provided in the light-emitting unit EMU of the pixel PXL, then a photoconversion layer CCL containing light scattering particles SCT may be arranged on the light-emitting unit EMU of the pixel PXL.

[0243] At least one of the fourth insulating layer INS4, the fifth insulating layer INS5, and the sixth insulating layer INS6 may be formed on one surface of the base layer BSL, which includes the light-emitting part EMU and / or the optical conversion layer CCL of the pixel PXL.

[0244] The fourth insulating layer INS4 may cover the light-emitting unit EMU and / or the optical conversion layer CCL of the pixel PXL to protect the EMU and / or optical conversion layer CCL. The fourth insulating layer INS4 may be a single layer or multiple layers. The fourth insulating layer INS4 may contain silicon nitride, silicon oxide, silicon oxynitride, or other insulating material.

[0245] The fifth insulating layer INS5 may be placed on the fourth insulating layer INS4. In one embodiment, the fifth insulating layer INS5 may be an overcoat layer comprising at least one organic insulating layer. The fifth insulating layer INS5 can substantially flatten the surface of the display layer DPL.

[0246] The sixth insulating layer INS6 may be placed on the fifth insulating layer INS5. The sixth insulating layer INS6 may be a capping layer containing silicon nitride, silicon oxide, silicon oxynitride, or other insulating material.

[0247] A color filter layer (CFL) may be placed on the display layer (DPL).

[0248] The color filter layer CFL may include color filters CF corresponding to the colors of the pixels PXL. For example, the color filter layer CFL may include a first color filter CF1 located in the light-emitting region EA of the first color pixel PXL1, a second color filter CF2 located in the light-emitting region EA of the second color pixel PXL2, and a third color filter CF3 located in the light-emitting region EA of the third color pixel PXL3. Each color filter CF may be provided on the sixth insulating layer INS6 so as to overlap with the light-emitting portion EMU of the corresponding pixel PXL.

[0249] The first color filter CF1 can selectively transmit light of the first color. The second color filter CF2 can selectively transmit light of the second color. The third color filter CF3 can selectively transmit light of the third color.

[0250] In one embodiment, the first, second, and third color filters CF1, CF2, and CF3 can be superimposed on each other in the non-emitting region (NEA) to function as a light-shielding pattern. In another embodiment, the first, second, and third color filters CF1, CF2, and CF3 are formed separately from each other above the light-emitting region (EA) of each pixel PXL, and a separate light-shielding pattern may be placed between the first, second, and third color filters CF1, CF2, and CF3.

[0251] A sealing layer ENC may be placed on the color filter layer CFL. The sealing layer ENC may include a seventh insulating layer INS7.

[0252] The seventh insulating layer INS7 may be a single layer or multiple layers. In one embodiment, the seventh insulating layer INS7 includes at least one inorganic film to prevent the intrusion of oxygen or moisture. In one embodiment, the seventh insulating layer INS7 includes at least one organic film to flatten the surface of the display device DD.

[0253] Figure 15 is a magnified view of a region of the pixel PXL shown in Figure 14. For example, Figure 15 is a magnified cross-sectional view of a region of the pixel PXL (e.g., region AR1 in Figure 14) centered on the first light-emitting element LD1. In one embodiment, the light-emitting elements LDs included in the pixel PXL may be substantially the same or similar types and / or structures of each other. For example, the second light-emitting element LD2 may be the same type and / or structure of the first light-emitting element LD1.

[0254] Figure 16 is a magnified view of a region of the light-emitting element LD shown in Figure 15. For example, Figure 16 shows a region of the light-emitting element LD (e.g., region AR2 in Figure 15) according to an embodiment in which the pixel PXL in Figures 14 and 15 includes the light-emitting element LD of Figure 3.

[0255] FIG. 17 is a diagram showing an enlarged view of a region of the light-emitting element LD shown in FIG. 15. For example, FIG. 17 shows a region (for example, the AR2 region in FIG. 15) of the light-emitting element LD according to an embodiment in which the pixels PXL in FIGS. 14 and 15 include the light-emitting element LD in FIG. 4.

[0256] Referring to FIGS. 15 to 17 in addition to FIGS. 1 to 14, the pixel PXL of the display device DD may include at least two pixel electrodes ELT separated from each other, and at least one light-emitting element LD electrically connected between the pixel electrodes ELT. Each light-emitting element LD includes a first semiconductor layer SCL1, an active layer ACT, and a second semiconductor layer SCL2 sequentially arranged along one direction, and may further selectively include an electrode layer ETL. Each light-emitting element LD may further include a multilayer oxide insulating film MLO and a protective film PRL surrounding at least the outer peripheral surfaces of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2.

[0257] The multilayer oxide insulating film MLO may include a first insulating film INF1 surrounding at least the outer peripheral surfaces of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2, a second insulating film INF2 surrounding the first insulating film INF1, and a third insulating film INF3 surrounding the second insulating film INF2. The first insulating film INF1 may include an M1 x O y type oxide (for example, an M1O2 type oxide). The second insulating film INF2 may include an M2 2x O (2y-1) type oxide (for example, an M22O3 type oxide). The third insulating film INF3 may include an M3 x O y type oxide (for example, an M3O2 type oxide).

[0258] The protective film PRL may include at least one of the fourth insulating film INF4 and the fifth insulating film INF5 surrounding the third insulating film INF3. For example, the protective film PRL may include only the fourth insulating film INF4 as shown in Figure 16, or it may include both the fourth insulating film INF4 and the fifth insulating film INF5 as shown in Figure 17. The protective film PRL may also be a multilayer film of three or more layers, further including one or more insulating films.

[0259] As mentioned above, the light-emitting LD according to the embodiment is M1 x O y First insulating film INF1, M2 containing type oxide 2x O (2y-1) The second insulating film INF2 and M3 contain type oxides. x O y The third insulating film INF3 may contain a type oxide. Oxygen vacancies (V) are present at the interfaces of the first, second, and third insulating films INF1, INF2, and INF3. O ) can be formed.

[0260] According to the embodiment, oxygen vacancies (V) formed at the interfaces of the first, second, and third insulating films INF1, INF2, and INF3 are O This allows for blocking or reducing the inflow of oxygen into the light-emitting laminate (LES). This improves the degradation characteristics of the light-emitting diode (LD) and enhances its reliability.

[0261] The display device DD according to this embodiment may include a pixel PXL containing the light-emitting element LD. This improves the degradation characteristics of the display device DD and enhances its reliability.

[0262] While embodiments of the present invention have been described above with reference to the attached drawings, any person with ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without altering its technical spirit or essential features. Therefore, the above embodiments are illustrative in all respects and should not be interpreted as limiting.

Claims

1. A first semiconductor layer, an active layer, and a second semiconductor layer are arranged sequentially along one direction. The outer surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer are surrounded by M1 ｘ O ｙ A first insulating film containing a type oxide, Surrounding the first insulating film, M2 ２ｘ O （２ｙ－１） A second insulating film containing a type oxide, Surrounding the second insulating film, M3 ｘ O ｙ A third insulating film containing a type oxide, The third insulating film includes a fourth insulating film surrounding the third insulating film, M1, M2, and M3 are each metallic substances. A light-emitting element in which x and y are each natural numbers.

2. The light-emitting element according to claim 1, wherein the sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film is 10 nm or less.

3. The light-emitting element according to claim 2, wherein the fourth insulating film has a thickness greater than the sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film.

4. The light-emitting element according to claim 1, wherein the thickness of the first insulating film is greater than the thickness of the second insulating film.

5. The light-emitting element according to claim 4, wherein the thickness of the third insulating film is greater than or equal to the thickness of the second insulating film.

6. The first insulating film is M1O ２ Contains type oxides, The second insulating film is M2 ２ O ３ and contains an O-type oxide. The third insulating film is M3O ２ The light-emitting element according to claim 1, comprising a type oxide.

7. The first insulating film is SiO ２ , ZrO ２ , HfO ２ , GeO ２ , TiO ２ TeO ２ It contains at least one of the following oxides, The second insulating film is Al ２ O ３ , Y ２ O ３ La ２ O ３ Ce ２ O ３ Lu ２ O ３ , Sc ２ O ３ Yb ２ O ３ The light-emitting element according to claim 6, comprising at least one oxide among the following.

8. The third insulating film is SiO ２ , ZrO ２ , HfO ２ , GeO ２ , TiO ２ TeO ２ The light-emitting element according to claim 7, comprising at least one oxide among the above.

9. The first insulating film is ZrO ２ Includes, The second insulating film is Al ２ O ３ Includes, The third insulating film is ZrO ２ The light-emitting element according to claim 8, including the light-emitting element according to claim 8.

10. The light-emitting element according to claim 1, further comprising a fifth insulating film surrounding the fourth insulating film and having a thickness greater than the thickness of the fourth insulating film.

11. The fourth insulating film is an inorganic film containing an oxide, The light-emitting element according to claim 10, wherein the fifth insulating film is an inorganic film containing an oxide different from the material of the fourth insulating film.

12. A first semiconductor layer, an active layer, and a second semiconductor layer are arranged sequentially along one direction. The outer surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer are surrounded by M1 ｘ O ｙ A first insulating film containing a type oxide, Surrounding the first insulating film, M2 ２ｘ O （２ｙ－１） A second insulating film containing a type oxide, Surrounding the second insulating film, M3 ｘ O ｙ It includes a third insulating film containing a type oxide, M1, M2, and M3 are each metallic substances. The aforementioned x and y are natural numbers, The thickness of the first insulating film is greater than the thickness of the second insulating film. A light-emitting element in which the thickness of the third insulating film is greater than or equal to the thickness of the second insulating film.

13. The light-emitting element according to claim 12, wherein the sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film is 10 nm or less.

14. The first insulating film is M1O ２ Contains type oxides, The second insulating film is M2 ２ O ３ Contains type oxides, The third insulating film is M3O ２ The light-emitting element according to claim 12, comprising a type oxide.

15. The first insulating film is SiO ２ , ZrO ２ , HfO ２ , GeO ２ , TiO ２ TeO ２ It contains at least one of the following oxides, The second insulating film is Al ２ O ３ , Y ２ O ３ La ２ O ３ Ce ２ O ３ Lu ２ O ３ , Sc ２ O ３ Yb ２ O ３ The light-emitting element according to claim 14, comprising at least one oxide among the above.

16. The third insulating film is SiO ２ , ZrO ２ , HfO ２ , GeO ２ , TiO ２ TeO ２ The light-emitting element according to claim 15, comprising at least one oxide among the following.

17. The first insulating film is ZrO ２ Includes, The second insulating film is Al ２ O ３ Includes, The third insulating film is ZrO ２ The light-emitting element according to claim 16, including the light-emitting element according to claim 16.

18. The light-emitting element according to claim 12, further comprising a fourth insulating film surrounding the third insulating film and having a thickness greater than the sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film.

19. The light-emitting element according to claim 18, further comprising a fifth insulating film surrounding the fourth insulating film and having a thickness greater than the thickness of the fourth insulating film.

20. A pixel includes a first electrode and a second electrode spaced apart from each other, and a light-emitting element electrically connected between the first electrode and the second electrode. The light-emitting element is A first semiconductor layer, an active layer, and a second semiconductor layer are arranged sequentially along one direction. The outer surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer are surrounded by M1 ｘ O ｙ A first insulating film containing a type oxide, Surrounding the first insulating film, M2 ２ｘ O （２ｙ－１） A second insulating film containing a type oxide, Surrounding the second insulating film, M3 ｘ O ｙ A third insulating film containing a type oxide, The third insulating film includes a fourth insulating film surrounding the third insulating film, M1, M2, and M3 are each metallic substances. A display device in which x and y are each natural numbers.

21. The display device according to claim 20, wherein the sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film is 10 nm or less.

22. The display device according to claim 21, wherein the fourth insulating film has a thickness greater than the sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film.

23. The thickness of the first insulating film is greater than the thickness of the second insulating film. The display device according to claim 20, wherein the thickness of the third insulating film is greater than or equal to the thickness of the second insulating film.

24. The first insulating film is M1O ２ Contains type oxides, The second insulating film is M2 ２ O ３ Contains type oxides, The third insulating film contains M3O ２ The display device according to claim 20, which contains an oxide of the M3O type.

25. The first insulating film is SiO ２ , ZrO ２ , HfO ２ , GeO ２ , TiO ２ TeO ２ It contains at least one of the following oxides, The second insulating film is Al ２ O ３ 、Y ２ O ３ 、La ２ O ３ 、Ce ２ O ３ 、Lu ２ O ３ 、Sc ２ O ３ 、Yb ２ O ３ The display device according to claim 24, comprising at least one oxide selected from the group consisting of Al

26. The third insulating film is SiO ２ , ZrO ２ , HfO ２ , GeO ２ , TiO ２ TeO ２ The display device according to claim 25, comprising at least one oxide.

27. The first insulating film is ZrO ２ Includes, The second insulating film is Al ２ O ３ Includes, The third insulating film is ZrO ２ The display device according to claim 26, including the following:

28. The display device according to claim 20, further comprising a fifth insulating film surrounding the fourth insulating film and having a thickness greater than the thickness of the fourth insulating film.

29. The fourth insulating film is an inorganic film containing an oxide, The display device according to claim 28, wherein the fifth insulating film is an inorganic film containing an oxide different from the material of the fourth insulating film.

30. The display device according to claim 20, wherein the pixel further includes a first alignment electrode and a second alignment electrode disposed below the light-emitting element and spaced apart from each other.

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