Chip short circuit verification method, apparatus, chip detection method, chip and consumable box

Abstract

A chip short-circuit verification method, apparatus, chip detection method, chip, and consumables box. The chip comprises a substrate having a first half and a second half; a ground terminal located in the first half of the substrate and having a ground wire contact portion for contacting a printer stylus; at least two conductive terminals located in the second half of the substrate and spaced apart from each other, wherein the conductive terminals have contact portions for contacting a printer stylus; and a detection unit located on the substrate and electrically connected to the ground terminal, and having a first detection segment, wherein the first detection segment is located between the first conductive terminal and the second conductive terminal.

Description

Technical Field

[0001] <Cross - reference to Related Applications> This application claims the priority of a Chinese patent application with an application number of 202310301995.4 and a title of "Chip Short - circuit Verification Method, Device, Chip and Ink Cartridge" filed on March 26, 2023, the priority of a Chinese patent application with an application number of 202321960927.0 and a title of "Chip and Ink Cartridge" filed on July 24, 2023, and the priority of a Chinese patent application with an application number of 202311737080.4 and a title of "Chip Short - circuit Verification Method, Device, Chip Detection Method, Chip and Consumable Box" filed on December 15, 2023, the entire texts of which are incorporated herein by reference.

[0002] This application relates to the technical field of printing devices, particularly to chip short - circuit verification methods, devices, chip detection methods, chips, and consumable boxes.

Background Art

[0003] A general printing device is equipped with a detachable consumable box to facilitate the replacement of the consumable box when the ink runs out. Ink cartridges, toner cartridges, ink bag boxes, etc. all belong to general consumable boxes, and usually, all are equipped with chips. Various information can be stored in the chips, and they can also communicate with the printing device.

[0004] Usually, power supply terminals (VDD), data terminals (DATA), clock terminals (CLK), reset terminals (RST / CE), and ground terminals (GND), etc. are provided on the chip. The ink in the consumable box may drip onto the terminals of the chip, or other conductive materials may adhere to the terminals. When adjacent terminals are connected through ink or conductive materials, short - circuit failures or burn - outs may occur in the chip or the printing device. Therefore, usually, short - circuit verification is performed on the chip, and only when the chip passes the short - circuit verification, the printing device sends subsequent normal communication commands to the chip.

Summary of the Invention

[0005] Currently, during the chip short-circuit verification phase, the printer first sends a short-circuit verification command to the chip. Subsequently, the data terminals on the chip feed back the waveform expected by the printer, indicating that no short circuit has occurred in the chip. Otherwise, it is determined that a short circuit has occurred in the chip. However, in actual application processes, if the chip's functionality is damaged, the chip cannot feed back the waveform expected by the printer during the chip short-circuit verification phase, resulting in an error in the chip short-circuit verification result.

[0006] Regarding the issue of errors in certifying short-circuit verification results for chips in related technologies, no effective solution has yet been proposed. [Means for solving the problem]

[0007] According to various embodiments of this application, a chip short-circuit verification method, apparatus, chip detection method, chip and consumable box are provided.

[0008] In a first aspect, the present application relates to a chip suitable for communication connection with a printer, comprising: a substrate having a first half and a second half; an earth terminal having an earth wire contact portion located in the first half of the substrate for contacting a printer stylus; at least two conductive terminals located in the second half of the substrate, spaced apart from each other, including a first conductive terminal and a second conductive terminal, each conductive terminal having a contact portion for contacting a printer stylus, and the distance between the contact portion of the first conductive terminal and the contact portion of the second conductive terminal being less than the distance between either one of them and the earth wire contact portion; and a detection unit located on the substrate and electrically connected to the earth terminal, comprising a first detection segment, the first detection segment being located between the first conductive terminal and the second conductive terminal, with the first detection segment and the first conductive terminal spaced apart from each other, and the first detection segment and the second conductive terminal spaced apart from each other.

[0009] In some embodiments, the detection unit further comprises a second detection segment, the second detection segment and the first detection segment located adjacent to each other on both sides of the first conductive terminal, and the second detection segment, in cooperation with the first detection segment, surrounds the first conductive terminal.

[0010] In some embodiments, the detection unit surrounds the first conductive terminal with a gap.

[0011] In some embodiments, the intersection of the second detection segment and the first detection segment is close to the contact portion of the first conductive terminal and away from the ground wire contact portion.

[0012] In some embodiments, at least two conductive terminals further include a third conductive terminal, the third conductive terminal and the first conductive terminal are spaced apart, and the second detection segment is located between the first conductive terminal and the third conductive terminal, and in the alignment direction of the third conductive terminal and the first conductive terminal, the projection of the second detection segment covers the first conductive terminal.

[0013] In some embodiments, there are four conductive terminals and one ground terminal, and the chip is equipped with a test terminal, which is electrically insulated from the printer's stylus when the chip is mounted.

[0014] In some embodiments, at least two conductive terminals further include a third conductive terminal and a fourth conductive terminal, wherein the distance between the contact portion of the third conductive terminal and the contact portion of the fourth conductive terminal is smaller than the distance between either one of them and the ground wire contact portion, the first conductive terminal and the second conductive terminal are arranged sequentially along a first direction, the fourth conductive terminal and the second conductive terminal are arranged sequentially along a second direction, the ground terminal, the third conductive terminal and the first conductive terminal are arranged sequentially along a second direction, the second direction and the first direction intersect, and the contact portion of the fourth conductive terminal and the ground wire contact portion are symmetrical with respect to a dividing cross-section for separating the first half and the second half.

[0015] In some embodiments, the detection unit further comprises a third detection segment, the third detection segment, the first detection segment and the second detection segment cooperating to surround the third conductive terminal, and / or the detection unit further comprises a fourth detection segment located between the second conductive terminal and the fourth conductive terminal, and the projection of the fourth detection segment covers the second conductive terminal in the direction of arrangement of the fourth conductive terminal and the second conductive terminal.

[0016] In some embodiments, the chip further comprises memory and a processor, the memory being electrically connected to the processor, the processor being electrically connected to a first conductive terminal, and the processor being for processing signals from the first conductive terminal. For example, the memory is electrically connected to the first conductive terminal. For example, the processor is electrically connected to a second conductive terminal. For example, the memory is electrically connected to a second conductive terminal.

[0017] In some embodiments, at least two conductive terminals further include a third conductive terminal and a fourth conductive terminal, wherein the contact portion of the first conductive terminal and the ground wire contact portion are asymmetric with respect to a dividing cross section for separating the first half and the second half, and the connection direction of the contact portion of the third conductive terminal and the ground wire contact portion intersects with the connection direction of the contact portion of the second conductive terminal and the contact portion of the fourth conductive terminal.

[0018] In some embodiments, the first conductive terminal may be a clock terminal, the second conductive terminal may be a data terminal, the third conductive terminal may be a power terminal, and the fourth conductive terminal may be a reset terminal.

[0019] As an example, the chip further comprises a circuit pattern, and the processor is electrically connected to a first conductive terminal and a second conductive terminal, respectively, by the circuit pattern, and is also electrically connected to memory by the circuit pattern. The processor may be for processing the signal from the second conductive terminal.

[0020] The chip provided in this application can also perform abnormality recognition between conductive terminals and circuit patterns by being equipped with a detection unit.

[0021] In a second aspect, the present application provides a consumable box equipped with the aforementioned chip.

[0022] In some embodiments, the consumable box comprises a box having a bottom wall and side walls, the chips being mounted on the side walls of the box, and the dividing cross section of the chips, which separates a first half from a second half, is perpendicular to the bottom wall.

[0023] In some embodiments, the ground terminal and the second conductive terminal are provided opposite each other and separated by a first detection segment, the ground terminal being located on one side of the first detection segment closer to the bottom wall, and the second conductive terminal being located on the one side of the first detection segment away from the bottom wall, with the extension direction of the first detection segment parallel to the bottom wall.

[0024] In a third aspect, the present application further provides a printing system comprising a printer and the aforementioned consumable box, which is detachably connected to the printer and in which a chip is electrically connected to the printer.

[0025] In a fourth aspect, the present application provides a chip detection method, the method being applied to a test chip provided with a detection unit, the test chip further comprising a substrate, a ground terminal, a clock terminal, a data terminal, a power terminal and a reset terminal, the detection unit being located on the substrate and electrically connected to the ground terminal, the detection unit comprising a first detection segment, a second detection segment and a ground segment, the first detection segment being connected to the ground terminal via the ground segment, the data terminal and the reset terminal both being located on one side of the first detection segment, the clock terminal and the power terminal both being located on the other side of the first detection segment, the second detection segment and the first detection segment being connected, the clock terminal and the power terminal being spaced apart, and the method is A step of obtaining a short - circuit verification signal; Based on the short - circuit verification signal, at a specified time in the verification response period, a step of setting a desired - level signal for the data terminal in the test - target chip; A step of obtaining the actual output - level signal of the data terminal to which the desired - level signal is set; Based on the actual output - level signal, a step of specifying a detection result of the test - target chip, the detection result of the test - target chip including normal function of the test - target chip or a failure of the test - target chip.

[0026] In some of the embodiments, the step of specifying a detection result of the test - target chip based on the actual output - level signal is: When the actual output - level signal matches the desired - level signal, as the detection result of the test - target chip, the function of the test - target chip is normal; When the actual output - level signal does not match the desired - level signal, as the detection result of the test - target chip, it is a failure of the test - target chip. The failure of the test - target chip includes at least one of a short - circuit of the remaining terminals other than the reset terminal in the test - target chip, a short - circuit of the reset terminal with the clock terminal and / or the power terminal, a short - circuit of any terminal other than the reset terminal with the detection unit, and a functional damage of the test - target chip.

[0027] In some of the embodiments, when the actual output - level signal matches the desired - level signal, the method further includes: A step of further specifying whether the voltage of the reset terminal of the test - target chip continues within a predetermined voltage range in the verification response period; When the voltage of the reset terminal of the test - target chip continues within a predetermined voltage range in the verification response period, the test - target chip is not short - circuited; If the voltage at the reset terminal of the chip under test does not remain within a predetermined voltage range during the verification response period, a short circuit will occur between the reset terminal and the data terminal or ground terminal of the chip under test.

[0028] In a fifth aspect, the present application provides a chip short-circuit verification method. Steps include obtaining a short-circuit verification signal, Based on the aforementioned short-circuit verification signal, the steps include setting a desired level signal to the data terminal of the chip under test at a specified time during the verification response period, The steps include acquiring the actual output level signal of the data terminal to which the desired level signal has been set, A step of identifying the short-circuit verification result of the test chip based on the actual output level signal, the short-circuit verification result being that the function of the test chip is normal, but the reset terminal and at least one terminal other than the reset terminal are short-circuited in the test chip, and the function of the test chip is normal and not short-circuited, or the function of the test chip is impaired.

[0029] In some of these embodiments, the step of identifying the short-circuit verification result of the chip under test based on the actual output level signal is: If the actual output level signal does not match the desired level signal, the short-circuit verification result includes damage to the function of the chip under test.

[0030] In some of these embodiments, when the actual output level signal matches the desired level signal, the function of the chip under test is normal, and the method further... The further step includes determining whether the voltage of the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period. If the voltage at the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period, then the chip under test is not short-circuited. If the voltage at the reset terminal of the chip under test does not remain within a predetermined voltage range during the verification response period, the reset terminal and at least one other terminal of the chip under test will be short-circuited.

[0031] In some of these embodiments, when the actual output level signal matches the desired level signal, the function of the chip under test is normal, and the method further... The process includes determining whether the test chip responds to a communication command within a preset communication period, wherein the communication command is a communication command transmitted by a printing device communicating with the test chip, and the preset communication period is after the verification response period. If, during the preset communication period, the test target chip does not respond to the communication command, the short-circuit verification result indicates that the test target chip is functioning normally, but the reset terminal and at least one terminal other than the reset terminal are short-circuited. If the test target chip responds to a communication command within the preset communication period, the short-circuit verification result indicates that the test target chip is functioning normally and is not short-circuited.

[0032] In some of these embodiments, the step of setting a desired level signal to the data terminal of the chip under test at a specified time in the verification response period based on the short-circuit verification signal is: The steps include identifying multiple clock times of the clock terminals in the chip under test based on the short-circuit verification signal, A step of identifying a verification response period based on multiple clock times, The verification response period includes the step of identifying the corresponding specified time for the data terminal on the test target chip, The method includes the step of setting a desired level signal at the corresponding specified time of the data terminal.

[0033] In some of these embodiments, the specified time includes a first specified time, a second specified time, and a third specified time, wherein the first specified time is earlier than the second specified time, the second specified time is earlier than the third specified time, and the step of setting a desired level signal at the corresponding specified time of the data terminal is: The method includes the steps of setting a low-level signal at the first designated time corresponding to the data terminal, setting a high-level signal at the second designated time corresponding to the data terminal, and setting a low-level signal at the third designated time corresponding to the data terminal.

[0034] In some of these embodiments, the step of acquiring a short-circuit verification signal is performed as follows: The process includes the step of acquiring the original waveform data transmitted by the printing device, If a short-circuit verification mark exists in the original waveform data, the original waveform data is identified as a short-circuit verification signal.

[0035] In its sixth aspect, the present application provides a chip short-circuit verification device. A first acquisition module for acquiring a short-circuit verification signal, A level signal setting module for setting a desired level signal to the data terminal of the chip under test at a specified time during the verification response period based on the aforementioned short-circuit verification signal, A second acquisition module for acquiring the actual output level signal of the data terminal to which a desired level signal has been set, The system includes a specific module for identifying the short-circuit verification result of the test chip based on the actual output level signal, wherein the short-circuit verification result indicates that the function of the test chip is normal, but the reset terminal and at least one terminal other than the reset terminal are short-circuited, meaning the function of the test chip is normal and not short-circuited, or the function of the test chip is damaged.

[0036] In the seventh aspect, the present application provides a chip comprising a clock terminal, a data terminal, a power terminal, a ground terminal, a reset terminal, and a processing unit for performing the chip detection method described in any one of the fourth aspects, or the chip short-circuit verification method described in any one of the fifth aspects.

[0037] In its eighth aspect, the present application provides a consumable box comprising the chip described in its seventh aspect. Details of one or more embodiments of this application are submitted below with the drawings and description to make other features, purposes, and advantages of this application easier to understand. [Brief explanation of the drawing]

[0038] To more clearly illustrate the examples or related technologies of this application, the drawings necessary for describing the examples or related technologies are briefly introduced below. Clearly, the drawings described below are merely examples of the present invention, and those skilled in the art can obtain other drawings based on the disclosed drawings without any creative work.

[0039] [Figure 1] This is a schematic diagram of the chip configuration provided in this application. [Figure 2] This is a schematic diagram of the chip configuration provided in this application. [Figure 3] This is a schematic diagram of the chip configuration provided in this application. [Figure 4] This is a schematic diagram of the chip configuration provided in this application. [Figure 5] This is a schematic diagram of the chip configuration provided in this application. [Figure 6] This is a schematic block diagram of the printing system provided in this application. [Figure 7] This is the waveform of the chip provided in this application during normal operation. [Figure 8] This is the waveform when the reset terminal and the clock terminal are short-circuited in the chip provided in this application. [Figure 9]This is the waveform when the reset terminal and the data terminal are short-circuited in the chip provided in this application. [Figure 10] This is the waveform when the reset terminal and the power terminal are short-circuited in the chip provided in this application. [Figure 11] This is the waveform when the clock terminal and the power terminal are short-circuited in the chip provided in this application. [Figure 12] This is the waveform when the clock terminal and the data terminal are short-circuited in the chip provided in this application. [Figure 13] This is the waveform when the power terminal and the data terminal are short-circuited in the chip provided in this application. [Figure 14] This is a schematic exploded view of the consumables box provided in this application. [Figure 15] This is a magnified view of a section of Figure 14. [Figure 16] This is a schematic front view of the consumables box provided in this application. [Figure 17] This is a schematic diagram of the chip configuration provided in this application. [Figure 18] This is a schematic diagram of the chip configuration provided in this application. [Figure 19] This is a schematic diagram illustrating an application scenario for the chip short-circuit verification method provided in this application. [Figure 20] This is a flowchart of the chip short-circuit verification method provided in this application. [Figure 21] This is a schematic diagram of the configuration of the test chip provided in this application. [Figure 22] This is the complete short-circuit verification waveform of the chip provided in this application, when the chip is functioning normally and there is no short circuit. [Figure 23] This is a schematic diagram of the waveform of the verification response time period provided by the printing device in related technologies. [Figure 24] This is a schematic diagram of the original waveform of a short-circuit verification signal transmitted by a printing device in related technology. [Figure 25] This is a schematic diagram of the original waveform for each terminal provided in this application. [Figure 26]This is a schematic waveform diagram showing a short circuit between the reset terminal and the clock terminal provided in this application. [Figure 27] This is a schematic waveform diagram showing a short circuit between the reset terminal provided in this application and the corresponding data terminal of SDA1. [Figure 28] This is a schematic waveform diagram showing a short circuit between the reset terminal provided in this application and the corresponding data terminal of SDA2. [Figure 29] This is a schematic waveform diagram showing a short circuit between the reset terminal provided in this application and the corresponding data terminal of SDA3. [Figure 30] This is a schematic waveform diagram showing a short circuit between the reset terminal provided in this application and the corresponding data terminal of the SDA4. [Figure 31] This is a schematic waveform diagram showing a short circuit between the reset terminal and the power terminal provided in this application. [Figure 32] This is a schematic waveform diagram showing a short circuit between the reset terminal and the ground terminal provided in this application. [Figure 33] This is a schematic diagram of a configuration applied to a test chip equipped with the detection unit provided in this application. [Figure 34] This is a flowchart of the chip detection method provided in this application. [Figure 35] This is a schematic diagram of the waveform when the clock terminal and power supply terminal are short-circuited, as provided in this application. [Figure 36] This is a schematic diagram of the waveform when the clock terminal and data terminal are short-circuited, as provided in this application. [Figure 37] This is a schematic diagram of the waveform when the power terminal and data terminal are short-circuited, as provided in this application. [Figure 38] This is a schematic diagram of the waveform when a short circuit occurs between another reset terminal and a clock terminal, as provided in this application. [Figure 39] This is a schematic waveform diagram of a short circuit between another reset terminal and a power terminal provided in this application. [Figure 40] This is a block diagram of the chip short-circuit verification device provided in this application. [Modes for carrying out the invention]

[0040] The following clearly and completely describes the technical solutions in the embodiments of this application with reference to the drawings of the embodiments of this application. Clearly, the embodiments described are only a selection of embodiments of this application, not all embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments of this application, without any creative work, are all within the scope of protection of this application.

[0041] In the description of this application, the orientations or positional relationships indicated by terms such as "center," "vertical," "horizontal," "length," "width," "thickness," "top," "bottom," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inside," "outside," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" are orientations or positional relationships based on those shown in the attached drawings and are merely for the purpose of facilitating and simplifying the description of the present invention. They do not indicate or suggest that the pointed-out device or element has a specific orientation or must be constructed and operated in a specific orientation, and therefore cannot be understood as limiting this application.

[0042] In this application, unless otherwise explicitly stated or limited, the first feature being "above" or "below" the second feature may mean that the first and second features are in direct contact, or that they are indirectly in contact via an intermediate medium. Furthermore, the first feature being "above," "above," and "on the top surface" of the second feature may mean that the first feature is directly above or diagonally above the second feature, or simply that the horizontal height of the first feature is greater than that of the second feature. The first feature being "below," "below," and "on the bottom surface" of the second feature may mean that the first feature is directly below or diagonally below the second feature, or simply that the horizontal height of the first feature is lower than that of the second feature.

[0043] Furthermore, the terms “first” and “second” are used merely to describe the purpose and cannot be understood as indicating or implying relative importance or the number of designated technical features.¹ This allows “first” and “second” to explicitly or implicitly indicate that a limited feature includes at least one such feature. For example, among a plurality of conductive terminals, the first conductive terminal may be referred to as the third conductive terminal, the third conductive terminal may be referred to as the first conductive terminal, the fourth conductive terminal may be referred to as the second conductive terminal, and the second conductive terminal may be referred to as the fourth conductive terminal. In the description of the present invention, “plural” means at least two, and unless otherwise clearly and specifically limited, for example, two, three, etc.

[0044] In this application, unless otherwise explicitly stated and limited, terms such as “connection” and “bonding” should be understood broadly, and unless otherwise explicitly stated, they may be, for example, fixed connections, removable connections, or integral connections, flexible connections, rigid connections in at least one direction, mechanical connections, electrical connections, direct connections, indirect connections via an intermediate medium, or direct connections with an intermediate medium, or internal communication between two elements or an interaction relationship between two elements. Terms such as “mounting,” “installation,” and “fixing” should also be understood broadly as connections. A person skilled in the art may understand the specific meaning of the above terms in this utility model depending on the specific situation.

[0045] Referring to Figure 1, Figure 1 shows the chip in this application. In some embodiments, the chip 100 provided in this application may comprise a substrate 10, an earth terminal 5, a detection unit 6, and at least two conductive terminals.

[0046] The substrate 10 may be a printed circuit board and may have a single-layer or multi-layer structure. The surface shown in Figure 1 may be the working surface of the substrate 10. For example, the chip 100 may have a circuit pattern (not shown) provided on the substrate 10, and the circuit pattern may be located on the working surface of the substrate 10 or on other layers. The circuit pattern is electrically connected to each conductive terminal. The substrate 10 may have a substantially rectangular outer contour in the XY plane, and this rectangular outer contour is considered to have a central axis. The substrate 10 may be divided into a first half A and a second half B, and the cross-section of the first half A and the second half B may be substantially perpendicular to the X-axis direction. For example, in Figure 1, the right half of the substrate 10 may be the first half A and the left half may be the second half B.

[0047] The ground terminal 5 and at least two conductive terminals may both be located on the operating surface of the substrate 10. The chip 100 may be electrically connected to the printer 200 by the ground terminal 5 and these conductive terminals (Figure 6). The chip 100 may be provided, for example, in the box 310 of the consumable box 300 (Figure 14) and also attached to the printer 200 together. The printer 200 can verify whether the chip 100 is fully attached, and the verification method can typically involve detecting the signals of each terminal and determining whether the terminals and the stylus make good contact.

[0048] As shown in Figure 1, the ground terminal 5 may include a ground wire contact portion 51 for contacting the stylus of the printer 200. While the chip 100 is being mounted to the printer 200, the rest of the ground terminal 5 can also pass the stylus of the printer 200, but after it is fully mounted, the ground wire contact portion 51 makes contact with the stylus to achieve further electrical connection.

[0049] The conductive terminals may include a first conductive terminal 1 and a second conductive terminal 2. For illustrative purposes, these conductive terminals may further include a third conductive terminal 3 and a fourth conductive terminal 4. The first conductive terminal 1 and the second conductive terminal 2 are located on the substrate 10, spaced apart from each other, and are positioned in a first direction, roughly the Y-axis direction. To understand this, the first conductive terminal 1 and the second conductive terminal 2 may be offset in a second direction, the X-axis direction. Each conductive terminal may have a contact portion for electrical connection to the stylus of the printer 200. The first conductive terminal 1 has a first contact portion 11 for electrical connection to the stylus of the printer 200, and the second conductive terminal 2 has a second contact portion 21. For illustrative purposes, the third conductive terminal 3 has a third contact portion 31, and the fourth conductive terminal 4 has a fourth contact portion 41.

[0050] As an example, the first conductive terminal 1 and the ground terminal 5 can be aligned in the X-axis direction and can be aligned in a line. The distance between the first contact portion 11 and the second contact portion 21 is smaller than the distance between either of them and the ground wire contact portion 51. As shown in Figure 1, these conductive terminals may be located in the second half B, which is the left half of the substrate 10, and the ground terminal 5 may be located in the first half A, which is the right half of the substrate 10. In a preferred embodiment, there are four conductive terminals and one ground terminal 5.

[0051] The detection unit 6 is located on the substrate 10 and is exposed on the working surface of the substrate 10. The detection unit 6 is electrically connected to the earth terminal 5. For example, the detection unit 6 may include an earth segment 60, which is connected to the earth terminal 5 and may have a shape that extends away from the earth terminal 5.

[0052] The detection unit 6 may include a first detection segment 61, which is located between the first conductive terminal 1 and the second conductive terminal 2. The first detection segment 61 and the ground terminal 5 may be indirectly electrically connected, for example, by a grounding segment 60 or by bypassing it through another route. As shown in Figure 1, the first detection segment 61 may be electrically connected to the ground terminal 5 by a fifth detection segment 65 and a grounding segment 60. The first detection segment 61 and the first conductive terminal 1 and the second conductive terminal 2 are each spaced apart.

[0053] The chip 100 is used for electrical connection with external equipment. For example, the ground terminal 5 and these conductive terminals contact the stylus of the external equipment to establish an electrical connection. In some cases, for example, the chip 100 is used as an ink cartridge chip, and ink may drip onto the chip 100, thus potentially causing a short circuit between the first conductive terminal 1 and the second conductive terminal 2. Since the first detection segment 61 of the detection unit 6 is located between the first conductive terminal 1 and the second conductive terminal 2, the ink droplet that caused the short circuit between the first conductive terminal 1 and the second conductive terminal 2 will also cover the first detection segment 61. Furthermore, since the first detection segment 61 is electrically connected to the ground terminal 5, both the first conductive terminal 1 and the second conductive terminal 2 are electrically connected to the ground terminal 5.

[0054] At least one of the first conductive terminal 1 and the second conductive terminal 2 transmits a high-voltage electrical signal during use and, after being electrically connected to the ground terminal 5, the output signal is changed to a continuously low-voltage signal. Such a signal change may be used to represent a possible short-circuit fault between the first conductive terminal 1 and the second conductive terminal 2.

[0055] The chip provided in this application can, for example, detect a failure due to a short circuit, ensuring the normal operation or prompt maintenance of the chip and external equipment, and at the same time ensuring the safe operation of the chip. The detection unit guides the voltage to the ground terminal to ensure that possible short-circuit locations are not burned out by high voltage.

[0056] In some embodiments, external devices are configured to report errors based on abnormally low voltage signals from conductive terminals. Such error reporting functions are configured to address situations such as insufficient installation, but the chip 100 provided in this application is configured to trigger error reporting when a conductive terminal is short-circuited by providing a detection unit 6, thus simplifying the fault recognition system and improving fault detection efficiency.

[0057] In some embodiments, the detection unit 6 may include a second detection segment 62. As shown in Figure 1, the second detection segment 62 is located on one side of the first conductive terminal 1 in the X-axis direction, for example, on the right side of the first conductive terminal 1 in the drawing, and the first detection segment 61 is located on one side of the first conductive terminal 1 in the Y-axis direction, for example, on the upper side in the drawing. Both the second detection segment 62 and the first detection segment 61 are located on adjacent sides of the first conductive terminal 1, and both surround the first conductive terminal 1 in at least part. The second detection segment 62 may be electrically connected to the ground terminal 5 by a ground segment 60.

[0058] In some embodiments, the second detection segment 62 may be electrically connected to the ground segment 60 by the fifth detection segment 65. As shown in Figures 4 and 5, in some other embodiments, the detection unit 6 may include a third detection segment 63, the third detection segment 63 may be electrically connected to the ground terminal 5 by the ground segment 60. The second detection segment 62 may be electrically connected to the ground segment 60 by the third detection segment 63.

[0059] The third detection segment 63 may be located on one side of the third conductive terminal 3 that is away from the second conductive terminal 2. The third detection segment 63 may work in cooperation with the second detection segment 62 to surround the third conductive terminal 3, and the third detection segment 63 may be provided at a distance from the third conductive terminal 3. Since the second conductive terminal 2 and the third conductive terminal 3 are separated by the first detection segment 61, the first detection segment 61 may work in cooperation with the second detection segment 62 to surround the third conductive terminal 3.

[0060] In an exemplary embodiment, the distance between the first detection segment 61 and the first conductive terminal 1 is the same as the distance between the first detection segment 61 and the second conductive terminal 2. For illustrative purposes, the distance between the first detection segment 61 and the first conductive terminal 1 is approximately the same as the width of the first detection segment 61. The first detection segment 61 is easy to form, allows for control over the layout of each conductive terminal, and ensures a compact structure.

[0061] As shown in Figure 1, as an example, the distance between the third contact portion 31 of the third conductive terminal 3 and the fourth contact portion 41 of the fourth conductive terminal 4 is smaller than the distance between either of them and the ground wire contact portion 51 of the ground terminal 5. The third conductive terminal 3 and the fourth conductive terminal 4 are spaced apart in the Y-axis direction and can be shifted laterally.

[0062] The third conductive terminal 3 and the ground terminal 5 are arranged in a row in the X-axis direction. For example, the first conductive terminal 1, the third conductive terminal 3, and the ground terminal 5 may be arranged sequentially in the second direction, for example, in a row. The second conductive terminal 2 and the fourth conductive terminal 4 may be arranged sequentially in the second direction, for example, in a row. In the exemplary embodiment, the first contact portion 11 of the first conductive terminal 1 and the ground wire contact portion 51 of the ground terminal 5 are symmetrical with respect to the dividing cross-section that separates the first half A and the second half B.

[0063] In some embodiments, the detection unit 6 further comprises a second detection segment 62 located between the first conductive terminal 1 and the third conductive terminal 3. The second detection segment 62 is spaced apart from the first conductive terminal 1 and spaced apart from the third conductive terminal 3. As shown in Figure 1, the second detection segment 62 may be indirectly electrically connected to the ground terminal 5 by a ground segment 60. If the first conductive terminal 1 and the third conductive terminal 3 are short-circuited by ink, the detection unit 6 may electrically connect the first conductive terminal 1 and the third conductive terminal 3 to the ground terminal 5. The cooperation of the first detection segment 61 and the second detection segment 62 contributes to the rapid and effective recognition of possible short-circuit problems between the first conductive terminal 1 and the fourth conductive terminal 4.

[0064] As an example, the projection of the second detection segment 62 in the X-axis direction covers the first conductive terminal 1, in other words, the length of the second detection segment 62 in the Y-axis direction is greater than the length of the first conductive terminal 1, and the second detection segment 62 completely separates the first conductive terminal 1 and the third conductive terminal 3. The mounting direction of the chip 100 may also be along the Y-axis direction, and the chip 100 contributes to achieving full detection of the first conductive terminal 1 and avoiding the risk of short circuits between the first conductive terminal 1 and the third conductive terminal 3.

[0065] In some embodiments, the detection unit 6 may include a fifth detection segment 65 located between the third conductive terminal 3 and the fourth conductive terminal 4. The fifth detection segment 65 is spaced apart from the third conductive terminal 3 and spaced apart from the fourth conductive terminal 4. As shown in Figure 1, the fifth detection segment 65 may be electrically connected to the ground terminal 5 by a ground segment 60. If the third conductive terminal 3 and the fourth conductive terminal 4 are short-circuited by ink, the detection unit 6 may electrically connect the third conductive terminal 3 and the fourth conductive terminal 4 to the ground terminal 5. The cooperation of the first detection segment 61 and the fifth detection segment 65 contributes to the rapid and effective recognition of possible short-circuit problems between the second conductive terminal 2 and the third conductive terminal 3.

[0066] In some embodiments, the detection unit 6 may include a fourth detection segment 64 located between the second conductive terminal 2 and the fourth conductive terminal 4. The fourth detection segment 64 may be spaced apart from the second conductive terminal 2 and the fourth conductive terminal 4, respectively. The fourth detection segment 64 may be electrically connected to the ground terminal 5 by a ground segment 60. If the second conductive terminal 2 and the fourth conductive terminal 4 are short-circuited by ink, the detection unit 6 may electrically connect the second conductive terminal 2 and the fourth conductive terminal 4 to the ground terminal 5. For example, the projection of the fourth detection segment 64 in the X-axis direction covers the second conductive terminal 2, in other words, the length of the fourth detection segment 64 in the Y-axis direction is greater than the length of the second conductive terminal 2, and the fourth detection segment 64 completely separates the second conductive terminal 2 and the fourth conductive terminal 4.

[0067] For example, the first conductive terminal 1 may be a clock terminal, the second conductive terminal 2 may be a data terminal, the third conductive terminal 3 may be a power terminal, and the fourth conductive terminal 4 may be a reset terminal. In some embodiments, the detection unit 6 consists of a ground segment 60, a first detection segment 61, a second detection segment 62, a fourth detection segment 64, and a fifth detection segment 65. The circuit layout of the chip 100 is highly reliable, and the power terminal and data terminal are fully detected.

[0068] As an example, chip 100 further includes a test terminal (not shown). With chip 100 mounted on printer 200, the test terminal and the printer 200's stylus are electrically isolated. Chip 100 can be tested either before shipment or after use, and test equipment can be electrically connected to the test terminal to obtain further information or feedback from chip 100.

[0069] As shown in Figure 2, Figure 2 shows the terminal layout of the chip provided in this application. The chip 100 may comprise a substrate 10, a ground terminal 5, a detection unit 6, and at least two conductive terminals. The detection unit 6 comprises a ground segment 60, a first detection segment 61, and may further comprise a fifth detection segment 65 located between a third conductive terminal 3 and a fourth conductive terminal 4. In some other embodiments, the fifth detection segment 65 can be considered as part of the first detection segment 61, and further in these embodiments, the second conductive terminal 2 and the fourth conductive terminal 4 are both located on one side of the first detection segment 61, and the first conductive terminal 1 and the third conductive terminal 3 are both located on the other side of the first detection segment 61. The circuit structure of the chip 100 is simple and can effectively detect short-circuit conditions in the Y-axis direction.

[0070] As shown in Figure 3, Figure 3 shows the terminal layout of the chip provided in this application. The chip 100 may comprise a substrate 10, a ground terminal 5, a detection unit 6, and at least two conductive terminals. The detection unit 6 comprises a ground segment 60, a fifth detection segment 65, and may further comprise a second detection segment 62 located between the first conductive terminal 1 and the third conductive terminal 3. In some embodiments, the detection unit 6 consists of the ground segment 60, the fifth detection segment 65, and the second detection segment 62. The chip 100 has a simple circuit structure and can effectively detect the third conductive terminal 3, for example, a power terminal.

[0071] As shown in Figure 4, Figure 4 shows the terminal layout of the chip provided in this application. The chip 100 may comprise a substrate 10, an earth terminal 5, a detection unit 6, and at least two conductive terminals. The detection unit 6 may comprise a ground segment 60, a first detection segment 61, a second detection segment 62, a third detection segment 63, and a fifth detection segment 65. The second detection segment 62 may be electrically connected to the earth terminal 5 by the third detection segment 63 and the ground segment 60.

[0072] Referring to Figures 1, 3, 4, and 5, in an exemplary embodiment, the detection unit 6 surrounds the third conductive terminal 3 with a gap, and the chip 100 can operate stably. The second detection segment 62 is provided spaced apart from the first detection segment 61 in the Y-axis direction. In some other embodiments, the detection unit can continuously surround the third conductive terminal 3, and the third conductive terminal 3 can be detected comprehensively.

[0073] In some embodiments, the detection unit 6 consists of a ground segment 60, a first detection segment 61, a second detection segment 62, a third detection segment 63, and a fifth detection segment 65. For example, the connection point between the third detection segment 63 and the fifth detection segment 65 is close to the third conductive terminal 3 and away from the ground terminal 5. The third detection segment 63 can effectively detect potential short-circuit problems on one side of the third conductive terminal 3 away from the fourth conductive terminal 4, and potential short-circuit problems on the other side away from the first conductive terminal 1.

[0074] For example, the chip 100 shown in Figure 4 is used and connected to a printer in the illustrated orientation, with the third conductive terminal 3 located below the fourth conductive terminal 4, and the third detection segment 63 including a portion located below the third conductive terminal 3 and a portion located to the right of the third conductive terminal 3 as shown. After oil ink drips below or to the right of the third conductive terminal 3, the detection unit 6 can short-circuit the third conductive terminal 3 to the ground terminal 5. In this case, the printer reports an error. In this way, the presence of abnormal ink dripping above the first conductive terminal 1 can be detected as quickly and accurately as possible, preventing situations such as ink dripping onto other conductive terminals or the printer's stylus, and further preventing situations such as the presence of the printer.

[0075] As shown in Figure 5, Figure 5 shows the terminal layout of the chip provided in this application. The chip 100 may comprise a substrate 10, an earth terminal 5, a detection unit 6, and at least two conductive terminals. The detection unit 6 comprises a ground segment 60, a first detection segment 61, a second detection segment 62, a third detection segment 63, and a fifth detection segment 65. The second detection segment 62 may be electrically connected to the earth terminal 5 by the third detection segment 63 and the ground segment 60. The connection point between the third detection segment 63 and the fifth detection segment 65 is close to the earth terminal 5 and away from the third conductive terminal 3. The third conductive terminal 3 can provide a stable and reliable electrical connection.

[0076] Referring to Figure 6, which is a block diagram of a printing system provided in this application, the printing system comprises a detachably connected printer 200 and a consumables box, the consumables box may include the aforementioned chip 100. The chip 100 is electrically connected to the printer 200, and each conductive terminal may, for example, be electrically connected to a stylus of the printer 200.

[0077] As an example, the chip 100 further comprises a memory 30 and a processor, the processor of which may be a first processor 20. The memory 30 is electrically connected to the first processor 20. Both the memory 30 and the first processor 20 may be electrically connected to a third conductive terminal 3, and both may be electrically connected to a conductive terminal, for example, a fourth conductive terminal 4.

[0078] The memory 30 can store information about the consumable box, such as ink capacity, ink type, and consumable box type. The memory 30 may be electrically connected to the second processor 201 of the printer 200 by conductive terminals, such as the second conductive terminal 2. The second processor 201 is communicatively connected to the memory 30 and can recognize the information stored in the memory 30.

[0079] The first processor 20 may be used to process the signal from the fourth conductive terminal 4, or it may be used to process the signal from the third conductive terminal 3. For example, during the detection period, if the first processor 20 responds that the signal from the fourth conductive terminal 4 is low voltage due to an error, it will emit an error reporting signal, and during the detection period, if the signal from the third conductive terminal 3 is low voltage due to an error, it will emit an error reporting signal. The printer 200 can report an error by transmitting an error reporting signal.

[0080] Referring to Figure 6, the present application provides a consumable box comprising an ink-containing box and the aforementioned chip. The chip substrate is connected to the box.

[0081] Referring to Figure 7, the chip 100 provided in this application may, when operating normally, have normal waveforms for the signals output from each conductive terminal. For example, the chip 100 includes a power terminal, a reset terminal, a data terminal, a clock terminal, and a ground terminal. The power terminal, reset terminal, data terminal, clock terminal, and ground terminal are all electrically connected to the memory 30 of the chip 100 and are also referred to as memory terminals, and are electrically connected to the printer 200. The printer 200 can recognize whether the signals output from each memory terminal are normal or not, and can operate normally based on normal waveforms. As shown in Figure 7, the chip 100 can be initialized after the voltage of the power signal VDD is raised, and when initialization is complete, the voltage of the reset signal RST is raised.

[0082] The values ​​shown in bytes 1 through 18 may be the voltage waveform of the short-circuit verification signal. The clock signal SCK may have a regular waveform, and the first data signal SDA1, the second data signal SDA2, the third data signal SDA3, and the fourth data signal SDA4 are black ( B It can correspond to the signals of the consumable boxes in the following colors: K), blue (C), magenta (M), and yellow (Y). The ground wire signal GND is continuously low voltage.

[0083] As an example, byte 19 represents the waveform during the standby period. A first processor 20 or a second processor 201 may be placed, and bytes 33 to 36 may be limited to short-circuit detection bytes. As an example, bytes 20 to 39 may be placed as the verification response period. The reset signal RST may be reduced to a low voltage in byte 39.

[0084] As shown in Figure 7, from byte 33 to byte 36, the power signal VDD remains at a high level throughout the process, the reset signal RST remains at a high level, the clock signal SCK is in a repeating low-high voltage cycle, the first data signal SDA1 is at a high level in the first half of byte 36 and at a low level for the remainder, in which case no short circuit is observed in chip 100, the second data signal SDA2 is at a high level in the first half of byte 35 and at a low level for the remainder, in which case no short circuit is observed in chip 100, the third data signal SDA3 is at a high level in the first half of byte 34 and at a low level for the remainder, in which case no short circuit is observed in chip 100, and the fourth data signal SDA4 is at a high level in the first half of byte 33 and at a low level for the remainder, in which case no short circuit is observed in chip 100.

[0085] In some other embodiments, the first half of byte 29 is set to the first time t1, the first half of byte 36 to the second time t2, and the latter half of byte 36 to the third time t3. By obtaining voltage data from each conductive terminal from these three time points, it is possible to determine which conductive terminals have a short circuit. Using the normal waveform in Figure 7 as an example, at time t1, the power supply signal VDD and reset signal RST can be obtained as high voltages, and the clock signal SCK and data signal as low voltages. At time t2, the power supply signal VDD and reset signal RST can be obtained as high voltages, the clock signal SCK as a low voltage, and the first data signal SDA1 as a high voltage. At time t3, the power supply signal VDD and reset signal RST can be obtained as high voltages, the clock signal SCK as a high voltage, and the data signal as a low voltage. In this case, it is determined that no short circuit has occurred between any of the memory terminals. The second time t2 and third time t3 are not the same for consumable boxes of different colors. Specifically, in the case of SDA1, the first half of byte 36 is the second time t2 and the second half of byte 36 is the third time t3; in the case of SDA2, the first half of byte 35 is the second time t2 and the second half of byte 35 is the third time t3; in the case of SDA3, the first half of byte 34 is the second time t2 and the second half of byte 34 is the third time t3; and in the case of SDA4, the first half of byte 33 is the second time t2 and the second half of byte 33 is the third time t3.

[0086] The chip 100 provided in this application can differentiate the occurrence of short circuits at different conductive terminals during use over other specific periods, and is not limited to the few segments provided herein.

[0087] In some other embodiments, if the voltage of all data terminals is low in the section from byte 33 to byte 36, the chip 100 is deemed to have generated an error, and for example, the printer 200 can report the error and determine which conductive terminal is short-circuited by analyzing the voltage status of each contact pin.

[0088] Referring to Figure 8, Figure 8 shows the waveform that chip 100 can output when the reset terminal and clock terminal are short-circuited before chip 100 is mounted on printer 200. Since the reset terminal and clock terminal can be electrically connected to the ground terminal 5 by the detection unit 6, the voltages of the reset terminal and clock terminal are continuously low from byte 33 to byte 36, and therefore the printer 200 reports an error, and the waveform indicates that there is a short circuit between the reset terminal and the clock terminal. On the other hand, since chip 100 cannot operate normally, the signal from the data terminal is continuously low from byte 20 to byte 36, meaning that the data terminal is not outputting a signal in this case.

[0089] In other cases, for example, if the reset terminal and the clock terminal are short-circuited at byte 31 due to ink dripping, the waveform from byte 20 to byte 30 will not be pulled down in the same way as the original waveform, but will be pulled down when it reaches byte 31.

[0090] In some embodiments, the first half of the 29th byte corresponds to the first time t1, the first half of the 36th byte corresponds to the second time t2, and the latter half of the 36th byte corresponds to the third time t3. At time t1, the power supply signal VDD can be acquired as a high voltage, the reset signal RST and clock signal SCK as low voltages, and the data signal as a low voltage. At time t2, the power supply signal VDD can be acquired as a high voltage, the reset signal RST and clock signal SCK as low voltages, and the data signal as a low voltage. At time t3, the power supply signal VDD can be acquired as a high voltage, the reset signal RST and clock signal SCK as low voltages, and the data signal as a low voltage. In this case, it is considered that the reset terminal and the clock terminal are short-circuited.

[0091] As an example, before the chip 100 is mounted on the printer 200, that is, when the reset terminal and the clock terminal are short-circuited, the chip 100 can output the waveform shown in Figure 9. The reset signal RST from the reset terminal and the data signal SDA from the data terminal are both continuously low, and the printer 200 reports an error and, based on the waveform, detects a short circuit between the reset terminal and the data terminal. The waveform shown in Figure 9 is realized by electrically connecting both the reset terminal and the data terminal to the ground terminal 5 by the detection unit 6.

[0092] Referring to Figure 10, after the reset terminal and the power terminal are short-circuited, both can be electrically connected to the ground terminal 5 by the detection unit 6. The power signal VDD and the reset signal RST may be continuously low voltage at the start. The clock signal SCK can output a normal waveform. Because the chip 100 is not functioning properly, the signals at the data terminals are continuously low voltage from byte 20 to byte 36. The printer 200 reports that the reset signal RST and the power signal VDD are continuously low voltage from byte 33 to byte 36, and can determine the specific short-circuit location based on the waveform.

[0093] Referring to Figure 11, after the clock terminal and the power terminal are short-circuited, both can be electrically connected to the ground terminal 5 by the detection unit 6. The power signal VDD and the clock signal SCK may remain at a low voltage at the start. The reset signal RST can be raised when initialization is complete. Because the chip 100 is not functioning properly, the signals at the data terminals remain at a low voltage from byte 20 to byte 36. The reset signal RST can be reduced to a low voltage at byte 39. The printer 200 reports that the clock signal SCK and the power signal VDD remain at a low voltage from byte 33 to byte 36, and can determine the specific short-circuit location based on the waveform.

[0094] Referring to Figure 12, after the clock terminal and data terminal are short-circuited, they can be electrically connected to the ground terminal 5 by the detection unit 6. After the voltage of the power signal VDD is raised, the chip 100 can be initialized, and when initialization is complete, the voltage of the reset signal RST is raised. The clock signal SCK and data signal SDA may remain at low voltages. The printer 200 reports that the clock signal SCK and data signal SDA are continuously at low voltages from byte 33 to byte 36, and can determine the specific short-circuit location based on the waveform. The reset signal RST may be reduced to a low voltage in byte 39.

[0095] Referring to Figure 13, after the power terminal and data terminal are short-circuited, they can be electrically connected to the ground terminal 5 by the detection unit 6. The reset signal RST can be raised when initialization is complete, and the clock signal SCK may have a normal waveform. The power signal VDD and data signal SDA may remain at low voltage. The printer 200 reports that the power signal VDD and data signal SDA are continuously at low voltage in bytes 33 to 36, and can determine the specific short-circuit location based on the waveform. The reset signal RST can be reduced to a low voltage in byte 39.

[0096] To make it clear, the chip, consumable box, and printed system provided in this application achieve fault detection for different conductive terminals through the shape design of the detection unit.

[0097] In another modified embodiment, the first processor 20 of the chip 100 detects the voltage of the memory terminal at the corresponding time, and in response to the detection of an error voltage, sends a short-circuit signal / error signal etc. to the printer 200, causing the printer 200 to stop operating.

[0098] Referring to Figure 14, the present application provides a consumable box 300 which may comprise a box 310 and a tip 100. The box 310 has a bottom wall 301 and side walls, the side walls comprising a first side wall 302. The tip 100 may be attached to the first side wall 302.

[0099] The consumable box 300 may be used, for example, to be mounted on a printer 200. In actual use, the Y-axis direction may be approximately vertical. The bottom wall 301 may face downward, the first side wall 302 can engage with the printer 200, and the tip 100 can be electrically connected to the printer 200. Exemplarily, the consumable box 300 includes an ink outlet 303, which may be located on the bottom wall 301. Each side wall can be bent relative to the bottom wall 301, for example, perpendicular to each other. The tip 100 may also be located on the bottom wall 301, with different mounting positions depending on the consumable box.

[0100] During the printing process, problems such as ink leaks or drips of user sweat may occur. For example, if oil ink drips onto chip 100, it could cause a short circuit and further damage chip 100 or the printer 200. The consumable box 300 provided in this application can detect short-circuit problems and ensure the normal operation and service life of the printing system.

[0101] Referring to Figure 15, the dividing cross section of the chip 100, which separates the first half from the second half, is perpendicular to the bottom wall 301. The ground terminal 5 may be located in the first half, and the first detection segment 61 may extend horizontally, for example in the X-axis direction, and the first conductive terminal 1 and the second conductive terminal 2 are separated by the first detection segment 61 so that they are located on the upper and lower sides. For example, ink, after contaminating the first conductive terminal 1, slides downward due to gravity and connects to the second conductive terminal 2. The chip 100 provided in this application, by having the detection unit 6 positioned, can quickly reduce error high voltage to low voltage, which helps to avoid short-circuit failures and burnouts that can occur in the chip 100 and printer 200 due to short circuits.

[0102] As an example, the ground terminal 5 and the second conductive terminal 2 are provided opposite each other and separated by the first detection segment 61. The ground terminal 5 is located on one side of the first detection segment 61 that is close to the bottom wall 301, and the second conductive terminal 2 is located on the one side of the first detection segment 61 that is away from the bottom wall 301. The extension direction of the first detection segment 61 is parallel to the bottom wall 301. The consumable box 300 can be detachably attached to the printer 200 in the Y-axis direction, which helps to avoid the ground terminal 5 coming into contact with ink droplets prematurely. The detection unit 6 can divide the conductive terminals into two rows, upper and lower, and at the same time avoid the printer 200's stylus.

[0103] Referring to Figure 16, the first side wall 302 may include a portion that slopes relative to the bottom wall 301, and the chip 100 can be mounted on the sloped portion. For example, in the chip 100, the cross-section dividing the first half and the second half may be parallel to the YZ plane, and the first detection segment 61 of the detection unit 6 is roughly perpendicular to the YZ plane and can still partition the first conductive terminal 1 and the second conductive terminal 2 on both the upper and lower sides. For example, the ground terminal 5 is located below the first detection segment 61. The consumable box 300 as a whole may be detachably mounted to the printer 200 in the Y-axis direction, and the mounting process may include, for example, a rotational movement.

[0104] Referring to Figure 17, other shapes may be used for the terminals of the chip 100. For example, the area of ​​the ground terminal 5 may be large, and the position of the ground wire contact portion 51 may not need to be changed. For example, the ground wire contact portion 51 and the first contact portion 11 may be provided symmetrically with respect to the central axis of the chip 100, and the ground wire contact portion 51 and the first contact portion 11 provided in this manner may be at the same height in the Y-axis direction.

[0105] Referring to Figure 18, in some other embodiments, the position of the ground wire contact portion 51 is moved correspondingly down or up by means of adding positioning holes, limiting walls, etc. to the tip 100. The ground wire contact portion 51 and the first contact portion 11 thus provided are at different heights in the Y-axis direction, that is, the ground wire contact portion 51 and the first contact portion 11 are provided asymmetrically with respect to the central axis of the tip 100. The actual alignment direction of both the ground wire contact portion 51 and the first contact portion 11, or the direction of connection between them, intersects the X-axis, in other words, the connection line between the ground wire contact portion 51 and the first contact portion 11, and the connection line between the second contact portion 21 and the fourth contact portion 41 intersect and are not parallel. As shown in Figure 18, the connection line between the third contact portion 31 and the ground wire contact portion 51, and the connection line between the second contact portion 21 and the fourth contact portion 41, do not necessarily intersect and are not parallel.

[0106] The chip short-circuit verification method provided in the embodiment of this application can be applied to the application scenario shown in Figure 19, which is a schematic diagram of the application scenario of the chip short-circuit verification method provided in the embodiment of this application. Here, terminal 102 communicates with server 104 via a network. A data storage system can store data that server 104 should process. The data storage system may be integrated into server 104 or located in the cloud or other network servers. Here, terminal 102 may be various fax machines, printers, etc., but is not limited to these. Server 104 may be implemented as an independent server or as a server cluster consisting of multiple servers.

[0107] This embodiment provides a chip short-circuit verification method that includes the following steps.

[0108] Step 1: Obtain the short-circuit verification signal.

[0109] For example, the short-circuit verification signal may be transmitted by the printing device and is used by the consumable box chip to perform short-circuit detection in cooperation with the printer before communication between the printing device and the consumable box chip. Unless otherwise specified, the terms "printing device" and "printer" are used interchangeably.

[0110] Step 2: Based on the short-circuit verification signal, set the desired level signal for the first terminal of the chip under test at a specified time during the verification response period.

[0111] The chip under test may have multiple terminals, such as a data terminal, power terminal, clock terminal, reset terminal, and ground terminal, and optionally, the first terminal is a data terminal.

[0112] Step 3: After the desired level signal is set, acquire the actual output level signal of the first terminal.

[0113] Step 4: Based on the actual output level signal, identify the short-circuit verification result of the chip under test. The short-circuit verification result indicates that the chip under test functions normally, but there is a short circuit between the second terminal and at least one other terminal on the chip under test; the chip under test functions normally and is not short-circuited; or the function of the chip under test is impaired.

[0114] In the above implementation process, it is possible to effectively determine whether the functionality of the chip under test is impaired based on whether the actual output level signal of the first terminal matches the desired level signal, thereby avoiding errors in certifying the short-circuit verification results during the short-circuit verification process for the chip under test.

[0115] If the actual output level signal and the desired level signal do not match, the short-circuit verification result indicates that the functionality of the chip under test is impaired.

[0116] The method for determining that the chip under test is functioning correctly when the actual output level signal matches the desired level signal further includes the following steps.

[0117] Step 1: Determine whether the voltage of the second terminal of the chip under test remains within a predetermined voltage range during the verification response period.

[0118] Step 2: If the voltage at the second terminal of the chip under test remains within the predetermined voltage range during the verification response period, the chip under test is not short-circuited.

[0119] Step 3: If the voltage of the second terminal of the chip under test does not remain within the predetermined voltage range during the verification response period, a short circuit occurs between the second terminal and at least one other terminal on the chip under test.

[0120] Specifically, after determining that the function of the chip under test is normal, the system further determines whether the voltage of the second terminal of the chip under test remains within a predetermined voltage range during the verification response period. If the voltage of the second terminal of the chip under test remains within the predetermined voltage range during the verification response period, the system determines that the function of the chip under test is normal and there is no short circuit. If the voltage of the second terminal of the chip under test does not remain within the predetermined voltage range during the verification response period, the system determines that the function of the chip under test is normal, but there is a short circuit between the second terminal and at least one other terminal.

[0121] Here, the second terminal is any terminal other than the first terminal on the chip under test, and by selection, the second terminal is the reset terminal.

[0122] In the implementation process described above, after confirming that the function of the chip under test is normal, it is possible to accurately determine whether or not the reset terminal and the remaining terminals are short-circuited in the chip under test based on the voltage state of the second terminal, thereby improving the accuracy of the short-circuit verification results of the chip under test.

[0123] In this embodiment, a chip short-circuit verification method is provided, and Figure 20 is a flowchart of the chip short-circuit verification method provided in the embodiment of this application. The implementing body of the method may be an electronic device, which may optionally be a server, a terminal device, or a consumable box chip. In this application, the implementing body is an example of a consumable box chip, but this application is not limited thereto. Specifically, as shown in Figure 20, the process includes the following steps.

[0124] Step S210 is performed, and a short-circuit verification signal is obtained.

[0125] For example, the short-circuit verification signal may be transmitted by the printing device and is used by the consumable box chip to perform short-circuit detection in cooperation with the printer before communication between the printing device and the consumable box chip.

[0126] Step S220 is performed, and based on the short-circuit verification signal, a desired level signal is set for the data terminal of the chip under test at a specified time during the verification response period.

[0127] Furthermore, the consumable box chip performs a short-circuit verification of the chip after receiving a short-circuit verification signal. Additionally, at a specified time within the response period of the chip short-circuit verification, a desired level signal is set for the data terminals of the chip under test.

[0128] Specifically, the test chip is a consumable box chip to be verified, and Figure 21 is a schematic diagram of the configuration of the test chip provided in the embodiment of this application. As shown in Figure 21, the test chip may be equipped with multiple terminals such as a data terminal 401, a power terminal 404, a clock terminal 403, a reset terminal 402, and a ground terminal 5, as well as memory (not shown). The data terminal 401, power terminal 404, clock terminal 403, reset terminal 402, and ground terminal 5 are all electrically connected to the memory. The memory is for storing relevant data required for the operation of the consumable box chip. After the consumable box chip receives a short-circuit verification signal, a desired level signal is set to the data terminal of the test chip at a specified time during the verification response period. Here, for the desired level signal, a "low-high-low" level signal may be set at three different specified times.

[0129] Step S230 is performed to obtain the actual output level signal of the data terminal to which the desired level signal has been set.

[0130] Step S240 identifies the short-circuit verification result of the chip under test based on the actual output level signal.

[0131] Here, the short-circuit verification result includes the following: the function of the chip under test is normal, but the reset terminal and at least one terminal other than the reset terminal are short-circuited on the chip under test; the function of the chip under test is normal and there is no short circuit; or the function of the chip under test is damaged.

[0132] Furthermore, after setting a desired level signal for the data terminal, the system acquires the level signal actually output by the data terminal, and then identifies the short-circuit verification result of the chip under test based on the actually output level signal.

[0133] Specifically, after setting a desired level signal for the data terminal, if the function of the chip under test is normal, even if the reset terminal and any other terminal on the chip under test are short-circuited, it does not affect the actual output of the data terminal; that is, the actual output level signal of the data terminal matches the desired level signal. If the function of the chip under test is impaired, an error will occur in the actual output of the data terminal, or the data terminal will be unable to output a level signal. In this case, the actual output level signal of the data terminal will not match the desired level signal, and therefore, the short-circuit verification result of whether or not the function of the chip under test is impaired can be determined based on the actual output level signal of the data terminal.

[0134] In the above implementation process, after the chip receives a short-circuit verification signal, the chip moves to the short-circuit verification phase. At a specified time during the verification response period of the short-circuit verification phase, the chip sets a desired level signal to the data terminal of the chip under test. Thus, based on the actual output level signal of the data terminal, the short-circuit verification result—whether or not the functionality of the chip under test is damaged—can be determined. This avoids errors in determining the short-circuit verification result due to the chip being unable to determine whether or not its functionality is damaged during the short-circuit verification process.

[0135] In some of these embodiments, the step of determining the short-circuit verification result of the chip under test based on the actual output level signal includes, if the actual output level signal and the desired level signal do not match, the short-circuit verification result indicates that the functionality of the chip under test is impaired.

[0136] For example, after setting a desired level signal for a data terminal, if the actual output level signal of the data terminal does not match the desired level signal, it is identified that the functionality of the chip under test is impaired.

[0137] In the above implementation process, it is possible to effectively determine whether the functionality of the chip under test is impaired based on whether the actual output level signal of the data terminal matches the desired level signal, thereby avoiding errors in certifying the short-circuit verification results during the short-circuit verification process for the chip under test.

[0138] In some of these embodiments, the method for determining that the chip under test is functioning correctly when the actual output level signal matches the desired level signal further includes the following steps.

[0139] Step 1: Determine whether the voltage at the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period.

[0140] Step 2: If the voltage at the reset terminal of the chip under test remains within the specified voltage range during the verification response period, the chip under test is not short-circuited.

[0141] Step 3: If the voltage at the reset terminal of the chip under test does not remain within a predetermined voltage range during the verification response period, the reset terminal and at least one other terminal on the chip under test will be short-circuited.

[0142] For example, if the actual output level signal matches the desired level signal, it can be determined that the chip under test is functioning normally. Furthermore, the voltage state of the reset terminal can be used to determine whether or not the chip under test is short-circuiting while functioning normally.

[0143] Specifically, after determining that the function of the chip under test is normal, the test further determines whether the voltage of the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period. If the voltage of the reset terminal of the chip under test remains within the predetermined voltage range during the verification response period, the test is determined to be functioning normally and not short-circuited. If the voltage of the reset terminal of the chip under test does not remain within the predetermined voltage range during the verification response period, the test is determined to be functioning normally, but at least one terminal other than the reset terminal is short-circuited. Here, the predetermined voltage range may be 1.78V to 3.3V, 1.65V to 4V, or any other voltage range, and is not limited thereto.

[0144] In one embodiment, the predetermined voltage range is such that the voltage at the reset terminal is low 15us before the waveform generation at the clock terminal, the voltage at the reset terminal remains at a high level throughout the entire communication period, and the voltage at the reset terminal is lower than 3.3V.

[0145] Normally, a data terminal is indicated as being raised or lowered when the voltage at the corresponding specified time is raised to 3.3V or lowered to 0V. If the function of the chip under test is normal, and the voltage of the reset terminal remains high and within the specified voltage range during the verification response period, it is indicated that the function of the chip under test is normal and there is no short circuit. Otherwise, it is recognized that the function of the chip under test is normal, but the reset terminal and at least one other terminal are short-circuited.

[0146] In the implementation process described above, after confirming that the function of the chip under test is normal, it is possible to accurately determine whether or not a short circuit occurs between the reset terminal and the remaining terminals in the chip under test, based on the voltage state of the reset terminal, thereby improving the accuracy of the short-circuit verification results for the chip under test.

[0147] In some of these embodiments, a method for determining that the function of the chip under test is normal when the actual output level signal matches the desired level signal includes the following steps:

[0148] Step 1: Determine whether the chip under test responds to communication commands during the preset communication period.

[0149] Here, the communication command is the communication command sent by the printing device communicating with the chip under test, and the preset communication period is after the verification response period.

[0150] Step 2: If the test chip does not respond to the communication command during the preset communication period, the short-circuit verification result will indicate that the test chip is functioning normally, but the reset terminal and at least one other terminal are short-circuited.

[0151] Step 3: If the test chip responds to a communication command within the preset communication period, the short-circuit verification result indicates that the test chip is functioning normally and is not short-circuited.

[0152] For example, after determining that the function of the chip under test is normal, it is possible to determine whether or not a short circuit occurs in the chip under test based on whether or not the chip under test responds to communication commands within a preset communication period.

[0153] Typically, when a printer and a consumable box chip communicate, the printer generally sends a short-circuit verification signal to the consumable box chip. Upon receiving the short-circuit verification signal, the consumable box chip moves to the short-circuit verification phase. During the verification response period in the short-circuit verification phase, the consumable box chip feeds back short-circuit verification data to verify whether the printer short-circuits. Only if the consumable box chip passes the short-circuit verification does the printer and the consumable box chip move to the communication phase. This communication phase may be a predetermined communication period; that is, the preset communication period is after the verification response period. During the preset communication period, the printer sends a communication command to the chip under test.

[0154] In this embodiment, since the actual output level signal of the chip under test matches the desired level signal, the chip under test is indicated to have passed the short-circuit verification during the short-circuit verification stage. However, in the actual process, the reset terminal may still short-circuit with at least one other terminal. Therefore, after the printing device transmits a communication command, it is possible to determine whether or not the chip under test is short-circuited based on whether or not the chip under test responds to the communication command.

[0155] During the preset communication period, if the test chip does not respond to the communication command, it is indicated that the test chip is faulty. However, if the test chip's function is determined to be normal during the short-circuit verification stage, then it is determined that the reset terminal and at least one other terminal on the test chip are short-circuited. Conversely, if the test chip responds to the communication command within the preset communication period, it is indicated that the test chip's function is normal and there is no short circuit.

[0156] In the above implementation process, after confirming that the function of the chip under test is normal, it is determined whether or not the chip under test is short-circuited based on whether or not it responds to communication commands at a predetermined communication stage. Thus, the short-circuit verification result of the chip under test is determined, and the accuracy of the short-circuit verification result is improved.

[0157] In some of these embodiments, the step of setting a desired level signal to the data terminals of the chip under test at a specified time in the verification response period based on a short-circuit verification signal includes the following steps:

[0158] Step 1: Based on the short-circuit verification signal, identify multiple clock times for the clock terminal on the chip under test.

[0159] Step 2: Identify the validation response period based on multiple clock times.

[0160] Step 3: Identify the corresponding specified time for the data terminal on the chip under test during the verification response period.

[0161] Step 4: Set the desired level signal at the corresponding specified time on the data terminal.

[0162] As an example, the printing device transmits a short-circuit verification command, and the signal waveform is shown in Figure 22, which is the complete short-circuit verification waveform of the chip when the chip function provided in the embodiment of this application is normal and there is no short circuit, where bytes 1 to 18 are the voltage waveform of the short-circuit verification signal, byte 19 is the waveform during the waiting period, and bytes 20 to 38 are the verification response period, and the corresponding voltage waveform during this period is the response voltage waveform that can be obtained by the printing device stylus. A voltage waveform, i.e., a terminal signal waveform, means a waveform exhibited by the terminal voltage at a high level or low level, or by a change between high and low levels, within a certain period of time. The process of receiving a short-circuit verification signal and providing feedback in response to the voltage waveform is called short-circuit communication verification. In one specific embodiment, the total time for short-circuit verification is approximately 4.4 ms. The short-circuit verification time is the sum of the time it takes to raise and lower the power supply signal. Here, the time for chip initialization is 4.1785 ms, which is the time from when the voltage at the power supply terminal is raised to when the voltage at the reset terminal is raised. In Figure 22, the signals from top to bottom are, in order, VDD is the power supply terminal signal, RST is the reset terminal signal, SCK is the clock terminal signal, and SDA1, SDA2, SDA3, and SDA4 are all data terminal signals. Here, the SDA1, SDA2, SDA3, and SDA4 signals correspond to the signals of the K, C, M, and Y colored consumable boxes, respectively.

[0163] Therefore, based on the received short-circuit verification signal, it can be determined that the chip under test has entered the short-circuit verification phase. After entering the short-circuit verification phase, the corresponding multiple clock times from byte 1 to byte 38 at the clock terminal are identified as the multiple clock times of the clock terminal. Then, of the multiple clock times, the corresponding time period from byte 20 to byte 38 is identified as the verification response period. Furthermore, using the K-colored consumable box as an example, the latter half of byte 27 and byte 36 during the verification response period are identified as the corresponding specified time for the data terminal, and the desired level signal is set at the corresponding specified time. Using the C-colored consumable box as an example, the latter half of byte 26 and byte 35 during the verification response period are identified as the corresponding specified time for the data terminal, and the desired level signal is set at the corresponding specified time. Using the M-colored consumable box as an example, the latter half of byte 25 and byte 34 during the verification response period are identified as the corresponding specified time for the data terminal, and the desired level signal is set at the corresponding specified time. Using a consumable box in color Y as an example, the latter half of the 24th byte and the 33rd byte during the verification response period are identified as the corresponding specified time for the data terminal, and the desired level signal is set at the corresponding specified time.

[0164] Specifically, the desired level signal includes both a high-level signal and a low-level signal, with the levels of the ground terminal and power terminal serving as reference quantities for the low-level and high-level signals, i.e., a signal with a voltage of 0V is the low-level signal, and a signal with a voltage of 3.3V is the high-level signal.

[0165] In one embodiment, a 0.8V signal may be recognized as a low-level signal and a 3.2V signal as a high-level signal. In another embodiment, a signal of 1.78V or less may be recognized as a low-level signal and a signal of 1.78V or more may be recognized as a high-level signal.

[0166] Figure 23 is a schematic waveform of the verification response time period provided by the printing device in the related technology. The clock terminal includes a total of nine clock times in two stages, where t1 / 2 / 3 are the corresponding designated times when the printing device detects the data terminal on the consumable box chip during the verification response period. By detecting the high and low levels of the level signals at t1 / 2 / 3, it is determined whether the consumable box chip has passed the short-circuit verification. Specifically, as shown in Figure 23, if the level signals at t1 / 2 / 3 are low-high-low, respectively, it is determined that the consumable box chip is not short-circuited. In this case, the printer does not report an error during the short-circuit verification stage, meaning that the consumable box chip is not short-circuited. However, if the consumable box chip is not short-circuited but its function is damaged, the printing device cannot detect the low-high-low data level signals at t1 / 2 / 3 according to the above judgment principle. Therefore, the printer reports an error during the short-circuit verification stage, making it impossible to accurately determine whether it is a short-circuit error or a chip function damage error.

[0167] To solve the above problem, in some embodiments, the specified time includes a first specified time, a second specified time, and a third specified time, where the first specified time is earlier than the second specified time and the second specified time is earlier than the third specified time, and the step of setting a desired level signal at the corresponding specified time of the data terminal includes the step of setting a low level signal at the corresponding first specified time of the data terminal, the step of setting a high level signal at the corresponding second specified time of the data terminal, and the step of setting a low level signal at the corresponding third specified time of the data terminal.

[0168] Specifically, as shown in Figure 22, the signals SDA1, SDA2, SDA3, and SDA4 at the data terminal correspond to three specified times, with the first specified time t1 and the second... 2These are the specified time t2 and the third specified time t3. Corresponding to the waveform of this embodiment, and referring to Figure 22, from the verification response period, SDA1 identifies the corresponding first specified time t1 as the latter half of byte 27, the corresponding second specified time t2 as the first half of byte 36, and the corresponding third specified time t3 as the latter half of byte 36 at the data terminal; SDA2 identifies the corresponding first specified time t1 as the latter half of byte 26, the corresponding second specified time t2 as the first half of byte 35, and the corresponding third specified time t3 as the latter half of byte 35; SDA3 identifies the corresponding first specified time t1 as the latter half of byte 25, the corresponding second specified time t2 as the first half of byte 34, and the corresponding third specified time t3 as the latter half of byte 34; SDA4 identifies the corresponding first specified time t1 as the latter half of byte 24, the corresponding second specified time t2 as the first half of byte 33, and the corresponding third specified time t3 as the latter half of byte 33.

[0169] Then, for each signal, a low-level signal is output at time t1, a high-level signal at time t2, and a low-level signal at time t3, so that SDA1, SDA2, SDA3, and SDA4 each output a "low-high-low" level signal.

[0170] In the above implementation process, the data terminal outputs a desired level signal at three specified times for each signal, so that it can pass the short-circuit verification of the associated printing device, and the printer will not report an error in the short-circuit verification. However, if the function of the chip under test is damaged, in this case the chip under test will not be able to output a desired level signal, and at this time the printer will report an error in the short-circuit verification, effectively allowing it to determine whether or not the function of the chip under test is damaged.

[0171] In some of these embodiments, the step of acquiring a short-circuit verification signal includes the following steps:

[0172] Step 1: Obtain the original waveform data transmitted by the printing device.

[0173] Step 2: If a short-circuit verification mark exists in the original waveform data, identify the original waveform data as a short-circuit verification signal.

[0174] As an example, Figure 24 shows a schematic diagram of the original waveform of a short-circuit verification signal transmitted by a printing device in the related technology. Communication commands between the printing device and the consumable box chip mainly consist of two types: one is a normal communication command and the other is a short-circuit verification signal. After receiving the original waveform data transmitted by the printing device, the consumable box chip can determine whether the waveform it is currently receiving is a short-circuit verification signal by detecting whether or not a short-circuit verification mark is present in the original waveform data.

[0175] Specifically, if the first two bytes of the original waveform data transmitted by the printing device are not the fixed data transmitted by the printing device during a normal communication command, both are determined to be short-circuit verification signals. If the data signal is detected to be a short-circuit verification signal, the chip under test issues a corresponding command to the printing device in response to the short-circuit verification by sending corresponding data at the corresponding time.

[0176] In the above implementation process, by determining whether or not a short-circuit verification mark exists in the original waveform data, it is possible to identify whether or not the signal currently received by the chip under test is a short-circuit verification signal, and to a certain extent, whether or not the command format transmitted by the printing device satisfies the requirements of the chip response short-circuit verification data is ignored. This speeds up the operating efficiency of consumable chips.

[0177] When using the short-circuit verification method of this application, the original waveforms of each terminal are shown in Figure 25, which is a schematic diagram of the original waveforms of each terminal provided in the embodiment of this application. Here, from byte 20 to byte 38, the reset terminal signal RST is continuously at a high level, the clock signal SCK is in a repeating low-high voltage cycle, the data signal SDA1 is at a high level in the first half of byte 36 and at a low level for the remainder, the data signal SDA2 is at a high level in the first half of byte 35 and at a low level for the remainder, the data signal SDA3 is at a high level in the first half of byte 34 and at a low level for the remainder, and the data signal SDA4 is at a high level in the first half of byte 33 and at a low level for the remainder. In this case, the consumable box chips of colors K, C, M, and Y are not short-circuited and are considered to be functioning normally.

[0178] As one embodiment, when the reset terminal and the clock terminal are short-circuited, Figure 26 shows the waveforms generated at each terminal of the chip under test according to the short-circuit verification method of this application. Figure 26 is a schematic diagram of the waveforms when the reset terminal and the clock terminal are short-circuited as provided in the embodiment of this application. Here, at least from byte 20 to byte 38, the reset terminal signal RST and the clock signal SCK are in a repeating low-high voltage cycle, the data signal SDA1 is at a high level in the first half of byte 36 and at a low level for the remainder, the data signal SDA2 is at a high level in the first half of byte 35 and at a low level for the remainder, the data signal SDA3 is at a high level in the first half of byte 34 and at a low level for the remainder, and the data signal SDA4 is at a high level in the first half of byte 33 and at a low level for the remainder. In this case, because the desired level signal is set for the data terminal of the chip under test at the specified time during the response period of the chip short circuit verification, the data level signal that could not originally be output as low-high-low at t1 / 2 / 3 is changed to a data level signal exhibiting low-high-low as shown in Figure 26. Therefore, the function of the consumable box chip is normal, and in this case, the printer does not report an error during the short circuit verification stage.

[0179] Specifically, when the reset terminal and the clock terminal are short-circuited, the drive capability of the reset terminal is weak, and the reset terminal waveform is affected by the voltage at the clock terminal. Therefore, during the short-circuit period, the reset terminal exhibits the same voltage as the clock terminal.

[0180] As one embodiment, when the reset terminal and the corresponding data terminal of SDA1 are short-circuited, the waveforms output by each terminal of the chip under test according to the short-circuit verification method of this application are shown in Figure 27. Figure 27 is a schematic waveform diagram of the state in which the reset terminal and the corresponding data terminal of SDA1 are short-circuited as provided in the embodiment of this application. From byte 20 to byte 38, the reset terminal and the data terminal are short-circuited, so the reset terminal exhibits a low level state for some bytes. Specifically, the reset terminal signal RST is low level for at least the latter half of byte 36 and the latter half of byte 27, the clock signal SCK is a repeating low-high voltage cycle, and the data signal SDA1 is low level for at least the latter half of byte 36 and the latter half of byte 27, and high level for the first half of byte 36. In this case, because the desired level signal is set for the data terminal of the test chip at the specified time during the response period of the chip short circuit verification, the data level signal that could not originally be output as low-high-low at t1 / 2 / 3 is changed to a data level signal exhibiting low-high-low as shown in Figure 27. Therefore, the function of the consumable box chip is normal, and in this case, the printer does not report an error during the short circuit verification stage.

[0181] As one embodiment, when the reset terminal and the corresponding SDA2 data terminal are short-circuited, Figure 28 shows the waveforms output by each terminal of the chip under test according to the short-circuit verification method of this application. Figure 28 is a schematic waveform diagram of the state in which the reset terminal and the corresponding SDA2 data terminal are short-circuited as provided in the embodiment of this application. Here, since the reset terminal and the data terminal are short-circuited from byte 20 to byte 38, the reset terminal exhibits a low level state for some bytes. Specifically, the reset terminal signal RST is low level for at least the latter half of byte 35 and the latter half of byte 26, the clock signal SCK is a repeating low-high voltage cycle, and the data signal SDA2 is low level for at least the latter half of byte 35 and the latter half of byte 26, and high level for the first half of byte 35. In this case, because the desired level signal is set for the data terminal of the chip under test at the specified time during the response period of the chip short circuit verification, the data level signal that could not originally be output as low-high-low at t1 / 2 / 3 is changed to a data level signal exhibiting low-high-low as shown in Figure 28. Therefore, the function of the consumable box chip is normal, and in this case, the printer does not report an error during the short circuit verification stage.

[0182] As one embodiment, when the reset terminal and the corresponding data terminal of SDA3 are short-circuited, Figure 29 shows the waveforms output by each terminal of the chip under test according to the short-circuit verification method of this application. Figure 29 is a schematic waveform diagram of the state in which the reset terminal and the corresponding data terminal of SDA3 are short-circuited as provided in the embodiment of this application. Here, since the reset terminal and the data terminal are short-circuited from byte 20 to byte 38, the reset terminal exhibits a low-level state for some bytes. Specifically, the reset terminal signal RST is low-level for at least the latter half of byte 34 and the latter half of byte 25, the clock signal SCK is a repeating low-voltage-high-voltage cycle, and the data signal SDA3 is low-level for at least the latter half of byte 34 and the latter half of byte 25, and high-level for the first half of byte 34. In this case, because the desired level signal is set for the data terminal of the chip under test at the specified time during the response period of the chip short circuit verification, the data level signal that could not originally be output as low-high-low at t1 / 2 / 3 is changed to a data level signal exhibiting low-high-low as shown in Figure 29. Therefore, the function of the consumable box chip is normal, and in this case, the printer does not report an error during the short circuit verification stage.

[0183] As one embodiment, when the reset terminal and the corresponding data terminal of SDA4 are short-circuited, Figure 30 shows the waveforms output by each terminal of the chip under test according to the short-circuit verification method of this application. Figure 30 is a schematic waveform diagram of the state in which the reset terminal and the corresponding data terminal of SDA4 are short-circuited as provided in the embodiment of this application. Here, since the reset terminal and the data terminal are short-circuited from byte 20 to byte 38, the reset terminal exhibits a low-level state for some bytes. Specifically, the reset terminal signal RST is low-level for at least the latter half of byte 33 and the latter half of byte 24, the clock signal SCK is a repeating low-voltage-high-voltage cycle, and the data signal SDA4 is low-level for at least the latter half of byte 33 and the latter half of byte 24, and high-level for the first half of byte 33. In this case, because the desired level signal is set for the data terminal of the chip under test at the specified time during the response period of the chip short circuit verification, the data level signal that could not originally be output as low-high-low at t1 / 2 / 3 is changed to a data level signal exhibiting low-high-low as shown in Figure 30. Therefore, the function of the consumable box chip is normal, and in this case, the printer does not report an error during the short circuit verification stage.

[0184] In other words, when the reset terminal is short-circuited with one of the corresponding data terminals SDA1 / 2 / 3 / 4, the desired level signal is set for the data terminal on the test chip at the specified time during the response period of the chip short-circuit verification. As a result, the data level signal that would not originally be output as low-high-low at t1 / 2 / 3 is changed to a low-high-low data level signal as shown in Figures 27 / 28 / 29 / 30. Therefore, the consumable box chip is functioning normally, and in this case, the printer does not report an error during the short-circuit verification stage. At the same time, when the reset terminal and the data terminal are short-circuited, the drive capability of the reset terminal is weak, so a low-high-low reset signal can be detected from the reset terminal at t1 / 2 / 3 as well.

[0185] As one embodiment, when the reset terminal and the power terminal are short-circuited, Figure 31 shows the waveforms output by each terminal of the test chip according to the short-circuit verification method of this application. Figure 31 is a schematic waveform diagram of the reset terminal and power terminal being short-circuited as provided in the embodiment of this application. Here, from byte 20 to byte 38, the reset terminal is pulled up simultaneously with the power terminal in advance, the power terminal remains high, and the data signal is low at least at times t1 and t3, and high at time t2. At the same time, because a desired level signal is set for the data terminal of the test chip at a specified time during the response period of the chip short-circuit verification, the data level signal that would not originally be output as low-high-low at t1 / 2 / 3 is changed to a data level signal exhibiting low-high-low as shown in Figure 31. Thus, the function of the consumable box chip is normal, and in this case, the printer does not report an error during the short-circuit verification stage.

[0186] Specifically, when the reset terminal and the power terminal are short-circuited, the reset terminal's driving capability is weaker than that of the power terminal. As a result, the reset terminal voltage is affected by the voltage at the power terminal, and during the short-circuit period, the reset terminal voltage waveform becomes similar to that of the power terminal, resulting in a phenomenon where the voltage is always at a high level. If the short circuit occurs early, a high level appears beforehand, and the reset terminal still shows a high level at byte 39.

[0187] As one embodiment, when the reset terminal and the ground terminal are short-circuited, Figure 32 shows the waveforms output by each terminal of the test chip according to the short-circuit verification method of this application. Figure 32 is a schematic waveform diagram of the reset terminal and ground terminal being short-circuited as provided in the embodiment of this application. Here, from byte 20 to byte 38, the reset terminal signal RST is continuously at a low level, and the data signal is at a low level at least at times t1 and t3, and at a high level at time t2. Specifically, because the reset terminal and the ground terminal are short-circuited, the voltage of the reset terminal is reduced from the original normal voltage to the ground voltage. At the same time, because a desired level signal is set for the data terminal of the test chip at a specified time during the response period of the chip short-circuit verification, the data level signal that would not originally be output as low-high-low at t1 / 2 / 3 is changed to a data level signal exhibiting low-high-low as shown in Figure 32. Therefore, the function of the consumable box chip is normal, and in this case, the printer does not report an error during the short-circuit verification stage.

[0188] Specifically, because the drive capability of the reset terminal is weaker than that of the ground terminal, the reset terminal is affected by the ground terminal. Therefore, during the short-circuit period, the voltage waveform at the reset terminal is similar to that of the ground terminal, showing a continuous low-level state.

[0189] To make it clear, the diagrams in each of the above embodiments show the detection waveforms of the reset terminal and the other terminals when a short-circuit fault already exists before the start of short-circuit detection. If a short-circuit fault occurs during the short-circuit detection period, the waveform before the short-circuit remains unaffected, while the waveform after the short-circuit changes according to the situation.

[0190] Figure 33 is a schematic diagram of a configuration applied to a test chip equipped with a detection unit provided in an embodiment of this application. As shown in Figure 33, the test chip 100 comprises a detection unit 6, a substrate 10, an earth terminal 5, a first conductive terminal 1, a second conductive terminal 2, a third conductive terminal 3, and a fourth conductive terminal 4. The detection unit 6 is located on the substrate 10 and electrically connected to the earth terminal 5. The detection unit 6 comprises a first detection segment 61, a second detection segment 62, and a ground segment 60. The first detection segment is connected to the earth terminal by the ground segment. The second conductive terminal 2 and the fourth conductive terminal 4 are both located on one side of the first detection segment 61. The first conductive terminal 1 and the third conductive terminal 3 are both located on the other side of the first detection segment 61. The second detection segment 62 is connected to the first detection segment 61, and the first conductive terminal 1 and the third conductive terminal 3 are spaced apart. Here, the first detection segment 61, the second detection segment 62, and the ground segment 60 are each metal wires. Of course, the detection unit 6 can be manufactured from other conductive materials such as carbon oil or rubber. Here, the test chip 100 includes a memory (not shown), and the ground terminal 5, first conductive terminal 1, second conductive terminal 2, third conductive terminal 3, and fourth conductive terminal 4 are all electrically connected to the memory. The first conductive terminal 1 may be a clock terminal, the second conductive terminal 2 may be a data terminal, the third conductive terminal 3 may be a power terminal, and the fourth conductive terminal 4 may be a reset terminal.

[0191] In this embodiment, a chip detection method applicable to the test target chip shown in Figure 33 is further provided. 34 This is a flowchart of a chip detection method provided in an embodiment of the present application, and as shown in Figure 34, the chip detection method includes the following steps.

[0192] Step S161: Obtain the short-circuit verification signal.

[0193] For example, the short-circuit verification signal may be transmitted by the printing device to a consumable box chip with a detection unit, and is used by the consumable box chip to perform fault detection in cooperation with the printer before communication between the printing device and the consumable box chip.

[0194] Step S162: Based on the short-circuit verification signal, a desired level signal is set for the data terminal of the chip under test at a specified time during the verification response period.

[0195] Furthermore, the consumable box chip performs a short-circuit verification of the chip after receiving a short-circuit verification signal. It also sets a desired level signal to the data terminals of the chip under test at a specified time during the response period of the chip short-circuit verification. The desired level signal may be set to a "low-high-low" level signal at three different specified times.

[0196] Step S163: Obtain the actual output level signal of the data terminal to which the desired level signal has been set.

[0197] Step S164: Identify the detection result of the chip under test based on the actual output level signal.

[0198] Here, the detection result for the chip under test includes whether the chip under test is functioning normally or whether the chip under test is faulty.

[0199] Furthermore, after setting a desired level signal for the data terminal, the system acquires the level signal actually output by the data terminal, and then identifies the fault detection result of the chip under test based on the actually output level signal.

[0200] In the above implementation process, by setting a desired level signal to the data terminal at a specified time during the verification response period, the fault detection result of the test target chip is identified from the actual output voltage of the data terminal, thereby enabling fault detection of the test target chip equipped with a detection unit.

[0201] In some of these embodiments, the step of identifying the detection result of the chip under test based on the actual output level signal includes the following steps:

[0202] Step 1: When the actual output level signal matches the desired level signal, the detection result for the chip under test indicates that the chip under test is functioning normally.

[0203] Step 2: If the actual output level signal does not match the desired level signal, the detection result for the chip under test is a failure of the chip under test, and the failure of the chip under test includes at least one of the following: a short circuit of the remaining terminals of the chip under test other than the reset terminal, a short circuit between the reset terminal and the clock terminal and / or power terminal, a short circuit between any terminal other than the reset terminal and the detection unit, and functional damage to the chip under test.

[0204] Specifically, if the actual output level signal of the data terminal matches the desired level signal, it indicates that the chip under test is functioning normally. If the actual output level signal does not match the desired level signal, it indicates that the chip under test has failed. The cause of the failure may include at least one of the following: a short circuit of the remaining terminals of the chip under test other than the reset terminal; a short circuit between the reset terminal and the clock terminal and / or power terminal; a short circuit between any terminal other than the reset terminal and the detection unit; and functional damage to the chip under test.

[0205] Figure 35 is a schematic waveform diagram of a short circuit between the clock terminal and the power terminal provided in an embodiment of this application. As shown in Figure 35, after the clock terminal and the power terminal are short-circuited, they may be electrically connected to the ground terminal 5 by the detection unit 6. The power signal VDD and the clock signal SCK are continuously reduced to low voltage from the normal voltage state in Figure 22. Because the chip 100 cannot operate normally, the signals at the data terminals are continuously low voltage from byte 20 to byte 36. In this case, the printer or consumable box chip can determine that the chip under test has failed because at least one of the clock signal SCK, power signal VDD, or data signal SDA is continuously low voltage from byte 33 to byte 36, and can determine the specific short-circuit location based on the waveform characteristics. At the same time, the printer reports an error during the short-circuit verification phase.

[0206] Figure 36 is a schematic waveform diagram of a short circuit between the clock terminal and the data terminal provided in an embodiment of this application. As shown in Figure 36, after the clock terminal and the data terminal are short-circuited, they may be electrically connected to the ground terminal 5 by the detection unit 6. After the voltage of the power signal VDD is raised, the chip 100 can be initialized, and when initialization is complete, the voltage of the reset signal RST is raised. The clock terminal and the data terminal are simultaneously connected to the detection unit 6, and therefore the short-circuited clock signal SCK and data signal SDA are continuously at low voltage. In this case, the printer or consumable box chip can determine that the chip under test has failed because the clock signal SCK and power signal VDD are continuously at low voltage from byte 33 to byte 36, and can determine the specific short-circuit location based on the waveform characteristics. At the same time, the printer reports an error during the short-circuit verification stage.

[0207] Figure 37 is a schematic waveform diagram of a short circuit between the power terminal and the data terminal provided in an embodiment of this application. As shown in Figure 37, after the power terminal and the data terminal are short-circuited, they may be electrically connected to the ground terminal 5 by the detection unit 6. The reset signal RST may be raised when initialization is complete, and the clock signal SCK may have a normal waveform. The power signal VDD and the data signal SDA may be continuously low voltage. In this case, the printer or consumable box chip can determine that the chip under test has failed because at least one of the power signal VDD and the data signal SDA is continuously low voltage from byte 33 to byte 36, and can determine the specific short-circuit location based on the waveform diagram. At the same time, the printer reports an error during the short-circuit verification stage.

[0208] Figure 38 is a schematic waveform diagram of a short circuit between the reset terminal and the clock terminal provided in an embodiment of this application. As shown in Figure 38, when the reset terminal and the clock terminal are short-circuited, the reset terminal and the clock terminal can be electrically connected to the ground terminal 5 by the detection unit 6. Therefore, the voltages of the reset terminal and the clock terminal are continuously low from byte 33 to byte 36, and the chip 100 cannot operate normally. Consequently, the signals of the data terminals are continuously low from byte 20 to byte 36. In this case, the printer or consumable chip can determine that the chip under test may fail because at least one of the reset signal RST, clock signal SCK, and data signal SDA is continuously low from byte 33 to byte 36, and that there is a short circuit between the reset terminal and the clock terminal based on the waveform characteristics. Simultaneously, the printer reports an error during the short-circuit verification phase.

[0209] Figure 39 is a schematic waveform diagram of a short circuit between another reset terminal and power terminal provided in an embodiment of this application. As shown in Figure 39, after the reset terminal and power terminal are short-circuited, they may be electrically connected to the ground terminal 5 by the detection unit 6. The power signal VDD and the reset signal RST may be continuously pulled down as low voltages at the start. The clock signal SCK can output a normal waveform. Because the chip 100 is not functioning properly, the signals at the data terminals are continuously low voltage from byte 20 to byte 36. The printer or consumable box chip can determine that the chip under test has failed because at least one of the reset signal RST, power signal VDD, and data signal SDA is continuously low voltage from byte 33 to byte 36, and can determine the specific short-circuit location based on the waveform. At the same time, the printer reports an error during the short-circuit verification phase.

[0210] In the above implementation process, by comparing whether the actual output level signal of the data terminal matches the desired level signal, it is possible to auxiliaryly detect whether or not a malfunction occurs in the function of the test target chip equipped with a detection unit.

[0211] In some of these embodiments, when the actual output level signal matches the desired level signal, the method further includes the following steps.

[0212] Step 1: Determine whether the voltage at the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period.

[0213] Step 2: If the voltage at the reset terminal of the chip under test remains within the specified voltage range during the verification response period, the chip under test is not short-circuited.

[0214] Step 3: If the voltage at the reset terminal of the chip under test does not remain within the specified voltage range during the verification response period, a short circuit will occur between the reset terminal and the data terminal or ground terminal on the chip under test.

[0215] For example, after determining that the function of the chip under test is normal, it is possible to determine whether or not a short circuit occurs between the reset terminal and the data terminal or ground terminal based on the voltage of the reset terminal of the chip under test.

[0216] If the voltage at the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period, the chip under test is not short-circuited. If the voltage at the reset terminal of the chip under test does not remain within a predetermined voltage range during the verification response period, there is a possibility that the reset terminal and data terminal are short-circuited, or that the reset terminal and the ground terminal are short-circuited, or that the reset terminal and the metal wire in the detection unit are short-circuited.

[0217] In the above implementation process, after confirming that the function of the chip under test is normal, the voltage during the verification response period of the reset terminal is used to determine whether or not a short circuit occurs between the reset terminal and the data terminal or the ground terminal in the chip under test, thereby accurately determining the possible short-circuit conditions of the chip under test.

[0218] In some of these embodiments, when the actual output level signal matches the desired level signal, the method further includes the following steps.

[0219] Step 1: Determine whether the chip under test responds to communication commands during the preset communication period.

[0220] Here, the communication command is the communication command sent by the printing device communicating with the chip under test, and the preset communication period is after the verification response period.

[0221] Step 2: If the test chip does not respond to the communication command during the preset communication period, the short-circuit verification result will indicate that the test chip is functioning normally, but a short circuit occurs between the reset terminal and the data terminal or ground terminal.

[0222] Step 3: If the test chip responds to a communication command within the preset communication period, the short-circuit verification result indicates that the test chip is functioning normally and is not short-circuited.

[0223] In the flowcharts for each of the embodiments described above, the steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated herein, the execution of these steps is not strictly limited to a specific sequence, and these steps may be executed in other sequences. Furthermore, at least some of the steps in the flowcharts for each of the embodiments described above may include multiple steps or stages, and these steps or stages do not necessarily have to be executed at the same time, but may be executed at different times. The execution sequence of these steps or stages does not necessarily have to be executed sequentially, but may be executed sequentially or alternately with other steps, or at least some of the steps or stages in other steps.

[0224] In this embodiment, a chip short-circuit verification device for realizing the above embodiment and selectable embodiments is further provided, and what has already been described will not be repeated. The "modules," "units," "subunits," etc. used below can realize a combination of software and / or hardware with predetermined functions. The devices described in the following embodiments are preferably realized in software, but realization in hardware, or a combination of software and hardware, is possible and conceivable.

[0225] Figure 40 is a block diagram of the configuration of a chip short-circuit verification device provided in an embodiment of this application, and as shown in Figure 40, the device is A first acquisition module 221 for acquiring a short-circuit verification signal, A level signal setting module 222 is used to set a desired level signal for the data terminals of the chip under test at a specified time during the verification response period, based on a short-circuit verification signal. A second acquisition module 223 for acquiring the actual output level signal of a data terminal to which a desired level signal has been set, The system includes a specific module 224 for identifying the short-circuit verification result of the chip under test based on the actual output level signal, and the short-circuit verification result indicates that the function of the chip under test is normal, but the reset terminal and at least one terminal other than the reset terminal are short-circuited, meaning the function of the chip under test is normal and there is no short circuit, or the function of the chip under test is damaged.

[0226] In some of these embodiments, if the actual output level signal and the desired level signal do not match, the short-circuit verification result indicates that the functionality of the chip under test is impaired.

[0227] In some of these embodiments, when the actual output level signal matches the desired level signal, the function of the chip under test is normal, and the specific module 224 further This is used to determine whether the voltage at the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period. If the voltage at the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period, it indicates that the chip under test is not short-circuited. If the voltage at the reset terminal of the chip under test does not remain within a predetermined voltage range during the verification response period, a short circuit will occur between the reset terminal and at least one other terminal on the chip under test.

[0228] In some of these embodiments, when the actual output level signal matches the desired level signal, the function of the chip under test is normal, and the specific module 224 further This is used to determine whether the chip under test responds to a communication command within a preset communication period. The communication command is a communication command sent by the print device communicating with the chip under test, and the preset communication period is after the verification response period. During the preset communication period, if the test chip does not respond to the communication command, the short-circuit verification result indicates that the test chip is functioning normally, but that the reset terminal and at least one other terminal are short-circuited. If the test chip responds to a communication command within the preset communication period, the short-circuit verification result indicates that the test chip is functioning normally and there is no short circuit.

[0229] In some of these embodiments, the level signal setting module 222 specifically, Based on the short-circuit verification signal, multiple clock times of the clock terminal on the chip under test are identified. Based on multiple clock times, the verification response period is identified. During the verification response period, the corresponding specified time for the data terminal on the chip under test is identified. It is used to set a desired level signal at the corresponding specified time on the data terminal.

[0230] In some of these embodiments, the specified time includes a first specified time, a second specified time, and a third specified time, where the first specified time is earlier than the second specified time, and the second specified time is earlier than the third specified time, and the level signal setting module 222 specifically, This is used to set a low-level signal at the first specified time corresponding to the data terminal, a high-level signal at the second specified time corresponding to the data terminal, and a low-level signal at the third specified time corresponding to the data terminal.

[0231] In some of these embodiments, the first acquisition module 221 specifically, Used to acquire the original waveform data transmitted by the printing device. If a short-circuit verification mark exists in the original waveform data, the original waveform data is identified as a short-circuit verification signal.

[0232] Each of the above modules may be a functional module or a program module, and may be implemented by software or by hardware. For modules implemented by hardware, the above modules may be located on the same processor, or each of the above modules may be located on different processors in any combination.

[0233] In this embodiment, a chip is further provided that includes a clock terminal, a data terminal, a power terminal, a ground terminal, a reset terminal, and a processing unit for performing the chip short-circuit verification method described in any of the above embodiments, or for performing the chip detection method described in any of the above embodiments.

[0234] In this embodiment, a consumable box equipped with the chip in the above embodiment is further provided to perform the chip short-circuit verification method or chip detection method described in any of the above embodiments.

[0235] Specifically, the consumable box may be at least one of the common consumable boxes such as ink cartridge boxes, toner cartridge boxes, and ink pouch boxes.

[0236] Figure 16 is a schematic diagram of the configuration of a consumable box provided in an embodiment of the present application, and as shown in Figure 16, the present application provides a consumable box 300 which may include a box 310 and a tip 100. The box 310 has a bottom wall 301 and side walls, the side walls comprising a first side wall 302. The tip 100 may be attached to the first side wall 302.

[0237] The consumable box 300 may be used, for example, to be attached to a printer. In actual use, the Y-axis direction may be approximately vertical. The bottom wall 301 may face downward, the first side wall 302 can be engaged with the printer, and the tip 100 can be electrically connected to the printer. Exemplarily, the consumable box 300 includes an ink outlet 303, which may be located in the bottom wall 301. Each side wall can be bent relative to the bottom wall 301, for example, perpendicular to each other. 。

[0238] Any combination of the technical features of the above embodiments is possible, and for the sake of brevity, not all possible combinations of the technical features of the above embodiments will be described. However, as long as these combinations of technical features are inconsistent, they should all be considered to fall within the scope described herein.

[0239] The above embodiments illustrate only a few embodiments of this application, and while the descriptions are specific and detailed, they should not be understood as limiting the scope of patent protection. It should be noted that those skilled in the art can make several further modifications and improvements without departing from the concept of this application, all of which fall within the scope of protection. Therefore, the scope of protection of this application should be based on the attached claims. [Explanation of symbols]

[0240] 1 1st conductive terminal 11 1st contact part 2 Second conductive terminal 21 2nd contact part 3 Third conductive terminal 31 Third contact part 4 4th conductive terminal 41 4th contact part 5. Ground terminal 51 Ground wire contact point 6. Detection Unit 60 Grounding Segments 61 First detection segment 62 Second Detection Segment 63 Third Detection Segment 64 Fourth Detection Segment 65 Fifth Detection Segment 10 Substrate 20 First Processor 30 Memory 100 Chip 200 Printer 201 Second Processor 300 Consumable Box 310 Box 301 Bottom Wall 302 First Side Wall 303 Ink Outlet 102 Terminal 104 Server 401 Data Terminal 402 Reset Terminal 403 Clock Terminal 404 Power Supply Terminal 221 First Acquisition Module 222 Level Signal Setting Module 223 Second Acquisition Module 224 Identification Module

Claims

1. It's a tip, Suitable for communication connections with printers, The aforementioned chip is A substrate having a first half and a second half, An earth terminal having an earth wire contact portion located on the first half of the circuit board for contacting the stylus of the printer, At least two conductive terminals located on the second half of the substrate and spaced apart from each other, wherein each conductive terminal has a contact portion for contacting the printer's stylus, and the at least two conductive terminals include a first conductive terminal and a second conductive terminal, wherein the distance between the contact portion of the first conductive terminal and the contact portion of the second conductive terminal is smaller than the distance between either one of them and the ground wire contact portion, A detection unit located on the substrate and electrically connected to the ground terminal, comprising a first detection segment, wherein the first detection segment is located between the first conductive terminal and the second conductive terminal, the first detection segment and the first conductive terminal are spaced apart, and the first detection segment and the second conductive terminal are spaced apart. A chip characterized by the following features.

2. The detection unit further comprises a second detection segment, the second detection segment and the first detection segment are located adjacent to each other on both sides of the first conductive terminal, and the second detection segment cooperates with the first detection segment to surround the first conductive terminal. The chip according to feature 1.

3. The intersection of the second detection segment and the first detection segment approaches the contact portion of the first conductive terminal and moves away from the ground wire contact portion. The chip according to feature 2.

4. The at least two conductive terminals further include a third conductive terminal, wherein the third conductive terminal and the first conductive terminal are spaced apart, and the second detection segment is located between the first conductive terminal and the third conductive terminal. In the arrangement direction of the third conductive terminal and the first conductive terminal, the projection of the second detection segment covers the first conductive terminal. The chip according to feature 2.

5. The at least two conductive terminals further include a third conductive terminal and a fourth conductive terminal, wherein the distance between the contact portion of the third conductive terminal and the contact portion of the fourth conductive terminal is smaller than the distance between either one of them and the ground wire contact portion. The first conductive terminal and the second conductive terminal are arranged along the first direction, the fourth conductive terminal and the second conductive terminal are arranged sequentially along the second direction, the ground terminal, the third conductive terminal and the first conductive terminal are arranged sequentially along the second direction, and the second direction and the first direction intersect. The contact portion of the first conductive terminal and the contact portion of the ground wire are symmetrical with respect to the dividing cross-section that separates the first half and the second half. The chip according to claim 2 or 3, characterized by the above.

6. The detection unit further comprises a third detection segment, and the third detection segment, the first detection segment, and the second detection segment cooperate to surround the third conductive terminal. And / or, the detection unit further comprises a fourth detection segment located between the second conductive terminal and the fourth conductive terminal, and in the direction of arrangement of the fourth conductive terminal and the second conductive terminal, the projection of the fourth detection segment covers the second conductive terminal. The chip according to feature 5.

7. The at least two conductive terminals further include a third conductive terminal and a fourth conductive terminal, the contact portion of the first conductive terminal and the ground wire contact portion are asymmetric with respect to a dividing cross section for separating the first half and the second half, and the connection direction of the contact portion of the third conductive terminal and the ground wire contact portion intersects with the connection direction of the contact portion of the second conductive terminal and the contact portion of the fourth conductive terminal. The chip according to any one of claims 1 to 3.

8. The at least two conductive terminals further include a third conductive terminal and a fourth conductive terminal, wherein the first conductive terminal is a clock terminal, the second conductive terminal is a data terminal, the third conductive terminal is a power terminal, and the fourth conductive terminal is a reset terminal. The chip according to any one of claims 1 to 3.

9. A consumable box comprising the chip described in any one of claims 1 to 8. A consumables box characterized by the following features.

10. The consumable box comprises a box having a bottom wall and side walls, the chip is attached to the side wall of the box, and the dividing cross section of the chip for separating the first half and the second half is perpendicular to the bottom wall. The ground terminal and the second conductive terminal are provided opposite each other and separated by the first detection segment, the ground terminal is located on one side of the first detection segment that is close to the bottom wall, and the second conductive terminal is located on one side of the first detection segment that is away from the bottom wall, and the extension direction of the first detection segment is parallel to the bottom wall. The consumable box according to feature 9.

11. A chip detection method, The method described above is applied to a test chip provided with a detection unit, the test chip further comprising a substrate, a ground terminal, a clock terminal, a data terminal, a power terminal, and a reset terminal, the detection unit located on the substrate and electrically connected to the ground terminal, the detection unit comprising a first detection segment, a second detection segment, and a ground segment, the first detection segment being connected to the ground terminal via the ground segment, the data terminal and the reset terminal both located on one side of the first detection segment, the clock terminal and the power terminal both located on the other side of the first detection segment, the second detection segment and the first detection segment being connected, the clock terminal and the power terminal being spaced apart, and the method described above is: Steps include obtaining a short-circuit verification signal, Based on the aforementioned short-circuit verification signal, the steps include setting a desired level signal to the data terminal of the chip under test at a specified time during the verification response period, The steps include acquiring the actual output level signal of the data terminal to which the desired level signal has been set, A step of determining the detection result of the chip under test based on the actual output level signal, the step of determining whether the detection result of the chip under test is normal functioning or a failure of the chip under test, including A chip detection method characterized by the above.

12. The step of identifying the detection result of the chip under test based on the actual output level signal is as follows: When the actual output level signal matches the desired level signal, the detection result of the chip under test indicates that the chip under test is functioning normally. If the actual output level signal does not match the desired level signal, the detection result of the chip under test is a failure of the chip under test, and the failure of the chip under test includes at least one of the following: a short circuit of the remaining terminals of the chip under test other than the reset terminal, a short circuit between the reset terminal and the clock terminal and / or power terminal, a short circuit between any terminal other than the reset terminal and the detection unit, and functional damage to the chip under test. The chip detection method according to feature 11.

13. When the actual output level signal matches the desired level signal, the method further: The steps include determining whether the voltage of the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period, If the voltage at the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period, the step of not short-circuiting the chip under test is completed. The step includes: if the voltage of the reset terminal of the chip under test does not remain within a predetermined voltage range during the verification response period, the reset terminal and the data terminal or ground terminal of the chip under test are short-circuited. The chip detection method according to claim 12, characterized by the features described above.

14. A chip short-circuit verification method, Steps include obtaining a short-circuit verification signal, Based on the aforementioned short-circuit verification signal, the steps include setting a desired level signal to the data terminal of the chip under test at a specified time during the verification response period, The steps include acquiring the actual output level signal of the data terminal to which the desired level signal has been set, A step of determining the short-circuit verification result of the test chip based on the actual output level signal, wherein the short-circuit verification result indicates that the function of the test chip is normal, but the reset terminal and at least one terminal other than the reset terminal are short-circuited, and the function of the test chip is normal and not short-circuited, or the function of the test chip is impaired. A chip short-circuit verification method characterized by the following:

15. The step of identifying the short-circuit verification result of the chip under test based on the actual output level signal is: If the actual output level signal does not match the desired level signal, the short-circuit verification result includes damage to the function of the chip under test. The chip short-circuit verification method according to feature 14.

16. When the actual output level signal matches the desired level signal, the function of the chip under test is normal, and the method further... The steps include determining whether the voltage of the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period, If the voltage at the reset terminal of the chip under test remains within a predetermined voltage range during the verification response period, the step of not short-circuiting the chip under test is completed. The procedure includes the step of short-circuiting the reset terminal of the chip under test and at least one other terminal of the chip under test if the voltage of the reset terminal of the chip under test does not remain within a predetermined voltage range during the verification response period. The chip short-circuit verification method according to feature 15.

17. When the actual output level signal matches the desired level signal, the function of the chip under test is normal, and the method further... A step of determining whether the test chip responds to a communication command within a preset communication period, wherein the communication command is a communication command transmitted by a printing device communicating with the test chip, and the preset communication period is a step that follows the verification response period. If the test target chip does not respond to the communication command during the preset communication period, the short-circuit verification result is that the function of the test target chip is normal, but the reset terminal and at least one terminal other than the reset terminal are short-circuited. If the test target chip responds to a communication command within the preset communication period, the short-circuit verification result includes a step in which the test target chip is functioning normally and is not short-circuited. The chip short-circuit verification method according to feature 15.

18. The step of setting a desired level signal to the data terminal of the chip under test at a specified time during the verification response period based on the aforementioned short-circuit verification signal is as follows: The steps include identifying multiple clock times of the clock terminals in the chip under test based on the short-circuit verification signal, A step of identifying a verification response period based on multiple clock times, The verification response period includes the step of identifying the corresponding specified time for the data terminal on the test target chip, The step of setting a desired level signal at the corresponding specified time of the data terminal includes: The chip short-circuit verification method according to feature 14.

19. The specified time includes a first specified time, a second specified time, and a third specified time, wherein the first specified time is earlier than the second specified time, the second specified time is earlier than the third specified time, and the step of setting the desired level signal at the corresponding specified time of the data terminal is as follows: The steps include: setting a low-level signal at the first designated time corresponding to the data terminal; setting a high-level signal at the second designated time corresponding to the data terminal; and setting a low-level signal at the third designated time corresponding to the data terminal. The chip short-circuit verification method according to feature 18.

20. The step of obtaining a short-circuit verification signal is: The steps include acquiring the original waveform data transmitted by the printing device, The step of identifying the original waveform data as a short-circuit verification signal if a short-circuit verification mark exists in the original waveform data includes the step of The chip short-circuit verification method according to feature 14.

21. A chip short-circuit verification device, A first acquisition module for acquiring a short-circuit verification signal, A level signal setting module for setting a desired level signal to the data terminal of the chip under test at a specified time during the verification response period based on the aforementioned short-circuit verification signal, A second acquisition module for acquiring the actual output level signal of the data terminal on which a desired level signal has been set, A specific module for identifying the short-circuit verification result of the test target chip based on the actual output level signal, wherein the short-circuit verification result indicates that the function of the test target chip is normal, but the reset terminal and at least one terminal other than the reset terminal are short-circuited on the test target chip, and the function of the test target chip is normal and not short-circuited, or the function of the test target chip is impaired. A chip short-circuit verification device characterized by the following features.

22. It's a tip, The system includes a clock terminal, a data terminal, a power terminal, a ground terminal, a reset terminal, and a processing unit for executing the chip detection method described in any one of claims 11 to 13, or the chip short-circuit verification method described in any one of claims 14 to 20. A chip characterized by the following features.

23. A consumables box comprising the chip described in claim 22. A consumables box characterized by the following features.

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