III-N Dual Gate Device

Abstract

Achieving high gain and low noise in RF circuits. [Solution] A III-N dual gate device and a method for manufacturing a III-N dual gate device. An example semiconductor device includes a III-N back barrier, a III-N channel layer on the III-N back barrier, and a two-dimensional electron gas (2DEG) channel in the III-N channel layer. The semiconductor device includes a source contact and a drain contact, and includes a first gate contact and a second gate contact between the source contact and the drain contact. Between the first gate contact and the second gate contact, the semiconductor device includes an n+GaN contact coupled to the III-N channel layer in a connection region.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices, and more particularly to III-N devices with dual gates. [Background technology]

[0002] Dual-gate transistors and cascodes are two circuit elements commonly used in radio frequency (RF) circuits. A dual-gate transistor is a type of field-effect transistor (FET) that has two gates instead of one. Dual-gate transistors are useful in RF amplifiers because they can achieve high gain and low noise.

[0003] On the other hand, a cascode is a type of circuit that combines two or more transistors to create a high-gain, low-noise amplifier. In a cascode circuit, two transistors are connected in series, with the drain of the first transistor connected to the source of the second transistor. This increases the maximum stable gain, making it useful in many RF circuits.

[0004] Dual-gate transistors and cascodes are widely used in RF circuits because they enable high-gain, low-noise amplification. Dual-gate transistors and cascodes are commonly used in low-noise amplifiers, mixers, frequency synthesizers, RF amplifiers, mixers, and other high-frequency circuits. By combining these circuit elements with passive components such as inductors and capacitors, engineers can design complex RF circuits for a variety of applications, including wireless communications and radar systems. [Overview of the project]

[0005] In a first aspect of this disclosure, the semiconductor device includes a III-N back barrier, a III-N channel layer on the III-N back barrier, and a two-dimensional electron gas (2DEG) channel within the III-N channel layer. The semiconductor device includes a source contact and a drain contact, and between the source contact and the drain contact are a first gate contact and a second gate contact. Between the first gate contact and the second gate contact is an n+GaN contact coupled to the III-N channel layer in a connection region. [Brief explanation of the drawing]

[0006] [Figure 1] This is a circuit diagram showing an example of a dual-gate transistor.

[0007] [Figure 2] This is a cross-sectional view showing an example of a dual-gate transistor configuration.

[0008] [Figure 3] This is a cross-sectional view of a dual-gate transistor showing an example where an ohmic metal is present on the n+GaN contact in the connection region.

[0009] [Figure 4] This is a cross-sectional view of a dual-gate transistor in an example that does not have an n+GaN contact but includes an ohmic metal.

[0010] [Figure 5] This is a cross-sectional view of a dual-gate transistor in an example where the first and second gate contacts are embedded to different depths.

[0011] [Figure 6] This is a cross-sectional view of a dual-gate transistor in an example where the access regions are recessed to different depths.

[0012] [Figure 7]Cross-sectional view of a dual-gate transistor in an example having one or more etching stop layers.

[0013] [Figure 8] Cross-sectional view of a dual-gate transistor in an example where the first gate contact 116 is embedded through both etching stop layers.

[0014] [Figure 9] Cross-sectional view of a dual-gate transistor in an example having a single etching stop layer.

[0015] [Figure 10] Cross-sectional view of a dual-gate transistor in an example having a "raised" n+ GaN contact.

[0016] [Figure 11] Planar view of a dual-gate transistor in a configuration with different gate widths.

[0017] [Figure 12] Planar view of a dual-gate transistor in an example where there is a non-conductive region in the gate.

[0018] [Figure 13] Cross-sectional view of an example of a dual-gate transistor fabricated with Ga-polarity GaN.

[0019] [Figure 14] Cross-sectional view of a transistor in an example where the n+ GaN contact extends through the barrier layer.

[0020] [Figure 15] Flow chart showing a manufacturing method 300 according to an example of a dual-gate HEMT having an n+ GaN contact.

Mode for Carrying Out the Invention

[0021] Detailed explanation This specification describes dual-gate transistors formed from III-N material systems. In some examples, a dual-gate transistor includes a substrate, a buffer layer, a III-N back barrier, a III-N channel layer, and a two-dimensional electron gas (2DEG) channel within the III-N channel layer. The dual-gate transistor includes a source contact and a drain contact, and between the source contact and the drain contact are a first gate contact and a second gate contact. The dual-gate transistor includes a III-N contact between the first gate contact and the second gate contact, coupled to the III-N channel layer in a connection region. The III-N contact may include highly doped n+GaN.

[0022] Figure 1 is a circuit diagram showing an example of a dual-gate transistor 100. This transistor includes a source (S) contact and a drain (D) contact, a first gate contact (G1) and a second gate contact (G2), and an impedance Z. The dual-gate transistor 100 is formed from a III-N material system.

[0023] Compared to some conventional transistors, the dual-gate transistor 100 may offer one or more of the following advantages: ● Increased gain per stage: ○ Reduction in the number of amplification stages (reduction in wafer area, miniaturization of the system, reduction in power consumption) As long as the additional resistance from the dual gate does not excessively increase the knee voltage, an improvement in power added efficiency (PAE) can be expected. ● Improved output power density: 〇 By improving the voltage withstand capability, it may be possible to achieve an increase in output power density in output amplifier applications. ● Improved switch performance: Dual-gate devices can reduce capacitance (Coff) in the off state. If the on-resistance (Ron) does not increase significantly, the product of Coff*Ron becomes smaller, potentially improving switching performance.

[0024] The dual-gate transistor may be suitable for use in one or more of the following applications. ● Power amplifier ● Variable gain amplifier 〇 By adjusting the bias voltage to G2, the gain of a signal leveling amplifier or a beamformer can be adjusted over a wide range. ● Low noise amplifier ● RF switch ● Front-end module including a transceiver module

[0025] FIG. 2 is a cross-sectional view showing a configuration example of the dual-gate transistor 100. The transistor 100 configured as a high electron mobility transistor (HEMT) includes a substrate layer 102, a buffer layer 104, and a III-N back barrier layer 106. The substrate layer 102 can be made of, for example, silicon, silicon carbide, sapphire, AlN, or GaN. The transistor 100 includes a III-N channel layer 108 on the III-N back barrier layer 106. In this specification, the terms such as III-nitride or III-N materials, layers, devices, etc. refer to materials or devices composed of compound semiconductor materials according to v B w Al x In y Ga z N a (D) b Here, v + w + x + y + z is about 1, 0 < v < 1, 0 < w < 1, 0 < x < 1, 0 < y < 1, 0 < z < 1, a + b is about 1, 0.9 < a < 1, 0 < b < 0.1, and (D) is any group V element other than nitrogen.

[0026] The buffer layer 104 may be formed from, for example, GaN, or may contain GaN, and may be configured to allow the growth of a high-quality III-N active device layer thereon. The back barrier layer 106 may be formed from, for example, AkGai-xN, or may contain AkGai-xN. The bandgap of the back barrier layer 106 may be larger than the bandgap of the buffer layer 104. The III-N channel layer 108 may be made of, for example, GaN. The III-N channel layer 108 may have a different composition from the back barrier layer 106, and may be configured, for example, so that the bandgap of the back barrier layer 106 is larger than the bandgap of the III-N channel layer 108.

[0027] The thicknesses of layers 108 and 106 are selected so as to induce a two-dimensional electron gas (2DEG) channel 110 (shown as a dashed line in Figure 2) in the III-N channel layer 108, adjacent to the interface between the back barrier layer 106 and the III-N channel layer 108. The 2DEG channel 110 is a layer of electrons formed at the interface of two semiconductor materials having different band gaps.

[0028] Transistor 100 includes a source contact 112 coupled to the III-N channel layer 108, and a drain contact 114 coupled to the III-N channel layer 108 and spaced apart from the source contact 112 along the length 122 of transistor 100. Transistor 100 includes a first gate contact 116 located above the III-N channel layer 108 and a second gate contact 118 located above the III-N channel layer 108, between the source contact 112 and the drain contact 114. Contacts 112 and 114 are electrically connected to the 2DEG channel 110. A voltage referenced to the potential of the source contact 112 is applied to the gate contacts 116 and 118, thereby modulating the charge within the 2DEG channel 110. In this specification, two or more contacts, or other items such as conductive layers or conductive components, are said to be “electrically connected” or “coupled” if they are connected by a sufficiently conductive material such that the potentials of each of those contacts or other items are always the same (i.e., approximately the same) under normal bias conditions.

[0029] In general, any suitable material may be used to form contacts 112, 114, 116, and 118. As shown in the example in Figure 2, the source contact 112 and drain contact 114 are formed of an ohmic metal on a III-N material. Metals with good conductivity, low contact resistance, and high thermal stability are typically used for the source contact 112 and drain contact 114. Metals commonly used in III-N transistors include nickel (Ni), gold (Au), aluminum (Al), titanium (Ti), platinum (Pt), and alloys such as titanium-aluminum (Ti / Al) alloys and nickel-gold (Ni / Au) alloys. The specific selection of contact material may depend on device requirements such as the desired operating temperature range, the type of III-N material used, and the specific device architecture.

[0030] For gate contacts 116 and 118, transistor 100 may contain materials with high work function. This is to allow effective control of carrier flow in channel 108 by the gate voltage, and may also provide desirable manufacturing properties such as surface adhesion and etching selectivity. Generally, metals such as platinum (Pt) and palladium (Pd), or alloys such as nickel-gold (Ni / Au), titanium-gold (Ti / Au), and titanium nitride (TiN) are used. If an additional insulating layer is placed between the III-N layer and the gate metal, metals with low work function such as Ti and Al, or alloys of these metals, may also be used to form the gate contacts. Examples of insulating layers include silicon nitride, aluminum oxide, silicon oxide, hafnium oxide, or aluminum silicon oxide. For example, Ni / Au or Ti / Au laminates may be used.

[0031] Transistor 100 includes an n+GaN contact 120 coupled to a III-N channel layer 108 in the connection region between the first gate contact 116 and the second gate contact 118. n+GaN refers to a type of gallium nitride (GaN) semiconductor material that is highly doped with impurities (e.g., silicon or germanium) to enhance conductivity. Here, "n" refers to the type of doping used to inject electrons into the crystal lattice structure of the GaN material to generate excess negative charge carriers. The "+" symbol indicates that the material is highly doped, meaning that high concentrations of impurities have been intentionally added to the material to enhance conductivity. n+GaN is an important material used in the development of high-power, high-frequency electronic devices such as power amplifiers and radio frequency (RF) switches. Due to its inherent material properties such as high electron mobility, high thermal conductivity, and wide bandgap, n+GaN is very well suited for use in these applications.

[0032] In this specification, n+GaN refers to GaN that has been doped to a degree suitable for applications requiring high-speed electronic devices such as power electronics and high-frequency transistors. The doping concentration is, for example, 1018 ~10 20 cm -3 It may be within the range of. The actual doping concentration achievable in a specific configuration depends on many factors such as the purity of the starting material, doping technology, growth conditions, etc. Therefore, the exact doping concentration of n+GaN may vary depending on the specific processing methods and conditions used in the manufacture of the material.

[0033] In the operation of transistor 100, when a voltage is applied to the first gate contact 116 with reference to the voltage of the source contact 112, an electric field is generated that modulates the electron density in the 2DEG channel 110 near the gate contact 116. As a result, the conductivity of the channel 108 near the gate contact 116 is modulated, and a variable current flows.

[0034] The second gate contact 118 can be used to control the output current and impedance at the drain contact 114 of the transistor 100. By applying a voltage and impedance to the second gate contact 118, the distribution of electrons in the 2DEG channel 110 can be further modulated, and the output impedance at the drain contact 114 can be increased. As a result, the voltage gain from the gate contact 116 to the drain contact 114 with the source contact 112 as a common terminal can be increased compared to a transistor without the second gate contact 118.

[0035] One of the advantages of the dual-gate configuration is that the gain is larger compared to a single-gate HEMT. Since the two gate contacts 116 and 118 can be biased independently, the device characteristics can be controlled in more detail. Transistor 100 can be used in high-frequency amplifiers, mixers, and other RF applications where high linearity and low noise are important.

[0036] In some examples, the buffer layer 104, back barrier layer 106, and channel layer 108 are N-polarity III-N layers, and the III-N channel layer 108 is located on the N-plane of the back barrier layer 106. The n+GaN contact 120 can also be formed as N-polarity GaN. Optionally, the substrate 102 may be removed after the formation of the other layers 104, 106, and 108, so that the final transistor structure does not include the substrate 102. Furthermore, optionally, some or all of the III-N layers located beneath the back barrier layer 106 (e.g., the buffer layer 104) may be removed after the formation of the back barrier 106 and the III-N channel layer 108.

[0037] The n+GaN contact 120 in the connection region can improve the conductivity of the transistor 100. The presence of the n+GaN contact 120 can be particularly useful when N-polarity n+GaN is used as the contact 120. This is because the n+GaN in the connection region enhances the conductivity of the 2DEG channel 110 and provides a highly conductive current path through the connection region without additional ohmic contact resistance.

[0038] n-polar GaN is a type of GaN crystal growth direction, referring to a specific surface of the GaN crystal where nitrogen (N) atoms are predominantly located. In n-polar GaN, the (000-1) crystal plane is the dominant surface, and gallium (Ga) atoms are mainly located on the (0001) plane. Compared to other GaN growth directions, such as the commonly used c-plane Ga-polar GaN (0001), n-polar GaN has several unique characteristics. For example, n-polar GaN transistors can be formed using a heterostructure in which a two-dimensional electron gas (2DEG) is formed above the charge-induced barrier layer due to an inverted polarization-induced field, resulting in improved gate controllability (high gain) and reduced contact resistance (high efficiency). Furthermore, n-polar GaN transistors generally exhibit high electron mobility at high charge densities.

[0039] In this case, by using N-polarity GaN in the dual-gate transistor 100, a highly conductive continuous two-dimensional electron gas (2DEG) channel 110 can be formed between the first gate contact 116 and the second gate contact 118, allowing the on-resistance (RON) of the transistor 100 to be kept relatively low compared to other devices. (For example, if Ga polarity is used for the contacts in the connection region, the 2DEG channel 110 becomes more susceptible to damage, resulting in higher resistance.) Furthermore, because the resistance per unit length of the connection region is low, the first gate contact 116 and the second gate contact 118 can be placed further apart, making the manufacturing of the transistor 100 easier.

[0040] Figure 3 is a cross-sectional view of a dual-gate transistor 100, showing an example in which an ohmic metal 124 is provided on the n+GaN contact 120 in the connection region. The ohmic metal 124 can be formed from any suitable type of material.

[0041] Typically, ohmic metals include materials that exhibit linear current-voltage (IV) behavior under low bias voltages. This means that the current flowing across the metal-semiconductor interface is directly proportional to the applied voltage. Examples of metals commonly used as ohmic contacts in III-N transistors include titanium (Ti), aluminum (Al), platinum (Pt), palladium (Pd), nickel (Ni), gold (Au), and tungsten (W). In addition to pure metals, alloys such as nickel-gold (Ni / Au) alloys and titanium-aluminum (Ti / Al) alloys are also commonly used as ohmic contacts in III-N devices.

[0042] The presence of the ohmic metal 124 causes the current within the connection region to flow through three distinct regions: within the 2DEG channel 110, within the n+GaN contact 120, and within the ohmic metal 124. While the current flowing through the n+GaN contact 120 and the ohmic metal 124 suffers losses due to contact resistance, each path increases the overall conductivity of the connection region.

[0043] Figure 4 is a cross-sectional view of a dual-gate transistor 100 in an example that does not have an n+GaN contact but includes an ohmic metal 124. Including an ohmic metal 124 on the surface of the III-N channel 108 in the connection region may provide an advantage in conductivity, but this advantage may be small compared to a configuration with an n+GaN contact.

[0044] Figure 5 is a cross-sectional view of a dual-gate transistor 100 in an example where the first gate contact 116 and the second gate contact 118 are embedded to different depths in the III-N channel layer 108. The first gate contact 116 is embedded to a first depth, and the second gate contact 118 is embedded to a second depth, where, in the illustrated example, the first depth is greater than the second depth.

[0045] This configuration is useful in terms of stability and power efficiency. By burying the first gate contact 116 more deeply, the threshold voltage of the second gate (VT2) can become larger in the negative direction than the threshold voltage of the first gate (VTI), which may be advantageous in some circuits.

[0046] In some examples, the length 128 of the second gate contact 118 is longer than the length 126 of the first gate contact 116. This can be useful, for example, to increase the gain of the first gate and improve the breakdown voltage of the second gate.

[0047] A potential drawback of configuring transistor 100 as shown in Figure 5 is that it may require two etching depths, which could increase manufacturing complexity. However, this configuration may have one or more of the following advantages. ● The vibration is reduced because the gain associated with the second gate contact 118 is low. ● When VT2 increases in the negative direction, the voltage held at the first gate contact 116 increases, and the total breakdown voltage (and therefore the power density) of transistor 100 increases. ● Due to the thick channel, the current flowing through the second gate contact 118 increases when VG2 = 0V. This may eliminate the need for a bias circuit for the second gate contact 118.

[0048] Figure 6 is a cross-sectional view of a dual-gate transistor 100 in an example where the access regions are recessed to different depths. As shown in this example, the first access region 130 between the source contact 112 and the n+GaN contact 120 is recessed to the first access region depth, and the second access region 132 between the drain contact 114 and the n+GaN contact 120 is recessed to the second access region depth, with the first access region depth being deeper than the second access region depth.

[0049] Depressing the access region to different depths can help improve gain or stability, for example, and may offer one or more of the following advantages: ● The first gate contact 116 does not need to hold a very large voltage between itself and the 2DEG located on the drain side, and therefore does not require a very large GaN cap / channel thickness for distributed control. By making the first gate contact 116 thinner, capacitance can be reduced and gain can be improved. ● The first gate contact 116 may be buried deeper than the second gate contact 118 (see Figure 5). This causes VT2 to be a negative value compared to VTI. This usually corresponds to LG2 being longer than LG1. ● Etching the access area around the first gate contact 116 simultaneously with the gate recess etching of the second gate contact 118 can be convenient and may reduce the number of processing steps.

[0050] Figure 7 is a cross-sectional view of a dual-gate transistor 100 in an example having one or more etching stop layers. As shown in Figure 7, the transistor 100 includes two etching stop layers 134 and 136. The first gate contact 116 is embedded up to the first etching stop layer 134, and the second gate contact 118 is embedded up to the second etching stop layer 136. These etching stop layers may be formed using materials with different compositions from the layers being etched, such as AlGaN, InAlN, or p+GaN.

[0051] An etching stop layer can be used to precisely control the etching depth. Furthermore, as shown in Figure 7, for example, it can be convenient to use the same etching stop layer to determine the depth of the access region around the first gate contact 116 and the gate recess depth of the second gate contact 118.

[0052] Figure 8 is a cross-sectional view of a dual-gate transistor 100 in an example where the first gate contact 116 penetrates both etching stop layers 134 and 136 and is embedded beyond the first etching stop layer 134. This is useful, for example, to bring the first gate contact 116 closer to the channel and improve transconductance and gain. The second gate contact 118 may be embedded in a similar manner, penetrating the second etching stop layer 136.

[0053] Figure 9 is a cross-sectional view of a dual-gate transistor 100 in an example having a single etching stop layer 136. A single etching stop layer 136 may be useful, for example, to simplify epitaxial growth and the formation of n+ contacts to 2DEG. A single etching stop layer 136 can be used to define the recess depth of the access region around the first gate contact 116 and the second gate contact 118. By embedding the first gate contact 116 beyond the etching stop layer, the transconductance can be improved while obtaining some degree of dispersion control.

[0054] Figure 10 is a cross-sectional view of a dual-gate transistor 100 in an example having a “raised” n+GaN contact 138. In the examples shown in Figures 2 to 9, the n+GaN contact 120 is shown as having been regrown from an etched portion of the III-N channel layer 108 or ion-implanted into the III-N channel layer 108. In the example shown in Figure 10, the n+GaN contact 138 is on the upper surface of the III-N channel layer 108. The n+GaN contact 138 can be formed by in-situ growth, n+ regrowth, or implantation. Other features shown in Figures 2 to 9, such as differences in gate depth, are also applicable to the “raised” n+GaN contact 138.

[0055] Figure 11 is a plan view of a dual-gate transistor 100 in a configuration where gates 116 and 118 have different widths. Generally, some or all of the contacts 112, 114, 116, 118, and 120 can have different widths. For example, the first gate contact 116 has a first gate width 140, the second gate contact 118 has a second gate width 141, and the second gate width 142 can be wider than the first gate width 141. The source contact 112 may have the same width as the first gate contact 116, and the drain contact 114 and n+GaN contact 120 may have the same width as the second gate contact 118.

[0056] Since the current flowing through the two cells is the same, widening the width of the second gate contact 118 can prevent it from acting as a current choke. This allows, for example, the second gate contact 118 to be grounded to the source potential DC-wise, potentially eliminating the need for a DC bias or bypass capacitor. In some cases, a stepwise change in the active width may create current diffusion resistance between the two cells.

[0057] Figure 12 is a plan view of a dual-gate transistor 100 in an example where the gate has non-conductive regions. As shown in Figure 12, the first gate contact 116 includes a plurality of non-conductive regions 142 along the width direction of the first gate contact 116. The non-conductive regions 142 are arranged alternately with conductive regions. The non-conductive regions 142 can be made non-conductive by, for example, ion implantation or etching. Thus, the current-carrying gate width of 2DEG under the first gate contact 116 is substantially narrower than the current-carrying gate width of 2DEG under the second gate contact 118. Compared to the example shown in Figure 11, the current flow is more uniform, and thus the problem of diffusion resistance can be reduced.

[0058] Figure 13 is a cross-sectional view showing an example of a dual-gate transistor 200 fabricated using Ga polar GaN. The transistor 200 includes a substrate 202, a buffer layer 204, a III-N channel layer 206, and a III-N barrier layer 208 on the III-N channel layer 206. The III-N barrier layer 208 and the III-N channel layer 206 are configured to form a 2DEG channel 210 within the III-N channel layer 206. The buffer layer may further include a back barrier for confining charge within the channel, depending on the nature of its composition or the presence of certain layers adjacent to the channel layer 206.

[0059] The transistor 200 includes a source contact 212 coupled to the III-N channel layer 206 and a drain contact 214 coupled to the channel layer 206 and spaced apart from the source contact 212 along the longitudinal direction of the transistor 200. Between the source contact 212 and the drain contact 214, the transistor 200 includes a first gate contact 216 and a second gate contact 218 coupled to the barrier layer 208.

[0060] The transistor 200 includes an n+GaN contact 220 coupled to a barrier layer 208 in the connection region between the first gate contact 216 and the second gate contact 218. The n+GaN contact 220 is formed from Ga-polarized GaN.

[0061] In the case of a Ga polar GaN regrowth junction, an overhang 222 can be provided to ensure that a 2DEG channel 210 exists adjacent to the embedded n+GaN. The overhang 222 may increase the charge concentration of the 2DEG channel 210 in the connection region.

[0062] The Ga-polar transistor 200 may not function as well as the example using N-polar GaN. This is because, unless the n+GaN contact 220 is embedded, the n+GaN contact 220 does not contribute significantly to the conductivity of the connection region. While the n+GaN contact 220 improves the conductivity of 2DEG within the channel, the improvement in conductivity is not as significant as in the N-polar GaN structure.

[0063] Figure 14 is a cross-sectional view of transistor 200 in an example where the n+GaN contact 220 penetrates the barrier layer 208 and extends to the channel layer 206. In this example, transistor 200 further includes an optional ohmic metal 224 on top of the n+GaN contact 220 in the connection region. In this case, the 2DEG channel 210 is divided, but resistance losses can be reduced by using sufficiently low-resistance n+GaN. The n+GaN contact 220 includes an overhang 226 extending toward the first gate 216 and the second gate 218.

[0064] Figure 15 is a flowchart illustrating an example of a method 300 for manufacturing a dual-gate HEMT (e.g., transistor 100 shown in Figures 1 to 12) having n+GaN contacts.

[0065] Method 300 includes preparing a substrate (302). The substrate may be, for example, a sapphire wafer or a silicon carbide substrate. The substrate is cleaned in preparation for epitaxial growth.

[0066] Method 300 includes growing a buffer layer (304). A thin buffer layer is grown on a substrate. This is, for example, to reduce lattice mismatch between the substrate and the GaN layer. This layer is usually made of AlGaN or GaN and is grown, for example, by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). In some regions, impurities such as iron or carbon may be doped to provide insulation, and Si or other electron-donating impurities may be doped to balance the charge of other parts of the structure.

[0067] Method 300 includes growing a back barrier layer (306). Growing a back barrier layer on a buffer layer can, for example, prevent electron leakage and improve the breakdown voltage of the device. This layer may be made of, for example, AlGaN and can be grown by, for example, MOCVD or MBE. Part of the thickness of this layer may be doped with Si or other impurities.

[0068] Method 300 includes growing a channel layer (308). The GaN channel layer is grown on top of the back barrier layer. The channel layer can be grown by, for example, MOCVD or MBE.

[0069] Method 300 includes forming an n+GaN contact in the connection region between a first gate and a second gate (310). The n+GaN contact may be formed, for example, on the surface of the channel layer, or from within an etched recess in the channel layer.

[0070] Method 300 includes forming source contacts, drain contacts, and first and second gate contacts (312). The n+ regions of the source and drain can be formed simultaneously with the n+GaN contacts in the connection region. Metal contacts are deposited to form the source and drain electrodes. These contacts are typically formed from a combination of metals such as Ti, Al, Ni, and Au, and can be patterned using photolithography and lift-off or etching. To form the gate contacts, a metal layer (e.g., Ti, Cr, Ru, Pt, or Pd) can be deposited on top of a thin insulating layer, for example. The channel region where the gate is deposited can be exposed using photolithography and / or etching.

[0071] In some examples, method 300 includes forming one or more etching stop layers. The etching stop layers may be used, for example, to define the recess depth of the gate contact and / or access region within the channel layer.

[0072] Method 300 includes testing and packaging the transistor (314). The completed device is tested to ensure that it meets the desired specifications regarding electrical performance. Once testing is complete, the device is packaged for use in a specific application.

[0073] Various semiconductor devices and methods for forming semiconductor devices have been described above. However, it should be understood that these are presented for illustrative purposes only and do not limit the present invention. Where it is shown that certain events occur in a specific order in the methods and steps described above, those skilled in the art will understand that the order of the specific steps can be changed, and that such changes will follow various modifications of this disclosure. Various embodiments have been specifically shown and described, and it will be understood that various modifications are possible in their form and details. Therefore, other embodiments are also within the scope of the following claims.

Claims

1. It is a semiconductor device, III-N back barrier layer and; The III-N channel layer on the III-N back barrier layer and; The 2DEG channel in the aforementioned III-N channel layer and; The source contact coupled to the III-N channel layer; A drain contact coupled to the III-N channel layer and spaced apart from the source contact along the length of the semiconductor device; Between the source contact and the drain contact, a first gate contact and a second gate contact coupled to the III-N channel layer; In the connection region between the first gate contact and the second gate contact, an n+GaN contact coupled to the III-N channel layer and Semiconductor devices, including those mentioned above.

2. The semiconductor device according to claim 1, wherein one or more of the n+GaN contact, the III-N channel layer, and the III-N back barrier layer include N-polarity GaN.

3. The semiconductor device according to claim 1, wherein the connection region includes an ohmic metal on the n+GaN contact.

4. The semiconductor device according to claim 1, wherein the first gate contact and the second gate contact are embedded to different depths in the III-N channel layer.

5. The semiconductor device according to claim 1, wherein the first gate contact is embedded to a first depth, and the second gate contact is embedded to a second depth, and the first depth is greater than the second depth.

6. The semiconductor device according to claim 1, wherein the length of the second gate contact is longer than the length of the first gate contact.

7. The semiconductor device according to claim 5, wherein the first access region between the source contact and the n+GaN contact is recessed to the depth of the first access region, and the second access region between the drain contact and the n+GaN contact is recessed to the depth of the second access region, and the depth of the first access region is greater than the depth of the second access region.

8. The semiconductor device according to claim 1, comprising one or more etching stop layers.

9. The semiconductor device according to claim 1, comprising first and second etching stop layers, wherein the first gate contact is embedded up to the first etching stop layer and the second gate contact is embedded up to the second etching stop layer.

10. The semiconductor device according to claim 1, comprising a first etching stop layer, wherein the first gate contact is embedded through the etching stop layer.

11. The semiconductor device according to claim 1, comprising a first etching stop layer, wherein a first access region between the source contact and the n+GaN contact is recessed to the first etching stop layer, and the second gate is recessed to the etching stop layer.

12. The semiconductor device according to claim 1, wherein the n+GaN contact extends from the etched region of the III-N channel.

13. The semiconductor device according to claim 1, wherein the n+GaN contact extends from the surface of the III-N channel.

14. The semiconductor device according to claim 1, wherein the first gate contact has a first gate width, and the second gate contact has a second gate width, the second gate width being wider than the first gate width.

15. The semiconductor device according to claim 1, wherein the first gate contact has a plurality of nonconductive regions along the width of the first gate contact, and the nonconductive regions are arranged alternately with the plurality of conductive regions.

16. It is a semiconductor device, III-N channel layer and; The III-N barrier layer on the III-N channel layer and; The 2DEG channel in the aforementioned III-N channel layer and; The source contact coupled to the III-N channel layer; A drain contact coupled to the III-N channel layer and spaced apart from the source contact along the width of the semiconductor device; Between the source contact and the drain contact, a first gate contact located above the III-N barrier layer and a second gate contact located above the III-N barrier layer; In the connection region between the first gate contact and the second gate contact, an n+GaN contact coupled to the III-N barrier layer, the n+GaN contact containing Ga polarity GaN and Semiconductor devices, including those mentioned above.

17. The semiconductor device according to claim 16, wherein one or both of the source contact and the drain contact include an overhang extending onto the surface of the III-N barrier layer.

18. The semiconductor device according to claim 16, wherein the n+GaN contact extends through the III-N barrier layer into the III-N channel layer.

19. The semiconductor device according to claim 18, wherein the connection region includes an ohmic metal on the n+GaN contact.

20. A method for manufacturing semiconductor devices, A III-N channel layer is formed on top of the III-N back barrier layer, thereby inducing a 2DEG channel in the III-N channel layer. Source and drain contacts are formed coupled to the III-N channel layer, and the source and drain contacts are spaced apart along the length of the semiconductor device. An n+GaN contact coupled to the III-N channel layer is formed in the connection region between the first gate contact and the second gate contact. First and second gate contacts are formed coupled to the III-N channel layer, and the first and second gate contacts are positioned between the source contact and the drain contact. Methods that include...

Images