3D DRAM with trimming without scaling

Abstract

Embodiments of this technology may include semiconductor processing methods and systems. The method and system may include providing a substrate to a processing area of ​​a semiconductor processing chamber, the substrate comprising one or more alternating pairs of a semiconductor material layer and a sacrificial material layer. The method includes forming one or more vertically extending features through one or more alternating pairs of semiconductor material layers and sacrificial material layers, and forming one or more sidewalls having alternating exposed sides of semiconductor material and sacrificial material. The method includes forming a protective material layer on the exposed side edge of the semiconductor material layer. The method includes laterally recessing at least a portion of the sacrificial material layer from one or more vertically extending features, and trimming portions of the semiconductor material layer adjacent to one or more vertically extending features.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Patent Application No. 63 / 588,931, filed on October 9, 2023, entitled "3D DRAM WITH ENLARGE - LESS TRIM", which is hereby incorporated by reference in its entirety.

[0002]

[0002] This technology relates to semiconductor systems and processes. More specifically, this technology relates to three - dimensional (3D) dynamic random access memory (DRAM) devices (3D DRAM), and methods of forming such devices.

Background Art

[0003]

[0003] Integrated circuits are made possible by processes that create layers of materials patterned complexly on a substrate surface. To create patterned materials on a substrate, a controlled method of forming and removing exposed materials is required. Material properties can affect how a device operates and also how films are removed relative to each other. During formation and removal, materials can be affected by unintentional removal, and as a result, the space within the device can be wasted. Such wasted areas within the device become more of a problem as the device continues to shrink.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used in the manufacture of high - quality devices and structures. This technology addresses these and other needs.

Summary of the Invention

[0005]

[0005] This technology generally covers semiconductor devices and methods for forming such devices. The method includes providing a substrate to a processing area of ​​a semiconductor processing chamber, the substrate comprising one or more alternating pairs of semiconductor material layers and sacrificial material layers. The method includes forming one or more vertically extending features through one or more alternating pairs of semiconductor material layers and sacrificial material layers. The method includes forming one or more sidewalls having alternating exposed edges of semiconductor material layers and sacrificial material layers. The method includes forming a protective material layer on the exposed edges of the semiconductor material layers. The method includes laterally recessing at least a portion of the sacrificial material layer from one or more vertically extending features. The method includes trimming a portion of the semiconductor material layer adjacent to one or more vertically extending features.

[0006]

[0006] In embodiments, the method includes cases where the protective material layer is formed by selective oxidation or nitridation of the side edge where the semiconductor material is exposed. In further embodiments, the method includes locations where the sacrificial material is laterally recessed before forming the protective material layer. Further embodiments, the method also includes filling the laterally recessed portions of the sacrificial material with dielectric material. Additionally or alternatively, the method includes removing the dielectric material before trimming. In more embodiments, the protective material layer is formed by directional deposition on the side edge where the semiconductor material is exposed. Further embodiments, the thickness of the protective material layer is from about 5 Å to about 500 Å. In more embodiments, the semiconductor material layer is optionally doped silicon material and the sacrificial material layer includes silicon germanium. In embodiments, one or more vertically extending features have a first width before trimming the semiconductor material layer and a second width after trimming the semiconductor material layer, the second width being about 10% or less greater than the first width. In further embodiments, the semiconductor material layer has a thickness about 400% or more greater than the thickness of the sacrificial material layer. In one embodiment, the method includes trimming the semiconductor material layer and then removing the protective material layer.

[0007]

[0007] The technology also generally covers methods for processing semiconductors. The method includes providing a substrate to a processing area of ​​a semiconductor processing chamber, the substrate comprising alternating pairs of silicon-containing material and silicon- and germanium-containing material. The method includes etching one or more access openings through the alternating pairs of silicon-containing material and silicon- and germanium-containing material to expose the side edges of the alternating pairs of silicon-containing material and silicon- and germanium-containing material. The method includes cases where the etching forms one or more sidewalls having alternating side edges of silicon-containing material and silicon- and germanium-containing material. The method includes forming a protective material layer on the side edges where the silicon-containing material is exposed. The method includes laterally recessing at least a portion of the silicon- and germanium-containing material from one or more access openings. The method includes trimming a portion of the silicon-containing material adjacent to the access opening.

[0008]

[0008] In the embodiment, the substrate contains more than 20 alternating pairs of silicon-containing material and silicon and germanium-containing material. In more embodiments, the thickness of the silicon and germanium-containing material is about 30 nm or less. Furthermore, in the embodiment, the silicon-containing material has a thickness about 400% or more greater than the thickness of the silicon and germanium-containing material. Additionally or alternatively, in the embodiment, the method includes etching one or more vertically extending features at the ends of the alternating pairs of silicon-containing material and silicon and germanium-containing material facing the exposed side edge, exposing the outer ends of the alternating pairs of silicon-containing material and silicon and germanium-containing material, and the etching removes at least a portion of the patterning stack and forms one or more outer sidewalls having alternating outer ends of silicon-containing material and silicon and germanium-containing material. The method includes forming a second protective layer on the exposed outer ends of the silicon-containing material. In embodiments, the method includes laterally recessing at least a portion of the silicon and germanium-containing material from one or more vertically extending features. Furthermore, in embodiments, the method includes trimming a portion of the semiconductor material layer adjacent to the access opening.

[0009]

[0009] In embodiments, the method includes etching one or more vertically extending features at the ends of alternating pairs of silicon-containing material layers and silicon- and germanium-containing material layers facing the exposed side edges to expose the outer ends of the alternating pairs of silicon-containing material layers and silicon- and germanium-containing material layers. In more embodiments, the method includes removing at least a portion of the patterning stack by etching and forming one or more outer sidewalls having alternating outer ends of the alternating pairs of silicon-containing material layers and silicon- and germanium-containing material layers. In embodiments, the method includes forming a second protective layer on the exposed outer ends of the silicon-containing material.

[0010]

[0010] The technology also generally covers methods for forming three-dimensional dynamic random access memory (3D DRAM) devices. The method includes providing a substrate to a processing area of ​​a semiconductor processing chamber, the substrate comprising one or more alternating pairs of silicon-containing material layers and silicon and germanium-containing material layers. The method includes forming one or more access openings through one or more alternating pairs of silicon-containing material layers and silicon and germanium-containing material layers, and forming one or more sidewalls having alternating exposed side edges of silicon-containing material layers and silicon and germanium-containing material layers. The method includes forming a protective material layer on the exposed side edges of the silicon-containing material layers. The method includes laterally recessing at least a portion of the silicon and germanium-containing material layers from one or more access openings. The method includes trimming a portion of the silicon-containing material layers adjacent to one or more access openings.

[0011]

[0011] Such techniques may offer numerous advantages over conventional systems and methods for forming 3D-DRAM devices. For example, by forming the devices described herein, expansion of the access opening may be little to no need to etch the recesses within the access opening, even if the access opening defines a high aspect ratio structure. Thus, the devices and methods described herein may provide increased recess dimensions, such as increased channel dimensions in the case of 3D DRAM. Embodiments of this technique, along with many of its advantages and features, will be described in more detail below in conjunction with the accompanying figures.

[0012]

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1A] The following are top views of exemplary processing systems according to several embodiments of this technology. [Figure 1B]A schematic cross-sectional view of an exemplary processing system according to several embodiments of this technology is shown. [Figure 2] The steps of an exemplary method for semiconductor processing according to several embodiments of this technology are shown. [Figure 3A-3H] The following are cross-sectional views of exemplary semiconductor structures according to several embodiments of this technology. [Modes for carrying out the invention]

[0014]

[0017] Some drawings are included as schematic diagrams. It should be understood that drawings are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic depictions, and may include exaggerated material for illustrative purposes.

[0015]

[0018] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0016]

[0019] In dynamic random access memory (DRAM) devices such as 3D DRAM, alternating layers of material may be formed on the substrate. These alternating layers may include alternating pairs of silicon-containing material and silicon- and germanium-containing material. As the number of layers increases, the difficulty of forming features also increases, at least in part, due to the high aspect ratio of the device. For example, during 3D DRAM processing, a vertically extending access opening may be formed, penetrating two or more layers of material. Subsequent processing may require the removal of material extending horizontally away from the access opening. Due to a lack of line of sight to the access opening, such horizontally extending recesses, referred to herein as “blind recesses,” are difficult to trim properly, especially as the size of the device continues to increase while a larger aspect ratio within the formed features is also desired. While 3D DRAM is used as an example of such blind recesses, it is clear that such challenges may be equally applicable to a variety of devices having one or more blind recesses formed from the main channel.

[0017]

[0020] Initial efforts to improve 3D DRAM devices involved increasing the size of the silicon-germanium layer compared to the silicon layer. In this way, all or part of the SiGe could be etched while retaining silicon. Thus, the controlled silicon layer and etched portion could be controlled during layer deposition. However, such structures were unsuitable for high aspect ratio structures because only a certain percentage of SiGe could exist without causing mechanical failure. Efforts were made to reduce the germanium concentration without reducing the thickness of the SiGe layer, but such attempts failed to achieve the germanium concentration required for selective etching compared to silicon. Attempts were made to utilize thinner SiGe layers compared to silicon, coupled with silicon recess trimming after SiGe removal. However, such efforts resulted in recesses in the access openings and, unfavorably, a reduction in the semiconductor channel length. In existing methods, the width of the access opening may be more than twice the width to trim an acceptable channel. Such phenomena either require an access opening that is too narrow to properly trim blind recesses, or require unacceptable dimensional losses, especially as the device continues to shrink.

[0018]

[0021] Remarkably, this technique has found that by carefully controlling the deposition and etching operations, excellent trimming can be achieved in one or more blind recesses without increasing the width of the access area (e.g., sidewalls). That is, controlled trimming of sacrificial material can be achieved by carefully depositing one or more protective films, while little or no removal of non-sacrificial material is observed. Therefore, devices formed according to this technique can exhibit excellent dimensional control, such as in blind recesses, without sacrificing the quality of the trimmed section.

[0019]

[0022] After describing a general configuration of a chamber configured to perform operations according to embodiments of this technology in which plasma processing may be carried out, specific methodologies and component configurations may be described. It should be understood that this technology is not intended to be limited to the specific films and processes described, as the described technology may be used to improve many film formation processes and may be applicable to various semiconductor processing chambers and processes.

[0020]

[0023] Figure 1A shows a top view of one embodiment of a processing system 10 comprising a deposition chamber, a processing chamber, an etching chamber, a baking chamber, and a curing chamber, according to an embodiment. In this figure, a pair of front-opening unified pods 12 supply substrates of various sizes. These substrates are received by a robotic arm 14, placed in a low-pressure holding area 16, and then placed in one of the semiconductor processing chambers 18a-f arranged in tandem sections 19a-c. A second robotic arm 11 can be used to transport the substrate wafers from the holding area 16 to the semiconductor processing chambers 18a-f and in the reverse direction. Each semiconductor processing chamber 18a-f can be equipped to perform several substrate processing steps, including the formation of stacks of semiconductor materials as described herein, in addition to other substrate processing, including plasma chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and plasma processing, annealing, ashing.

[0021]

[0024] The semiconductor processing chambers 18a-f may include one or more system components for depositing, plasma processing, curing, and / or etching dielectric films or other films on a substrate. In one configuration, a second pair of semiconductor processing chambers (e.g., 18c-d and 18e-f) may be used to deposit dielectric material on a substrate, and a third pair of semiconductor processing chambers (e.g., 18a-b) may be used to process the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 18a-f) may be configured to deposit and process stacks of alternating dielectric films on a substrate. One or more of the described processes may be performed in a chamber separated from the manufacturing system as shown in various embodiments. It will be understood that system 10 envisions further configurations of deposition chambers, processing chambers, etching chambers, annealing chambers, and curing chambers for dielectric films.

[0022]

[0025] FIG. 1B shows a cross-sectional view of an exemplary semiconductor processing chamber 100 according to some embodiments of the present technology. This figure can show an overview of a system incorporating one or more aspects of the present technology, and / or it can be specifically configured to perform one or more operations according to embodiments of the present technology. Further details of the chamber 100 or the method implemented may be further described below. Chamber 100 can be utilized to form a tensile nitride film according to some embodiments of the present technology, but it should be understood that the method can be similarly performed in any chamber where film formation can occur. The semiconductor processing chamber 100 can include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and surrounding the substrate support 104 within the processing space 120. The substrate 103 can be provided to the processing space 120 through an opening 126 that can conventionally be sealed for processing using a slit valve or door. The substrate 103 can be placed on the surface 105 of the substrate support during processing. The substrate support 104 can be rotatable along an axis 147 where the shaft 144 of the substrate support 104 can be located, as indicated by arrow 145. Alternatively, the substrate support 104 may be lifted to rotate as needed during the deposition process.

[0023]

[0026] A plasma profile modulator 111 may be located within the semiconductor processing chamber 100 to control the plasma distribution across the substrate 103 placed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108, which may be located adjacent to the chamber body 102, separating the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106, or it may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member, and may be a ring electrode. The first electrode 108 may be a continuous loop around the outer circumference of the semiconductor processing chamber 100 surrounding the processing space 120, or it may be discontinuous at positions selected as desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or a flat plate electrode, such as a secondary gas distributor.

[0024]

[0027] One or more isolators 110a, 110b, which may be dielectric materials such as ceramics or metal oxides, for example, aluminum oxide and / or aluminum nitride, may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define an opening 118 for distributing the process precursor into the processing space 120. The gas distributor 112 may be connected to a first power supply 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power supply that can be connected to the semiconductor processing chamber. In some embodiments, the first power supply 142 may be an RF power supply.

[0025]

[0028] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. Also, the gas distributor 112 may be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive and the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered by a first power source 142 as shown in FIG. 1B, or in some embodiments, the gas distributor 112 may be connected to ground.

[0026]

[0029] The first electrode 108 may be connected to a first tuning circuit 128 that can control the ground path of the semiconductor processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be a variable capacitor or other circuit element, or may include these. The first tuning circuit 128 may be or include one or more inductors 132. The first tuning circuit 128 can be any circuit that enables a variable or controllable impedance under plasma conditions present in the processing space 120 during processing. In some of the illustrated embodiments, the first tuning circuit 128 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The leg of the first circuit may include a first inductor 132A. The leg of the second circuit may include a second inductor 132B connected in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a connection point that connects both the leg of the first circuit and the leg of the second circuit to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be connected to the first electronic controller 134. Thereby, a certain degree of closed-loop control of the plasma conditions inside the processing space 120 can be obtained.

[0027]

[0030] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be embedded in the substrate support 104 or connected to the surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed configuration of conductive elements. The second electrode 122 may also be a tuning electrode and may be connected to a second tuning circuit 136 by a conduit 146, such as a cable having a selected resistance, such as 50 ohms, located within the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be connected to the second electronic controller 140 to provide further control to the plasma conditions in the processing space 120.

[0028]

[0031] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be connected to the substrate support 104. The third electrode may be connected to a second power supply 150 via a filter 148, which may be an impedance matching circuit. The second power supply 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power supplies. In some embodiments, the second power supply 150 may be RF bias power.

[0029]

[0032] The lid assembly 106 and substrate support 104 in Figure 1B can be used with any semiconductor processing chamber for plasma processing or heat processing. During operation, the semiconductor processing chamber 100 can perform real-time control of the plasma conditions in the processing space 120. The substrate 103 can be placed on the substrate support 104, and a process gas can flow through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can exit the semiconductor processing chamber 100 through the outlet 152. Power may be connected to the gas distributor 112 to form a plasma in the processing space 120. In some embodiments, the substrate may be electrically biased using a third electrode 124.

[0030]

[0033] When the plasma is excited in the processing space 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. Subsequently, electronic controllers 134 and 140 may be used to adjust the flow characteristics of the ground path, represented by two tuning circuits 128 and 136. Setpoints may be transmitted to the first tuning circuit 128 and the second tuning circuit 136 to provide separate control over the deposition rate and the uniformity of plasma density from center to edge. In embodiments where both electronic controllers are variable capacitors, electronic sensors may independently adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0031]

[0034] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using their respective electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each variable capacitor, and the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range depends on the frequency and voltage characteristics of the plasma and may have the minimum capacitance range of each variable capacitor. Therefore, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 may be high. As a result, a plasma shape is created with minimum aerial or lateral coverage above the substrate support. As the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the plasma's aerial coverage increases to its maximum value, efficiently covering the entire working area of ​​the substrate support 104. If the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may contract away from the chamber wall, reducing the air coverage of the substrate support. The second electronic controller 140 has a similar effect, and since the capacitance of the second electronic controller 140 can be changed, the air coverage of the plasma on the substrate support can be increased or decreased.

[0032]

[0035] Electronic sensors 130 and 138 may be used to tune their respective circuits 128 and 136 in a closed loop. Depending on the type of sensor used, a setpoint for current or voltage may be attached to each sensor, and the sensors may be provided with control software that determines the adjustment to the corresponding electronic controllers 134 and 140 and minimizes deviation from the setpoint. As a result, the plasma shape can be selected and dynamically controlled during processing. The foregoing description is based on electronic controllers 134 and 140, which may be variable capacitors, but it should be understood that any electronic component with adjustable characteristics can be used to provide tuning circuits 128 and 136 with adjustable impedance.

[0033]

[0036] Figure 2 shows an exemplary step of Method 200 for forming a semiconductor structure according to an embodiment of the present technology. Method 200 may include one or more steps, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed before the described steps, prior to the commencement of the Method. For example, the Method may commence after several layers have been deposited, such as to manufacture a 3D DRAM structure. However, as described above, the figure shows only one exemplary process in which the process according to an embodiment of the present technology may be used, and it should be understood that the description herein is not intended to limit the Technology to this process or structure alone. Some or all of the steps may be performed in a chamber or system tool, as described above, or in different chambers on the same system tool that may include the chamber in which the steps of Method 200 may be performed.

[0034]

[0037] Method 200 may include additional steps before commencing the enumerated steps. For example, additional processing steps may include forming a structure on the substrate, which may include both forming and removing material. The preprocessing steps may be performed in the chamber in which Method 200 may be performed, or processing may be performed in one or more other semiconductor processing chambers before supplying the substrate to the semiconductor processing chamber in which Method 200 may be performed. In any case, Method 200 may optionally include supplying the substrate to the processing area of ​​a semiconductor processing chamber, such as the semiconductor processing chamber 100 described above, or another chamber, which may include the components described above. The substrate may be a pedestal, such as a substrate support 104, and may be deposited on a substrate support, which may be present in the processing area of ​​a chamber, such as the processing space 120 described above. Method 200 describes the steps schematically shown in Figures 3A to 3H, which are illustrated in conjunction with the steps of Method 200. Figures 3A to 3H show only partial schematic diagrams, and it should be understood that the substrate may include any number of structural regions having the embodiments shown in the figures, as well as alternative structural embodiments from which the operation of this technology can still be benefited. Nevertheless, as shown in Figure 3A, the semiconductor structure 300 may have several layers of material deposited on the substrate 305. The semiconductor structure 300 may be formed from any number of materials, such as a base wafer or substrate made of silicon or a silicon-containing material, germanium, other substrate materials, and one or more materials that may be formed on the substrate during semiconductor processing.

[0035]

[0038] As shown in Figure 3A, the substrate 305 may be any number of materials (e.g., a base wafer or substrate made from silicon or a silicon-containing material, germanium, other substrate materials, and one or more materials that may be formed on the substrate during semiconductor processing). In embodiments, the substrate 305 may include a bulk substrate, an epitaxially grown substrate, and / or silicon on an insulating wafer. As used herein, the term “semiconductor substrate” refers to a substrate whose entirety is made of semiconductor material. A semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, a semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> ), may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 includes a semiconductor material, for example, silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 305 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials that can form substrates are described herein, any material that can function as a basis on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed is included in the spirit and scope of this disclosure.

[0036]

[0039] In embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron-donating element during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. As used herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers.

[0037]

[0040] In embodiments, one or more materials may be formed on the substrate 305 by pretreatment. For example, the substrate may, in embodiments, be pretreated with alternating pairs of a semiconductor material 310, which may be a silicon-containing material, and a sacrificial material 315, which may be a silicon and germanium-containing material, which may be applicable to the formation of a device 300 (e.g., a 3D DRAM structure). As shown in Figure 4A, the film stack may be deposited on the substrate 305. The film stack may include multiple unit stacks (e.g., three unit stacks in the illustrated embodiment) that are used partially sacrificially to form a 3D DRAM cell. As will become clear, this method forms three layers of a 3D DRAM cell. In other examples, it may be possible to form additional layers of a 3D DRAM cell by repeating the unit stacks of the film stack. Alternatively, it may be possible to form one layer of a 3D DRAM cell by using one instance of a unit stack within the film stack.

[0038]

[0041] Nevertheless, in the embodiment, the alternating pairs of silicon-containing material 310 and silicon and germanium-containing material 315 formed on the substrate may include more than 10 alternating pairs, for example more than 20 alternating pairs, for example more than 30 alternating pairs, for example more than 32 alternating pairs, for example more than 34 alternating pairs, for example more than 36 alternating pairs, for example more than 38 alternating pairs, more than 40 pairs, more than 44 alternating pairs, more than 48 alternating pairs, more than 50 alternating pairs, more than 52 alternating pairs, more than 56 alternating pairs, more than 60 alternating pairs, more than 64 alternating pairs, more than 68 alternating pairs, more than 72 alternating pairs, or any range or value between these.

[0039]

[0042] The thickness of each pair of alternating silicon and germanium-containing material 315 and silicon-containing material 31 may be about 30 nm or more. In this way, a suitable space for accommodating the insulating space described later is provided. Therefore, in the embodiment, the thickness of each pair may be about 35 nm or more, for example, about 40 nm or more, about 45 nm or more, about 50 nm or more, about 55 nm or more, about 60 nm or more, about 65 nm or more, about 70 nm or more, about 75 nm or more, about 80 nm or more, about 85 nm or more, about 90 nm or more, about 95 nm or more, about 10 nm or more, or a range or value in between these.

[0040]

[0043] However, unlike conventional cells, this technology can result in an increase in the semiconductor material layer relative to the sacrificial material layer ratio. That is, the processes and methods described herein can provide deposition and etching independent of the selectivity of the sacrificial layer alone. Therefore, the semiconductor structure 300 produced by this technology may exhibit improved mechanical strength and stability because the amount of weak sacrificial layer may be reduced while maintaining the overall pair thickness necessary for forming a robust insulating space.

[0041]

[0044] In this embodiment, the thickness of the semiconductor material may be about 10% or more than the thickness of the sacrificial material layer, for example, about 20% or more, for example, about 30% or more, for example, about 40% or more, for example, about 50% or more, for example, about 60% or more, for example, about 70% or more, for example, about 80% or more, for example, about 90% or more, for example, about 100% or more, for example, about 125% or more, for example, about 150% or more, for example, about 175% or more, for example, about 200% or more, for example, about 250% or more, for example, about 300% or more, for example, about 350% or more, for example, about 400% or more, for example, about 450% or more, for example, about 500% or more, for example, about 550% or more, for example, about 600% or more, for example, about 650% or more, for example, about 700% or more, or any range or value in between these.

[0042]

[0045] Because the thickness of the semiconductor material is increased, at least partially, the doping content of the sacrificial layer may not be particularly limited. For example, in embodiments where the sacrificial material is SiGe, the germanium content may be in the range of about 1% to about 50% by weight of the layer, for example, less than or equal to about 45% by weight, less than or equal to about 40% by weight, less than or equal to about 35%, less than or equal to about 30%, less than or equal to about 25%, less than or equal to about 20%, less than or equal to about 15%, less than or equal to about 10%, less than or equal to about 5%, or for example, more than or equal to about 2.5%, more than or equal to about 5%, more than or equal to about 7.5%, more than or equal to about 10%, more than or equal to about 15%, more than or equal to about 20%, more than or equal to about 25%, more than or equal to about 30%, more than or equal to about 35%, more than or equal to about 40%, more than or equal to about 45%, or any range or value in between. For example, a higher percentage of germanium may be present without adversely affecting the mechanical stability of the structure by at least partially reducing the thickness of the sacrificial material layer.

[0043]

[0046] As shown in Figure 3A, regardless of the ratio of the semiconductor layer 310 to the sacrificial layer 315, the semiconductor device 300 may have access openings 325 formed therein. Although only one access opening 325 is shown, it is clear that two or more access openings may be provided depending on the device and the orientation of the device. Nevertheless, the access openings 325 may be formed through one or more cells of the semiconductor device 300 and provide access to each layer of the cell. In embodiments, the access openings 325 may be formed by any method known in the art. For example, in embodiments, one or more access openings 325 may be patterned using a mask 302 and then etched. As shown, the etching may be any etching suitable for penetrating both the semiconductor material 310 and the sacrificial material 315.

[0044]

[0047] As shown in Figure 3B, the optional step 205 may include laterally removing a portion of the sacrificial material 315. Removing a portion of the sacrificial material may allow for one or more additional deposition processes to form the protective layer 330 (Figure 3C). Depending on the semiconductor material and the selected sacrificial material, one or more removal processes may be possible in step 205, but in some embodiments, the etching process is a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process). In embodiments, the extent to which the sacrificial material 315 is laterally removed is controlled by the duration of the etching process. For example, in embodiments, the sacrificial material 315 may be laterally removed based on the desired length of the channel and isolation recess. In some embodiments, the selective wet etching process may include a hydrogen fluoride (HF), a fluoride (F2), or an NH4OH etchant.

[0045]

[0048] In embodiments, the initial removal of the sacrificial material in step 205 may be desirable, if utilized, to at least partially fill the recess 335 formed in the optional step 210, as will be described in more detail below. For example, one or more non-line-of-sight deposition methods, such as atomic layer deposition (ALD) and / or chemical vapor deposition (CVD), can be used to fill the recess 335 with dielectric material. In embodiments, suitable dielectric materials may include silicon oxide, silicon nitride, combinations thereof, and other dielectrics known in the art.

[0046]

[0049] By utilizing the optional step 210, the protective layer 330 can be formed in step 215 by oxidizing the sidewall of the access opening 325. That is, by utilizing the optional filling step 210, the protective layer 330 can be prevented from forming within the recess 335 and thus can be formed on the vertically extending sidewall 340 of the access opening 325. Furthermore, by utilizing the optional filling step 210, sidewall oxidation or nitriding known in the art can be used to form the protective layer 330 without requiring extensive processing. Moreover, the dielectric material filled within the recess 335 can be easily removed after the protective layer 330 has been formed by one or more selective etching processes, allowing for further processing without damaging the protective layer 330. Nevertheless, in embodiments, it may be desirable to perform one or more cleaning processes, such as Siconi® cleaning, to remove surface oxides present before the formation of the protective layer 330.

[0047]

[0050] However, as described above, in the embodiment, the optional filling step 210 may not be necessary. Instead, directional deposition may be used to deposit the protective layer 330 on the vertically extending sidewall 340 of the access opening 325. Various deposition methods may be used as are known in the art, but in the embodiment, the directional deposition process may include physical vapor deposition (PVD), ion beam deposition (IBD), electron beam (EB) deposition, electron beam ion-assisted deposition (EB-IAD), or a combination thereof. Nevertheless, the protective layer 330 may be formed from one or more materials, such as one or more of the dielectric materials described above. That is, by utilizing one or more directional deposition processes in operation 215, and by selecting one or more line-of-sight deposition methods, the protective layer 330 may be formed mainly on the sidewall 340 of the access opening 325. Therefore, little or no protective layer 330 may be formed within the recess 335.

[0048]

[0051] Nevertheless, as described above, in the embodiments, the protective layer 330 can be formed in step 215 without removing any portion of the sacrificial material in step 205 or without filling the recesses formed in step 210. For example, in embodiments where the sacrificial material is less susceptible to nitriding, the access opening 325 may be subjected to nitriding in step 215 to form a nitrogen-containing protective layer 330. For example, in this example, the protective layer may contain silicon nitride. However, it should be understood that, as long as the dielectric is formed on the semiconductor material 310 but not on the sacrificial material 315, one or more additional dielectric formation processes may be utilized based on the materials selected for the sacrificial material and the semiconductor material.

[0049]

[0052] Regardless of the method used to form the protective layer 330, the method may be carried out for a sufficient amount of time to form a protective layer having the following thicknesses: approximately 5 Å or more, e.g., approximately 6 Å or more, e.g., approximately 7 Å or more, e.g., approximately 8 Å or more, e.g., approximately 9 Å or more, e.g., approximately 10 Å or more, e.g., approximately 15 Å or more, e.g., approximately 20 Å or more, e.g., approximately 30 Å or more, e.g., approximately 40 Å or more, e.g., 50 Å or more, e.g., approximately 75 Å or more, e.g., approximately 100 Å or more, e.g., approximately 125 Å or more, e.g., approximately 150 Å or more, e.g., approximately 175 Å or more, e.g., approximately 200 Å or more, e.g., approximately 250 Å or more, e.g., approximately 300 Å or more, e.g., approximately 350 Å or more, e.g., approximately 400 Å or more, e.g., approximately 450 Å or more, e.g., approximately 500 Å or more, or any range or value in between. In this way, the protective layer 330 may have a thickness sufficient to protect the side wall 340 of the access opening 325 without interfering with subsequent operation.

[0050]

[0053] Therefore, regardless of whether a portion of the sacrificial material is removed in step 205 or the recess formed in step 210 is filled, a protective layer 330 may be formed on the sidewall 340 of the access opening 325 (e.g., a vertically extending sidewall), as shown in Figure 3C. If not completed in step 205 or filled in step 210, step 220 may include laterally removing sacrificial material from at least a portion of the recess 335 or removing the dielectric material filled in step 210. In embodiments, the lateral removal may include any one or more of the embodiments described above with respect to the optional step 205.

[0051]

[0054] In this way, as shown in Figure 3D, an etching process specific to the semiconductor material 310 can be utilized in the trimming step 225. That is, by utilizing the protective layer 330 described herein, an etching process specific to the semiconductor material can be utilized without reducing the width w of the access opening 325. Furthermore, as described above, surprisingly, such a process is also suitable for a relatively thin sacrificial material layer 315. For example, unlike conventional systems where only the sacrificial material is removed to form a channel (e.g., the thickness of the sacrificial material layer determined the maximum thickness of the formed isolation recess 350), the semiconductor material is etched during trimming.

[0052]

[0055] Furthermore, remarkably, the protective layer 330 protects the vertically extending sidewalls 340 of the access opening 325 (e.g., the lateral edges of the formed channel) without hindering etching from each recess 335. Thus, the protective layer 330 advantageously allows etching from within the recess 335 formed by removing sacrificial material, while preventing the removal of material from the side edges. In this way, the width w of the access opening 325 is maintained, while the channel 345 is thinned, forming a robust isolation recess 350.

[0053]

[0056] For example, unlike conventional processes and devices, the width w of the access opening can generally retain the initially etched width. Therefore, in embodiments, the width of the access opening after the trimming step 225 may be about 10% or less of the width of the access opening before trimming (e.g., the access opening formed by the masking and etching described above), for example, about 9% or less, about 8% or less, about 7% or less, about 6% or less, about 5% or less, about 4% or less, about 3% or less, about 2% or less, about 1% or less, or any range in between. As can be understood, in embodiments, some width may be lost for one or more cleaning or removal steps, but the width is largely maintained during trimming.

[0054]

[0057] Therefore, in embodiments, the method according to the present technology can provide excellent channel 345 and separation section 350 thickness while exhibiting improved mechanical stability and increased channel length. For example, the channel width c may be about 50 nm or less, e.g., about 45 nm or less, e.g., about 40 nm or less, e.g., about 35 nm or less, e.g., about 30 nm or less, e.g., about 25 nm or less, e.g., about 20 nm or less, or about 10 nm or more, e.g., about 12.5 nm or more, e.g., about 15 nm or more, e.g., about 17.5 nm or more, e.g., about 10 nm, or any range or value in between these.

[0055]

[0058] Furthermore, the separation width I may be approximately 40 nm or more, for example approximately 45 nm or more, for example approximately 50 nm or more, for example approximately 55 nm or more, for example approximately 60 nm or more, or approximately 100 nm or less, for example approximately 95 nm or less, for example approximately 90 nm or less, for example approximately 85 nm or less, for example approximately 80 nm or less, for example approximately 75 nm or less, for example approximately 70 nm or less, for example approximately 65 nm or less, for example approximately 60 nm, or any range or value in between these.

[0056]

[0059] Surprisingly, the width w of the access aperture may be less than 150 nm, for example, less than or equal to about 140 nm, for example less than or equal to about 135 nm, for example less than or equal to about 130 nm, for example less than or equal to about 125 nm, for example less than or equal to about 120 nm, for example less than or equal to about 115 nm, for example less than or equal to about 110 nm, for example less than or equal to about 105 nm, for example less than or equal to about 100 nm, for example less than or equal to about 95 nm, for example less than or equal to about 90 nm, or more than or equal to about 50 nm, for example more than or equal to about 55 nm, for example more than or equal to about 60 nm, for example more than or equal to about 70 nm, for example more than or equal to about 75 nm, for example more than or equal to about 80 nm, for example more than or equal to about 90 nm, for example more than or equal to about 95 nm, or any range or value in between these.

[0057]

[0060] As shown in Figure 3E, in operation 230, the protective layer 330 can be removed after the separation recess 350 has been trimmed to the desired size. The protective layer 330 can be removed by any suitable etching process, such as wet or dry etching. For example, if the protective layer 330 is silicon nitride, a thermal phosphoric acid etching process may be used to remove the protective layer 330.

[0058]

[0061] After removing the protective layer 330, the semiconductor device 300 can generally be re-entered into a standard processing flow. For example, in the embodiment, the gate oxide 402, diffusion barrier 404 (such as TiN in the embodiment), one or more gate metals 406, and one or more insulators 408 may be formed in the isolation recess 350 and in one or more insulating dielectric materials 410 formed within the access opening 325, as shown in Figure 3F.

[0059]

[0062] However, surprisingly, the methods described herein may also be applicable to forming transistors on the opposite side of the semiconductor device 300. Thus, in embodiments, one or more second access openings 425 may be formed on the outside 405 of the semiconductor device 300. Furthermore, a protective layer 430 may be formed along one or more sidewalls 440 of the one or more second access openings 425. Furthermore, in embodiments, according to any one or more of the methods described above, any remainder of the sacrificial material 315 may be removed from the recess.

[0060]

[0063] By utilizing the protective layer 430, which can be formed according to any one or more of the methods described above, the remaining portion of the isolation recess 350 is selectively etched as described above, and the recess 470 forms one or more transistor components, as shown in Figure 3G. Surprisingly, as described above, by utilizing the protective layer 430, the lateral edges of the channel 445 can be preserved while the transistor recess 470 is being trimmed (e.g., the trimming recess 335 remaining after the formation of the isolation recess 350). Therefore, the etching process on the capacitor side or transistor side of the semiconductor device 300 may result in little to no loss of channel length.

[0061]

[0064] Nevertheless, as shown in Figure 3H, the protective layer 430 may be removed using any one or more of the methods described above after the desired channel width and / or isolation recess width has been achieved. In embodiments, the thickness may be any one or more of the thicknesses described above with respect to the channel, recess, and access opening. After the protective layer 430 is removed, the semiconductor structure 300 can again enter a standard process flow to form the transistor components and the rest of the 3D DRAM capacitor components (in this example, one or more source / drain regions 480, patterning and filling of bit lines 482, formation of electrodes 484, etc.). However, although 3D DRAM has been used as an example as described herein, it should become clear that this method is suitable for forming one or more blind recesses in a variety of devices, including high aspect ratio devices.

[0062]

[0065] In embodiments, forming the protective layer 330 / 430 may include one or more plasma precursors to the semiconductor structure 300. In embodiments, the deposition precursor may include at least one nitrogen-containing precursor, at least one oxygen-containing precursor, at least one silicon-containing precursor, a combination thereof, and other dielectric precursors known in the art. The silicon-containing precursor may be silane and disilane, among other silicon-containing precursors useful for semiconductor processing, or may include them. The nitrogen-containing precursor may be ammonia (NH3) and a mixture of molecular nitrogen and hydrogen (N2+H2), among other nitrogen-containing precursors useful for semiconductor processing, or may include them. The deposition precursor may also include at least one carrier gas. Embodiments of the carrier gas may include molecular nitrogen (N2), helium, xenon, or argon, and may include other carrier gases useful for semiconductor processing. The oxygen-containing precursor may be any oxygen-containing material used or useful in semiconductor processing. For example, the oxygen-containing precursor may be or may include vapor (H2O), molecular oxygen (O2), ozone (O3), nitrous oxide (N2O), hydrogen peroxide (H2O2), oxygen-containing plasma, alcohol-based compounds, or alcohol-based plasma.

[0063]

[0066] Embodiments of Method 200 may further include, in step 215 and in an optional step 210, generating plasma emissions of a deposition precursor within the processing area of ​​a semiconductor processing chamber to form a protective layer. The deposition plasma can be generated by supplying plasma power to the deposition precursor flowing into the processing area. In some embodiments, the plasma power can be supplied by a radio frequency (RF) power supply electrically coupled to at least one electrode in the semiconductor processing chamber. In embodiments, the RF power supply can power at least one electrode, thereby creating an electric field in the processing area of ​​the semiconductor processing chamber that energizes the deposition precursor and forms a deposition plasma. The plasma power supplied to the deposition precursor may be about 60 watts or less, about 55 watts or less, about 50 watts or less, about 45 watts or less, about 40 watts or less, about 35 watts or less, about 30 watts or less, or less. The frequency of the RF power supplied to the deposition precursor may be 13.56 MHz in one non-limiting example. In some embodiments, the plasma power supplied to the deposition precursor may be supplied continuously, but in additional embodiments, the plasma power may be pulsed. In pulsed embodiments, the supplied RF plasma output is approximately 10 kHz or less and may have pulse frequencies of approximately 9 kHz or less, approximately 8 kHz or less, approximately 7 kHz or less, approximately 6 kHz or less, approximately 5 kHz or less, approximately 4 kHz or less, approximately 3 kHz or less, approximately 2 kHz or less, approximately 1 kHz or less, or less. In some pulsed embodiments, the off-period of the duty cycle of the plasma output may allow for greater diffusion of plasma emitters in the deposited silicon and nitrogen-containing material. The longer the diffusion time of plasma emitters, the more uniform the deposited material may be formed.

[0064]

[0067] In embodiments, the deposition of the protective layer within one or more access openings can be carried out at a deposition temperature that affects the deposition rate of the material. For example, the processing area of ​​a semiconductor processing chamber may be characterized by deposition temperatures of approximately 550°C or less, approximately 500°C or less, approximately 475°C or less, approximately 450°C or less, approximately 425°C or less, approximately 400°C or less, approximately 375°C or less, approximately 350°C or less, or approximately 300°C or less, or below. This technology can protect the thermal balance of the device by depositing at temperatures of approximately 500°C or less.

[0065]

[0068] The above description provides numerous details for illustrative purposes to facilitate understanding of various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0066]

[0069] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be considered to limit the scope of the Art. Moreover, while methods or processes may be described sequentially or stepwise, it should be understood that the actions may occur simultaneously or in a different order than described.

[0067]

[0070] Where a range of values ​​is provided, unless explicitly stated otherwise in the context, each intervening value between the upper and lower limits of that range is understood to be specifically disclosed down to the smallest unit of the lower limit. Any narrow range between any listed or unlisted intervening values ​​within the stated range, and any other listed or intervening values ​​within that stated range, are also included. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each range in which either or both limit values ​​are included in a narrower range, or neither is included in a narrower range, is further included in this art, provided that any limit values ​​are specifically excluded from the stated range. Where a stated range includes one or both limit values, ranges excluding either or both of these included limit values ​​are also included. When referring to measurable values ​​such as quantity or duration, “about” and / or “approximately” as used herein and in the appended claims includes variations of ±20%, ±10%, ±5%, or +0.1% from a given value, and such variations are appropriate in the context of the systems, devices, circuits, methods, and other implementations described herein. When referring to measurable values ​​such as quantity, time periods, or physical attributes (such as frequency), “substantially” as used herein and in the appended claims also includes variations of ±20%, ±10%, ±5%, or ±0.1% from a given value, as is appropriate in relation to the systems, devices, circuits, methods, and other implementations described herein.

[0068]

[0071] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless the context clearly indicates otherwise. Thus, for example, “a precursor” refers to multiple such precursors, and “a layer” refers to one or more layers and equivalents well known to those skilled in the art, and the same applies to other forms.

[0069]

[0072] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integers, components, or actions, but not to exclude the presence or addition of one or more other features, integers, components, actions, or groups.

Claims

1. A semiconductor processing method, To provide a substrate in the processing area of ​​a semiconductor processing chamber that includes one or more alternating pairs of a semiconductor material layer and a sacrificial material layer, Forming one or more vertically extending features through one or more alternating pairs of the semiconductor material layer and the sacrificial material layer, wherein one or more sidewalls having alternately exposed side edges of the semiconductor material layer and the sacrificial material layer, A protective material layer is formed on the side edge where the semiconductor material layer is exposed. To laterally indent at least a portion of the sacrificial material layer from one or more vertically extending features, The portion of the semiconductor material layer adjacent to one or more vertically extending features is trimmed. A semiconductor processing method, including the following.

2. The semiconductor processing method according to claim 1, wherein the protective material layer is formed by selective oxidation or nitridation of the side edge where the semiconductor material is exposed.

3. The semiconductor processing method according to claim 1, wherein the sacrificial material is recessed laterally before the protective material layer is formed.

4. The semiconductor processing method according to claim 3, further comprising filling the laterally recessed portion of the sacrificial material with a dielectric material.

5. The semiconductor processing method according to claim 4, further comprising removing the dielectric material before trimming.

6. The semiconductor processing method according to claim 1, wherein the protective material layer is formed by directional deposition on the side edge where the semiconductor material is exposed.

7. The semiconductor processing method according to claim 1, wherein the thickness of the protective material layer is approximately 5 Å to approximately 500 Å.

8. The semiconductor processing method according to claim 1, wherein the semiconductor material layer is an optionally doped silicon material, and the sacrificial material layer contains silicon germanium.

9. The semiconductor processing method according to claim 1, wherein the one or more vertically extending features have a first width before trimming the semiconductor material layer and a second width after trimming the semiconductor material layer, the second width being about 10% or less greater than the first width.

10. The semiconductor processing method according to claim 1, wherein the thickness of the semiconductor material layer is about 400% or more greater than the thickness of the sacrificial material layer.

11. The semiconductor processing method according to claim 1, further comprising removing the protective material layer after trimming the semiconductor material layer.

12. A semiconductor processing method, To provide a substrate in the processing area of ​​a semiconductor processing chamber that includes alternating pairs of silicon-containing material and silicon and germanium-containing material, One or more access openings are etched through the alternating pairs of the silicon-containing material and the silicon and germanium-containing material, exposing the side ends of the alternating pairs of the silicon-containing material and the silicon and germanium-containing material, and the etching forms one or more side walls having alternating side ends where the alternating pairs of the silicon-containing material and the silicon and germanium-containing material are alternately exposed. A protective material layer is formed on the side edge where the silicon-containing material is exposed. To laterally indent at least a portion of the silicon and germanium-containing material through one or more access openings, A portion of the silicon-containing material is trimmed adjacent to the access opening. Methods that include...

13. The semiconductor processing method according to claim 12, wherein the substrate contains more than 20 alternating pairs of the silicon-containing material and the silicon and germanium-containing material.

14. The semiconductor processing method according to claim 12, wherein the thickness of the silicon and germanium-containing material is about 30 nm or less.

15. The semiconductor processing method according to claim 12, wherein the thickness of the silicon-containing material is about 400% or more greater than the thickness of the silicon and germanium-containing material.

16. At the ends of the alternating pairs of the silicon-containing material and the silicon and germanium-containing material, opposite to the exposed side ends, one or more vertically extending features are etched to expose the outer ends of the alternating pairs of the silicon-containing material and the silicon and germanium-containing material, and by etching, at least a portion of the alternating pairs is removed, and one or more outer side walls are formed having alternatingly exposed outer ends of the alternating pairs of the silicon-containing material and the silicon and germanium-containing material. A second protective layer is formed on the exposed outer end of the silicon-containing material, The semiconductor processing method according to claim 12, further comprising:

17. The semiconductor processing method according to claim 16, further comprising laterally indenting at least a portion of the silicon and germanium-containing material from one or more vertically extending features.

18. The semiconductor processing method according to claim 17, further comprising trimming a portion of the silicon-containing material adjacent to the access opening.

19. A method for forming a three-dimensional dynamic random access memory (3D DRAM) device, To provide a substrate in the processing area of ​​a semiconductor processing chamber that includes one or more alternating pairs of silicon-containing material layers and silicon and germanium-containing material layers, To form an access opening that penetrates one or more alternating pairs of the silicon-containing material layer and the silicon and germanium-containing material layer, thereby forming one or more side walls having alternating exposed side edges of the silicon-containing material layer and the silicon and germanium-containing material layer, A protective material layer is formed on the side edge where the silicon-containing material is exposed. To cause a lateral recess in at least a portion of the silicon and germanium-containing material layer through one or more access openings, Trimming a portion of the silicon-containing material layer adjacent to one or more of the aforementioned access openings Methods that include...

20. At the end of the alternating pair of the silicon-containing material layer and the silicon and germanium-containing material layer, opposite to the exposed side end, one or more vertically extending features are etched to expose the outer end of the alternating pair of the silicon-containing material layer and the silicon and germanium-containing material layer, and by the etching, at least a portion of the alternating pair is removed, and one or more outer side walls are formed having alternating exposed outer ends of the alternating pair of the silicon-containing material layer and the silicon and germanium-containing material layer. A second protective layer is formed on the exposed outer end of the silicon-containing material, The method according to claim 19, including the method described in claim 19.

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