3D memory molded film stack

Abstract

This book provides a three-dimensional (3D) memory structure and a method for forming it. In some embodiments, the 3D memory manufacturing structure includes a base silicon (Si) layer, a silicon germanium (SiGe) layer disposed on top of the base silicon layer, and a doped silicon (Si) layer disposed on at least one side of the SiGe layer, wherein the doped Si layer contains a dopant which is at least one of carbon (C) or boron (B).

Description

Technical Field

[0001] Embodiments of the present principle generally relate to semiconductor manufacturing.

Background Art

[0002] Data storage and retrieval have been limiting factors for many aspects of the computing industry. Memory devices can easily adjust the overall performance of modern computing devices. To make memory faster, the memory structure has been shrunk to a small size and the density of the memory structure has been dramatically increased. Three-dimensional memory structures such as three-dimensional dynamic random access memory (3D DRAM) or other memory structures can be used to further increase the memory density. In some three-dimensional memory structures, alternating layers of Si and SiGe grow epitaxially from a crystalline silicon substrate. However, the inventors have observed that there is strain induced by the lattice mismatch between Si and Ge, which can lead to undesirable results such as deformation or curvature of the substrate.

[0003] Therefore, the inventors have provided a Si / SiGe three-dimensional memory structure and a method for manufacturing the same that reduce or eliminate the warping of the substrate.

Summary of the Invention

[0004] This specification provides a three-dimensional (3D) memory structure, as well as methods and apparatuses for forming such structures.

[0005]

[0005] In some embodiments, the 3D memory fabrication structure includes a base silicon (Si) layer, a silicon germanium (SiGe) layer disposed on top of the base silicon layer, and a doped silicon (Si) layer disposed on at least one side of the SiGe layer, wherein the doped Si layer contains a dopant which is at least one of carbon (C) or boron (B). In some embodiments, the 3D memory fabrication structure includes a base silicon (Si) layer, a silicon germanium (SiGe) layer disposed above the base silicon layer, and a doped silicon (Si) layer abutting one side of the SiGe layer, wherein the doped Si layer contains a dopant which is at least one of carbon (C) or boron (B). In some embodiments, one or more of the base silicon layer and the silicon germanium layer are not doped. In some embodiments, the SiGe layer contains about 10 to 25 atomic percent germanium. In some embodiments, the doped Si layer contains about 0.1 to 2 atomic percent dopant. In some embodiments, the amount of dopant in the doped Si layer varies from the bottom to the top of the doped Si layer. In some embodiments, the SiGe layer has a thickness less than the thickness of the doped Si layer, and the thickness of the doped Si layer is less than the thickness of the base Si layer. In some embodiments, the doped Si layer is placed on top of the base Si layer, the SiGe layer is placed on top of the doped Si layer, and a second doped Si layer is placed on top of the SiGe layer. In some embodiments, the doped Si layer is placed on top of the base Si layer, and the SiGe layer is placed on top of the doped Si layer. In some embodiments, the SiGe layer is placed on top of the base Si layer, and the doped Si layer is placed on top of the SiGe layer. In some embodiments, the base Si layer, the SiGe layer, and the doped Si layer are part of a repeating film stack, and the film stack is repeatedly deposited in multiple layers.

[0006] In some embodiments, a method for forming a three-dimensional (3D) memory structure is: Depositing a base silicon (Si) layer onto a substrate; Depositing a doped Si layer on a base silicon layer, wherein the doped Si layer contains a dopant that is at least one of carbon or boron; and Forming a silicon germanium (Si) layer on top of a base silicon layer. This includes forming a film stack on a substrate. In some embodiments, the doped Si layer is deposited on top of the SiGe layer. In some embodiments, the doped Si layer is deposited between the base Si layer and the SiGe layer. In some embodiments, the doped Si layer is a first doped Si layer deposited between the base Si layer and the SiGe layer, further comprising depositing a second doped Si on top of the SiGe layer. In some embodiments, the film stack is repeatedly deposited in multiple layers.

[0007] In some embodiments, apparatus and systems for forming a three-dimensional (3D) memory structure are provided according to any of the embodiments disclosed herein.

[0008] In some embodiments, a non-temporary computer-readable medium is provided, which, when executed, causes a processing chamber to perform one of the methods for forming a 3D memory structure described herein.

[0009] Other embodiments and further embodiments of this disclosure are described below.

[0010]

[0010] Embodiments of the present disclosure, which have been briefly summarized above and described in more detail below, can be understood by referring to exemplary embodiments of the present disclosure shown in the accompanying drawings. However, since this disclosure may permit other equally valid embodiments, the accompanying drawings merely illustrate typical embodiments of this disclosure and should not be considered limiting in scope. [Brief explanation of the drawing]

[0011] [Figure 1] A schematic side view of a three-dimensional (3D) memory structure according to at least some embodiments of this disclosure is shown. [Figure 2] A schematic side view of a 3D memory structure according to at least some embodiments of this disclosure is shown. [Figure 3] A schematic side view of a 3D memory structure according to at least some embodiments of this disclosure is shown. [Figure 4] This is a flowchart illustrating a method for forming a 3D memory structure according to at least some embodiments of the present disclosure. [Figure 5] This is a schematic diagram of an apparatus for processing substrates according to at least some embodiments of the present disclosure. [Modes for carrying out the invention]

[0012] For ease of understanding, the same reference numerals were used where possible to indicate identical elements common to multiple figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be usefully incorporated into other embodiments without further description.

[0013] The methods and structures provided herein enable the fabrication of three-dimensional (3D) memory structures, or film stacks. For example, the methods and structures provided herein enable the fabrication of 3D memory cells including a gate-all-around (GAA) structure around a crystalline silicon (c-Si) channel. For example, embodiments of the present disclosure provide modifiable structures suitable for further use in the fabrication of process sequences for the manufacture of 3D memory cells, such as dynamic random-access memory (DRAM), NAND memory, etc., or as part of such process sequences. The three-dimensional memory structures provided herein advantageously reduce or eliminate wafer warping and defects observed in some other three-dimensional memory structures.

[0014] Figure 1-3 shows a schematic side view of a 3D memory structure according to at least a portion of the embodiments of the present disclosure. Similar elements in the figures have the same reference numerals and their descriptions are not repeated.

[0015] Figure 1 shows a schematic side view of a 3D memory structure formed on a substrate 100. The substrate 100 can be any suitable substrate used in the manufacture of 3D memory, such as a semiconductor wafer, and may further include one or more layers and / or structures on which the 3D memory structure is formed. In some embodiments, the 3D memory structure includes a film stack 110 that can be repeatedly formed on top of each other multiple times, such as tens or hundreds of times. As used herein, “layer” refers to a single crystal layer of a material, as well as multiple crystal layers of the same material that combine to form a single crystal layer.

[0016]

[0020] The film stack 110 includes a base silicon (Si) layer 102, a doped Si layer 104 (e.g., a first doped Si layer), a silicon germanium (SiGe) layer 106, and a doped Si layer 108 (e.g., a second doped Si layer).

[0017] The base Si layer 102 is configured to function as a channel for the 3D memory structure once manufacturing is complete. In some embodiments, the base Si layer 102 is an undoped Si layer and can be formed by a suitable deposition process such as epitaxial deposition. In some embodiments, the base silicon layer 102 is formed to a thickness of less than about 50 nm, for example, about 10 to 60 nm.

[0018] In some embodiments, the doped Si layer 104 is deposited, for example, on (or directly on) a base Si layer 102. The doped Si layer 104 can be formed by a suitable deposition process, such as epitaxial deposition. In some embodiments, the doped Si layer 104 may be formed to a thickness of about 10–100 nm. The dopants in the doped Si layer 104 may be carbon, boron, or both carbon and boron. The dopant concentration in the doped Si layer 104 may be substantially uniform, constant, or the dopant concentration may vary. For example, the dopant concentration may vary from a lower amount (e.g., zero or some amount other than the nominal amount) near the start of the deposition process to a higher amount as the film deposition process continues. In some embodiments, the dopant concentration may change from a lower amount (e.g., zero or something other than the nominal amount) near the start of the deposition process to a higher amount as the film deposition process continues through the intermediate region of the layer, and then decrease again to a lower amount (e.g., zero or something other than the nominal amount) near the end of the deposition process. The change in dopant concentration may be continuous or stepwise.

[0019] The inventors observed that if the dopant concentration in the doped Si layer is too low, it does not help to reduce the compressive stress by the SiGe film to the desired level, and if the dopant concentration in the doped Si layer is too high, it leads to epitaxial defects. Therefore, in some embodiments, the dopant concentration can be from about 0.1 to about 2 atomic percent. The inventors observed that by providing a dopant concentration within this range, compressive stress is advantageously reduced, reducing or eliminating substrate warping and / or defect problems, while maintaining similar selectivity for silicon during subsequent silicon-germanium etching processes performed downstream of the 3D memory manufacturing process. The inventors further observed that, advantageously, a low dopant concentration in the doped Si layer 104 minimizes the adverse effects of dopant migration or diffusion into the base Si layer 102 (e.g., into the Si channels of the final device).

[0020] In some embodiments, the SiGe layer 106 is deposited on, for example, directly on, a doped Si layer 104. In some embodiments, the SiGe layer 106 is an undoped SiGe layer that can be formed by a suitable deposition process such as epitaxial deposition. In some embodiments, the SiGe layer 106 is formed to a thickness of about 5 to 20 nm. In some embodiments, the SiGe layer 106 contains about 10 to 25 atomic percent Ge. The SiGe layer 106 is a sacrificial layer in the 3D memory manufacturing sequence and is subsequently removed in a downstream etching process. The inventors have observed that the SiGe layer 106 having the above-described Ge concentrations retains good etching rate and selectivity compared to Si doped with both Si and C and / or B (e.g., base Si layer 102 and doped Si layer 104).

[0021]

[0025] In some embodiments, the doped Si layer 108 (e.g., a second doped Si layer) is deposited on top of the SiGe layer 106, for example, directly on top of it. The doped Si layer 108 can be formed by a suitable deposition process such as epitaxial deposition. In some embodiments, the doped Si layer 108 may be formed to a thickness of about 10 to 100 nm. The dopants in the doped Si layer 108 may be carbon, boron, or both carbon and boron. The dopant concentration in the doped Si layer 108 may be substantially uniform or constant, or the dopant concentration may be varied in the same manner as described above with respect to the doped Si layer 104. For the same reasons as described above with respect to the doped Si layer 104, in some embodiments, the dopant concentration in the doped Si layer 108 may be about 0.1 atomic% to about 2 atomic%. In some embodiments, the doped Si layer 104 and the doped Si layer 108 may be substantially identical to each other in terms of dopant, dopant concentration, dopant concentration gradient, or thickness. In some embodiments, the doped Si layer 104 and the doped Si layer 108 may differ from each other in terms of dopant, dopant concentration, dopant concentration gradient, or thickness.

[0022] In some embodiments, as shown by the dashed lines, a transition layer 112 can be formed between one or more of the various layers of the membrane stack 110. For example, when depositing the various layers in an epitaxial deposition process, as the gas sources for various dopants or elements other than Si are controlled (e.g., turned on or off, ramped up or down), the interface layer (e.g., transition layer) can be formed with a composition that changes from the composition of the underlying layer on which the subsequent layer is formed to the composition of the subsequent layer. For example, when depositing a doped Si layer 104 on a base Si layer 102, a transition layer 112 can be formed when introducing a dopant precursor in the deposition process. Similarly, when the deposition of the doped Si layer 104 is completed and the deposition of the SiGe layer 106 is started, a transition layer 112 can be formed between stopping the flow of the dopant precursor and introducing a germanium precursor in the deposition process. Further, there may be a period between stopping the flow of the dopant precursor and introducing the flow of the germanium precursor, during which a Si layer (e.g., transition Si layer) with little or no dopant and little or no germanium can be formed. The transition layer 112 can be present between any two adjacent layers, including all adjacent layers within the membrane stack 110. However, the transition layer 112 need not be present between all adjacent layers of the membrane stack 110. In some embodiments, the transition layer 112 is formed between a doped silicon layer and a SiGe layer. Each transition layer 112 can generally have a thickness of up to about 10 nm.

[0023] In some embodiments, only one of the doped Si layer 104 or the doped Si layer 108 is provided. For example, in some embodiments, as shown in FIG. 2, the doped Si layer 104 is omitted in the film stack 210 in which the SiGe layer 106 is deposited (with or without the transition layer 112) on the base Si layer 102 (e.g., directly thereon). Alternatively, in some embodiments, as shown in FIG. 3, the doped Si layer 108 is omitted in the film stack 310 and the SiGe layer 106 is the topmost layer in the film stack 310.

[0024] In some embodiments, the total thickness of the film stacks 110, 210, 310 is between about 80 nm, for example between about 50 nm and 100 nm. In some embodiments, the thickness of the base silicon layer 102 can be set by taking the desired total unit thickness of the film stacks 110, 210, 310 and subtracting the thicknesses of the SiGe layer, the doped Si layer, and any transition layer 112.

[0025] Although FIGS. 1 - 3 only illustratively show one film stack 110, 210, 310, each film stack 110, 210, 310 is repeated multiple times (e.g., a second film stack is formed directly on the first film stack, a third film stack is formed on the second film stack, etc.) to form a structure suitable for further processing of the 3D memory device. For example, in a typical 3D memory structure, the film stacks 110, 210, 310 can be repeated about 100 times or more. The inventors have observed that by forming such a structure using the repeated film stacks 110, 210, 310 described herein, acceptable substrate warpage and low stress are advantageously maintained and good (e.g., low) epitaxial defects are obtained. Further, such a structure utilizing the repeated film stacks 110, 210, 310 described herein advantageously supports the subsequent processing steps necessary to ultimately form the 3D memory device.

[0026]

[0030] Figure 4 is a flowchart illustrating a method 400 for forming a 3D memory structure according to at least some embodiments of the present disclosure, such as by a heteroepitaxy process including chemical vapor deposition or other known deposition techniques. Method 400 is suitable for use in the manufacture of the structures described above with respect to Figures 1-3, which each show a schematic side view of various embodiments of the present disclosure.

[0027] Method 400 generally begins in block 402, where a base Si layer 102 is deposited on the substrate 100 (see, for example, Figures 1-3). The base Si layer can be formed by any preferred process (e.g., chemical vapor deposition (CVD)) in a preferred process chamber, such as an RP EPI chamber commercially available from Applied Materials, Inc. in Santa Clara, California.

[0028] Next, in block 404, a doped Si layer 104 (e.g., a first doped Si layer) may be deposited on top of the base Si layer (see, for example, Figures 1 and 3). The first doped Si layer may be formed by any suitable process, such as chemical vapor deposition (CVD), and may be formed in the same chamber as the base Si layer. In some embodiments, the first doped Si layer is deposited directly on top of the base Si layer. In some embodiments, the first doped Si layer is deposited directly on top of a transition layer (e.g., a transition layer 112) which is deposited directly on top of the base Si layer.

[0029] Next, in block 406, a SiGe layer 106 is deposited on top of the first doped Si layer (see, for example, Figures 1 and 3) or on top of the base Si layer (see, for example, Figure 2). The SiGe layer may be formed by any suitable process, such as chemical vapor deposition (CVD), and may be formed in the same chamber as the base silicon layer and, if present, the first doped silicon layer. In some embodiments, the SiGe layer is deposited directly on the aforementioned underlying layer (e.g., the Si base layer or the first doped Si layer). In some embodiments, the SiGe layer is deposited directly on a transition layer (e.g., transition layer 112) which is deposited directly on one or more of the first doped Si layer or the base Si layer.

[0030] Next, if the first doped Si layer is not present in block 408 (e.g., not deposited in the optionally selected block 404), the doped Si layer 108 can be deposited on the SiGe layer to form a film stack 210 (see, for example, Figure 2). If the first doped Si layer is present (e.g., deposited in the optionally selected block 404), then the doped Si layer 108 can be optionally deposited on the SiGe layer. For example, in the embodiment corresponding to Figure 1, the doped Si layer 104 is the first doped Si layer (deposited on the base Si layer), and the doped Si layer 108 is the second doped Si layer (deposited on the SiGe layer), and the deposited layers define the film stack 110. In the embodiment corresponding to Figure 3, the doped Si layer 108 is not deposited, and the first doped Si layer (e.g., doped Si layer 104) is the only doped Si layer in the film stack 310.

[0031]

[0035] The second doped Si layer may be formed by any suitable process, such as chemical vapor deposition (CVD), and may be formed in the same chamber as the base Si layer, the first doped Si layer (if present), and the SiGe layer. In some embodiments, the doped Si layer is deposited directly on top of the SiGe layer. In some embodiments, the doped Si layer is deposited directly on top of a transition layer (e.g., transition layer 112) which is deposited directly on top of the SiGe layer. In all embodiments, any transition layer formed is part of a defined film stack (e.g., film stacks 110, 210, 310).

[0032] Next, in block 410, blocks 402 to 408 can be repeated to form one or more additional film stacks on top of the initial film stack. For example, block 402 can be repeated to deposit a second base Si layer on top of a doped Si layer (e.g., Figures 1 and 2) or a SiGe layer (e.g., Figure 3). The repeated deposition of film stacks allows for the formation of a specific memory structure or the number of repeated film stacks required for the structure, providing considerable flexibility in memory structure design. The repeated film stacks may be the same as the previously deposited film stack, or they may differ from the previously deposited film stack in terms of dopant concentration, gradient, transition layer, etc. For example, generally speaking, each film stack in a plurality of film stacks including a 3D memory structure (e.g., film stacks 110, 210, 310) may independently be any of the above-described embodiments of the film stacks, including a plurality of identical film stacks, a plurality of film stacks each having a unique configuration, or a plurality of film stacks having two or more different film stack configurations.

[0033] Once the desired number of iterations are completed in 410, method 400 is generally finished. However, the resulting structures shown in Figures 1-3 may be further processed to continue manufacturing 3D memory devices with reduced stress-induced defects compared to conventional 3D memory devices.

[0034] The method 400 described above can be carried out in a processing chamber configured for epitaxial deposition, such as the RP EPI chamber or other similar chambers. The processing chamber may be a standalone processing chamber or part of an integrated tool (or cluster tool) that includes at least a suitable processing chamber configured for chemical vapor deposition (CVD).

[0035] For example, an integrated tool (e.g., tool 500) as described below with respect to Figure 5 facilitates the operation of the method described herein such that vacuum breaks between processes are limited or absent. Reduced vacuum breaks can limit or prevent contamination (e.g., oxidation) of parts of the substrate, reduce the amount of time between processes, and further increase throughput by reducing or eliminating certain processes such as pre-cleaning or other steps that would be required when the processes are run continuously in a standalone processing chamber.

[0036]

[0040] The tool 500 includes a vacuum airtight processing platform (processing platform 501), a factory interface 504, and a system controller (e.g., system controller 502). The processing platform 501 comprises several processing chambers, such as 514A, 514B, 514C, and 514D, which are operably connected to a vacuum substrate transfer chamber (transfer chamber 503). The factory interface 504 is operably connected to the transfer chamber 503 by one or more load lock chambers (two load lock chambers, such as 506A and 506B shown in Figure 5).

[0037] In some embodiments, the factory interface 504 comprises at least one docking station 507 and at least one factory interface robot 538 for facilitating the transfer of one or more semiconductor substrates (e.g., wafers). The docking station 507 is configured to receive one or more forward-opening unified pods (FOUPs). In the embodiment of Figure 5, four FOUPs (e.g., 505A, 505B, 505C, and 505D) are shown. The factory interface robot 538 is configured to transfer substrates from the factory interface 504 to the processing platform 501 through load lock chambers (e.g., 506A and 506B). Each of the load lock chambers 506A and 506B has a first port connected to the factory interface 504 and a second port connected to the transfer chamber 503. The load lock chambers 506A and 506B are connected to a pressure control system (not shown) that pumps down and vents the load lock chambers 506A and 506B to facilitate the passage of substrates between the vacuum environment of the transfer chamber 503 and the substantial surrounding environment (e.g., atmospheric environment) of the factory interface 504. The transfer chamber 503 has a vacuum robot 542 located inside the transfer chamber 503. The vacuum robot 542 is capable of transferring substrates 521 between the load lock chambers 506A and 506B and the processing chambers 514A, 514B, 514C, and 514D.

[0038] In some embodiments, processing chambers 514A, 514B, 514C, and 514D are connected to a transfer chamber 503. Processing chambers 514A, 514B, 514C, and 514D each comprise at least one CVD chamber configured for the processes described above. Additional CVD chambers and / or other chambers may also be provided.

[0039] In some embodiments, at least one deposition chamber is provided, configured to deposit repeating film stacks of silicon (Si) layers, doped Si layers, and silicon germanium (SiGe) layers, as described above in any one of Figures 1 to 3.

[0040] In some embodiments, one or more optional service chambers (illustrated as 516A and 516B) may be coupled to the transfer chamber 503. Service chambers 516A and 516B may be configured to perform other substrate processes such as degassing, pre-cleaning, etching, orientation, substrate measurement, preheating, and cooling.

[0041]

[0045] In some embodiments, the system controller 502 controls the operation of the tool 500 by controlling a computer (or controller) associated with the chamber connected to the tool 500, either by direct control of the chamber connected to the tool, or alternatively. During operation, the system controller 502 enables data collection and feedback from each chamber and system to optimize the performance of the tool 500. The system controller 502 generally includes a central processing unit (CPU) 530, memory 534, and support circuitry 532. The CPU 530 may be any form of general-purpose computer processor that may be used in an industrial setting. The support circuitry 532 is conventionally connected to the CPU 530 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. Software routines, such as the processing method described above, may be stored in memory 534 (e.g., a non-temporary computer-readable storage medium) and, when executed by the CPU 530, translate the CPU 530 into a purpose-specific computer (system controller 502) to execute the method 400 described above. The software routine may also be stored and / or executed by a second controller (not shown) located remotely from the tool 500. In some embodiments, the system controller 502 is a controller that directly controls the processing chamber to perform the method 400 described above.

[0042] While the descriptions in the prior specification apply to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure.

Claims

1. A three-dimensional (3D) memory manufacturing structure, Base silicon (Si) layer, A silicon germanium (SiGe) layer is disposed above the base silicon layer, A doped silicon (Si) layer disposed on at least one side of the SiGe layer, the doped silicon (Si) layer containing a dopant which is at least one of carbon (C) or boron (B) A three-dimensional (3D) memory manufacturing structure equipped with [the following features].

2. The 3D memory manufacturing structure according to claim 1, wherein one or more of the base silicon layer and the silicon germanium layer are not doped.

3. The 3D memory manufacturing structure according to claim 1, wherein the SiGe layer contains about 10 to 25 atomic percent of germanium.

4. The 3D memory manufacturing structure according to claim 1, wherein the doped Si layer contains about 0.1 to 2 atomic percent of the dopant.

5. The 3D memory manufacturing structure according to claim 1, wherein the amount of dopant in the doped Si layer varies from the bottom of the doped Si layer to the top of the doped Si layer.

6. The 3D memory manufacturing structure according to claim 1, wherein the SiGe layer has a thickness less than the thickness of the doped Si layer, and the thickness of the doped Si layer is less than the thickness of the base Si layer.

7. The 3D memory manufacturing structure according to claim 1, wherein the doped Si layer is disposed on the base Si layer, the SiGe layer is disposed on the doped Si layer, and the structure further comprises a second doped Si layer disposed on the SiGe layer.

8. The doped Si layer is placed on the base Si layer, and the SiGe layer is placed on the doped Si layer, or The SiGe layer is placed on the base Si layer, and the doped Si layer is placed on the SiGe layer. A 3D memory manufacturing structure according to any one of claims 1 to 7.

9. The 3D memory manufacturing structure according to any one of claims 1 to 7, wherein the doped Si layer is in direct contact with the SiGe layer.

10. The 3D memory manufacturing structure according to any one of claims 1 to 7, further comprising a transition Si layer disposed between the SiGe layer and the doped Si layer.

11. The 3D memory manufacturing structure according to any one of claims 1 to 7, wherein the base Si layer, the SiGe layer, and the doped Si layer are part of a repeating film stack, and the film stack is repeatedly deposited multiple times on top of each other with either a uniform dopant concentration or a varied dopant concentration within at least two of the film stacks of the repeating film stack.

12. A method for forming a three-dimensional (3D) memory structure, Depositing a base silicon (Si) layer onto a substrate, A method of depositing a doped Si layer on the base Si layer, wherein the doped Si layer contains a dopant which is at least one of carbon or boron, and Depositing a silicon germanium (SiGe) layer on the aforementioned base silicon layer, This is done by forming a film stack on the substrate. Methods that include...

13. The doped Si layer is deposited on top of the SiGe layer, or The SiGe layer is deposited on top of the doped Si layer. The method according to claim 12.

14. The method according to claim 12, wherein the doped Si layer is a first doped Si layer, the SiGe layer is deposited on the first doped Si layer, and a second doped Si layer is deposited on the SiGe layer.

15. The method according to claim 12, wherein one or more of the base silicon layer and the SiGe layer are not doped.

16. The method according to claim 12, wherein the SiGe layer contains about 10 to 25 atomic percent germanium.

17. The method according to claim 12, wherein the doped Si layer contains about 0.1 to 2 atomic percent of the dopant.

18. The method according to claim 12, wherein the SiGe layer has a thickness less than the thickness of the doped Si layer, and the thickness of the doped Si layer is less than the thickness of the base Si layer.

19. The method according to any one of claims 12 to 18, wherein the film stacks are repeatedly deposited multiple times, overlapping each other.

20. A non-temporary computer-readable medium having instructions formed on it that, when executed, cause a process chamber to perform the method according to any one of claims 12 to 18.

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