Method and structure for high-strength dielectrics in hybrid junctions

Abstract

Structures for semiconductor devices having a high dielectric film on the upper surface of the structure can be used to form semiconductor devices consisting of a hybrid junction structure in which the dielectric surface area is reduced and the pitch of the metal studs is reduced. For example, the dielectric constant of the dielectric film may be greater than 7 or 8. Semiconductor devices can be formed by hybrid junctioning a dielectric film of a structure to a dielectric film of a similar structure. Dielectric film-oxide-metal-substrate structures can be formed so that the dielectric film is on the upper surface of the laminate. Multi-material etching can be used to etch features into the dielectric film and the oxide in the dielectric film-oxide-metal-substrate stack. Chemical mechanical polishing techniques can be used to precisely form the surface of the structure in preparation for hybrid junctions.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Non - Provisional Application No. 18 / 460,154, filed on September 1, 2023, entitled "METHODS AND STRUCTURES FOR HIGH STRENGTH DIELECTRIC IN HYBRID BONDING", the content of which is hereby incorporated by reference in its entirety for all purposes.

[0002]

[0002] This technology relates to semiconductor systems, processes, and devices. More specifically, this technology relates to processes and semiconductor devices for hybrid bonding.

Background Art

[0003] Background Art

[0003] Hybrid bonding (which may also be referred to as heterogeneous integration) is a semiconductor manufacturing technology that enables miniaturization of three - dimensional semiconductor device manufacturing processes related to advanced node technologies that require heterogeneous integration. Hybrid bonding involves creating a strong bond between dies, wafers, and / or substrates without the need for adhesives or interconnect materials. However, heterogeneous integration technology can be limited by pitch reduction. As the desired pitch is reduced, the available dielectric surface area at the contact joints of the hybrid bond also decreases. Thus, in a hybrid bonding system, there may be a large proportion of the bonding surface between dies that becomes dielectric. As the desired pitch decreases, standard hybrid bonding techniques and systems may not be able to provide sufficient bonding strength adequately.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to improve the system for hybrid bonding as the pitch is reduced. This technology addresses these and other needs.

Summary of the Invention

[0005]

[0005] In some embodiments, a semiconductor device for a hybrid junction may include a metal layer covering a substrate, a dielectric layer covering the metal layer and defining one or more recessed sets of features within the dielectric layer, a dielectric film covering the dielectric layer and having a dielectric constant greater than about 7, and a copper-containing material deposited within the set of one or more features.

[0006]

[0006] In some embodiments, a method for forming a semiconductor device may include forming a metal layer on a substrate, forming a dielectric layer on the metal layer, forming a dielectric film having a dielectric constant greater than about 7 on the dielectric layer, etching trenches in the dielectric film and the dielectric layer such that the trenches extend downward from the upper surface of the dielectric film to at least the upper surface of the metal layer, and filling the trenches with a copper-containing material.

[0007]

[0007] In some embodiments, a method for forming a semiconductor device may include forming a metal layer on a substrate, forming a barrier film having a dielectric constant of about 5 or less on the metal layer, forming a tetraethyl orthosilicate layer on the barrier film, forming a dielectric film having a second dielectric constant greater than 7 on the tetraethyl orthosilicate layer, etching trenches in the dielectric film, the tetraethyl orthosilicate layer, and the barrier film, wherein the trenches extend downward from the upper surface of the dielectric film to at least the upper surface of the metal layer, etching trenches, forming a liner in the trenches, and filling the trenches with a copper-containing material.

[0008]

[0008] In any embodiment, any and all of the following features may be implemented in any combination, without limitation. The semiconductor device may further include a second structure, the second structure comprising a second metal layer covering a second substrate, a second dielectric layer covering the second metal layer and defining a second set of one or more recessed features in the second dielectric layer, a second dielectric film covering the second dielectric layer and having a second dielectric constant greater than about 7, and a second copper-containing material deposited within the second set of one or more features, wherein the dielectric film of the first structure may be hybrid-bonded to the second dielectric film of the second structure, and the copper-containing material of the first structure is in contact with the second copper-containing material of the second structure. The dielectric constant may be greater than about 8. The dielectric film may have a thickness of 5 nm. The dielectric film may contain Al2O3. The copper-containing material may be characterized by a dish profile having a dish depth of about 1 nm or less. Etching trenches in dielectric films and dielectric layers may include etching the trenches in the dielectric film using chlorine-based etching. Etching trenches in dielectric films and dielectric layers may include etching the trenches in dielectric films and dielectric layers using multi-material etching. Multi-material etching may include two or more of chlorine-based etching, fluorine-based etching, oxygen plasma etching, and fluorine and oxygen-based etching. The formation of the metal layer and the dielectric layer may be performed in a first chamber, and the etching of trenches in the dielectric film and dielectric layer may be performed in a second chamber, and the first structure may be moved from the first chamber to the second chamber without exposing the substrate to the external atmosphere. The first structure may be in contact with one or more slurries and one or more platens, which may remove a portion of the copper-containing material and a second portion of the dielectric film. By bringing the first structure into contact with one or more slurries and one or more platens, the copper-containing material can be recessed into a trench below the upper surface of the dielectric film by a distance of approximately 1 nm or less.By contacting the first structure with one or more slurries and one or more platens, the copper-containing material can be characterized by a dish profile. A liner may be formed in a trench, and filling the trench with the copper-containing material may include covering the liner with the copper-containing material. The method may further include contacting the first structure with a hydrogen-containing precursor and contacting the first structure with a second structure. The second structure includes a second metal layer covering a second substrate, a second dielectric layer covering the second metal layer and defining a second set of one or more features in the second dielectric layer, a second dielectric film covering the second dielectric layer and having a second dielectric constant greater than about 7, and a second copper-containing material deposited in the second set of one or more features, wherein the dielectric film of the first structure may be hybrid-bonded to the second dielectric film of the second structure, and the copper-containing material of the first structure is in contact with the second copper-containing material of the second structure. Joining the first structure to the second structure may include bringing the first structure into contact with water and annealing the first and second structures. The dielectric constant of the second structure may be greater than about 8, and the dielectric constant of the fourth structure may be greater than 8.

[0009]

[0009] A further understanding of the properties and advantages of various embodiments can be achieved by referring to the remainder of this specification and the drawings. In the drawings, similar reference numbers are used across several drawings to refer to similar components. In some cases, sublabels are associated with reference numbers to indicate one of several similar components. When a reference number is referred to without specifying an existing sublabel, it is intended to refer to all such several similar components. [Brief explanation of the drawing]

[0010] [Figure 1] A top view of one embodiment of a deposition, etching, baking, and curing chamber processing system, which may be included or configured according to several embodiments, is shown. [Figure 2] The operation of a semiconductor processing method according to several embodiments is shown. [Figure 3A-3D] The following are schematic cross-sectional views illustrating exemplary structures that include material layers and are processed according to several embodiments. [Figure 4] The operation of a semiconductor processing method according to several embodiments is shown. [Figure 5A-E] The following are schematic cross-sectional views illustrating exemplary structures that include and are processed with material layers, according to several embodiments. [Modes for carrying out the invention]

[0011]

[0015] Structures for semiconductor devices having a high dielectric film on the upper surface of the structure can be used to form semiconductor devices consisting of a hybrid junction structure with reduced dielectric surface area and reduced metal stud pitch. For example, the dielectric constant of the dielectric film may be greater than 7 or 8. Semiconductor devices can be formed by hybrid junctioning a dielectric film of a structure to a dielectric film of a similar structure. Dielectric film-oxide-metal-substrate structures can be formed to have a dielectric film on the upper surface of the laminate. Multi-material etching can be used to etch features into the dielectric film and the oxide in the dielectric film-oxide-metal-substrate stack. Chemical mechanical polishing techniques can be used to precisely form the surface of the structure in preparation for hybrid junctions.

[0012]

[0016] Conventional hybrid bonding systems can provide sufficient bonding strength to bond two wafers under certain conditions, but conventional systems may be limited to a specific minimum size and / or minimum percentage surface area pitch of the dielectric on the wafer surface. Therefore, the wafer is limited to a certain percentage of the metal pads on the wafer surface, resulting in a limited metal density. For example, the pitch may be as small as 1 micron, and the dielectric bonding surface may be approximately 80% or more of the bonding surface between wafers. This technology overcomes these problems associated with conventional hybrid bonding systems by increasing the bonding strength between the dielectrics of the die. By forming a high-dielectric-constant dielectric layer on each die before hybrid bonding of the wafers, the dielectric layer has stronger bonding strength, enabling a reduction in the wafer pitch and a higher density of metal pads.

[0013]

[0017] In summary, hybrid bonding is a semiconductor manufacturing technique that combines the advantages of both direct bonding and conventional bonding methods. This allows for the integration of different materials at the molecular level, facilitating the development of advanced semiconductor devices with improved performance, functionality, and miniaturization that do not require the use of metal interconnects. Hybrid bonding is particularly useful in the fabrication of three-dimensional semiconductor devices.

[0014]

[0018] When a system consisting of two wafers (die, substrate, etc.) is joined to each other via a hybrid bond, the dielectric layers of the wafers are first treated to create a reactive layer via surface activation. The dielectric layers can then be brought into contact with each other and bonded, for example, by spontaneous hydrophilic oxide-oxide bonding. Once the dielectric layers are bonded, the metal pads of each wafer are separated by a dishing gap. The system can then be annealed so that the dielectric layers remain approximately the same size as the metal, while the metal pads of each wafer thermally expand and connect. Upon completion of annealing, the wafers are joined by the hybrid bond.

[0015]

[0019] The remaining disclosure will, as is customary, identify specific hybrid bonding processes that utilize the disclosed technology, but it will be readily apparent that the systems and methods are equally applicable to a variety of other processes that may occur in the described chambers. Therefore, the technology should not be considered limited to use in the described etching or deposition processes alone. Before describing the systems and methods or operations of exemplary process sequences according to several embodiments of the technology, this disclosure will discuss one possible system that can be used in the technology. It should be understood that the technology is not limited to the described apparatus, and the processes discussed can be performed in any number of processing chambers and systems.

[0016]

[0020] Figure 1 shows a top view of one embodiment of a deposition, etching, baking, and curing chamber processing system 100, which may be included or configured according to several embodiments of the present technology. In this figure, a pair of front-opening unified pods 102 supply substrates of various sizes. These substrates are received by a robotic arm 104, placed in a low-pressure holding area 106, and then placed in one of the substrate processing chambers 108a-f arranged in tandem sections 109a-c. A second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and in the reverse direction. Each substrate processing chamber 108a-f may be equipped to perform several substrate processing operations, including periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma processing, degassing, orientation, and other substrate processing, as well as the dry etching process described herein.

[0017]

[0021] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching material films on a substrate or wafer. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, may be used to deposit material on the substrate, and a third pair of processing chambers, e.g., 108a-b, may be used to cure, anneal, or process the deposited film. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to deposit and cure films on the substrate. One or more of the processes described may be performed in additional chambers separated from the manufacturing system shown in different embodiments. It will be understood that system 100 envisions further configurations of deposition chambers, etching chambers, annealing chambers, and curing chambers for material films. In addition, any number of other processing systems may be used in conjunction with this technology, and these processing systems may incorporate chambers for performing any of the specific operations. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining a vacuum environment in various sections such as the aforementioned holding and transfer areas may enable operation within multiple chambers while maintaining a specific vacuum environment between individual processes.

[0018]

[0022] A chamber incorporated into System 100, or more specifically into System 100 or another processing system, may be used to manufacture structures according to some embodiments of the Art. Figure 2 shows an exemplary operation flow chart in Method 200 for forming a semiconductor device 300 for a hybrid bond that enables reduced pitch and stronger bond strength, according to some embodiments of the Art. Method 200 may be performed in a variety of processing chambers in which the operation can be performed, such as the chamber incorporated into System 100 described above. Method 200 may include one or more operations before the start of Method 200, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed before the operations described. Method 200 may include a number of optional operations that may or may not be specifically associated with some embodiments of the method according to embodiments of the Art. Method 200 may illustrate the operations schematically shown in Figures 3A to 3D. These figures will be described in conjunction with the operations of Method 200. The figure shows only a partial schematic diagram, and it should be understood that the substrate 302 may include any number of additional materials and features having various properties and characteristics, as shown in the figure.

[0019]

[0023] It should be understood that the specific steps shown in Figure 2 provide a specific method for forming a semiconductor device 300 for a hybrid junction according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. Furthermore, the individual steps shown in Figure 2 may include a plurality of substeps, which may be performed in various sequences depending on the individual step. In addition, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included in the scope of this disclosure.

[0020]

[0024] Figures 3A - 3D illustrate a progressive structure for forming a semiconductor device 300 for hybrid bonding according to several embodiments. The method of flowchart 200 describes the operations schematically shown in Figures 3A - 3D, and the illustration thereof is described in conjunction with the operations of this method. The drawings show only partial schematic views with limited details, and it should be understood that in some embodiments, the substrate may include any number of semiconductor regions having an aspect as shown in the drawings and alternative structural aspects that can still benefit from any of the aspects of the present technology.

[0021]

[0025] In operation 202, the method of flowchart 200 for forming the first structure 301 may include forming a metal layer 304 on the substrate 302. As shown in Figure 3A, the structure 300 may include the substrate 302. The substrate 302 may have a substantially planar surface or a non-uniform surface in various embodiments. The substrate 302 may be made of materials such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon on insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 426 may have various dimensions, such as a wafer with a diameter of 200 mm or 300 mm, and rectangular or square panels. The substrate 302 may be disposed within the processing region of a semiconductor processing chamber. Although shown as a planar substrate, the substrate 302 is included only to represent the underlying structure, and it should be understood that it can include any number of layers or features on a wafer or other substrate, and structures as described below can be formed.

[0022]

[0026] As shown in FIG. 3A, the first structure 301 may include a metal layer 304. The metal layer 304 may include various integrated circuits. For example, the integrated circuits can be created using techniques such as CMOS, NMOS, or any other suitable integrated circuit technology. Thus, the metal layer 304 can include various layers of metal, oxide, and semiconductor. The metal used for the metal layer may include copper or any other highly conductive metal. Although copper is discussed regularly in this application, it should be understood that any number of conductive metal materials may be used in embodiments of this technology, and the technology should not be limited to a particular conductive metal material.

[0023]

[0027] In some embodiments, the layers described herein (e.g., the substrate 302, the metal layer 304, and the barrier film 306, the second dielectric layer 308, and the dielectric film 310, and other layers described herein) can be directly stacked on top of each other such that the first layer overlays the second layer. For example, the metal layer 304 can directly overlay the substrate 302 such that there is no intervening layer. In some embodiments, the layers described herein can have a layer between them. For example, the metal layer 304 can overlay an intervening layer that overlays the substrate 302. Further, any process for forming or depositing materials can be used when forming the layers. For example, chemical vapor deposition (CVD) can be used in some embodiments, and atomic layer deposition (ALD) can be used in other embodiments. Details regarding specific layers and / or materials are also described herein.

[0024]

[0028] In operation 204, the method of flowchart 200 for forming the first structure 301 may include forming a dielectric layer 308 on top of the metal layer 304. As shown in FIG. 3A, the dielectric layer 308 may include one or more layers of dielectric. Exemplary dielectrics may include silicon oxide, tetraethyl orthosilicate (also referred to as TEOS or TeOs), or any other type of oxide. The dielectric layer 308 may also be referred to as an oxide layer.

[0025] In some embodiments, the first structure 301 may include a barrier film 306 between the dielectric layer 308 and the metal layer 304. The barrier film 306 may have a low dielectric constant to reduce the dielectric constant of the copper damascene structure in order to realize faster and stronger devices. Some barrier films may have a dielectric constant of less than 5 or lower. Exemplary barrier films include silicon nitride films and low dielectric constant barrier films such as BLoK (Si-CH compound) or N-BLoK (Si-CHN compound) developed by Applied Materials. The barrier film 306 may also be called a capping layer for the metal layer. While dielectric layers will be described periodically in the following description, it should be understood that any number of dielectric materials and / or layers of dielectric materials may be used in embodiments of this technology, and this technology should not be limited to specific dielectric materials.

[0026]

[0029] In operation 206, the method of forming the first structure 301 in flowchart 200 may include forming a dielectric film 310 on the dielectric layer 308. As shown in Figure 3A, the structure 300 may include the dielectric film 310. In some examples, the dielectric film 310 may be a dielectric material having a dielectric constant K of about 7 or more. An example of a dielectric film having a sufficiently high dielectric constant K of 7 may be silicon nitride (Si3N4). In some examples, the dielectric film 310 may be a dielectric material having a dielectric constant K of about 8 or more. In some examples, the dielectric film 310 may have a dielectric constant K of about 9 or more. Examples of dielectric films having a sufficiently high dielectric constant K of 9 or higher include aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanate (SrTiO3), zirconium oxide (ZrO2), hafnium oxide (hafnium(IV) oxide, also known as HfO2), hafnium silicate (hafnium(IV) silicate, also known as HfSiO4), lanthanum oxide (La2O3), yttrium oxide (yttrium(III) oxide, also known as Y2O3), and ranthium aluminate (LaAlO3). These materials may require special end-line treatment and / or special etching due to their chemical properties compared to more conventional materials such as silicon oxide. In some examples, the dielectric film 310 may have a dielectric constant K of about 10 or higher. In some examples, the dielectric film 310 may have a dielectric constant K of about 11 or higher.

[0027]

[0030] In some embodiments, the formation of the dielectric film 310 can be carried out in a different chamber of system 100 than the formation of the dielectric layer 308. In some embodiments, the formation of each layer can be carried out in different chambers. In some embodiments, the formation of the dielectric layer 308, barrier film 306, metal layer 304, and / or substrate 302 can be carried out in a single chamber.

[0028]

[0031] In some examples, forming a dielectric film 310 may involve depositing a dielectric material via atomic layer deposition. Depositing the dielectric material may involve contacting a first structure 301 with a hydrogen-containing precursor. The first structure 301 can be contacted with the hydrogen-containing precursor to hydroxylate the surface of the dielectric layer 308. By hydroxylating the surface of the dielectric layer 308, a surface activation layer can be formed on the dielectric layer 308, thereby forming hydrogen atoms from the lattice of the dielectric layer 308. The hydrogen-containing precursor can be contacted with the first structure via any suitable means, such as CVD plasma CVD, ALD, etc.

[0029]

[0032] Once the surface of the dielectric layer 308 is activated to form a surface activation layer, a precursor can be applied to the first structure 301 to form a dielectric film 310. In some embodiments, the structure 301 may be in contact with one or more precursors. The precursors react with the surface of the surface activation layer of the dielectric layer 308 to deposit atomic layers of a material, such as a dielectric. To deposit atomic layers of a dielectric material and form a dielectric film 310, as in conventional ALD processes, the first structure 301 may be in contact with a first precursor, then a second precursor (or any number of precursors), and by alternating contact between the first precursor and the second precursor (or any number of precursors). One or more precursors 718 may be selected to produce a specific dielectric film 310 on the surface of the dielectric layer 308. For example, an ALD process for depositing aluminum oxide may alternate between trimethylaluminum and water precursors. Any suitable combination of precursors can be used.

[0030]

[0033] In the embodiment, it may be determined whether the target thickness of the dielectric film 310 has been achieved following operation 206. If the target thickness of the dielectric film 310 has not been achieved, another ALD cycle may be performed. An exemplary range of target thicknesses for interrupting further cycles to form the dielectric film 710 includes about 10 nm or less. Additional exemplary thickness ranges include about 9.5 nm or less, about 9.0 nm or less, about 8.5 nm or less, about 8.0 nm or less, about 7.5 nm or less, about 7.0 nm or less, about 6.5 nm or less, about 6.0 nm or less, about 5.5 nm or less, about 5.0 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, 2.0 nm, about 1.5 nm or less, about 1.0 nm or less, about 0.5 nm or less, or less, and include any part of the values ​​listed.

[0031]

[0034] In operation 208, the method of forming the first structure 301 in flowchart 200 may include etching features into the dielectric layer 308, the dielectric film 310, and the barrier film 306 (if applicable). Features etched into the dielectric layer 308 and the dielectric film 310 may include trenches, openings, or vias, or any other structures useful for semiconductor processing. As shown in Figure 3B, the structure 300 may include trenches 320 within the dielectric film 310 and the dielectric layer 308. In some embodiments, the trenches 320 may extend from the upper surface of the dielectric film 310 to at least the upper surface of the metal layer 304. Although only four features are shown in the figure, it should be understood that exemplary structures may have any number of features defined along the structure according to embodiments of the Art.

[0032]

[0035] The etchants used to etch features into the dielectric layer 308, the dielectric film 310, and, where applicable, the barrier film 306, may include a variety of semiconductor processing etchings, which may be chlorine, fluorine, oxygen plasma, or a solution or plasma such as fluorine and oxygen. In some embodiments, the etchants may be applied one at a time. In some embodiments, multiple etchants may be combined to form a multi-material etching. The etchants of the dielectric film 310 may be different from those of the dielectric layer 308 or some of the etchants of the dielectric layer 308. In some embodiments, chlorine etching may be used on the dielectric film 310 of the material aluminum oxide. In some embodiments, fluorine etching may be used on the TEOS layer of the dielectric layer 308. In some embodiments, ashing etching, such as oxygen plasma, may be used to remove organic matter. In some embodiments, fluorine and oxygen etching may be used on the BLoK layer or n-BLoK layer of the barrier film 306. In some embodiments, one or more etchings may be dry reactive ion etchings. In some embodiments, one or more etchings may be wet etchings. Different etchants can have selectivity for different layers, so that when an etchant is used, it primarily etches the target layer rather than other layers exposed to etching. For example, fluorine etching used on the TEOS layer of dielectric layer 308 can selectively etch the TEOS layer rather than the dielectric film 310. The etching selectivity can result in etching of the target layer at a ratio of about 1.5:1 or higher compared to one or more other layers, and this ratio can be about 1.6:1 or higher, about 1.7:1 or higher, about 1.8:1 or higher, about 1.9:1 or higher, about 2.0:1 or higher, about 2.1:1 or higher, about 2.2:1 or higher, about 2.3:1 or higher, about 2.4:1 or higher, about 2.5:1 or higher, about 2.6 or higher, about 2.7:1 or higher, about 2.8:1 or higher, about 2.9:1 or higher, about 3.0:1 or higher, or higher.

[0033]

[0036] In operation 210, the method of forming the first structure 301 in flowchart 200 may include filling the features with a metal-containing material. As shown in Figure 3C, the structure 300 may include a metal-containing material 322 within a trench 320. The metal-containing material 322 may be a highly conductive material that can be used as an interconnect between integrated circuits. In some examples, the metal in the metal-containing material 322 includes copper, such that the metal-containing material 322 is a copper-containing material. The metal used to fill the features may include copper or any other highly conductive metal. Although copper is discussed periodically in this application, it should be understood that any number of conductive metallic materials may be used in embodiments of the Art, and the Art should not be limited to any particular conductive metallic material.

[0034]

[0037] In some embodiments, a liner is formed in the trench before the trench is filled with the metal-containing material. As shown in Figure 3C, the structure 300 may include a liner 324 in the trench 320 such that the liner is present in the trench 320 between the dielectric layer 308 and the metal-containing material 322. In some embodiments, the liner 324 may be tantalum nitride or any other suitable liner material incorporated to limit or prevent the diffusion of metal into the dielectric material.

[0035]

[0038] In some embodiments, after the features are filled with the metal-containing material 322, the first structure 301 may be polished via a chemical mechanical polishing (CMP) process, as described more specifically herein in relation to Figures 4 and 5A–5E and as described in U.S. Patent Application No. 17 / 411,599, the entire process of which is incorporated herein by reference. After the first structure 301 has been polished via the CMP process, the upper surface of the metal-containing material 322 may be recessed relative to the upper surface of the dielectric film 310, for example, as shown in Figure 3C. The CMP process may cause the upper surface of the metal-containing material 322 to form a recessed or dished shape, which may be characterized by a nadia or dish depth, which is the difference in height between the lowest point in the metal and the surface in the dielectric material where the features are formed, or the difference in edge height of the metal within the features. If the depth of the recess from the upper surface of the metal-containing material 322 to the upper surface of the dielectric film 310 combined with the nadia or dish depth (referred to as the combined depth) is too large, the material may not be useful for a particular end product. For example, copper-to-copper hybrid junctions are one such application that can be sensitive to inaccurate composite depths. In some applications of copper-copper hybrid junctions, if the composite depth is too large, the copper-copper bond may not be strong enough, or may not form at all, due to limited contact between the mating feature and the stud. A composite depth of less than 5 nm may be small enough for, for example, copper-to-copper hybrid junctions.

[0036]

[0039] In some embodiments, the liner 324 may be polished by CMP so that its upper surface aligns with the upper surface of the dielectric layer 308. In some embodiments, the liner 324 may be polished via the CMP process so that its upper surface aligns with the upper surface of the metal-containing material 322, as shown in Figure 3C. In some embodiments, the liner 324 may be polished via the CMP process so that its upper surface is recessed relative to the upper surface of the dielectric layer 308 and protrudes relative to the upper surface of the metal-containing material 322.

[0037]

[0040] In some examples, the method of flow chart 200 may further include bonding the first structure 301 to the second structure 331 via a hybrid bond, as shown in Figure 3E. In some embodiments, the second structure 331 is similar to the first structure 301 in the layout, layers, and materials used. The second structure 331 may include a second metal layer 334 covering the second substrate 332. The second metal layer 334 may be similar to the metal layer 304 so that all descriptions of the metal layer 304 are applicable to the second metal layer 334. The second substrate 332 may be similar to the substrate 302 so that all descriptions of the substrate 302 are applicable to the second substrate 332. The second structure 331 may further include a second dielectric layer 338 superimposed on the second metal layer 334, defining a second set of one or more features within the second dielectric layer 338. The second dielectric layer 338 of the second structure 331 can be similar to the dielectric layer 308 of the first structure 301, so that all descriptions of the dielectric layer 308 are applicable to the second dielectric layer 338. In some embodiments, the second structure 331 may include a second barrier film 336 between the second dielectric layer 338 and the second metal layer 334. The second barrier film 336 can be similar to the barrier film 306, so that all descriptions of the barrier film 306 are applicable to the second barrier film 336. The second structure 331 may include a second dielectric film 340 covering the second dielectric layer 338. The second dielectric film 340 can be similar to the dielectric film 310, so that all descriptions of the dielectric film 310 are applicable to the second dielectric film 340. In some embodiments, the material used for the dielectric film 310 is the same material used for the second dielectric film 340. The second structure 331 may include a second metal-containing material 354 deposited within a second set of one or more features. The second metal-containing material 354 may be similar to the metal-containing material 322, such that all descriptions of the metal-containing material 322 are applicable to the second metal-containing material 354. In some embodiments, the material used for the metal-containing material 322 is the same material used for the second metal-containing material 354. In some embodiments, the second dielectric film 340 does not overlap with the second metal-containing material 354.In some embodiments, the second structure 331 may include the second liner 354 within a second set of one or more features, such that the second liner 354 lies between a second set of one or more features in the second dielectric layer 338 and the second metal-containing material 354. The second liner 354 may be similar to the liner 324, such that all descriptions of the liner 324 are applicable to the second liner 354. In some embodiments, the first structure 301 may be considered hybrid-bonded to the second structure 331. In some embodiments, the dielectric film 310 may be considered hybrid-bonded to the second dielectric film 430. In some embodiments, the metal-containing material 322 may be considered hybrid-bonded to the second metal-containing material 354.

[0038]

[0041] In some embodiments, bonding the first structure 301 to the second structure 331 may involve using a surface activation process on the first structure 301 and / or the second structure 331. The surface activation process may involve contacting the first structure 301 and / or the second structure 331 with a hydrogen-containing precursor. The surface activation process can activate the upper surface of the dielectric film 310 of the first structure 301 and / or the upper surface of the second dielectric film 340 of the second structure 331 such that one or both of its surfaces are hydroxylated to have dangling hydroxyl groups. In some embodiments, water is then applied to the upper surface of the dielectric film 310 of the first structure 301 and / or the upper surface of the second dielectric film 340 of the second structure 331.

[0039]

[0042] Next, the upper surface of the dielectric film 310 of the first structure 301 and the upper surface of the second dielectric film 340 of the second structure 331 can be aligned and brought into contact. When the upper surface of the dielectric film 310 comes into contact with the upper surface of the second dielectric film 340, spontaneous bonding occurs mainly via van der Waals coupling, establishing an initial junction between the upper surface of the dielectric film 310 and the upper surface of the second dielectric film 340. As a result, the first structure 301 and the second structure 331 are joined to each other through the contact between the upper surface of the dielectric film 310 and the upper surface of the second dielectric film 340. The initial junction between the first structure 301 and the second structure 331 may not be the final junction, but it can be used to align the first structure 301 and the second structure 331 when additional processes are performed to finalize the hybrid junction.

[0040]

[0043] The combined structure of the first structure 301 and the second structure 331 can then be annealed. During the annealing operation, the dielectric film 310 and the second dielectric film 340 may further form oxide-oxide covalent bonds that enhance the bonding strength between the dielectric film 310 and the second dielectric film 340. In some embodiments, water and / or dangling hydroxyl groups help to form oxide-oxide covalent bonds between the dielectric film 310 and the second dielectric film 340. Because the dielectric constants of the dielectric film 310 and the second dielectric film 340 are high (e.g., 7 or higher, or 9 or higher, as described herein), the covalent bond between the upper surface of the dielectric film 310 and the upper surface of the second dielectric film 340 is very strong. The strength of the covalent bond makes it possible to use a lower ratio of surface area between the dielectric film 310 and the second dielectric film 340 than in conventional hybrid bonding techniques. Once an oxide-oxide covalent bond is formed between the dielectric film 310 and the second dielectric film 340, the junction between the dielectric film 310 and the second dielectric film 340 may be indistinguishable from the junction within the dielectric film 310 and / or the second dielectric film 340. Because the dielectric film 310 and the second dielectric film 340 have high dielectric constants (e.g., 7 or more or 9 or more as described herein), the junction strength between the dielectric film 310 and the second dielectric film 340 may be more than twice as strong as the junction strength between conventional dielectric layers that are hybrid-bonded to each other. For example, the junction strength between the aluminum oxide dielectric film 310 and the aluminum oxide second dielectric film 340 may be more than twice as strong as the junction strength between conventional dielectric layers (such as silicon oxide) that are hybrid-bonded.

[0041]

[0044] Annealing of the combined structure can also push the metal-containing material 322 toward the second metal-containing material 354. As previously mentioned, the combined depth of the metal-containing material 322 (and by extension of the second metal-containing material 354) is important for bonding the metal-containing materials. If the combined depth is 5 nm or less, the subsequent annealing for bonding the metal-containing material 322 and the second metal-containing material 354 may be effective because the metal-containing material 322 and the second metal-containing material 354 can come close enough to bond to each other during the annealing step of the hybrid bond. During the annealing step, the metal-containing materials from the two structures can be pushed toward each other, come into contact with each other, and bond. With the reduced annealing temperature according to some embodiments of this technique, the amount of expansion may be insufficient to enable proper bonding between coppers unless dishing is sufficiently reduced. By performing a polishing operation according to this technique, dishing can be reduced, thereby improving the bonding ability between substrates at reduced annealing temperatures.

[0042]

[0045] Once the annealing process is complete, the first structure 301 and the second structure 331 are hybrid-junctioned to form a single semiconductor device or a single structure. Using hybrid junctions makes it possible to manufacture complex semiconductor devices from multiple structures and to form interconnections between them.

[0043]

[0046] Figure 4 shows an exemplary flow chart of operations in the chemical mechanical polishing method 400 according to several embodiments of the present technology. Method 400 can be performed in various processing chambers including polishing systems, as well as in any other chambers, such as the chamber incorporated into the system 100 described above. Method 400 may include one or more operations, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that can be performed before the operations described, prior to the commencement of Method 400. Method 400 may include a number of optional operations, which may or may not be specifically associated with some embodiments of the method according to embodiments of the present technology. Method 400 can illustrate the operations schematically shown in Figures 5A to 5E, and the illustrations will be described in conjunction with the operations of Method 400. The figures show only partial schematics, and it should be understood that the substrate 505 may include any number of additional materials and features having various properties and embodiments, as shown in the figures.

[0044]

[0047] It should be understood that the specific steps shown in Figure 4 provide a specific method of chemical mechanical polishing according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. Furthermore, the individual steps shown in Figure 4 may include multiple substeps, which may be performed in various sequences depending on the individual steps. In addition, additional steps may be added or removed depending on the specific application. Many variations, modifications, and alternatives are also included in the scope of this disclosure.

[0045]

[0048] Method 400 may or may not include optional operations for developing a semiconductor structure in a particular polishing operation, such as one or more semiconductor processing operations that develop one or more layers of material on a substrate and clamp the substrate to a carrier head of a polishing system. It should be understood that Method 400 can be performed on any number of semiconductor structures or substrates 505 (e.g., substrate 302, dielectric layer 308, and / or metal layer 304 in Figure 3A), as shown in Figure 5A, including an exemplary structure 500 (e.g., first structure 301 in Figure 3A) on which a dielectric film 510 (e.g., dielectric film 310 in Figure 3A), a liner 515 (e.g., liner in Figure 3C), and a copper-containing layer 520 (e.g., metal-containing layer 322 in Figure 3C) may be formed. While the dielectric film 510 will be described periodically in the following description, it should be understood that the technique should not be limited to any specific dielectric material on which features may be formed, as the following description can also be applied to any dielectric of the dielectric layer 308 described in relation to Figure 3A. In the following description, the copper-containing layer will be mentioned periodically, but any number of metal-containing materials may be used in embodiments of this technology, and it should be understood that this technology should not be limited to any specific metal-containing material on which features can be formed. As shown in Figure 5A and described in relation to Figure 3B, the dielectric film 510 may be processed to form one or more recesses or features such as trenches, openings or vias, or any other structures useful for semiconductor processing. The substrate 505 may be any number of materials, such as a base wafer or substrate 505 made from silicon or a silicon-containing material, or other substrate materials. For example, in some embodiments, the substrate may be processed to include one or more materials or structures for semiconductor processing, such as the dielectric film 510, the liner 515, and the copper-containing layer 520. Although only two features are shown in the figure, it should be understood that the exemplary structure may have any number of features defined along the structure according to embodiments of this technology.

[0046]

[0049] In some embodiments, method 400 may include, in an optional operation 402, providing the substrate 505 to a polished assembly such as the substrate 505 shown in Figure 5A. The substrate 505 may include a dielectric film 510 defining one or more recessed features from the surface of the dielectric film 510, a liner 515 extending across the dielectric film 510 and dielectric layers (e.g., dielectric layer 308) and one or more features, and a copper-containing layer 520 deposited on the liner 515 and extending across one or more features. In some embodiments, the liner 515 may be tantalum nitride, or any other suitable liner material incorporated to limit or prevent the diffusion of metal into the dielectric film, dielectric layers, or other dielectric materials. As described above, the dielectric film 510, the liner 515, and the copper-containing layer 520 may be formed by any number of processing techniques that can be performed to develop the substrate and produce the described structure.

[0047]

[0050] As will be explained in more detail below, during polishing in Method 400, the overall removal rate of metals such as the copper-containing layer 520 may be greater than the removal rate of dielectric materials such as the dielectric film 510 when using a metal-selective slurry. In addition, the dielectric-selective slurry may also cause some removal of metal when exposed to the polishing pad and slurry. Furthermore, the removal rate within the copper-containing layer 520 may be greater towards the center of the copper in one or more features, since this copper may be a softer bulk material. If this removal rate is too fast, a concave or dished shape may be formed in the copper during polishing. As mentioned above, in polishing processes for copper-to-copper hybrid bonding applications, too much dishing may be considered a defect. The concave or dished shape may be characterized by a nadia or dish depth, which is the difference in height between the lowest point in the metal and the surface on which the feature is formed in the dielectric material, or the difference in edge height of the metal within the feature. If the nadia or dish depth is too large, the material may not be useful for certain end products. For example, copper-to-copper hybrid bonding is one such application that can be sensitive to inaccurate nadia or dish depths. In some applications of copper-to-copper hybrid bonding, if the nadia or dish depth is too large, contact with the studs from the mating features may be limited, resulting in insufficient or no copper-to-copper bonding at all. In these applications, the substrate 505 having the copper-containing layer 520 may be in contact with a secondary substrate for mating between the trailing ends of the line process and before the annealing operation. Dielectric material on each substrate 505, such as a dielectric film 510, may be in contact with the dielectric material of the other substrate so that two separate substrates bond to one structure. During the annealing operation, the dielectric materials may form oxide-oxide covalent bonds. The copper-containing layer 520 of the mating substrate may also be extruded to contact the copper-containing layer 520 of the substrate 505. If the depth of the nadia or dish is too great, the copper-containing layer 520 may be too recessed to connect with the copper studs and make contact with other copper-containing layers during the annealing operation.

[0048]

[0051] After providing the substrate 505 to the polishing assembly, operation 404 allows the substrate 505 to be brought into contact with the first slurry. As used throughout this disclosure, contacting the substrate 505 with the slurry can result in a chemical operation that polishes the substrate 505, so contact can be used interchangeably with polishing. In some embodiments, in operation 404, method 400 may include bringing the substrate 505 into contact with a first platen in addition to the first slurry. In some embodiments, by bringing the substrate 505 into contact with the first slurry and the first platen, a first portion of the copper-containing layer 520 can be removed. Operation 404 can remove the first portion of the copper-containing layer 520 so that the copper-containing layer 520 can be recessed beneath the liner 515, which allows for complete isolation of the copper region across the substrate 505 and ensures that the metal does not connect discontinuous regions of copper across the substrate. By removing the first portion of the copper-containing layer 520, individual copper plugs within the copper-containing layer 520 can be isolated. A copper plug may refer to a portion of the copper-containing layer 520 extending into one or more features. The first slurry may be selective for copper, and even if the copper-containing layer 520 is removed, a considerable amount of the liner 515 may not be removed. Therefore, operation 404 may remove the copper-containing layer 520 such that the liner 515 can be at least partially exposed, and the copper-containing layer 520 can be recessed to expose the liner 515 across the surface of the substrate and / or one or more features of the dielectric film 510, as shown in Figure 5B.

[0049]

[0052] In operation 406, the substrate 505 may come into contact with the second slurry. In some embodiments, in operation 406, method 400 may include bringing the substrate 505 into contact with a second platen in addition to the second slurry. In some embodiments, the second slurry and the second platen may remove at least a portion of the liner 515 and / or a first portion of the dielectric film 510. The second slurry may be selective in removing the liner 515 and may not remove a considerable amount of the copper-containing layer 520. The second slurry is selective for oxide and nitride materials and removes the liner and / or oxide material in a ratio of about 1.5:1 or higher compared to copper, the ratio of which may be about 1.6:1 or higher, about 1.7:1 or higher, about 1.8:1 or higher, about 1.9:1 or higher, about 2.0:1 or higher, about 2.1:1 or higher, about 2.2:1 or higher, about 2.3:1 or higher, about 2.4:1 or higher, about 2.5 or higher, about 2.6:1 or higher, about 2.7:1 or higher, about 2.8:1 or higher, about 2.9:1 or higher, about 3.0:1 or higher, or higher. The second slurry may remove any portion of the liner 515 that may be exposed after operation 404. That is, the portion of the liner 515 between the dielectric film 510 and the first portion of the copper-containing layer 520, for example, the portion of the copper-containing layer 520 removed in operation 404, may be removed during operation 406. Since a portion of the liner 515 can be removed, the copper-containing layer 520 may protrude above the dielectric film 510 based on the selectivity of the removal, as shown in Figure 5C.

[0050]

[0053] After the substrate 505 has come into contact with the second slurry, in operation 408, the substrate 505 may come into contact with a third slurry. In some embodiments, in operation 408, method 400 may include bringing the substrate 505 into contact with a third platen in addition to the third slurry. The third slurry, and in some embodiments the third platen, may remove at least a second portion of the copper-containing layer 520. The third slurry may be selective in removing the copper-containing layer 520 and may not remove a substantial amount of the dielectric film 510. In some embodiments, the third slurry may remove a second portion of the copper-containing layer 520 that may be exposed after operations 404 and 406. That is, the copper-containing layer 520 protruding above the dielectric film 510 may be removed during operation 408 so that the copper-containing layer 520 may be recessed beneath the dielectric film 510, as shown in Figure 5D. Operation 408 may be performed at a higher pressure than operation 404 or operation 406. This higher pressure may result in faster removal of the softer bulk copper from the center of one or more features of the substrate 505. This faster removal may result in dishing occurring in the copper-containing layer 520, as shown in the figure. In some embodiments, the third slurry may be the same as the first slurry. Additionally or alternatively, the third platen may be the same as the first platen.

[0051]

[0054] During contact between the substrate 505 and the third slurry, the copper-containing material 520 may be intentionally recessed beneath the dielectric film 510. Intentionally creating a recess or dishing of the copper-containing material 520 to a level below that is suitable for a copper-to-copper hybrid junction is preferable because it is possible to extend the duration of operation 410 and to have greater control over the duration of operation 410. For example, if the copper-containing material 520 is only slightly recessed beneath the dielectric film 510, the duration of operation 410 will be very short, and undesirable, larger-than-ideal dishing of the copper-containing material 520 may occur inadvertently, potentially leading to uniformity issues or material etching. If the copper-containing material 520 is excessively recessed beneath the dielectric film 510, operation 410 may take longer and be a slower process, which allows for finer control over the final nadia or dish depth.

[0052]

[0055] Following operation 408, the copper-containing layer 520 may be characterized by a concave profile within one or more features of the dielectric film 510. The copper-containing layer 520 may be additionally or alternatively characterized by a dish profile having a dish depth. After operation 408, the lower limit of the dish depth of the concave profile or dish profile may be about 5 nm or more within the surface of the dielectric film 510, and it may be about 6 nm or more, about 7 nm or more, about 8 nm or more, about 9 nm or more, about 10 nm or more, about 6 nm or more, about 11 nm or more, about 12 nm or more, about 13 nm or more, about 14 nm or more, about 15 nm or more, or more.

[0053]

[0056] Nadia or dish depths exceeding 5 nm may be too large for, for example, copper-to-copper hybrid bonding. If the nadia or dish depth is approximately 5 nm or greater, the copper may be too far apart, making subsequent annealing ineffective for bonding separate copper elements. While separate copper elements may be pushed toward each other during annealing, if the nadia or dish depth is too great, the copper elements will not bond to one another. If the nadia or dish depth is too small, the dielectric materials of the substrate 505 will not be able to bond sufficiently to each other, causing the copper to protrude from one or both sides of the substrate 505. Furthermore, the temperature during annealing may be limited by other components on the substrate 505, such as gallium nitride, which may have a thermal limit of approximately 400°C. This thermal limit can prevent annealing from occurring at temperatures much higher than approximately 400°C. Performing bonding at lower temperatures can also reduce the amount of thermal expansion, further limiting copper expansion and bonding between copper materials. Therefore, additional processing may be required to fine-tune the depth of the nadia or dish of the copper-containing layer 520 so that copper-to-copper bonds can be formed when separate copper elements of the two substrates 505 come into contact.

[0054]

[0057] In operation 410, the substrate 505 may come into contact with the fourth slurry. In some embodiments, in operation 410, method 400 may include bringing the substrate 505 into contact with the fourth platen in addition to the fourth slurry. In some embodiments, the fourth slurry and the fourth platen may remove at least a second portion of the dielectric film 510. In some embodiments, the fourth slurry may be selective in removing the dielectric film 510 and may not remove a substantial amount of the copper-containing layer 520. By bringing the substrate 505 into contact with the fourth slurry and the fourth platen, a third portion of the copper-containing layer 520 may be further removed. In operation 410, the copper-containing material 520 may be recessed so that the fourth slurry and the fourth platen do not immediately remove the copper-containing material 520. Instead, the fourth slurry and the fourth platen may remove only the dielectric film 510 until it is removed to a level close to the copper-containing material 520. Once the dielectric film 510 is removed to a level near the copper-containing material 520, the fourth slurry and the fourth platen may also remove the copper-containing material 520. The fourth slurry and the fourth platen may begin removing the copper-containing material 520 when the dielectric film 510 is about 2 nm or less (e.g., about 1 nm or less) higher than the copper-containing material 520. After operation 408, the fourth slurry may remove any dielectric film 510 that may extend above the copper-containing layer 520. That is, the dielectric film 510 above the copper-containing layer 520 may be removed during operation 410 such that the copper-containing layer 520 can be recessed below the dielectric film 510 by a smaller amount than in operation 408, as shown in Figure 5E. In some embodiments, the fourth slurry may be the same as the second slurry. Additionally or alternatively, the fourth platen may be the same as the second platen.

[0055]

[0058] Contact between the substrate 505 and the fourth slurry, and in some embodiments with the fourth platen, may be continued for a period of about 10 seconds or longer. A period of about 10 seconds or longer may allow for fine-tuning of the process to remove a desired amount of dielectric film 510 so that the concave profile of the dish profile of the copper-containing layer 520 or the remaining nadia of the dish depth may be accurate. As will be further described below, accurate lower dimensions of the concave profile of the dish profile or the dish depth may be required for further processing and applications of the semiconductor substrate.

[0056]

[0059] In some embodiments, method 400 may include diluting the second slurry to form a fourth slurry. By diluting the second slurry to form the fourth slurry, the rate at which the dielectric film 510 is removed when the substrate 505 comes into contact with the fourth slurry can be controlled. The fourth slurry may be diluted before operation 410 or on the platen during operation 410. The fourth slurry may be characterized by a slurry concentration of about 50% or less of the second slurry, about 47% or less of the second slurry, about 45% or less of the second slurry, about 43% or less of the second slurry, about 40% or less of the second slurry, about 37% or less of the second slurry, about 35% or less of the second slurry, about 33% or less of the second slurry, or a lower slurry concentration. Similar to the removal selectivity between the dielectric film 510 and copper described above, the fourth slurry is a diluted version of the second slurry and can remove the dielectric film 510 and the copper-containing layer 520 in a ratio in which the concave profile or dish-shaped depth of the dish-shaped profile of the copper-containing layer 520 can be sufficiently accurate for the subsequent copper-to-copper hybrid junction.

[0057]

[0060] Diluting the fourth slurry may reduce the removal selectivity between the dielectric film 510 and copper. By diluting the fourth slurry, the removal selectivity between the dielectric film 510 and copper may decrease to about 2:1 or less, and the removal selectivity between the dielectric film 510 and copper may decrease to about 1.9:1 or less, about 1.8:1 or less, about 1.7:1 or less, about 1.6:1 or less, about 1.5:1 or less, about 1.4:1 or less, about 1.3:1 or less, about 1.2:1 or less, about 1.1:1 or less, or less, possibly 1.1:1 or less. A removal selectivity of about 2:1 or less between the dielectric film 510 and copper allows the fourth slurry to remove the dielectric film 510 and the copper-containing layer 520 at a sufficiently slow rate, thereby reducing copper dishing by slowly removing oxides and edge metal materials during the removal operation. As shown in Figure 4, the more the fourth slurry is diluted, the lower the removal selectivity may become. The removal selectivity between the dielectric film 510 and copper being approximately 2:1 or less may allow the fourth slurry to remove the dielectric film 510 and the copper-containing layer 520 at a speed such that the concave profile of the dish profile of the copper-containing layer 520 or the nadia of the dish depth can have sufficient precision for the subsequent copper-to-copper hybrid junction.

[0058]

[0061] Referring again to Figure 4, during operation 410, the dielectric film 510 can be etched or removed at an etching rate of approximately 15 nm per minute or less by bringing the substrate 505 into contact with the fourth slurry. The etching rate is slow enough for the fourth slurry to remove the dielectric film 510 at a rate slow enough to control the final nadia or dish depth of the copper-containing layer 520, which may result in the structure being usable in a variety of applications, such as copper-to-copper hybrid junctions. By slowing down the removal of the dielectric film 510, the removal of the copper-containing layer 520 can also be slowed down. Slowing down the removal of the copper-containing layer 520 may help reduce the nadia or dish depth within the copper-containing layer 520, which may result in the material being usable in copper-to-copper hybrid junctions. The etching rate may be about 15 nm / min or less, and may be about 14 nm / min or less, about 13 nm / min or less, about 12 nm / min or less, about 11 nm / min or less, about 10 nm / min or less, about 9 nm / min or less, about 8 nm / min or less, about 7 nm / min or less, about 6 nm / min or less, about 5 nm / min or less, about 4 nm / min or less, about 3 nm / min or less, about 2 nm / min or less, or about 1 nm / min or less, or less. Again, the etching rate of silicon dioxide 510 in the embodiments of the present disclosure allows for fine-tuning of the removal of silicon dioxide 510, and the depth of the copper-containing layer 520 or dish depth can be preferably controlled depending on the final application of the structure. By slowly etching the dielectric film 510, the copper-containing layer 520 can also be etched more slowly. By etching the copper-containing layer 520 at a slower rate, the depth of the nadia or dish can be reduced, which makes the substrate 505 ideal for copper-to-copper hybrid junctions, as described herein.

[0059]

[0062] After operation 410, the copper-containing layer 520 may again be characterized by a concave profile or dish profile within one or more features of the dielectric film 510. After operation 410, the lower limit of the concave profile or the dish depth of the dish profile may be about 5 nm or less within the surface of the dielectric film 510, and may be about 4 nm or less, about 3 nm or less, about 2 nm or less, about 1 nm or less, about 0.5 nm or less, or less.

[0060]

[0063] Nadia or dish depths of less than 5 nm may be small enough for, for example, a copper-to-copper hybrid bond. When the nadia or dish depth is 5 nm or less, subsequent annealing may be effective for bonding separate copper elements because the coppers can come close enough to bond to each other during the annealing operation. During the annealing step, copper elements from separate substrates can be pushed toward each other, come into contact with each other, and bond. With the reduced annealing temperature according to some embodiments of this technique, the amount of expansion may be insufficient to allow for proper bonding between coppers unless the dishing is sufficiently reduced. By performing a polishing operation according to this technique, dishing can be reduced, thereby improving the bonding ability between substrates at reduced annealing temperatures.

[0061]

[0064] In some embodiments, various operations (e.g., operations 202, 204, 206, 208, 210, 402, 404, 406, 408, 410) and some of these operations can be performed in different chambers of system 100. When the substrate is moved from the first chamber to the second chamber, the substrate is moved without being exposed to the external atmosphere. For example, operation 206 for forming a dielectric film on a dielectric layer can be performed in a different chamber than operations 202 and 204 for forming the substrate, metal layer, and dielectric layer. The use of different chambers may relate to different conditions required for different operations. For example, chambers for etching dielectric layers and dielectric films may require special settings due to the special properties of the dielectric material used for the dielectric film. Similarly, the CMP processes described in relation to operations 402, 404, 406, 408, and 410 may be performed in a different chamber than operations 202, 204, and 206.

[0062]

[0065] As used herein, the terms “about,” “approximately,” and “substantially” should be interpreted as being within the range expected by those skilled in the art in light of this specification.

[0063]

[0066] In the above description, for the sake of clarity and to provide a complete understanding of various embodiments, numerous specific details have been included. However, it will be apparent that some embodiments can be carried out without some of these specific details. In other examples, well-known structures and devices are shown in the form of block diagrams.

[0064]

[0067] The above description provides only illustrative embodiments and does not limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments provides a feasible disclosure for implementing at least one embodiment. It should be understood that various modifications may be made to the function and arrangement of the elements without departing from the spirit and scope of some embodiments, as described in the appended claims.

[0065]

[0068] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be understood that embodiments can be carried out even without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0066]

[0069] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe operations as sequential processes, many operations can be performed in parallel or simultaneously. Moreover, the order of operations may be rearranged. A process terminates when an operation is completed, but there may be additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function's return to the calling function or main function.

[0067]

[0070] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0068]

[0071] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. If implemented by software, firmware, middleware, or microcode, program code or code segments for performing the required tasks may be stored in a machine-readable medium. One or more processors may perform the required tasks.

[0069]

[0072] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments may be used individually or collectively. Furthermore, embodiments may be used in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, this specification and the drawings should be considered illustrative, not limiting.

[0070]

[0073] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be understood that the method described above may be performed by hardware components or embodied by a sequence of machine-executable instructions, which can be used to cause a machine (e.g., a general-purpose or special-purpose processor, or a logic circuit programmed with instructions) to perform the method. These machine-executable instructions may be stored in one or more machine-readable media (e.g., CD-ROM or other types of optical disks, floppy diskettes, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions). Alternatively, the method may be implemented by a combination of hardware and software.

Claims

1. A semiconductor device for hybrid bonding, The first structure, A metal layer covering the substrate, The dielectric layer covers the metal layer and defines one or more recessed features within the dielectric layer, A dielectric film covering the dielectric layer and having a dielectric constant greater than approximately 7, The copper-containing material deposited within the set of one or more features The first structure including Semiconductor devices including [this].

2. The second structure is, A second metal layer covering the second substrate, The second dielectric layer covers the second metal layer and defines a second set of one or more recessed features in the second dielectric layer, A second dielectric film covering the second dielectric layer and having a second dielectric constant greater than approximately 7, A second copper-containing material deposited within a second set of one or more features The second structure includes The semiconductor device according to claim 1, further comprising the dielectric film of the first structure being hybrid-bonded to the second dielectric film of the second structure, and the copper-containing material of the first structure being in contact with the second copper-containing material of the second structure.

3. The semiconductor device according to claim 1, wherein the dielectric constant is greater than about 8.

4. The semiconductor device according to claim 1, wherein the dielectric film has a thickness of 5 nm.

5. The dielectric film is Al ２ O ３ The semiconductor device according to claim 1.

6. The semiconductor device according to claim 1, wherein the copper-containing material is characterized by a dish profile having a dish depth of about 1 nm or less.

7. A method for forming a semiconductor device, To form a first structure, and to form the above first structure is Forming a metal layer on a substrate, Forming a dielectric layer on the aforementioned metal layer, A dielectric film having a dielectric constant greater than approximately 7 is formed on the dielectric layer, Etching trenches within the dielectric film and the dielectric layer, wherein the trenches extend downward from the upper surface of the dielectric film to at least the upper surface of the metal layer. The trench is filled with a copper-containing material. Methods that include...

8. The method according to claim 7, wherein etching the dielectric film and the trenches in the dielectric layer includes etching the trenches in the dielectric film using chlorine-based etching.

9. The method according to claim 7, wherein etching the dielectric film and the trenches in the dielectric layer includes etching the dielectric film and the trenches in the dielectric layer using multi-material etching, wherein the multi-material etching includes two or more of chlorine-based etching, fluorine-based etching, oxygen plasma etching, and fluorine and oxygen-based etching.

10. The method according to claim 7, wherein forming the metal layer and forming the dielectric layer is performed in a first chamber, etching the trenches in the dielectric film and the dielectric layer is performed in a second chamber, and the first structure is moved from the first chamber to the second chamber without exposing the substrate to the external atmosphere.

11. The method according to claim 7, further comprising bringing the first structure into contact with one or more slurries and one or more platens, wherein the one or more slurries and one or more platens remove a portion of the copper-containing material and a second portion of the dielectric film.

12. The method according to claim 11, wherein the copper-containing material is recessed into the trench below the upper surface of the dielectric film by a distance of about 1 nm or less by bringing the first structure into contact with the one or more slurries and one or more platens.

13. The method according to claim 12, wherein the copper-containing material is characterized by a dish profile by bringing the first structure into contact with the one or more slurries and one or more platens.

14. The method according to claim 7, further comprising forming a liner in the trench, and filling the trench with the copper-containing material, comprising covering the liner with the copper-containing material.

15. Contacting the above-mentioned first structure with a hydrogen-containing precursor, The first structure is brought into contact with the second structure, wherein the second structure is A second metal layer covering the second substrate, The second dielectric layer covers the second metal layer and defines a second set of one or more features within the second dielectric layer, A second dielectric film covering the second dielectric layer and having a second dielectric constant greater than approximately 7, A second copper-containing material deposited within a second set of one or more features, Including contact, The first structure is joined to the second structure, wherein the dielectric film of the first structure is hybrid-bonded to the second dielectric film of the second structure, and the copper-containing material of the first structure is in contact with the second copper-containing material of the second structure. The method according to claim 7, further comprising:

16. Joining the first structure to the second structure Bringing the above-mentioned first structure into contact with water, Annealing the first structure and the second structure The method according to claim 15, including the method described in claim 15.

17. A method for forming a semiconductor device, To form the first structure, Forming a metal layer on a substrate, A barrier film having a dielectric constant of approximately 5 or less is formed on the aforementioned metal layer. Forming a tetraethyl orthosilicate layer on the barrier film, A dielectric film having a second dielectric constant greater than 7 is formed on the tetraethyl orthosilicate layer, Etching trenches within the dielectric film, the tetraethyl orthosilicate layer, and the barrier film, wherein the trenches extend downward from the upper surface of the dielectric film to at least the upper surface of the metal layer. Forming a liner in the trench, The trench is filled with a copper-containing material. Forming a first structure including A method that includes this.

18. The above-mentioned first structure is brought into contact with a hydrogen-containing precursor, The first structure is brought into contact with the second structure, wherein the second structure is A second metal layer covering the second substrate, A second barrier film on the second metal layer, having a third dielectric constant of about 5 or less, and defining a second set of one or more features, A second tetraethyl orthosilicate layer on the second barrier film further defines a second set of the one or more features, A second dielectric film covering the second tetraethyl orthosilicate layer, having a fourth dielectric constant greater than about 7, and further defining a second set of the one or more features, A second copper-containing material deposited within a second set of one or more features, Including bringing the first structure into contact with the second structure, The first structure is joined to the second structure, wherein the dielectric film of the first structure is hybrid-bonded to the second dielectric film of the second structure, and the copper-containing material of the first structure is in contact with the second copper-containing material of the second structure. The method according to claim 17, further comprising:

19. Joining the first structure to the second structure Bringing the above-mentioned first structure into contact with water, Annealing the first structure and the second structure The method according to claim 18, including the method described in claim 18.

20. The method according to claim 18, wherein the second dielectric constant is greater than about 8 and the fourth dielectric constant is greater than 8.

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