Power semiconductor devices containing beryllium metal coatings

Abstract

Semiconductor devices and methods are provided. In one example, the semiconductor device includes an active region containing one or more active semiconductor cells. The semiconductor device includes a metal film structure on the active region. The metal film structure contains beryllium. The metal film structure further contains copper. The metal film structure further contains aluminum.

Description

Detailed Description of the Invention

[0001] [Claiming Priority] This application claims the benefit of priority based on U.S. Patent Application No. 18 / 304,869, filed on April 21, 2023. This application claims the priority and benefit of the cited application and incorporates its entire content by reference.

[0002] [Field] The present disclosure generally relates to power semiconductor devices.

[0003] [Background] A wide variety of power semiconductor devices are known in the art, including, for example, power metal-oxide-semiconductor field-effect transistors ("MOSFETs"), insulated-gate bipolar transistors ("IGBTs"), and various other devices. These power semiconductor devices are often manufactured from wide-bandgap semiconductor materials such as silicon carbide or gallium nitride-based materials. In the specification, the term "wide-bandgap semiconductor" encompasses any semiconductor having a bandgap of at least 1.4 eV. Power semiconductor devices are designed to selectively block or pass large voltages and / or currents. For example, in the blocking state, a power semiconductor device may be designed to maintain a potential of hundreds or thousands of volts.

[0004] [Summary] Aspects and advantages of embodiments of the present disclosure are shown in part in the following description, can be learned from the description, or can be learned through the implementation of the embodiments.

[0005] One exemplary aspect of the present disclosure is directed to a semiconductor device. The semiconductor device includes an active region that includes one or more active semiconductor cells. The semiconductor device includes a metal film structure over the active region. The metal film structure comprises beryllium.

[0006] Another exemplary aspect of this disclosure relates to a semiconductor device. The semiconductor device includes an active region comprising one or more silicon carbide-based MOSFETs. The semiconductor device includes a metal film structure on the active region. The metal film structure includes bonding pads associated with the gate contact, source contact, or drain contact of the semiconductor device. The metal film structure comprises beryllium.

[0007] Another exemplary aspect of this disclosure relates to a method, which involves depositing a metallic film structure on an active region comprising one or more wide-bandgap semiconductor cells. The metallic film structure comprises beryllium.

[0008] These and other features, aspects and advantages of various embodiments will be better understood by referring to the following description and appended claims. The appended drawings incorporated herein and forming part thereof illustrate embodiments of the present disclosure and, together with the description, illustrate the relevant principles.

[0009] With reference to the attached drawings, embodiments intended for those skilled in the art will be described in detail herein. [Brief explanation of the drawing]

[0010] [Figure 1] This is a perspective view of a semiconductor device including a metal coating structure according to an exemplary embodiment of the present disclosure. [Figure 2] This is a cross-sectional view of an exemplary semiconductor device including a metal coating structure according to an exemplary embodiment of the present disclosure. [Figure 3] This figure shows an exemplary metal coating structure for a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 4] This figure shows an exemplary metal coating structure for a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 5] Figure 4 is a cross-sectional view of a semiconductor device. [Figure 6] This figure shows an exemplary semiconductor package for a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 7] This figure shows an exemplary semiconductor package for a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 8] This is a flowchart of an exemplary method according to an exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] Herein, embodiments are referred to in detail. One or more examples of embodiments are shown in the drawings. Each example is provided for the purpose of describing an embodiment and is not intended to limit the disclosure. In practice, it will become apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the scope or spirit of the disclosure. For example, features illustrated or described as part of one embodiment can be used in conjunction with another embodiment to obtain further embodiments. For this reason, aspects of the disclosure are intended to cover such modifications and variations.

[0012] Exemplary embodiments of this disclosure relate to semiconductor devices, and more particularly to semiconductor devices having a metal film structure containing beryllium, such as a beryllium alloy. As used herein, the term "alloy" refers to a mixture of metallic elements.

[0013] A “metal film structure” is any layer, structure, or other part of a semiconductor device, semiconductor die, or semiconductor package that incorporates metal for thermal and / or electrical conduction. A “metal film structure” may include, for example, contacts, interconnects, bonding pads, backside metal films, metal layers, or metal coatings.

[0014] A semiconductor device may include, for example, a semiconductor die. The semiconductor die may include one or more active regions of a semiconductor and one or more metal film structures. The active regions may include one or more active semiconductor cells having individual "unit cell" semiconductor devices such as MOSFETs, Schottky diodes, and high electron-mobility transistor devices (HEMTs). The semiconductor die may be placed in a semiconductor package. The semiconductor package may include, for example, a housing (e.g., an epoxy molded compound (EMC)), a submount such as a lead frame, and a connection structure between the semiconductor die and the submount (e.g., a die attach material and / or wire bond). In some examples, a passivation layer (e.g., a silicon nitride and / or polyimide passivation layer) may be placed on the semiconductor die.

[0015] The semiconductor die may be based on a wide-bandgap semiconductor material. The wide-bandgap semiconductor material has a bandgap greater than approximately 1.40 eV and is silicon carbide and / or Group III nitrides (e.g., gallium nitride). For example, in some examples, the active semiconductor cell may include one or more silicon carbide-based MOSFETs. In some examples, the active semiconductor cell may include one or more silicon carbide-based Schottky diodes. In some examples, the active semiconductor cell may include one or more Group III nitride-based transistor devices, such as gallium nitride-based high-electron-mobility transistor devices. The active semiconductor cell may include other devices, such as other wide-bandgap semiconductor devices, without departing from the scope of this disclosure.

[0016] A metal film structure in a semiconductor device may be used to provide, for example, electrically conductive connections and / or thermally conductive connections to the active region of the semiconductor device. The metal film structure may include, for example, one or more contacts, interconnects, bonding pads, backside layers, metal layers, or metal coatings of the semiconductor device.

[0017] Power semiconductor devices may experience anomalies and / or failures due to deformation, delamination, shift, or movement (e.g., glacial movement) of the copper and / or aluminum metal film structure. In addition, cracks in the passivation layer of power semiconductor devices may occur due to thermomechanical stress on the semiconductor die surface during different reliability tests, such as thermal cycling (TC). A mismatch in the coefficient of thermal expansion (CTE) between the EMC and different parts of the semiconductor die, and the high-temperature flexural modulus of the EMC, can induce shear stress from the edge to the center of the semiconductor die, leading to deformation, delamination, and / or ratcheting of the metal film structure. This can consequently stress the passivation layer, ultimately inducing defects or cracks in the passivation layer.

[0018] In some power semiconductor device packages, aluminum-copper alloys have been introduced into the metal coating structure as an alternative metal coating material to aluminum. Aluminum-copper alloys may exhibit slightly higher resistance to metallic deformation and higher resistance to metallic corrosion in the presence of ionic impurities. However, metal coating structures based on aluminum-copper alloys may suffer from residual stress, thermal stress relaxation, and accelerated galvanic corrosion of aluminum, particularly at interfaces with connecting structures such as wire bonds. Furthermore, CTE mismatch between the metal coating structure and other parts of the semiconductor die, including silicon nitride passivation layers or other passivation layers, remains a concern.

[0019] Aluminum-copper alloys are also vulnerable to damage in high-power wire bonding processes where thick aluminum wires (e.g., 15 mils or 20 mils) or copper wires are used to achieve higher allowable currents. This can induce further damage to the semiconductor die. The damage may be more pronounced in bonding pads having a smaller thickness (e.g., about 4 μm). On the other hand, an increased thickness of the metal coating pad (e.g., from about 5 μm to about 6 μm) may have adverse effects such as the risk of metal migration. Furthermore, the diffusion of copper into the semiconductor die when an aluminum copper alloy is used in the metal coating structure may cause reliability concerns.

[0020] According to an exemplary aspect of the present disclosure, a semiconductor device may include a metal coating structure. The metal coating structure may include beryllium. For example, in some embodiments, the metal coating structure may include a beryllium alloy. The metal coating structure may include copper and beryllium (e.g., a copper-beryllium alloy). The metal coating structure may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0021] In some examples, the metal coating structure may include a ternary beryllium alloy. The ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may include cobalt, thereby enhancing the microstructural stability of the metal coating structure.

[0022] In an exemplary aspect of the present disclosure, the metal coating structure may be an electrode / contact (e.g., a source, drain, and / or gate contact). In some examples, the metal coating structure may be an interconnect. In some examples, the metal coating structure may be a bonding pad (e.g., for wire bonding). In some examples, the metal coating structure may provide a backside metal coating or other metal coating layer.

[0023] In some examples, the mechanical and / or electrical properties of the metal film structure can be controlled and / or adjusted by the ratio of beryllium to other metals in the metal film structure. For example, the metal film layer may include from about 0.1% beryllium to about 3% beryllium, such as from about 0.2% beryllium to about 2% beryllium, such as from about 0.2% beryllium to about 0.1% beryllium, such as from about 0.2% beryllium to about 0.5% beryllium, such as about 0.5% beryllium.

[0024] Beryllium is a low-density metal with high thermal and electrical conductivity, high strength, high resistance to fatigue and corrosion, and low responsiveness to magnetic fields. Beryllium may also act as a CTE modulator. Beryllium alloys such as copper-beryllium alloys, aluminum-beryllium alloys, and ternary beryllium alloys can have highly stable tensile properties even at high temperatures (e.g., in the range of about 250 °C to about 300 °C). The mechanical stability of these alloys can remain intact over a wide temperature range and exhibit inherent resistance to thermal stress relaxation at high temperatures and during different reliability tests such as TC, high temperature reverse bias (HTRB) tests, high voltage-high humidity high temperature reverse bias (HV-H3TRB) tests, etc. This can reduce the deformation, peeling, and / or ratcheting phenomena of the metal film structure and, as a result, reduce damage to the passivation layer. In addition, the corrosion resistance of beryllium metal alloys is expected to exceed that of aluminum and copper.

[0025] Aspects of this disclosure offer technical effects and advantages. For example, metal film structures containing beryllium, as illustrated in the examples of this disclosure, can address various reliability challenges in high-performance semiconductor packaging, such as aluminum splashout, pad cratering, galvanic corrosion, passivation layer cracking, and shift or deformation of the metal film structure. Metal film structures containing beryllium (e.g., beryllium alloys) can exhibit similar CTE values ​​to those of different parts of the semiconductor die while being resistant to mechanical stresses, for example, those induced by the encapsulating material (EMC) of the semiconductor package. Furthermore, the improved structural robustness of beryllium-containing metal film structures allows these alloys to enhance the reliability of the wire bonding process and may enable a reduction in the thickness of the metal film structure (e.g., bonding pad thickness) without the risk of damaging the underlying layers of the semiconductor die during the wire bonding process.

[0026] In some cases, using a metal film structure with beryllium (e.g., beryllium alloy) instead of aluminum or aluminum-copper alloy can reduce failures during testing of semiconductor devices. In addition, the metal film structure can reduce delamination of the metal film structure. In some cases, using a metal film structure with beryllium (e.g., beryllium alloy) instead of aluminum or aluminum-copper alloy can enable thicker (e.g., 15 mil or 20 mil) wire bonding integration (Al or Cu wire bonds) in semiconductor packages. In some cases, using a metal film structure with beryllium (e.g., beryllium alloy) instead of aluminum or aluminum-copper alloy can improve the capabilities of the metal film structure, allowing for a metal film that can withstand stress from EMC without passivation layer cracking. In some cases, using a metal film structure with beryllium (e.g., beryllium alloy) instead of aluminum or aluminum-copper alloy can reduce copper diffusion into the semiconductor die.

[0027] In addition, aluminum metal coatings are typically deposited at temperatures ranging from approximately 400°C to 450°C for better film uniformity. However, temperatures above approximately 400°C can cause recrystallization of crystal grains, leading to their growth to a larger size and consequently reducing their mechanical strength. The addition of beryllium can raise the recrystallization temperature by approximately 100°C or more, leading to improved mechanical stability.

[0028] Although terms such as "first," "second," and "third" may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be called the second element, and similarly, the second element may be called the first element. As used herein, the term "and / or" includes any combination of one or more of the related enumerated items.

[0029] The terms used herein are intended solely to describe specific embodiments and are not intended to limit the invention. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless otherwise explicitly indicated in the context. It will be further understood that, where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” identify the presence of a described feature, integer, step, action, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to which the present invention pertains. Terms used herein should be construed to have meanings consistent with their meanings in the context of this specification and related art, and it will be further understood that they should not be construed in an idealized or overly formal sense unless expressly defined herein.

[0031] When an element such as a layer, region, or substrate is described as being "on" or "onto" another element, it will be understood that it may be directly on or able to extend directly onto the other element, or that there may be an intervening element. In contrast, when an element is described as being "directly on" or "directly onto" another element, there is no intervening element. When an element is described as being "connected" or "joined" to another element, it will be understood that it may be directly connected to or able to join with the other element, or that there may be an intervening element. In contrast, when an element is described as being "directly connected" or "directly joined" to another element, there is no intervening element.

[0032] Relative terms such as “downward,” “upward,” “top,” “bottom,” “horizontal,” “lateral,” or “vertical” may be used herein to describe the relationship between one element, layer, or region shown in the figure and another element, layer, or region. It will be understood that these terms are intended to include various orientations of the device in addition to the orientation shown in the figure.

[0033] Embodiments of the present disclosure are described herein with reference to schematic cross-sectional views of idealized embodiments (and intermediate structures) of the present invention. Thicknesses of layers and regions in the drawings may be exaggerated for clarity. Furthermore, deformations from the shapes shown should be expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as being limited to specific shapes of regions shown herein, and should include, for example, deviations in shape due to manufacturing. Similarly, it will be understood that dimensional variations should be expected based on the standard deviation in the manufacturing procedure. Where used herein, “approximately” or “about” includes values ​​within 10% of the nominal value.

[0034] Throughout the series, similar numbers refer to similar elements. Therefore, the same or similar numbers may be explained by reference to other drawings, even if they are not mentioned or explained in their corresponding drawings. Furthermore, elements not indicated by reference numbers may be explained by reference to other drawings.

[0035] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions characterized by having a conduction type such as n-type or p-type, which refers to the majority carrier concentration within the layer and / or region. Thus, an N-type material has an equilibrium concentration of negatively charged electrons, while a P-type material has an equilibrium concentration of positively charged pores. Some materials may be designated with "+" or "-" (such as N+, N-, P+, P-, N++, N--, P++, P--, etc.) to indicate a relatively large ("+") or small ("-") majority carrier concentration compared to another layer or region. However, such notation does not mean that a particular concentration of majority or minority carriers exists within the layer or region.

[0036] Aspects of this disclosure will be discussed with reference to silicon carbide-based semiconductor structures. Those skilled in the art using the disclosures provided herein will understand that power semiconductor devices according to exemplary embodiments of this disclosure can be used with any semiconductor material, such as other wide-bandgap semiconductor materials, without departing from the scope of this disclosure. Exemplary wide-bandgap semiconductor materials include silicon carbide (e.g., silicon alpha-carbide with a 2.996 eV bandgap at room temperature) and Group III nitrides (e.g., gallium nitride with a 3.36 eV bandgap at room temperature).

[0037] Typical embodiments are disclosed in the drawings and this specification, and certain terms are used, but they are used only in a general and descriptive sense and are not intended to limit the scope set forth in the following claims.

[0038] Next, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0039] Figure 1 shows an exemplary semiconductor device 100 according to an exemplary embodiment of the present disclosure. The semiconductor device 100 may be, for example, a semiconductor die. The semiconductor device 100 may include a semiconductor structure 102 having an active region containing one or more active semiconductor cells (e.g., silicon carbide-based MOSFETs, silicon carbide-based Schottky diodes, Group III nitride-based HEMTs, etc.). The semiconductor structure 102 may include a wide-bandgap semiconductor such as silicon carbide and / or Group III nitride (e.g., GaN, AlGaN, etc.). The semiconductor structure 102 may include one or more epitaxial layers formed on a substrate such as a silicon carbide substrate.

[0040] The semiconductor device 100 may include one or more metal film structures. These one or more metal film structures may include, for example, a bonding pad 104. The bonding pad 104 may be used to make an electrical connection to the semiconductor device 100 using a connection structure such as a wire bond. The bonding pad 104 may be placed on an adhesive layer 106 to fix the bonding pad 104 to the semiconductor structure 102 and provide, for example, a gate connection, a source connection, a Kelvin connection, a sensor connection, or other suitable connection. The adhesive layer 106 may be, for example, titanium. In some embodiments, the bonding pad 104 may have a thickness of about 4 μm or less.

[0041] In some examples, the semiconductor device 100 may include a backside metal film structure 108 on the semiconductor structure 102. In some semiconductor packages, the backside metal film structure 108 may be fixed to a submount (e.g., the lead frame of the semiconductor package) using, for example, a die attach material to provide thermal and / or electrical connections (e.g., drain connections) for the semiconductor device 100.

[0042] The semiconductor device 100 may include a passivation layer 110. The bonding pad 104 may be exposed through an opening in the passivation layer 110. The passivation layer may include one or more suitable passivation materials such as silicon nitride. In some examples, the passivation layer 110 may be a polymer such as polyimide. In some examples, the passivation layer 110 may be SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, or other dielectric materials.

[0043] According to exemplary embodiments of this disclosure, the bonding pad 104 and / or the back-side metal coating structure 108 may contain beryllium. For example, the bonding pad 104 and / or the back-side metal coating structure 108 may contain beryllium. For example, in some embodiments, the bonding pad 104 and / or the back-side metal coating structure 108 may contain a beryllium alloy. The bonding pad 104 and / or the back-side metal coating structure 108 may contain copper and beryllium (e.g., a copper-beryllium alloy). The bonding pad 104 and / or the back-side metal coating structure 108 may contain aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0044] In some examples, the bonding pad 104 and / or the back-side metal coating structure 108 may include a ternary beryllium alloy. The ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may also include cobalt, which can enhance the microstructural stability of the metal coating structure.

[0045] In exemplary embodiments of this disclosure, the bonding pad 104 and / or the back-side metal coating structure 108 may contain about 0.1% to about 3% beryllium, for example, about 0.2% to about 2% beryllium, for example, about 0.2% to about 0.1% beryllium, for example, about 0.2% to about 0.5% beryllium, for example, about 0.5% beryllium.

[0046] Figure 2 shows a cross-sectional view of at least a portion of a semiconductor device 120 according to an exemplary embodiment of the present disclosure. In some embodiments, the semiconductor device 120 shown in Figure 2 may be a single unit cell of the active semiconductor cell of the semiconductor device 100 of Figure 1.

[0047] As shown in the figure, the semiconductor device 120 includes a semiconductor structure 122. The semiconductor structure 122 may include one or more wide-bandgap semiconductor materials and may include doping and / or different epitaxial layer structures to form one or more active semiconductor cells for a semiconductor device (e.g., silicon carbide-based MOSFETs, silicon carbide-based Schottky diodes, Group III nitride-based HEMTs, etc.). The semiconductor structure 122 may include one or more epitaxial layers formed on a substrate such as a silicon carbide substrate.

[0048] The semiconductor device 120 may include metal film structures such as contacts for the semiconductor device 120. In the example in Figure 2, one or more metal film structures may include a source contact 124, a drain contact 126, and / or a gate contact 128. A gate dielectric layer 130 (e.g., silicon dioxide) may be placed between the gate contact 128 and the semiconductor structure 122. The semiconductor device 120 may also include one or more passivation layers (e.g., a silicon nitride layer, a polyimide layer, etc.) which are not shown in Figure 2 for the sake of simplicity in illustration.

[0049] According to exemplary embodiments of this disclosure, one or more of the metal coating structures of Figure 2, including one or more of the source contact 124, the drain contact 126, and / or the gate contact 128, may include beryllium. For example, in some embodiments, at least a portion of the source contact 124, the drain contact 126, and / or the gate contact 128 may include a beryllium alloy. At least a portion of the source contact 124, the drain contact 126, and / or the gate contact 128 may include copper and beryllium (e.g., a copper-beryllium alloy). At least a portion of the source contact 124, the drain contact 126, and / or the gate contact 128 may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0050] In some examples, at least a portion of the source contact 124, drain contact 126, and / or gate contact 128 may include a ternary beryllium alloy. The ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may include cobalt, which can enhance the microstructural stability of the metal coating structure.

[0051] In exemplary embodiments of this disclosure, at least a portion of the source contact 124, drain contact 126, and / or gate contact 128 may contain beryllium in an amount ranging from about 0.1% to about 3%, for example, from about 0.2% to about 2%, for example, from about 0.2% to about 0.1%, for example, from about 0.2% to about 0.5%, for example, about 0.5%.

[0052] Figure 3 shows an exemplary metal film layer of a semiconductor device 140, including a front-side metal film layer 142 on a semiconductor structure 144. The semiconductor device 140 may also include a back-side metal film layer 146. The back-side metal film layer 146 may include a drain mounting pad 148 on the back side of the semiconductor structure 144. The semiconductor structure 144 may include one or more wide-bandgap semiconductor materials and may include doping and / or different epitaxial layer structures to form one or more active semiconductor cells for semiconductor devices (e.g., silicon carbide-based MOSFETs, silicon carbide-based Schottky diodes, Group III nitride-based HEMTs, etc.). The semiconductor structure 144 may include one or more epitaxial layers formed on a substrate such as a silicon carbide substrate.

[0053] The surface metal film layer 142 may include a metal film structure comprising a gate pad 150, gate runners 152, an edge termination structure 154, a source pad 156, and / or additional bond pads 158 (e.g., a source Kelvin bond pad or a sensor bond pad). Multiple gate runners 152 (e.g., gate buses) may extend from the gate pad 150 to better distribute gate signals to the outer edge and center of the power semiconductor device 140. The edge termination structure 154 may wrap around the power semiconductor device 140 to buffer the electric field so that the voltage over distance is reduced.

[0054] The metal film layer 142 may include metal film pads (e.g., gate pad 150 and source pad 156) for power and signal connections to other components (e.g., submounts, lead frames, terminals, etc.) so that the metal film layer 142 acts as a bonding layer for the power semiconductor device 140. The gate pad 150 and / or source pad 156 may have a thickness of 4 μm or less. Signal connections to the gate pad 150 may be made, for example, using wire bonds. The source pad 156 may be directly on the active region of the semiconductor structure 144. Power connections to the source pad 156 may be made using clips or similar attachments that are directly soldered, sintered, or welded to the source pad 156. The source pad 156 may function as a source contact or other contact (e.g., ohmic contact, Schottky contact, etc.) for semiconductor cells in the active region of the semiconductor structure 144 of the power semiconductor device 140.

[0055] The power semiconductor device 140 may include additional bonding pads 156 (for example, for connection to wire bonds or other connection structures). The additional bonding pads 156 may be used, for example, for source Kelvin connections and / or sensor connections for the semiconductor device 140.

[0056] According to exemplary embodiments of the present disclosure, one or more parts of the metal coating structure of Figure 3, including one or more parts of the gate pad 150, gate runner 152, edge termination structure 154, source pad 156, additional bond pad 158, and / or drain mounting pad 148, may include beryllium. For example, in some embodiments, one or more parts of the gate pad 150, gate runner 152, edge termination structure 154, source pad 156, additional bond pad 158, and / or drain mounting pad 148 may include a beryllium alloy. One or more parts of the gate pad 150, gate runner 152, edge termination structure 154, source pad 156, additional bond pad 158, and / or drain mounting pad 148 may include copper and beryllium (e.g., a copper-beryllium alloy). At least a portion of one or more of the gate pad 150, gate runner 152, edge termination structure 154, source pad 156, additional bond pad 158, and / or drain mounting pad 148 may include aluminum and beryllium (e.g., aluminum-beryllium alloy).

[0057] In some examples, at least a portion of one or more of the gate pad 150, gate runner 152, edge termination structure 154, source pad 156, additional bond pad 158, and / or drain mounting pad 148 may include a ternary beryllium alloy. The ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may include cobalt, which can enhance the microstructural stability of the metal coating structure.

[0058] In exemplary embodiments of the present disclosure, at least a portion of one or more of the gate pad 150, gate runner 152, edge termination structure 154, source pad 156, additional bond pad 158, and / or drain mounting pad 148 may include beryllium from about 0.1% to about 3%, e.g., from about 0.2% to about 2%, e.g., from about 0.2% to about 0.1%, e.g., from about 0.2% to about 0.5%, about 0.5%, etc.

[0059] Figure 4 shows an exemplary metal film layer of a semiconductor device 160, which includes a plurality of surface-side metal film layers on a semiconductor structure 162, including a first metal film layer 164 and a second metal film layer 166 overlapping at least a portion of the first metal film layer 164. An insulating layer 168 may be located between the first metal film layer 164 and the second metal film layer 166.

[0060] The first metal film layer 164 may be on the semiconductor structure 162. The semiconductor structure 162 may include one or more wide-bandgap semiconductor materials and may include doping and / or different epitaxial layer structures to form one or more active semiconductor cells for semiconductor devices (e.g., silicon carbide-based MOSFETs, silicon carbide-based Schottky diodes, Group III nitride-based HEMTs, etc.). The semiconductor structure 162 may include one or more epitaxial layers formed on a substrate such as a silicon carbide substrate.

[0061] The first metal film layer 164 may include a metal film structure comprising gate runners 170 and gate vias 172. Multiple gate runners 170 (e.g., a gate bus) are used to distribute gate signals through the semiconductor device 160. The multiple gate runners 170 in Figure 4 form a gate runner network. The gate runner network in Figure 4 is a cross-gate runner network. More specifically, two gate runners may intersect each other in the central portion of the first metal film layer 164, or they may be substantially perpendicular to each other. In addition, the two gate runners may have approximately the same length or they may have different lengths. Other suitable gate runner configurations / networks may be used without departing from the scope of this disclosure.

[0062] The gate via 172 may be used to transmit a signal to the gate runner 170. The gate via 172 may extend through the central portion of the semiconductor device 150. However, other suitable configurations and / or locations of the gate via may be used without departing from the scope of this disclosure.

[0063] The insulating layer 168 may be on the first metal film layer 164. The insulating layer 168 may include insulating portions 174. The insulating portions 174 may be dielectric materials (e.g., silicon nitride, polymer, etc.). The insulating portions 174 can be patterned to insulate or mask one or more metal film structures of the first metal film layer 164. More specifically, the insulating portions 174 can be patterned to cover certain structures in the first metal film layer 164 while leaving other features (e.g., active regions of the semiconductor structure 144) uncovered.

[0064] For example, the insulating portion 174 may include a masking portion 176 that can be implemented to insulate or mask the gate runner 170 of the first metal coating layer 164. The insulating portion 174 may be patterned to form a source contact opening 178. The source contact opening 178 may accommodate, for example, a source contact extending from a source bond pad 180 on the second metal coating layer 166. The insulating portion 174 may include a gate pad portion 182. The gate via 172 may extend through the insulating portion 174 of the insulating layer 168.

[0065] The second metal film layer 166 may be located on the insulating layer 168 such that the insulating layer 168 is located between the first metal film layer 164 and the second metal film layer 166. In some embodiments, the second metal film layer 166 may act as a bonding layer for the semiconductor device 160. In the example of Figure 4, the second metal film layer 166 includes a gate pad 184 in the central edge region of the semiconductor device 160, which may be a useful location for packaging. The second metal film layer 166 may include a planar interconnect structure 186 that connects the gate pad 184 to a gate via 172 and, consequently, electrically conductively connects to the gate runner 170 of the semiconductor device 160. The second metal film layer 166 may include a large source bonding pad 180. The source contact may extend from the source pad 180 to the active region of the semiconductor structure 162 of the semiconductor device 160 through the source contact opening 178 of the insulating layer 168.

[0066] The second metal coating layer 166 may be used for interconnecting the semiconductor device 160 to elements of the semiconductor package, including submounts, lead frames, terminals, etc. The interconnection method may vary depending on the package type and may include wire bonding, soldering, sintering, conductive epoxy, or similar electrically conductive materials.

[0067] The semiconductor device 160 may include other structures without departing from the scope of this disclosure. For example, the semiconductor device 160 may include a backside metal film layer (not shown) on the back side of the semiconductor structure 160, including a drain mounting pad. The semiconductor device 160 may include a passivation layer (not shown) on the second metal film layer 166. The semiconductor device 160 may include an edge termination structure.

[0068] Figure 5 shows a cross-sectional view of the semiconductor device 160 of Figure 4 taken along line A-A'. Figure 5 is intended to represent a structure for identification and illustrative purposes and is not intended to represent the structure to a physical scale. As shown, the power semiconductor device 160 includes a first metal film layer 164 on the semiconductor structure 162. The semiconductor device 160 includes an insulating layer 168. The semiconductor device 160 includes a second metal film layer 166 (e.g., a bonding layer). Certain layer boundaries are shown by dashed lines for illustrative purposes. A person skilled in the art using the disclosures provided herein will understand that the layers of the power semiconductor device 160 may all be assembled together to form a composite structure in the finally assembled semiconductor device 160 which may or may not include individual layer boundaries.

[0069] As shown in Figure 5, the power semiconductor device 160 includes a gate pad 184 and a source pad 180 in a second metal film layer 166. The insulating portion of the insulating layer 168 includes a gate pad portion 182. The first metal film layer 164 includes a gate runner 170. The insulating portion 188 may separate the gate runner 170 from other metal film structures (e.g., source contacts). The insulating layer 168 includes a source contact opening for accommodating a source contact extending from the source pad 180 to the active region of the semiconductor structure 142.

[0070] According to exemplary embodiments of this disclosure, one or more portions of the metal coating structures of Figures 4 and 5, including one or more portions of the first metal coating layer 164 and / or the second metal coating layer 166, may contain beryllium. For example, in some embodiments, one or more portions of the first metal coating layer 164 and / or the second metal coating layer 166 may contain a beryllium alloy. One or more portions of the first metal coating layer 164 and / or the second metal coating layer 166 may contain copper and beryllium (e.g., a copper-beryllium alloy). One or more portions of the first metal coating layer 164 and / or the second metal coating layer 166 may contain aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0071] In some examples, at least a portion of one or more of the first metal coating layer 164 and / or the second metal coating layer 166 may contain a ternary beryllium alloy. The ternary beryllium alloy may contain aluminum (or copper), beryllium, and a ternary element. The ternary element may contain silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may also contain cobalt, which can enhance the microstructural stability of the metal coating structure.

[0072] In exemplary embodiments of this disclosure, at least a portion of one or more of the first metal coating layer 164 and / or the second metal coating layer 166 may contain beryllium in an amount of about 0.1% to about 3%, for example, about 0.2% to about 2%, for example, about 0.2% to about 0.1%, for example, about 0.2% to about 0.5%, for example, about 0.5%.

[0073] Figure 6 shows an exemplary semiconductor package of a semiconductor device 200 according to an exemplary embodiment of the present disclosure. The semiconductor device includes a semiconductor die 202. The semiconductor die 202 includes one or more metal film structures including a bonding pad 204. The bonding pad 204 may be bonded to one or more electrical leads 206 using a wire bond 208. The wire bond 208 may be aluminum and / or copper. The wire bond 208 may have a thickness of about 15 mil to about 20 mil (e.g., about 381 μm to about 508 μm). The bonding pad 204 may have a thickness of, for example, about 4 μm or less. The back-side metal film layer on the semiconductor die 202 may be bonded to a submount 210 (e.g., a lead frame) using, for example, a die attach material. The submount 210 may be bonded to one or more termination structures 212. The sealing material 214 (e.g., EMC) can seal the semiconductor die 202, including its metal film structure, wire bond 208, submount 210, and other parts of the semiconductor package.

[0074] According to exemplary embodiments of this disclosure, one or more parts of the metal film structure of the semiconductor die 202, including one or more parts of the bonding pad 204 and / or the back-side metal film layer, may include beryllium. For example, in some embodiments, the metal film structure of the semiconductor die 202 may include a beryllium alloy. The metal film structure of the semiconductor die 202 may include copper and beryllium (e.g., a copper-beryllium alloy). The metal film structure of the semiconductor die 202 may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0075] In some examples, the metal film structure of the semiconductor die 202 may include a ternary beryllium alloy. The ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may also include cobalt, which can enhance the microstructural stability of the metal film structure.

[0076] In exemplary embodiments of this disclosure, the metal film structure of the semiconductor die 202 may include about 0.1% to about 3% beryllium, for example, about 0.2% to about 2% beryllium, for example, about 0.2% to about 0.1% beryllium, for example, about 0.2% to about 0.5% beryllium, for example, about 0.5% beryllium.

[0077] Figure 7 shows a cross-sectional view of an exemplary semiconductor package of a semiconductor device 220 according to an exemplary embodiment of the present disclosure. Figure 7 is intended to represent structures for identification and illustrative purposes and is not intended to represent structures to a physical scale. The semiconductor device 220 may include a housing 222. The semiconductor device 220 may include a conductive submount 224 (e.g., a patterned conductive submount) on which a semiconductor die 226 is mounted (e.g., using a die attach material). The semiconductor die 226 may include one or more metal film structures such as bonding pads 228. In some embodiments, the semiconductor die 226 may be connected to the conductive submount 224 using wire bonds 230. The conductive submount 224 may be mounted on a base layer 232 (e.g., an insulating layer). An inert gel 234 may fill the space between the semiconductor die 226 and the housing 222.

[0078] According to exemplary embodiments of this disclosure, at least one or more parts of the metal film structure of the semiconductor die 226, including at least a portion of one or more bonding pads 228, may include beryllium. For example, in some embodiments, the metal film structure of the semiconductor die 226 may include a beryllium alloy. The metal film structure of the semiconductor die 226 may include copper and beryllium (e.g., a copper-beryllium alloy). The metal film structure of the semiconductor die 226 may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0079] In some examples, the metal film structure of the semiconductor die 226 may include a ternary beryllium alloy. The ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may also include cobalt, which can enhance the microstructural stability of the metal film structure.

[0080] In exemplary embodiments of this disclosure, the metal film structure of the semiconductor die 226 may include about 0.1% to about 3% beryllium, for example, about 0.2% to about 2% beryllium, for example, about 0.2% to about 0.1% beryllium, for example, about 0.2% to about 0.5% beryllium, for example, about 0.5% beryllium.

[0081] Figures 6 and 7 show exemplary semiconductor packages for illustrative and discussional purposes. Those skilled in the art will understand that different semiconductor package configurations may be used by means of the disclosures provided herein without departing from the scope of this disclosure.

[0082] Figure 8 shows a flowchart of an exemplary method 240 according to an exemplary embodiment of the present disclosure. Figure 8 shows exemplary processing steps for illustrative and discussional purposes. Those skilled in the art will understand, by using the disclosure provided herein, that any processing step of any of the methods described herein may be adjusted, modified, include steps not shown, be omitted, and / or rearranged without departing from the scope of the disclosure.

[0083] In 242, the method includes depositing a metal film structure on the active region of a semiconductor structure. The semiconductor structure may be a semiconductor structure that may include one or more wide-bandgap semiconductor materials and may include doping and / or different epitaxial layer structures to form one or more active semiconductor cells (e.g., wide-bandgap semiconductor cells) for a semiconductor device (e.g., silicon carbide-based MOSFETs, silicon carbide-based Schottky diodes, Group III nitride-based HEMTs, etc.). The metal film structure may be any of the metal film structures described herein. As an example, the method may include depositing a metal film structure 104 on the active region of the semiconductor structure 102 in Figure 1.

[0084] According to exemplary embodiments of this disclosure, at least a portion of the metal coating structure may include beryllium. For example, at least a portion of the metal coating structure may include a beryllium alloy. The metal coating structure may include copper and beryllium (e.g., a copper-beryllium alloy). The metal coating structure may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0085] In some examples, the metal film structure may include a ternary beryllium alloy. The ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may also include cobalt, which can enhance the microstructural stability of the metal film structure.

[0086] In exemplary embodiments of this disclosure, the metal coating structure may include about 0.1% to about 3% beryllium, for example, about 0.2% to about 2% beryllium, for example, about 0.2% to about 0.1% beryllium, for example, about 0.2% to about 0.5% beryllium, for example, about 0.5% beryllium.

[0087] In Figure 8, part 244, the method may include depositing a passivation layer on the active region of the semiconductor structure. In some examples, the passivation layer may contain silicon nitride. The passivation layer may contain a polymer such as polyimide. In some examples, the passivation layer may be SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, or other dielectric materials. As an example, the passivation layer 110 may be deposited on the semiconductor structure 102 in Figure 1.

[0088] In Figure 8, 246, the method may include opening the passivation layer to expose the metal coating structure. For example, the method may include opening the passivation layer 110 to expose the bonding pad 104 in Figure 1.

[0089] In Figure 8, 248, the method may include attaching an assembly including a semiconductor structure, a metal film structure, and / or a passivation layer to a submount such as a lead frame. For example, the method may include attaching the back-side metal film structure 108 in Figure 1 to the submount (e.g., using a die attach material).

[0090] In Figure 8, 250, the method may include bonding one or more electrical connection structures (e.g., wire bonds) to a metal-coated structure. For example, a wire bond may be bonded to the metal-coated structure 104 in Figure 1.

[0091] In Figure 8, 252, the method may include sealing an assembly comprising a semiconductor structure, a metal film structure, and / or a passivation layer. For example, the assembly may be sealed with EMC.

[0092] Examples of this disclosure are provided below. Features of some examples may be combined with features of others without departing from the scope of this disclosure.

[0093] One exemplary aspect of this disclosure relates to a semiconductor device. The semiconductor device includes an active region comprising one or more active semiconductor cells. The semiconductor device includes a metal film structure on the active region. The metal film structure comprises beryllium.

[0094] In some examples, the metal film structure is one or more of the contacts, interconnects, or bonding pads of a semiconductor device.

[0095] In some examples, the metal coating structure further contains copper. In some examples, the metal coating structure contains aluminum.

[0096] In some examples, the metal coating structure includes a range of approximately 0.1% to approximately 3% beryllium. In some examples, the metal coating structure includes a range of approximately 0.1% to approximately 3% beryllium. In some examples, the metal coating structure includes a range of approximately 0.2% to approximately 0.5% beryllium.

[0097] In some examples, the metal coating structure includes a ternary beryllium alloy. In some examples, the ternary beryllium alloy includes aluminum, beryllium, and a ternary element, the ternary element being silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some examples, the ternary beryllium alloy includes aluminum, beryllium, and a ternary element, the ternary element being cobalt.

[0098] In some examples, the metal film structure includes the source contact, drain contact, or gate contact of the MOSFET.

[0099] In some examples, the semiconductor device further includes a passivation layer. In some examples, the passivation layer includes silicon nitride. In some examples, the passivation layer includes a polymer. In some examples, the polymer includes polyimide.

[0100] In some examples, one or more active semiconductor cells include wide-bandgap semiconductors. In some examples, one or more active semiconductor cells include one or more silicon carbide-based MOSFETs. In some examples, one or more active semiconductor cells include one or more silicon carbide-based Schottky diodes. In some examples, one or more active semiconductor cells include one or more Group III nitride-based high-electron-mobility transistor devices.

[0101] Another exemplary aspect of this disclosure relates to a semiconductor device. The semiconductor device includes an active region comprising one or more silicon carbide-based MOSFETs. The semiconductor device includes a metal film structure on the active region. The metal film structure includes bonding pads associated with the gate contact, source contact, or drain contact of the semiconductor device. The metal film structure comprises beryllium. The metal film structure comprises beryllium.

[0102] In some examples, the metal coating structure further contains copper. In some examples, the metal coating structure further contains aluminum.

[0103] In some examples, the metal coating structure includes a range of approximately 0.1% to approximately 3% beryllium. In some examples, the metal coating structure includes a range of approximately 0.1% to approximately 3% beryllium. In some examples, the metal coating structure includes a range of approximately 0.2% to approximately 0.5% beryllium.

[0104] In some examples, the metal coating structure includes a ternary beryllium alloy. In some examples, the ternary beryllium alloy contains aluminum, beryllium, and a ternary element, the ternary element being silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some examples, the ternary beryllium alloy contains aluminum, beryllium, and a ternary element, the ternary element being cobalt.

[0105] In some examples, semiconductor devices include an adhesive layer between the metal film structure and the active region. In some examples, the adhesive layer contains titanium.

[0106] In some examples, semiconductor devices include a passivation layer. In some examples, the passivation layer includes silicon nitride. In some examples, the passivation layer includes a polymer. In some examples, the polymer includes polyimide.

[0107] In some examples, semiconductor devices include encapsulation materials.

[0108] In some examples, semiconductor devices include one or more wire bonds on a metal film structure.

[0109] Another exemplary aspect of this disclosure relates to a method, which involves depositing a metallic film structure on an active region comprising one or more wide-bandgap semiconductor cells, the metallic film structure comprising beryllium.

[0110] In some examples, the metal film structure is one or more of the contacts, interconnects, or bonding pads of a semiconductor device.

[0111] In some examples, the metal coating structure further contains copper. In some examples, the metal coating structure contains aluminum.

[0112] In some examples, the metal coating structure includes a range of approximately 0.1% to approximately 3% beryllium. In some examples, the metal coating structure includes a range of approximately 0.1% to approximately 3% beryllium. In some examples, the metal coating structure includes a range of approximately 0.2% to approximately 0.5% beryllium.

[0113] In some examples, the metal coating structure includes a ternary beryllium alloy. In some examples, the ternary beryllium alloy contains aluminum, beryllium, and a ternary element, the ternary element being silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some examples, the ternary beryllium alloy contains aluminum, beryllium, and a ternary element, the ternary element being cobalt.

[0114] In some examples, the method may include depositing a passivation layer on an active region. In some examples, the method may include opening the passivation layer to expose a metal film structure and bonding one or more electrical connection structures to the metal film structure.

[0115] In some examples, the method may include mounting an assembly having an active region and a metal coating structure onto a lead frame, and sealing the assembly.

[0116] In some examples, one or more active semiconductor cells include wide-bandgap semiconductors. In some examples, one or more active semiconductor cells include one or more silicon carbide-based MOSFETs. In some examples, one or more active semiconductor cells include one or more silicon carbide-based Schottky diodes. In some examples, one or more active semiconductor cells include one or more Group III nitride-based high-electron-mobility transistor devices.

[0117] While the subject matter of the present invention has been described in detail with respect to certain exemplary embodiments, it will be understood that those skilled in the art who understand the above will readily generate alternatives, variations, and equivalents to such embodiments. Therefore, as will be readily understood to those skilled in the art, the scope of this disclosure is illustrative and not limiting, and the subject disclosure does not preclude the inclusion of such modifications, variations, and / or additions to the subject matter.

Claims

1. An active region containing one or more active semiconductor cells, The metal coating structure on the active region, Equipped with, The aforementioned metal film structure is a semiconductor device containing beryllium.

2. The semiconductor device according to claim 1, wherein the metal film structure is one or more of the contacts, interconnects, or bonding pads of the semiconductor device.

3. The semiconductor device according to claim 1, wherein the metal film structure further comprises copper.

4. The semiconductor device according to claim 1, wherein the metal coating structure further comprises aluminum.

5. The semiconductor device according to claim 1, wherein the metal film structure includes a range from about 0.1% beryllium to about 3% beryllium.

6. The semiconductor device according to claim 1, wherein the metal film structure includes a range from about 0.2% beryllium to about 0.5% beryllium.

7. The semiconductor device according to claim 1, wherein the metal film structure includes a ternary beryllium alloy.

8. The semiconductor device according to claim 7, wherein the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, the ternary element comprising silver, copper, magnesium, silicon, titanium, vanadium, or zinc.

9. The semiconductor device according to claim 7, wherein the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, the ternary element comprising cobalt.

10. The semiconductor device according to claim 1, wherein the metal film structure includes a source contact, drain contact, or gate contact of a MOSFET.

11. The semiconductor device according to claim 1, further comprising a passivation layer.

12. The semiconductor device according to claim 11, wherein the passivation layer comprises silicon nitride.

13. The semiconductor device according to claim 11, wherein the passivation layer comprises a polymer.

14. The semiconductor device according to claim 13, wherein the polymer includes polyimide.

15. The semiconductor device according to claim 1, wherein the one or more active semiconductor cells include a wide-bandgap semiconductor.

16. The semiconductor device according to claim 1, wherein the one or more active semiconductor cells include one or more silicon carbide-based MOSFETs.

17. The semiconductor device according to claim 1, wherein the one or more active semiconductor cells include one or more silicon carbide-based Schottky diodes.

18. The semiconductor device according to claim 1, wherein the one or more active semiconductor cells include one or more Group III nitride-based high electron mobility transistor devices.

19. It is a semiconductor device, An active region comprising one or more silicon carbide-based MOSFETs, A metal film structure on the active region, wherein the metal film structure includes a bonding pad associated with the gate contact, source contact, or drain contact of the semiconductor device. Equipped with, The aforementioned metal film structure is a semiconductor device containing beryllium.

20. The semiconductor device according to claim 19, wherein the metal film structure further comprises copper.

21. The semiconductor device according to claim 19, wherein the metal coating structure further comprises aluminum.

22. The semiconductor device according to claim 19, wherein the metal film structure includes a range from about 0.1% beryllium to about 3% beryllium.

23. The semiconductor device according to claim 19, wherein the metal film structure includes a range from about 0.2% beryllium to about 0.5% beryllium.

24. The semiconductor device according to claim 19, wherein the metal film structure includes a ternary beryllium alloy.

25. The semiconductor device according to claim 24, wherein the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, the ternary element comprising silver, copper, magnesium, silicon, titanium, vanadium, or zinc.

26. The semiconductor device according to claim 24, wherein the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, the ternary element comprising cobalt.

27. The semiconductor device according to claim 19, further comprising an adhesive layer between the metal film structure and the active region.

28. The semiconductor device according to claim 27, wherein the adhesive layer contains titanium.

29. The semiconductor device according to claim 19, further comprising a passivation layer.

30. The semiconductor device according to claim 29, wherein the passivation layer comprises silicon nitride.

31. The semiconductor device according to claim 29, wherein the passivation layer comprises a polymer.

32. The semiconductor device according to claim 31, wherein the polymer includes polyimide.

33. The semiconductor device according to claim 19, further comprising a sealing material.

34. The semiconductor device according to claim 19, further comprising one or more wire bonds on the metal film structure.

35. The method comprises depositing a metal film structure on an active region containing one or more wide-bandgap semiconductor cells. The method comprising the aforementioned metal coating structure containing beryllium.

36. The method according to claim 35, wherein the metal coating structure includes a contact, an interconnect, or a bonding pad.

37. The method according to claim 36, wherein the metal coating structure includes copper.

38. The method according to claim 36, wherein the metal coating structure includes aluminum.

39. The method according to claim 36, wherein the metal coating structure includes a range of about 0.1% to about 3% beryllium.

40. The method according to claim 36, wherein the metal coating structure includes a range of about 0.2% to about 0.5% beryllium.

41. The method according to claim 36, wherein the metal coating structure includes a ternary beryllium alloy.

42. The method according to claim 41, wherein the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, the ternary element comprising silver, copper, magnesium, silicon, titanium, vanadium, or zinc.

43. The method according to claim 41, wherein the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, the ternary element comprising cobalt.

44. The method according to claim 35, further comprising depositing a passivation layer on the active region.

45. Opening the passivation layer to expose the metal coating structure, Bonding one or more electrical connection structures to the aforementioned metal film structure, The method according to claim 44, further comprising:

46. Attaching the assembly comprising the active region and the metal coating structure to the lead frame, To seal the aforementioned assembly, The method according to claim 45, further comprising:

47. The method according to claim 35, wherein the one or more wide-bandgap semiconductor cells include one or more silicon carbide-based MOSFETs.

48. The method according to claim 35, wherein the one or more wide-bandgap semiconductor cells include one or more silicon carbide-based Schottky diodes.

49. The method according to claim 35, wherein the one or more wide-bandgap semiconductor cells include one or more group III nitride-based high-electron-mobility transistor devices.

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