Trench power semiconductor device and method of manufacturing the same

Abstract

A trench-type power semiconductor device and its manufacturing method are disclosed. The trench-type power semiconductor device includes a semiconductor substrate, a drift layer, a first trench, a first doped region, a second doped region, and a gate. The drift layer is disposed on the semiconductor substrate and has a main surface. The first trench is formed on the drift layer. The first doped region is disposed on the drift layer and includes a first portion and a second portion. The first portion is adjacent to the main surface, and the second portion is adjacent to the first trench. The second doped region is disposed on the first doped region and includes a third portion and a fourth portion, respectively located in the first portion and the second portion. The gate is disposed in the first trench, and a bottom corner of the first trench is laterally misaligned with a lateral edge of the first doped region below the first trench.

Description

Technical Field

[0001] This invention relates to a semiconductor element, and more particularly to a trench power semiconductor device and its manufacturing method. Background Technology

[0002] As the on-state performance of planar power semiconductor devices approaches its theoretical limit, devices employing trench structures are gaining increasing attention. Trench structures offer more compact cell designs, thereby increasing channel density. However, this structure also introduces some drawbacks, including reliability issues with the trench's gate oxide layer and larger gate-drain charge.

[0003] This is mainly due to the presence of the trench structure, which increases the reverse electric field of the gate oxide layer at the bottom of the trench and the increase in the overlap area between the gate and drain. In order to reduce the electric field in the gate oxide layer, various improved structures have been proposed, such as adding a shielding region at the bottom of the trench and using a double trench structure to combine deeply doped regions.

[0004] However, in order to suppress the increase of the reverse electric field, existing technologies usually sacrifice some channels that cannot conduct electrons, and additional photomasks are required to form more complex structures, especially in the definition of the source doping region, which greatly increases the complexity and cost of the process. Summary of the Invention

[0005] Therefore, the purpose of this invention is to improve existing trench power semiconductor devices.

[0006] According to one aspect of the present invention, a method for manufacturing a trench power semiconductor includes the following steps: first, providing a semiconductor substrate, the semiconductor substrate including a first layer and a second layer disposed on the first layer, the first layer having a first conductivity type, and the second layer having a second conductivity type opposite to the first conductivity type; forming a stacked layer on the second layer, the stacked layer including a top layer, a bottom layer, an intermediate layer located between the top layer and the bottom layer, and a cover layer located on the top layer, the top layer and the bottom layer having at least one identical first chemical composition, and the stacked layer having a portion to be removed and a portion to be retained when viewed from a plan view.

[0007] Then, the portion to be removed from the stacked layer is removed, exposing the second layer and forming multiple recesses, while the retained portion forms multiple first platforms; a spacer layer is deposited, the spacer layer including at least the first chemical component, and the spacer layer including a horizontal spacer and a vertical spacer, the horizontal spacer including a first portion formed on the second layer and a second portion formed on the first platform, the vertical spacer connecting the top layer and the bottom layer of the stacked layer and forming on the side of the first platform; the horizontal spacer of the spacer layer is removed, so that the recess exposes the second layer.

[0008] Then, a first masking layer is deposited, which has at least one identical second chemical composition to the cover layer. The first masking layer includes a first horizontal portion and a first vertical portion. The first horizontal portion includes a first platform formed on the second layer and a first flat top formed on the first platform. The first vertical portion is connected to the side of the vertical interval.

[0009] Then, the first platform in the first masking layer is removed; using the first flat top and the first vertical portion as a mask, the exposed second layer and part of the first layer are removed to form a plurality of trenches; a second masking layer is deposited, the second masking layer having at least one identical second chemical composition to the first masking layer, the second masking layer including a second horizontal portion and a second vertical portion, the second horizontal portion including a second platform formed on the second layer and a second flat top formed on an unremoved portion between the trenches, the second vertical portion being connected to the side of the unremoved portion; the second platform in the second masking layer is removed.

[0010] Then, using the second flat top and the second vertical portion as a mask, a first doped region with the second conductivity type is implanted in the first layer below the trench; the second mask layer, the first mask layer, and the capping layer in the unremoved portion are removed to expose a plurality of second terraces; a third mask layer is deposited, the third mask layer including at least the first chemical composition, the third mask layer including a third horizontal portion and a third vertical portion, the third horizontal portion including a third platform formed on the first doped region and a third flat top formed on the second terrace, and the third vertical portion connected to the side of the second terrace.

[0011] Then, the third platform and the third flat top in the third masking layer are removed to expose the first doped region not covered by the third vertical portion and the first layer on the second platform not covered by the third vertical portion; using the third vertical portion as a mask, a second doped region is implanted in the exposed first doped region and the first layer, the second doped region having the first conductivity type; and, a sacrificial portion of the third masking layer and the second platform on the first layer is removed.

[0012] In one embodiment, the width of the trench is controlled by a first lateral thickness of the first vertical portion, and the width of the first doped region is controlled by a second lateral thickness of the second vertical portion.

[0013] In one embodiment, the width of the first doped region is smaller than that of the trench.

[0014] In one embodiment, a thickness of the second vertical portion of the second masking layer provides a lateral misalignment between a bottom corner of the trench and a side edge of the first doped region below the trench.

[0015] In one embodiment, the trench power semiconductor is an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a diode.

[0016] According to one aspect of the present invention, a method for manufacturing a trench power semiconductor includes the following steps:

[0017] A semi-finished semiconductor device is provided, comprising a semiconductor substrate and a stacked layer. The semiconductor substrate includes a first layer and a second layer disposed on the first layer. The first layer has a first conductivity type, and the second layer has a second conductivity type opposite to the first conductivity type. A plurality of trenches are formed on a main surface of the semiconductor substrate, and the stacked layer is formed on a portion of the main surface where the trenches are not formed.

[0018] Then, a masking layer is formed on the stacked layer, the masking layer including a horizontal portion and a vertical portion, the horizontal portion including a platform formed on a bottom wall of the trench and a flat top formed on the stacked layer, the vertical portion extending downward from the flat top to a side wall of the trench.

[0019] Then, the platform of the horizontal section is removed to expose the bottom wall of the trench.

[0020] Then, using the masking layer as a mask, a first doped region is implanted in a region below the trench, the first doped region having the second conductivity type, wherein a thickness of the vertical portion of the masking layer provides a lateral misalignment between a bottom corner of the trench and a side edge of the first doped region below the trench.

[0021] According to another aspect of the present invention, a high-speed switching shielded gate trench power semiconductor device includes: a semiconductor substrate, a drift layer, a first trench, a first doped region, a second doped region, and a gate. The drift layer has a first conductivity type and is disposed on the semiconductor substrate, the drift layer having a main surface; the first trench is formed on the drift layer; the first doped region has a second conductivity type opposite to the first conductivity type, the first doped region is disposed on the drift layer and includes a first portion and a second portion, the first portion being adjacent to the main surface, and the second portion being adjacent to a bottom wall of the first trench; the second doped region has the first conductivity type, the second doped region is disposed on the first doped region and includes a third portion and a fourth portion, the third portion being located in the first portion, and the fourth portion being located in the second portion; the gate is disposed in the first trench, the gate including a gate portion located in the first trench and an insulating portion located in the first trench and electrically isolating the gate portion. A lateral misalignment is formed between a bottom corner of the first trench and a side edge of the first doped region below the first trench.

[0022] In one embodiment, the trench power semiconductor is an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a diode.

[0023] In one embodiment, it further includes: a conductive post having the second conductivity type, the conductive post being disposed through the first doped region.

[0024] In one embodiment, the invention further includes an insulating layer and a metal layer. The insulating layer is formed on the gate, the first doped region, the conductive pillar, and the second doped region. The insulating layer includes a second trench located on the conductive pillar and a portion of the second doped region adjacent to the conductive pillar. The metal layer is formed on the insulating layer and in the second trench, and the metal contacts the conductive pillar and the portion of the second doped region adjacent to the conductive pillar. Attached Figure Description

[0025] 『 Figure 1 This is a schematic cross-sectional view of a semiconductor device according to some aspects of this disclosure.

[0026] 『 Figure 2A "to" Figure 2X This is a schematic diagram of the manufacturing process of a semiconductor device according to some aspects of this disclosure.

[0027] 『 Figure 3 This is a schematic cross-sectional view of a semiconductor device according to other aspects of this disclosure. Detailed Implementation

[0028] The semiconductor device of this disclosure will now be described with reference to the accompanying drawings. It should be understood that other examples may be used without departing from this disclosure, and structural or logical modifications may be made. For example, features in the drawings or description of one example may be combined with other examples to form another example, and this disclosure is intended to encompass these modifications and variations. Furthermore, specific terminology is used in the illustrative descriptions, but this should not be construed as limiting the appended claims.

[0029] In this disclosure, when an element such as a layer, portion, region, or substrate is referred to as "on top of," "over," or "above" another element, it may be directly on top of, directly over, or directly above the element; or there may be other elements in between. Conversely, when an element is referred to as "directly on top of," "directly over," or "directly above" another element, there are no intermediate elements.

[0030] This disclosure uses spatial relative terms to describe the relationship between one element, layer, portion, or region and another element, layer, portion, or region in the figures, such as "above," "over," "on top," "below," "below," "under," and other similar terms, but only for convenience in describing the relationship between one element or feature and another element or feature in the figures. In addition to covering the orientation depicted in the figures, the spatial relative terms also cover other orientations of the device during use or operation. The device may be oriented in other orientations, and the spatial relative descriptions used in this disclosure can be interpreted accordingly. Furthermore, the terms "lateral" or "lateral direction" as used in this disclosure should be understood to mean a direction or extent that is substantially (generally) parallel to the lateral extent of the semiconductor device, and thus substantially parallel to its surface or extending from its side. Conversely, the terms "depth direction" or "thickness direction" are understood to mean a direction that is substantially perpendicular to its surface and therefore perpendicular to the lateral direction.

[0031] In this disclosure, the terminology used in the description of various examples is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context specifically indicates or intentionally limits the number of elements, the singular forms "a" and "the" as used in this disclosure also include the plural forms. On the other hand, the terms "comprising," "including," and "containing" as used in this disclosure indicate the presence of the stated feature, element, and / or component, without excluding the addition or presence of one or more other features, elements, components, and / or groups thereof. Unless the contrary is clearly apparent from the context or specifically indicated or intentionally limited, indefinite and definite articles shall include both plural and singular forms.

[0032] In this disclosure, N-type doping is referred to as the first conductivity type, and P-type doping is referred to as the second conductivity type; alternatively, semiconductor devices can be formed using the opposite doping relationship, i.e., the first conductivity type can be P-type doping, and the second conductivity type can be N-type doping. In this disclosure, P-type or N-type doping can be used as examples, but this disclosure is not limited to the exemplified conductivity types, and doping with opposite conductivity types can also be used. The "-" or "+" indication next to the conductivity type N or P indicates the relative doping concentration. For example, N- means a doping concentration lower than that of the N-type doped region, while N+ doped region has a higher doping concentration than the N-type doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different N-type doped regions can have the same or different absolute doping concentrations.

[0033] In the accompanying drawings, the thickness of each layer, section, and region has been enlarged for clarity. Figure 1 The image shows a cross-sectional schematic diagram of an example of a trench power semiconductor device disclosed herein, exemplified by a metal-oxide-semiconductor field-effect transistor (MOSFET). The device includes an N+ type substrate 900, an N- type drift layer 901, a P-type region 902, an N+ type region 903, a P+ type pillar 904, a gate oxide 905, a gate 906, an oxide layer 907, and a metal layer 908. In other examples, the trench power semiconductor device may be an insulated-gate bipolar transistor (IGBT) or a diode element.

[0034] The N-type drift layer 901 is located on the N+ type substrate 900. A first trench TR1 is formed on the N-type drift layer 901. The P-type region 902 includes a first P-type portion 902a and a second P-type portion 902b. The first P-type portion 902a is disposed on the N-type drift layer 901, and the second P-type portion 902b is disposed below the first trench TR1. The N+ type region 903 includes a first N+ type portion 903a and a second N+ type portion 903b. The first N+ type portion 903a is disposed on the first P-type portion 902a, and the second N+ type portion 903b is disposed on the second P-type portion 902b. The P+ type pillar 904 includes a first P+ type pillar 904a and a second P+ type pillar 904b, which are respectively disposed below the first P-type portion 902a and the first trench TR1. The first P+ type pillar 904a passes through the first P-type portion 902a along a thickness direction to the N-type drift layer 901. The second P+ type pillar 904b is located in the first trench TR1 and passes through the second N+ type portion 903b and the second P-type portion 902b along the thickness direction to the N+ type substrate 900.

[0035] The gate oxide 905 is formed in the first trench TR1, and the gate 906 is formed in the gate oxide 905. The oxide layer 907 and the metal layer 908 are disposed on the P-type region 902, the N+ type region 903 and the P+ type pillar 904, and the oxide layer 907 further forms a second trench TR2, and the metal layer 908 is filled in the second trench TR2.

[0036] One sidewall SW of the first trench TR1 and one side edge of the second P-type portion 902b are intentionally misaligned laterally, with a gap between them forming a lateral misalignment D. This lateral misalignment D reduces the effect of local electric field concentration caused by the geometry of the first trench TR1, alleviates the electric field density at the bottom edge of the first trench TR1, thus improving the problem of reduced breakdown voltage, enhancing reliability, and reducing leakage current.

[0037] The following describes a method for manufacturing the trench power semiconductor device according to one aspect of this disclosure, specifically involving a method for forming trenches and doped regions using a self-alignment process to improve dimensional accuracy and eliminate the cost of additional photomasks.

[0038] First refer to 『 Figure 2A A drift layer 101 is formed on a semiconductor layer 100, the semiconductor layer 100 having a first conductivity type (e.g., N-type), and the drift layer 101 is disposed on the semiconductor layer 100 and has the first conductivity type. It should be understood that the drift layer 101 can be formed by epitaxial growth on the semiconductor layer 100 or by implantation on the semiconductor layer 100.

[0039] Next, a P-type layer 102 is formed in the drift layer 101 as a body region. An oxide layer 200 and a first nitride layer 300 are then formed on the P-type layer 102. The P-type layer 102 can be disposed in the drift layer 101 and adjacent to a main surface of the drift layer 101. The conductivity type of the P-type layer 102 is opposite to that of the drift layer 101. The P-type layer 102 can be formed by implanting a P-type dopant (e.g., boron ions or aluminum ions) into the N-type drift layer 101 to form an anti-doped P-type region near the main surface.

[0040] In one example, the semiconductor layer 100 is a substrate of a semiconductor material, which may be a silicon carbide (SiC) substrate, or may contain other semiconductors such as silicon, germanium, silicon-germanium, or diamond, or may contain semiconductor compounds and / or semiconductor alloys, depending on the final application. The semiconductor layer 100 may be referred to as a semiconductor substrate on its own; or, the semiconductor layer 100, the drift layer 101, and the P-type layer 102 may be collectively referred to as a semiconductor substrate. The semiconductor substrate is then used to form a stacked layer or a stacked structure thereon, which is used partially or wholly as one or more self-alignment masks, as will be detailed below. In one example, the drift layer 101 and the P-type layer 102 are respectively a first layer and a second layer in the semiconductor substrate.

[0041] Then, a semiconductor layer 301, a first silicon dioxide layer 400, a second nitride layer 401, and a second silicon dioxide layer 402 are formed on the first nitride layer 300, as shown in Figure ''. Figure 2B As shown in the image.

[0042] Perform one or more patterning processes, using a mask to remove portions of the first silicon dioxide layer 400, the second nitride layer 401, and the second silicon dioxide layer 402, as shown in [the image / description]. Figure 2C As shown in the image; and by removing portions of the semiconductor layer 301, the first nitride layer 300, and the oxide layer 200, the P-type layer 102 is exposed, as shown in the image. Figure 2D As shown in the diagram. It should be understood that the above-mentioned removal can be performed using the same patterning process or in multiple patterning processes. Here, multiple first mesa M1 and multiple recesses R1 located between the first mesa M1 are formed.

[0043] See 『 Figure 2E Next, a nitride 401a is deposited, which forms on the second silicon dioxide layer 402, the P-type layer 102, and extends downward along one sidewall of the second nitride layer 401. The nitride 401a serves as a spacer layer, comprising a horizontal spacer 401b and a vertical spacer 401c. The horizontal spacer 401b includes a first portion formed on the P-type layer 102 and a second portion formed on the first platform M1. Then, the nitride 401a on the second silicon dioxide layer 402 and the P-type layer 102 is removed, as described above. Figure 2F As shown in the diagram. Anisotropic etching is then performed to remove the nitride 401a on the sidewall of the second silicon dioxide layer 402, leaving the nitride 401a (vertical spacing 401c) formed on the sidewall beneath the second silicon dioxide layer 402, as shown in the diagram. Figure 2G As shown in the image.

[0044] See 『 Figure 2H An oxide 402a is deposited, which forms on the second silicon dioxide layer 402 and the P-type layer 102, and extends downward along one sidewall of the second silicon dioxide layer 402. The oxide 402a serves as a first masking layer, which includes a first horizontal portion 402b and a first vertical portion 402c. The first horizontal portion 402b includes a first platform formed on the P-type layer 102 and a first flat top formed on the first platform. The first vertical portion 402c is formed on the side of the vertical spacing 401c.

[0045] Then, a patterning process is performed to remove a portion of the oxide 402a formed on the P-type layer 102. The removed oxide 402a controls the width of the trench to be formed subsequently. In one example, the boundary of this portion of the oxide 402a is adjacent to the oxide 402a formed on the sidewall, so that the oxide 402a will appear as... Figure 2I As shown in the image.

[0046] Next, a portion of the drift layer 101 and the P-type layer 102 are removed to form a first trench TR1, as shown in the image. Figure 2J As shown in the diagram. Viewed in the planar direction, the removed drift layer 101 and the P-type layer 102 are located between the oxide 402a. In other words, the first trench TR1 left after removal is flush with one side edge 402d of the oxide 402a. Viewed in the thickness direction, the P-type layer 102 is removed until the drift layer 101 is exposed, and a portion of the drift layer 101 is removed. For the purpose of explanation, the structure between the first trenches TR1 is referred to as the second platform M2. Thus, the width of the first trench TR1 is controlled by the first lateral thickness of the first vertical portion 402c.

[0047] See 『 Figure 2K Next, an oxide 402e is deposited, which forms on the second silicon dioxide layer 402 and in the first trench TR1. Then, the oxide 402e located on a bottom wall BW of the first trench TR1 is removed, leaving the remaining portion of the oxide 402e, as shown in [the image / description]. Figure 2L As shown in the diagram. Here, the portion of oxide 402e formed on one sidewall SW within the first trench TR1 is intentionally retained. This oxide 402e acts as a mask, and the thickness of this portion controls the width of the P-type region to be formed later. Here, oxide 402e serves as a second masking layer, returning to the diagram. Figure 2KThe second masking layer includes a second horizontal portion 402g and a second vertical portion 402f. The second horizontal portion 402g includes a second platform 402g-1 formed on the P-type layer 102 and a second flat top 402g-2 formed on the second platform M2. The second vertical portion 402f is formed on the side of the second platform M2 and extends downward to the sidewall SW of the first trench TR1. In one example, the width of the oxide 402e is greater than the width of the P-type layer 102 between adjacent first trenches TR1.

[0048] Subsequently, using the oxide 402e as a mask, a P-type region 102a is formed in the drift layer 101 as another substrate region, such as ' Figure 2M As shown in the diagram. Because the oxide 402e has the second vertical portion 402f, which protrudes laterally from the sidewall SW of the first trench TR1 and has a thickness, a lateral edge 102b of the P-type region 102a is misaligned with the sidewall SW of the first trench TR1 by a certain distance; or, it prevents the lateral edge 102b of the P-type region 102a from falling below a bottom corner BC of the first trench TR1. In this way, the width of the P-type region 102a is controlled by a second lateral thickness of the second vertical portion 402f.

[0049] Remove the oxide 402e, and further deposit a nitride 401d, as shown in the image. Figure 2N As shown in the diagram. The nitride 401d covers and grows on the second nitride layer 401. Furthermore, the nitride 401d is also deposited in the first trench TR1. Here, the nitride 401d serves as a third masking layer, comprising a third horizontal portion 401e and a third vertical portion 401f. The third horizontal portion 401e includes a second platform formed on the P-type region 102a and a third flat top formed on the second platform M2. The third vertical portion 401f is formed on the side of the second platform M2. Then, the nitride 401d on the bottom wall BW of the first trench TR1 and the nitride 401d on the P-type layer 102 are removed, leaving the third vertical portion 401f of the nitride 401d and the third flat top on the second platform M2, as shown in the diagram. Figure 2O As shown in the image.

[0050] Subsequently, using the third horizontal portion 401e and the third vertical portion 401f of the nitride 401d as a mask, an N+ region 500 is formed in the P-type layer 102 and the P-type region 102a, serving as a source region, as shown in [the image / description]. Figure 2PAs shown in the diagram. The N+ region 500 is formed by implanting an N-type dopant (e.g., nitrogen ions, phosphorus ions, or arsenic ions) into the P-type layer 102 and the P-type region 102a to form a heavily doped N-type region. In one example, […]. Figure 2O The width of the nitride in the ' ' is greater than the width of the P-type layer 102 between the adjacent first trench TR1.

[0051] Next, the nitride (third vertical portion 401f) in the first trench TR1, the nitride (third horizontal portion 401e) on the oxide layer 200, the first nitride layer 300, and the semiconductor layer 301 are removed. The oxide layer 200 is provided to facilitate removal at this location. Figure 2Q As shown in the image. Then, remove the oxide layer 200.

[0052] See 『 Figure 2R A P+ type pillar 600 is formed in the N+ region 500 below the P-type layer 102 and the first trench TR1. The P+ type pillar 600 can serve as a source contact or as a termination ring.

[0053] Next, a gate oxide layer 700 is deposited, such as ' Figure 2S As shown in the figure, a spacer layer 701 is deposited on the gate oxide layer 700 in the first trench TR1. The spacer layer 701 is formed on the sidewall SW of the first trench TR1, as shown in the figure. Figure 2T As shown in the diagram, the spacer layer 701 can be a polysilicon. Then, a gate oxide layer 700' is deposited to form a structure as shown in the diagram. Figure 2U As shown, in addition to deposition, the gate oxide layer 700 can also be grown by thermal oxidation.

[0054] See 『 Figure 2V An oxide layer 800 is deposited, and a second trench TR2 is formed in the oxide layer 800. The second trench TR2 is located on the P+ type pillar 600 and the N+ region 500 adjacent to the P+ type pillar 600. The width of the second trench TR2 is greater than that of the P+ type pillar 600, and at least partially exposes the N+ region 500, thus forming a trench like the one described above. Figure 2W As shown in the image. Then, a metal 801 is deposited to form a structure as shown in the image. Figure 2X As shown, the metal 801 is formed on the oxide layer 800 and fills the second trench TR2, and contacts the P+ type pillar 600 and the N+ region 500.

[0055] In the above manufacturing process, the oxide layer 200, the first nitride layer 300, the semiconductor layer 301, the first silicon dioxide layer 400, the second nitride layer 401, and the second silicon dioxide layer 402 can be collectively referred to as a stacked layer. This stacked layer may include a top layer (the second nitride layer 401), a bottom layer (the oxide layer 200), an intermediate layer (the first nitride layer 300 and / or the semiconductor layer 301), and a capping layer (the second silicon dioxide layer 402). The above example uses nitrides as the top and bottom layers, but this disclosure is not limited to this. The top and bottom layers may have at least one identical first chemical composition (or they may be identical chemical compositions). Utilizing the homogeneity or identical chemical composition of the top and bottom layers helps in the formation of the lateral structure of the stacked layer, i.e., the vertical spacing 401c.

[0056] The portion grown from the second silicon dioxide layer 402 can be referred to as a first masking layer (e.g., '...'). Figure 2J The oxide 402a) and a second masking layer (such as ' Figure 2L The oxide 402e is used as a first self-alignment mask and a second self-alignment mask.

[0057] The first self-aligned mask is used to form the first trench TR1, and the second self-aligned mask is used to form the P-type region 102a. The first mask layer is, for example, the first horizontal portion 402b and the first vertical portion 402c of oxide 402a. The second mask layer is, for example, the second horizontal portion 402g and the second vertical portion 402f of oxide 402e. The first self-aligned mask layer is formed based on the stacked layers, and the second self-aligned mask layer is formed based on the first self-aligned mask layer. The above examples use oxides as the first mask layer, the second mask layer, and the capping layer, but this disclosure is not limited thereto. Utilizing the fact that the first mask layer, the second mask layer, and the capping layer have homogeneous or identical chemical compositions can facilitate the formation of the lateral structure of the self-aligned mask, namely the first vertical portion 402c of oxide 402a and the second vertical portion 402f of oxide 402e.

[0058] The nitride 401d can be referred to as a third masking layer, used as a third self-aligned mask. This third masking layer is formed based on the stacked layers and preferably has at least one identical third chemical component to the top layer and / or the bottom layer of the stacked layers. The above example uses a nitride as the third masking layer, the top layer, and the bottom layer, but this disclosure is not limited thereto. The third masking layer, the top layer, and the bottom layer only need to have at least one identical third chemical component. Utilizing the homogeneity or identical chemical components of the third masking layer, the top layer, and the bottom layer can facilitate the formation of the lateral structure of the third masking layer, i.e., the third vertical portion 401f.

[0059] According to one aspect of this disclosure, Figure 2W In one example, a trench power semiconductor is described, where a bottom corner of the first trench TR1 forms a lateral misalignment D between it and a lateral edge 102b of a first doped region (the P-type region 102a) beneath the first trench TR1. It should be understood that, based on... Figure 2W Trench power semiconductors derived from or manufactured using the structure described in the example also fall under this category. Furthermore, this example uses the structure described in the example... Figure 2A "to" Figure 2W "or" Figure 2X As Figure 2W The example describes the manufacturing process of trench power semiconductors, but this disclosure is not limited to this. Other methods or processes can also be used to manufacture them, and the two can be independent of each other.

[0060] According to another aspect of this disclosure, a method for manufacturing another trench power semiconductor is provided, comprising the above-mentioned... Figure 2A "to" Figure 2X The process of ' ' is explained as follows.

[0061] First, a semi-finished semiconductor device is provided, which can be described as follows: Figure 2J As shown, the semiconductor substrate includes a semiconductor layer 100, a drift layer 101, and a P-type layer 102 (collectively referred to as the semiconductor substrate). In one example, the drift layer 101 and the P-type layer 102 are respectively a first layer and a second layer in the semiconductor substrate. A plurality of first trenches TR1 are formed on a main surface of the semiconductor substrate.

[0062] A stacked layer is formed on the semiconductor substrate. The stacked layer may include the oxide layer 200, the first nitride layer 300, the semiconductor layer 301, the first silicon dioxide layer 400, the second nitride layer 401, and the oxide 402a. The stacked layer is formed on a portion of the main surface where the first trench TR1 is not formed.

[0063] Next, a masking layer is formed on the stacked layers. This masking layer can be the oxide 402e, such as ' Figure 2K As shown, the oxide 402e includes the second horizontal portion 402g and the second vertical portion 402f. The second horizontal portion 402g includes the second platform 402g-1 formed on the P-type layer 102 and the second flat top 402g-2 formed on the stacked layer. The second vertical portion 402f is formed on the side of the stacked layer and extends downward to the sidewall SW of the first trench TR1.

[0064] Then, the second platform 402g-1 of the second horizontal portion 402g is removed to expose the bottom wall BW of the first groove TR1, as shown in the image. Figure 2L As shown in the image.

[0065] Using this masking layer as a mask, the first doped region (the P-type region 102a) is implanted in a region below the first trench TR1. The first doped region has the second conductivity type, such as... Figure 2M As shown in the figure. The thickness of the second vertical portion 402f of the masking layer provides the lateral misalignment D between the bottom corner BC of the first trench TR1 and the lateral edge 102b of the first doped region below the first trench TR1.

[0066] 『 Figure 3 This shows another example of a trench-type power semiconductor device, an insulated-gate bipolar transistor (IGBT), which is similar to... Figure 1 The difference is that a collector layer 909 is further provided on one bottom surface of the N+ type substrate 900.

[0067] In summary, by intentionally misaligning the trenches and the doped regions beneath them laterally, the local electric field concentration effect caused by the trench geometry is reduced, alleviating the electric field density at the bottom edge of the trench. This improves the problem of reduced breakdown voltage, enhances device reliability, and reduces leakage current. Furthermore, the manufacturing method disclosed herein employs a self-aligned process to form the trenches and doped regions, improving dimensional accuracy and eliminating the cost of additional photomasks.

[0068] [Symbol Explanation]

[0069] 100: Semiconductor layer

[0070] 101: Drift Layer

[0071] 102: P-type layer

[0072] 102a: P-type region

[0073] 102b: Lateral edge

[0074] 200: Oxide layer

[0075] 300: First nitride layer

[0076] 301: Semiconductor layer

[0077] 400: First silicon dioxide layer

[0078] 401: Second nitride layer

[0079] 401a: Nitride

[0080] 401b: Horizontal Spacing

[0081] 401c: Vertical Spacing

[0082] 401d: Nitride

[0083] 401e: Level 3

[0084] 401f: Third vertical section

[0085] 402: Second silicon dioxide layer

[0086] 402a: Oxide

[0087] 402b: Level 1

[0088] 402c: First vertical section

[0089] 402d: Side

[0090] 402e: Oxide

[0091] 402f: Second vertical section

[0092] 402g: Second level portion

[0093] 402g-1: Second Platform

[0094] 402g-2: Second flat top

[0095] 500: N+ region

[0096] 600: P+ type column

[0097] 700: Gate oxide layer

[0098] 701: Spacer layer

[0099] 700': Gate oxide layer

[0100] 800: Oxide layer

[0101] 801: Metal

[0102] 900: N+ type substrate

[0103] 901: N-type drift layer

[0104] 902: P-type region

[0105] 902a: First P-type section

[0106] 902b: Second P-type section

[0107] 903: N+ type region

[0108] 903a: First N+ type part

[0109] 903b: Second N+ type part

[0110] 904: P+ type column

[0111] 904a: First P+ type column

[0112] 904b: Second P+ type column

[0113] 905: Gate oxide

[0114] 906: Gate

[0115] 907: Oxide layer

[0116] 908: Metallic layer

[0117] 909: Collector layer

[0118] TR1: First trench

[0119] TR2: Second trench

[0120] M1: First Station

[0121] M2: Second Station

[0122] R1: Depression

[0123] SW: Sidewall

[0124] BW: bottom wall

[0125] BC: Bottom corner

[0126] D: Lateral misalignment.

Claims

1. A method for manufacturing a trench-type power semiconductor device, characterized in that, Includes the following steps: A semiconductor substrate is provided, the semiconductor substrate including a first layer and a second layer disposed on the first layer, the first layer having a first conductivity type, and the second layer having a second conductivity type opposite to the first conductivity type; A stacked layer is formed on the second layer, the stacked layer including a top layer, a bottom layer, an intermediate layer between the top layer and the bottom layer and a cover layer on the top layer, the top layer and the bottom layer having at least one identical first chemical composition, and the stacked layer having a portion to be removed and a portion to be retained when viewed from a plan view. Remove the portion of the stacked layer to be removed, exposing the second layer and forming multiple recesses; the retained portion forms multiple first platforms. A spacer layer is deposited, the spacer layer including at least the first chemical component, and the spacer layer including a horizontal spacer and a vertical spacer, the horizontal spacer including a first portion formed on the second layer and a second portion formed on the first platform, and the vertical spacer connecting the top layer and the bottom layer of the stacked layers and formed on the side of the first platform. Remove the horizontal gap of the spacer layer to expose the second layer in the recess; A first masking layer is deposited, the first masking layer having at least one identical second chemical composition to the cover layer. The first masking layer includes a first horizontal portion and a first vertical portion. The first horizontal portion includes a first platform formed on the second layer and a first flat top formed on the first platform. The first vertical portion is connected to the side of the vertical interval. Remove the first platform from the first mask layer; Using the first flat top and the first vertical portion as a mask, the exposed second layer and part of the first layer are removed to form multiple grooves; A second masking layer is deposited, the second masking layer having at least one identical second chemical composition to the first masking layer, the second masking layer including a second horizontal portion and a second vertical portion, the second horizontal portion including a second platform formed on the second layer and a second flat top formed on an unremoved portion between the trenches, the second vertical portion being connected to the side of the unremoved portion. Remove the second platform from the second mask layer; Using the second flat top and the second vertical portion as a mask, a first doped region is implanted in the first layer below the trench, and the first doped region has the second conductivity type. Remove the second masking layer, the first masking layer, and the overlay layer from the remaining portion to expose multiple second platform sections; A third masking layer is deposited, the third masking layer including at least the first chemical composition, the third masking layer including a third horizontal portion and a third vertical portion, the third horizontal portion including a third platform formed on the first doped region and a third flat top formed on the second platform, and the third vertical portion connected to the side of the second platform. Remove the third platform and the third flat top in the third masking layer to expose the first doped region not covered by the third vertical portion and the first layer on the second platform not covered by the third vertical portion; Using the third vertical portion as a mask, a second doped region is implanted into the exposed first doped region and the first layer, the second doped region having the first conductivity type; and Remove the third masking layer and the second platform portion located on the first layer.

2. The manufacturing method according to claim 1, characterized in that, The width of the trench is controlled by a first lateral thickness of the first vertical portion, and the width of the first doped region is controlled by a second lateral thickness of the second vertical portion.

3. The manufacturing method according to claim 1, characterized in that, The width of the first doped region is smaller than that of the trench.

4. The manufacturing method according to claim 1, characterized in that, The thickness of the second vertical portion of the second masking layer provides a lateral misalignment between a bottom corner of the trench and a side edge of the first doped region below the trench.

5. The manufacturing method according to claim 1, characterized in that, The trench power semiconductor is an insulated gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, or a diode.

6. A method for manufacturing a trench power semiconductor, characterized in that, Includes the following steps: A semi-finished semiconductor device is provided, comprising a semiconductor substrate and a stacked layer. The semiconductor substrate includes a first layer and a second layer disposed on the first layer. The first layer has a first conductivity type, and the second layer has a second conductivity type opposite to the first conductivity type. A plurality of trenches are formed on a main surface of the semiconductor substrate, and the stacked layer is formed on a portion of the main surface where the trenches are not formed. A masking layer is formed on the stacked layer. The masking layer includes a horizontal portion and a vertical portion. The horizontal portion includes a platform formed on a bottom wall of the trench and a flat top formed on the stacked layer. The vertical portion extends downward from the flat top to a side wall of the trench. Remove the horizontal portion of the platform to expose the bottom wall of the trench; and Using the masking layer as a mask, a first doped region is implanted in a region below the trench, the first doped region having the second conductivity type, wherein a thickness of the vertical portion of the masking layer provides a lateral misalignment between a bottom corner of the trench and a lateral edge of the first doped region below the trench.

7. A trench-type power semiconductor device, characterized in that, include: A semiconductor substrate; A drift layer having a first conductivity type is disposed on the semiconductor substrate, the drift layer having a main surface; A first trench is formed on the drift layer; A first doped region having a second conductivity type opposite to the first conductivity type, the first doped region being disposed on the drift layer and including a first portion and a second portion, the first portion being adjacent to the main surface, and the second portion being adjacent to a bottom wall of the first trench; A second doped region having the first conductivity type, the second doped region being disposed in the first doped region and including a third portion and a fourth portion, the third portion being located in the first portion and the fourth portion being located in the second portion; as well as A gate is disposed in the first trench, the gate including a gate portion located in the first trench and an insulating portion located in the first trench and electrically isolating the gate portion; Wherein, a bottom corner of the first trench and a side edge of the first doped region below the first trench form a lateral misalignment.

8. The trench power semiconductor device according to claim 7, characterized in that, The trench power semiconductor is an insulated gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, or a diode.

9. The trench power semiconductor device according to claim 7, characterized in that, Also includes: A conductive post having the second conductivity type is disposed in the first doped region.

10. The trench power semiconductor device according to claim 9, characterized in that, Also includes: An insulating layer is formed on the gate, the first doped region, the conductive pillar and the second doped region, the insulating layer including a second trench located on the conductive pillar and the portion of the second doped region adjacent to the conductive pillar; as well as A metal layer is formed on the insulating layer and in the second trench, the metal layer contacting the conductive post and a portion of the second doped region adjacent to the conductive post.

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