Time-to-digital converter (TDC) with a single-stage delay pair and noise shaping for wide input range and quantization noise reduction in a phase-locked loop (PLL).

Abstract

Disclosed are a time-to-digital converter (TDC) using a single-stage delay pair for a wide input range and quantization noise reduction in a phase-locked loop (PLL), and a method for manufacturing the associated device. Embodiments disclosed in the detailed description include a single-stage vernier time-to-digital converter (TDC) that mitigates the effects of device mismatch and thus avoids potential spria stones in fractional-N PLL applications. Combined with a delta-sigma noise shaping stage and a ring oscillator-based coarse TDC, the present invention achieves a good trade-off between resolution, detection range, and PLL lock speed.

Description

[Technical Field]

[0001] I. Areas of Disclosure

[0001] The technology of the present disclosure generally relates to phase-locked loops, and more particularly to time-to-digital converters that provide fast locking and low noise. [Background technology]

[0002] II. Background

[0002] Phase-locked loops (PLLs) are widely used to generate signals that oscillate consistently at a desired frequency and produce the lowest possible noise. For example, PLLs can be used to generate carrier signals for wired or wireless communication, or system clocks for clocking digital logic circuits within integrated circuits. As feature sizes become smaller, made possible by advances in integrated circuit (IC) manufacturing, the advantages of using digital PLLs (DPLLs) become greater. In a DPLL, one component that can significantly affect the quality of the generated output signal is the time-to-digital converter (TDC) circuit. In a PLL, the TDC circuit receives two signals (e.g., rising edges) separated by a period related to the phase difference between the generated output signal and a reference signal. The TDC circuit converts the period into an integer used to adjust the control of a digitally controlled oscillator that generates the output signal.

[0003]

[0003] Since the purpose of the DPLL is to consistently maintain the phase of the output signal near the phase of the reference signal, it is desirable to measure the time difference in fine increments (e.g., with higher resolution) in order to detect smaller changes. On the other hand, when the DPLL is first powered on, the phases of the output signal and the reference signal may be widely separated. Measuring for a long time with very small increments may require a significant amount of circuitry, which occupies area and consumes power on the IC. If the DPLL cannot determine the phase difference between the output signal and the reference signal, it can take a much longer time to synchronize the output signal to the reference signal at power-on. Therefore, in this regard, it is desirable to increase the size of the increment of time measurement so that the circuit can be reduced.

[0004]

[0004] Conventional Vernier TDCs use two delay circuit columns to measure the time difference, but the number of stages required for a given input range increases with the resolution. Also, if the delay of the delay stages is inconsistent, e.g., due to process variations, noise (e.g., spurious tones) can be generated in the output signal. Another option to reduce the number of circuits and avoid inconsistent delays is a single-stage Vernier TDC that includes a single delay stage used in a feedback method. However, the delay time of the single-stage delay affects both the input range and the resolution of the TDC circuit, which are opposing requirements. Therefore, a TDC circuit with a wide detection range without sacrificing resolution is desired.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Summary

[0005] Aspects disclosed in the detailed description include a single-stage Vernier time-digital converter (TDC) for a wide input range and reduction of quantization noise in a phase-locked loop (PLL). A method for a high-speed lock DPLL with low spurious tones is also disclosed.

[0006]

[0006] The TDC circuit is extremely important for the ability of the PLL to accurately track the reference signal. The Vernier TDC is a well-known design that requires a chain of long delay circuits that can occupy area, consume power, and generate noise in the output signal due to inconsistent delays. The single-stage pair TDC adopts the concept of the Vernier TDC but uses a single-stage delay pair in the feedback loop to reduce the circuit and avoid inconsistent delays. Since the TDC measures the period in increments with a specific resolution, there will inevitably be a remaining portion (e.g., time residue) that cannot be reflected in the integer generated by the TDC. In an exemplary TDC circuit, the first measurement circuit determines the integer and residue of the time increment within the period, and the second measurement circuit generates a fractional indicator indicating whether the cumulative time residue and the previous time residue exceed an integer time increment. In some examples, the fractional indicator can be used in the PLL to improve the resolution of the TDC, thereby providing more frequent and finer adjustments to the digital control oscillator (DCO). In this way, the TDC circuit can have a wider detection range while pushing the quantization noise to a higher frequency range that can be filtered by the PLL.

Means for Solving the Problems

[0007]

[0007] In this regard, a time-to-digital converter (TDC) circuit is disclosed. The TDC circuit includes a first measuring circuit configured to receive a start pulse signal and a stop pulse signal that are temporally separated by a period, to determine an integer of a first consecutive time increment within the period, and to determine the time residual of a period smaller than the first time increment (step). The TDC circuit further includes a second measuring circuit configured to add the time residual to a previously accumulated residual to produce a current accumulated residual, and to produce a fractional indicator indicating whether the magnitude of the current accumulated residual (positive or negative) is greater than half of the first time increment (step). Furthermore, in response to the fractional indicator indicating that the magnitude of the current accumulated residual is greater than half of the first time increment, the circuit produces a next accumulated residual that includes the difference between the first time increment and the current accumulated residual, and in response to the fractional indicator indicating that the magnitude of the current accumulated residual is less than half of the first time increment, the circuit produces a next accumulated residual that includes the current accumulated residual.

[0008]

[0008] In another embodiment, a method for a TDC circuit is disclosed. This method includes receiving a start pulse signal and a stop pulse signal separated in time by a period; determining an integer of a first time increment within the period and a time residual less than the first time increment; adding the time residual to a previously accumulated residual to generate a current accumulated residual; and generating a fractional indicator indicating whether the current accumulated residual differs from the first time increment by more than half of the first time increment. The method further includes, in response to the fractional indicator indicating that the current accumulated residual differs from the first time increment by more than half of the first time increment, generating a next accumulated residual that includes the difference between the first time increment and the current accumulated residual; and in response to the fractional indicator indicating that the current accumulated residual differs from the first time increment by less than half of the first time increment, generating a next accumulated residual based on the current accumulated residual.

[0009]

[0009] In another embodiment, a phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a digitally controlled oscillator (DCO), a loop filter circuit, a division circuit, and a time-digital (TDC) system. The (TDC) system includes a coarse TDC circuit and a fine TDC circuit. The fine TDC circuit includes a first measuring circuit configured to receive start pulse and stop pulse signals that are temporally separated by period, to determine an integer of a first consecutive time increment within a period, and to determine the time residual of a period that is less than one of the first time increments. The fine TDC circuit further includes a second measurement circuit configured to: add the time residual to the previously accumulated residual to generate the current accumulated residual; generate a fractional indicator indicating whether the magnitude of the current accumulated residual is greater than half of the first time increment; generate the next accumulated residual containing the difference between the first time increment and the current accumulated residual in response to the fractional indicator indicating that the magnitude of the current accumulated residual is greater than half of the first time increment; and generate the next accumulated residual containing the current accumulated residual in response to the fractional indicator indicating that the magnitude of the current accumulated residual is less than half of the first time increment. The PLL circuit further includes a range determination circuit configured to: determine whether the duration of a period is within a period range; generate an integer corresponding to the duration of the period in the coarse TDC circuit in response to the determination that the duration of the period exceeds the maximum period within the period range; and generate an integer corresponding to the duration of the period in the fine TDC in response to the determination that the duration of the period is within a period range. [Brief explanation of the drawing]

[0010] Brief explanation of the drawing [Figure 1]

[0010] This is an exemplary block diagram of a time-digital (TDC) system, which includes an exemplary TDC circuit having a first measurement circuit for determining the number of time increments within a period, and a second measurement circuit for accumulating the residual and generating an indicator of the fraction of the time increment in order to reduce quantization noise in the PLL. [Figure 2]

[0011] This block diagram shows an example of a phase-locked loop (PLL) including the exemplary TDC circuit shown in Figure 1, which has a first measurement circuit for determining the number of time increments within a period, and a second measurement circuit for accumulating the residual and generating an indicator of the fraction of the time increment in order to reduce quantization noise in the PLL. [Figure 3]

[0012] This is a flowchart of the method of the exemplary TDC circuit shown in Figure 1, which determines the number of time increments within a period, accumulates the remainder, and generates an indicator of the fraction of the time increment. [Figure 4]

[0013] This is a logic circuit diagram illustrating the details of the first measurement circuit in the TDC of Figure 1 for determining the number of time increments within a period and providing the remaining time to the second measurement circuit. [Figure 5]

[0014] This timing diagram shows the operation of the first measurement circuit in Figure 4 in an example of two reference cycles of the reference clock. [Figure 6A]

[0015] This is a logic circuit diagram showing details of the second measurement circuit in the TDC in Figure 1 for adding the residue from the first measurement circuit to the previously accumulated residue, generating a fractional indicator for higher resolution, and calculating the next accumulated residue. [Figure 6B]

[0016] This is a logic diagram showing an analog adder circuit for adding the remainder from the first measurement circuit to the previously accumulated remainder. [Figure 7]

[0017] This timing diagram in Figure 1 shows the TDC circuit, where the time residual from the first measurement circuit is added to the previously accumulated residual to generate the current accumulated residual, and where, if the current accumulated residual exceeds the fractional time increment, the time increment is subtracted from the current accumulated residual to generate the next accumulated residual. [Figure 8]

[0018] Figure 4 is a logic circuit diagram of a calibration circuit for calibrating the timing resolution of the first measurement circuit. [Figure 9]

[0019] This is a timing diagram showing the signals of the calibration circuit in Figure 8 during the calibration process. [Figure 10]

[0020] This is a block diagram of an exemplary processor-based system that may include a PLL containing a TDC circuit within a TDC system, as shown in Figures 1, 4, 6A, and 6B. [Modes for carrying out the invention]

[0011] Detailed explanation

[0021] Hereafter, several exemplary embodiments of this disclosure will be described with reference to the drawings. In this specification, the term “exemplary” is used to mean “serving as an example, case, or illustration.” No embodiment described as “exemplary” in this specification should necessarily be construed as being preferable or advantageous to any other embodiment.

[0012]

[0022] Embodiments disclosed in the detailed description include a single-stage vernier time-to-digital converter (TDC) for a wide input range and quantization noise reduction in a phase-locked loop (PLL). Methods for a fast-locked DPLL with low spurious stone are also disclosed.

[0013]

[0023] In this regard, Figure 1 is a block diagram of an exemplary time-digital (TDC) system 100 within an integrated circuit chip 101, which includes an exemplary TDC circuit 102 having a first measuring circuit 104 for determining an integer 106 that represents an integer number of time increments TI within a period TP between a start pulse signal START and a stop pulse signal STOP. The period TP between the start pulse signal START and the stop pulse signal STOP is controlled by a reference clock C REF and feedback clock C FB The period between TP is equal to the period between . However, as explained below, the reference clock C REF is the feedback clock C FB Even if the start pulse signal START may precede or be delayed by the stop pulse signal STOP, the start pulse signal START precedes the stop pulse signal STOP.

[0014]

[0024] The first measurement circuit 104 generates a time residue TR, which is the remaining part of the period TP and is smaller than the time increment TI. In one example, TP = N(TI)+TR, where N is the integer 106. The time residue TR may also be referred to as the remaining time. The TDC circuit 102 also includes a second measurement circuit 108 that generates a fractional indicator 110 indicating whether the current cumulative residue CAR (not shown here) exceeds a fraction of the time increment TI based on the sum of the time residue TR and a previously accumulated residue PAR (not shown here).

[0015]

[0025] Before describing the TDC system 100 of FIG. 1 in more detail, first, referring to FIG. 2, an example of a phase-locked loop (PLL) 200 that can be used by the TDC system 100 will be described. The first measurement circuit 104 and the second measurement circuit 108 of the TDC circuit 102 will be described in more detail with reference to FIGS. 4-7.

[0016]

[0026] The PLL 200 in FIG. 2 is an example in which the TDC system 100 including the TDC circuit 102 can be used. The PLL 200 includes a digital control oscillator (DCO) 202 that generates an output clock signal C OUT oscillating at an output frequency F OUT . The output clock signal C OUT may be, for example, a carrier signal for wired or wireless communication, or a system clock in the digital logic circuit of the IC chip 101. For such applications, it is desirable for the output clock signal C OUT to have minimal noise and consistent phase and frequency. To improve the consistency of the phase and frequency, the PLL 200 receives a reference clock signal C OUT from, for example, a crystal oscillator or other reliable and consistent source for comparison with the output clock signal C REF . The output frequency F OUT may be different from the reference frequency F REF of the reference clock signal C REF . For example, the output frequency F OUT may be different from the reference frequency F REFX can be a multiple of . The PLL200 outputs a clock signal C OUT Output frequency F OUT Divide by X to obtain the reference clock signal C REF For comparison, the feedback frequency F FB Feedback clock signal C having FB Includes a division circuit 204 that generates [the result].

[0017]

[0027] In some examples, the multiple X is not an integer, but the division circuit 204 can be a multimodulus divider (MMD) capable only of integer division. The mismatch between X and the nearest integer is the output clock signal C. OUT To obtain the average of non-integer multiples, a dithering circuit (not shown) may be used to toggle the integer divisor of the division circuit 204 between two or more integer values ​​(for example, between 10 and 11 if the average is 10.65). This type of dithering circuit improves the frequency accuracy compared to a PLL without a dithering circuit, but the output clock signal C OUT It continues to generate noise. The PLL, including the TDC system 100 and TDC circuit 102 in Figure 1, pushes the quantization noise out of the PLL bandwidth where it can be effectively filtered, regardless of whether the dithering circuit is coupled to the divider circuit, thereby blocking the output clock signal C OUT Reduces noise.

[0018]

[0028] Referring further to Figure 2, the PLL 200 directly receives the reference clock signal C from the division circuit 204 as the start pulse signal START and the stop pulse signal STOP. REF and feedback clock signal C FB It may receive a reference clock signal C. In some examples, the PLL200 includes a phase frequency detector (PFD)206 in addition to the TDC208. The TDC208 may be the TDC system 100 in Figure 1, which includes the TDC circuit 102. In examples that include the PFD206, the PFD206 receives a reference clock signal C. REF and feedback clock signal C FBIt receives the feedback clock signal C. FB The phase of the clock signal C is referenced. REF It compares the phase with that of the reference clock signal C and generates a start pulse signal START and a stop pulse signal STOP, indicating the phase difference as a period TP. For example, PFD206 generates the start pulse signal START as a pulse with a leading edge (e.g., a step in voltage) and the stop pulse signal STOP with a leading edge, such that the leading edge is temporally separated by the period TP corresponding to the phase difference. TDC208 generates an integer 210, which is a quantification of the period TP. The integer 210 indicates the number of time increments within the period TP and can be positive or negative. The integer 210 is the reference clock signal C REF The output clock C may change with each cycle and is filtered by the loop filter 212. The loop filter 212 filters the output clock C OUT Frequency F OUT To control it, a filtered control signal 214 is provided to the DCO202. The integer 210 is the reference clock C REF Feedback clock C FB It is based on the time / phase offset of the two phases, bringing them closer together, and ultimately the reference clock signal C REF Phase and feedback clock signal C FB DCO202 is used to achieve a "locked state" in which the phases are the same or maintained within a small (e.g., undetectable) phase difference.

[0019]

[0029] Returning to Figure 1, the TDC system 100 has a reference clock C REF and feedback clock C FB The system includes a range determination circuit 112 that receives (these are separated by period TP). The range determination circuit 112 determines the sign of period TP in the sign detection circuit 114 and determines whether the duration of period TP is within the period range of the TDC circuit 102. In the TDC system 100, the feedback clock C FB The reference clock C REFIf received before, the period TP has a negative sign. In the TDC system 100, the reference clock C REF The reference clock C REF If received before the reference clock C, period TP has a positive sign. The sign detection circuit 114 generates a sign indicator SIGN that indicates the sign or polarity of period TP. If the sign indicator SIGN is positive, the start pulse signal START is set to reference clock C REF Based on this, the stop pulse signal STOP is controlled by the feedback clock C FB Based on the above. On the other hand, if the sign indicator SIGN is negative, the reorder circuit 116 in the range determination circuit 112 uses the reference clock C REF A start pulse signal START is generated from this, and the feedback clock C FB A stop pulse signal STOP is generated from this. In this way, the start pulse signal START arrives at the first measurement circuit 104 before the stop pulse signal STOP, independently of the sign indicator SIGN.

[0020]

[0030] The range determination circuit 112 includes a lower limit detector 118 and an upper limit detector 120. The lower limit detector 118 determines whether the period TP separating the start pulse signal START and the stop pulse signal STOP is less than the time incremental resolution of the TDC circuit 102. If so, the lower limit detector 118 generates a signal RST1 to reset the TDC circuit 102 in order to prepare the TDC circuit 102 for the next start pulse signal START. In the illustrated example, the period TP is the minimum detectable time or resolution T of the TDC circuit 102. RES If it is less than T, the lower limit detector 118 sets the flip-flop circuit DFF1 to a low level. Specifically, if the stop pulse signal STOP propagates through the first delay circuit 122 having a first delay period ("first delay") T1 before the start pulse signal START propagates through the second delay circuit 124 having a second delay period ("second delay") T2, the flip-flop circuit DFF1 is set to a low level, thereby generating the signal RST1. RES =T1-T2. The period TP is equal to the resolution T.RES If it is shorter than (which occurs, for example, in a locked state), the TDC system 100 makes no adjustment to the integer 125 provided to the loop filter 212 in Figure 2. For example, if no adjustment is needed, the integer 125 output from the TDC system 100 may be "0", and the output clock C out and reference clock C REF This indicates that the phase difference between the two is neither positive nor negative. Note that flip-flop circuits, which are edge-triggered memory elements, are used in contrast to level-sensitive latch circuits. Flip-flop circuits (also referred to herein as "flip-flops") may also be known as data flip-flops or arbiter circuits.

[0021]

[0031] The upper limit detector 120 determines whether the period TP exceeds the maximum detection time of the TDC circuit 102, where the maximum detection time corresponds to the maximum number of time increments TI detectable by the TDC circuit 102 within the period TP. In this example, if the upper limit detector 120 determines that the period TP exceeds the maximum detection time, the coarse TDC circuit 127 is activated, and a signal RST2 is generated to reset the TDC circuit 102 and prepare the TDC circuit 102 for the next start pulse signal START. In this case, if the stop pulse signal does not arrive at the flip-flop circuit DFF2 before the start pulse signal START propagates through the delay circuits 126A and 126B, the flip-flop circuit DFF2 generates the signal RST2. The coarse TDC circuit 127 outputs clock C OUT and reference clock C REF It can be first activated immediately after power-on, when the phase may be significantly shifted. The coarse TDC circuit 127 can measure TP for a much longer period than the TDC circuit 102, but has a much coarser resolution. Compared to the coarse TDC circuit 127, the TDC circuit 102 is sometimes called the fine TDC circuit 102 because it measures the period with a higher resolution time increment TI.

[0022]

[0032] As an example, the resolution of the coarse TDC circuit 127 can be determined by a loop of delay circuits 128(1) to 128(3) (e.g., a ring oscillator), each having a delay T3. The counter 130 counts the number of times the start pulse signal START propagates through the loop of delay circuits 128(1) to 128(3) before the stop pulse signal STOP is received. The coarse TDC circuit 127 generates an integer 132 representing the period TP. The sign correction circuit 134 receives the sign indicator SIGN, and if the sign indicator SIGN is negative, converts the integer 132 to a negative number. It should be understood that the integer 132 generated by the coarse TDC circuit 127 may coincide with the integer 106 generated by the TDC circuit 102. That is, the difference in resolution between the time increment TI of the TDC circuit 102 and the time measured by the loop of delay circuits 128 is taken into account in the generation of integers 106 and 132.

[0023]

[0033] The first measurement circuit 104 provides the second measurement circuit 108 with a time residual TR as the time difference between the pulse on the first residual input 135 and the pulse on the second residual input 136.

[0024]

[0034] The TDC system 100 includes an adder 138 that adds an integer 106 generated by a first measurement circuit 104 and a fractional indicator 110 generated by a second measurement circuit 108 to generate a high-resolution integer 140. The sign flip-flop circuit 142 stores the sign indicator SIGN until the TDC circuit 102 generates the integer 106. The sign correction circuit 144 corrects the high-resolution integer 140 if the SIGN generated by the sign flip-flop circuit 142 indicates that the time residual TR is negative. The selector circuit 148 selects either the high-resolution integer 140 from the TDC circuit 102 or the integer 132 from the coarse TDC circuit 127, depending on which one is to be used. In this specification, the term “flip-flop circuit” may be used synonymously with the terms “data flip-flop” or “flip-flop”.

[0025]

[0035] Figure 3 is a flowchart of the method of the exemplary TDC circuit of Figure 1 for determining the number of time increments TI and the fraction of time increments within a period TP, the method comprising receiving a start pulse signal START and a stop pulse signal STOP separated in time by the period TP (block 302), determining an integer 106 of the first time increment TI within the period TP and a time residual TR smaller than the first time increment TI (block 304). The method comprises adding the time residual TR to a previously accumulated residual PAR to generate the current accumulated residual CAR (block 306), and generating a fraction indicator 110 indicating whether the difference between the current accumulated residual and the first time increment is greater than the fraction of the first time increment TI (block 308). The method further includes generating the next cumulative residual NAR, which includes the difference between the first time increment TI and the current cumulative residual CAR, in response to the fraction indicator 110 indicating that the difference between the current cumulative residual CAR and the first time increment TI is greater than a fraction of the first time increment TI (block 310), and generating the next cumulative residual NAR, which includes the difference between the current cumulative residual CAR and the first time increment TI, in response to the fraction indicator 110 indicating that the difference between the current cumulative residual CAR and the first time increment TI is less than a fraction of the first time increment TI (block 312).

[0026]

[0036] Figure 4 is a logic circuit diagram showing details of a first measurement circuit 400, which may be the first measurement circuit 104 in the TDC circuit 102 of Figure 1. The first measurement circuit 400 is used to determine the number of time increments TI within the period TP and to provide the remaining time TR to the second measurement circuit 108.

[0027]

[0037] The first measurement circuit 400 employs a method similar to a vernier TDC circuit (not shown), in which the start pulse signal propagates through a sequence of delay circuits, each having a first delay T1 ("first delay period T1"), and the stop pulse signal propagates through a sequence of delay circuits, each having a second delay T2 ("second delay period T2"). Since the second delay T2 is shorter than the first delay T1, the stop pulse signal eventually catches up to the start pulse signal after X delay circuits. From this, it can be determined that the start pulse signal and the stop pulse signal in this example are separated by a period of at least X × T1 - T2. In such a circuit, the first problem is that the time difference between the start pulse signal and the stop pulse signal may include a time residual less than T1 - T2, which cannot be measured by a vernier circuit. Since the resolution of time measurement by a vernier circuit is limited to T1 - T2, the time residual may allow for a difference or error less than T1 - T2 in the PLL. A second problem with the vernier circuit is that the delay circuits in the first column may not all have the same delay T1, for example, due to process variations during manufacturing, and for the same reason, the delay circuits in the second column may not all have exactly the same delay T2, which can introduce noise into the output clock generated by the PLL. The TDC circuit 102 addresses both of these problems. The first problem is addressed by the second measurement circuit 108 in Figure 1, which will be described in detail with reference to Figure 6. The second problem is addressed as follows.

[0028]

[0038] The first measurement circuit 400 includes a first delay feedback circuit 402, which has a first delay circuit 404 that receives a start pulse signal START at a first delay input 406. The first delay feedback circuit 402 delays the start pulse signal START using the first delay circuit 404, generating a delayed start pulse signal DSTRT at a first delay output 408. The first delay circuit 404 has a delay of duration T1. In this respect, the first delay circuit 404 corresponds to a stage in the first delay circuit sequence in the vernier circuit, but instead of passing the delayed start pulse signal DSTRT to the next delay circuit, the first delay feedback circuit 402 feeds back the delayed start pulse signal DSTRT from the first delay output 408 to the first delay input 406, iteratively using the first delay circuit 404 again.

[0029]

[0039] In a similar embodiment, the first measurement circuit 400 includes a second delay feedback circuit 410 comprising a second delay circuit 412 that receives a stop pulse signal STOP at a second delay input 414. The second delay feedback circuit 410 delays the stop pulse signal STOP using the second delay circuit 412, generating a delayed stop pulse signal DSTP at a second delay output 416. The second delay circuit 412 has a delay of duration T2, which is shorter than T1. Therefore, the measurement of the time increment TI by the first measurement circuit 400 (resolution T RES The (also known as) is T1-T2. In this regard, the second delay circuit 412 corresponds to a stage in the second delay circuit sequence in the vernier circuit, while the second delay feedback circuit 410 feeds back the delayed stop pulse signal DSTP from the second delay output 416 to the second delay input 414, iteratively reusing the second delay circuit 412. By using the first delay feedback circuit 402 and the second delay feedback circuit 410, the first delay circuit 404 and the second delay circuit 412 are reused, so that delay mismatches due to different cascade cells do not occur, as in the case of conventional vernier TDC. In this regard, the first measurement circuit 400 avoids spurious stones.

[0030]

[0040] The first measurement circuit 400 includes a flip-flop circuit 418 having a data output 420 that is set when a delayed start pulse signal DSTRT is first provided to data input 422 and a delayed stop pulse signal DSTP is first provided to clock input 424. The data output 420 is reset in subsequent iterations if a delayed stop pulse signal DSTOP is generated at the second delayed output 416 before the delayed start pulse signal DSTRT is generated at the first delayed output 408. In other words, the flip-flop 418 is reset when the propagation of the delayed stop pulse signal DSTOP through the second delayed feedback circuit 410 catches up with the propagation of the delayed start pulse signal DSTRT through the first delayed feedback circuit 402.

[0031]

[0041] The first measurement circuit 400 includes a counter circuit 426 which includes a counter 428 and a count flip-flop 430. A trigger flip-flop 432 in the first measurement circuit 400 is used to detect the transition of the count mode flip-flop 418 and to trigger the generation of a time residual TR as the difference between a first time residual signal TRS1 at a first residual output 434 and a second time residual signal TRS2 at a second residual output 436.

[0032]

[0042] A description of the first measurement circuit 400 and additional features of its operation is provided with further reference to Figure 4 and also to the timing diagram 500 in Figure 5. Figure 5 is a timing diagram showing signals at specific points in the first measurement circuit 400. These signals are represented as binary values ​​(e.g., "0" or low and "1" or high) that can represent voltage levels at identified points in the first measurement circuit 400. The transitions between these binary values ​​are referred to herein, for example, as "rising edges" and "falling edges" when the passage of time is from left to right.

[0033]

[0043] Specifically, from top to bottom, timing diagram 500 includes inputs 438 and 440 that receive a start pulse signal START and a stop pulse signal STOP, respectively. Next, Figure 5 includes a first delay input 406, a second delay input 414, a first delay output 408, and a second delay output 416. Figure 5 also includes the data output 420 of the count mode flip-flop 418 and a node 442 used to trigger the generation of the time residual TR. Finally, Figure 5 includes the first residual output 434 and the second residual output 436 from which the time residual TR is generated.

[0034]

[0044] As shown in Figure 5, the leading edge L1 of the start pulse signal START, where the level of the start pulse signal START rises, occurs at time t0, and at time t1, the leading edge L2 of the stop pulse signal STOP indicates the rising edge of the stop pulse signal STOP. The time between the leading edge of the start pulse signal START and the leading edge of the stop pulse signal STOP is the period TP measured by the first measurement circuit 400 in time increment TI (i.e., TP = t1 - t0). The start pulse signal START and the stop pulse signal STOP are received by the pulse generation circuit 444. The pulse generation circuit 444 generates a wide pulse WP corresponding to the start pulse signal START on the first delay input 406 and a narrow pulse NP corresponding to the stop pulse signal STOP on the second delay input 414. The rising edge of the narrow pulse NP follows the rising edge of the wide pulse WP by a period of TP, but the narrow pulse NP and the wide pulse WP fall simultaneously.

[0035]

[0045] The wide pulse WP propagates through the first delay circuit 404 to the first delayed output 408, passing through the first delay circuit 404 and passing through the first NOR gate R1 and the second NOR gate R2. The first delayed output 408 is coupled to the input of the AND gate A1, which is further coupled to the first NOR gate R1. In this respect, a feedback loop is formed from the first delayed output 408 back to the first delayed input 406. The total time T1_P of the first feedback loop, from the first delayed output 408 back to the first delayed output 408 through the first delayed feedback circuit 402, includes the propagation delays through the NOR gates R1 and R2, the AND gate A1, and the first delay circuit 404.

[0036]

[0046] The narrow pulse NP propagates through the third NOR gate R3 and the fourth NOR gate R4 before propagating through the second delay circuit 412 to the second delayed output 416. The second delayed output 416 is coupled to the input of another AND gate A2, which is further coupled back to the third NOR gate R3. In this respect, a feedback loop is also formed from the second delayed output 416 back to the second delayed input 414. The total time T2_P of the second feedback loop through the second feedback delay circuit 410 includes propagation through the NOR gates R3 and R4, AND gate A2, and the second delay circuit 412.

[0037]

[0047] The wide pulse WP on the first delayed output 408 is also called the delayed start pulse signal DSTART, and the narrow pulse NP on the second delayed output 416 is also called the delayed stop pulse signal DSTOP. The first delayed output 408 is coupled to the data input 422 of the count-mode flip-flop 418, and the second delayed output 416 is coupled to the clock input 424 of the count-mode flip-flop 418. The range determination circuit 112 in Figure 1 includes a lower limit detector 118 for determining that the period TP provided to the TDC circuit 102 in Figure 1 is greater than or equal to T1-T2. Therefore, when the wide pulse WP first propagates through the first delayed circuit 404 to the first delayed output 408 (see time t2), the rising edge of the wide pulse WP arrives at the data input 422 before the rising edge of the narrow pulse NP (see t3) arrives at the clock input 424. Therefore, the rising edge of the narrow pulse NP triggers the count-mode flip-flop 418, causing the wide pulse WP to propagate from the data input 422 to the data output 420. The second delayed output 416 is also coupled to the counter 428 of the counter circuit 426, thereby incrementing the counter 428 each time the narrow pulse NP propagates through the second delayed circuit 412 onto the second delayed output 416 (see t3 and t4) after the wide pulse WP has already propagated through the first delayed circuit 404 to the first delayed output 408. Thus, the counter 428 counts the iterations of the narrow pulse NP through the second delayed feedback circuit 410. The number of iterations is provided to the count flip-flop 430 on node 446.

[0038]

[0048] The data output 420 remains high as the wide pulse WP and narrow pulse NP are iteratively fed back through the first delay feedback circuit 402 and the second delay feedback circuit 410, respectively. Because the delay T2 of the second delay feedback circuit 410 is shorter than the delay T1 of the first delay feedback circuit 402, the rising edge of the delayed stop pulse signal DSTOP (or narrow pulse NP) arrives at the second delay output 416 after several iterations, before the rising edge of the delayed start pulse signal DSTRT (or wide pulse WP) arrives at the first delay output 408 (see t5). If the narrow pulse NP arrives at the clock input 424 of the count-mode flip-flop 418 before the wide pulse WP arrives at the data input 422 of the count-mode flip-flop 418, then the data input 422 of the count-mode flip-flop 418 remains low as the narrow pulse NP clocks the data input 422 all the way to the data output 420, thereby causing the data output 420 to drop to a low level at t6.

[0039]

[0049] As described above, the number of iterations of the delayed stop pulse signal DSTOP on the second delayed output 416 is provided by the counter 428 to the count flip-flop 430 on node 446. When the data output 420 drops to a low level, the count flip-flop 430 stores the count value in node 446 to generate an integer 448 (which may be the integer 106 in Figure 1). In this regard, the first measurement circuit 400 determines the number of time increments TI (equal to T1-T2) that occur within the period TP. The remaining time in the period TP is the time residue TR, which is the difference between the rising edge on the second delayed output 416 and the rising edge on the first delayed output 408, or the amount of time that the rising wide pulse WP is led by the rising narrow pulse NP.

[0040]

[0050] Furthermore, as the data output 420 drops to a low level, the AND gates 450 and 452 coupled to the second delayed output 416 and the first delayed output 408, respectively, are turned on. Thus, based on the narrow pulse NP, the first rising edge occurs on the first residual output 434. Later, the rising edge occurs on the second residual output 436 (corresponding to the wide pulse WP). The time between the rising edge on the first residual output 434 and the rising edge on the second residual output 436 is the time residual TR between the rising edge of the second delayed output 416 and the rising edge of the first delayed output 408.

[0041]

[0051] Reference clock C shown in Figure 2 REF Each cycle generates a start pulse signal START and a stop pulse signal STOP. Therefore, the reference clock C REF When the integer 106 is generated in the first cycle, the first measurement circuit 400 needs to be reset in preparation for measuring the period TP in the next cycle. In this regard, the first measurement circuit 400 includes a reset flip-flop 454 having a clock input 456 coupled to the negative data output 458 of the count-mode flip-flop 418. As described above, when the delayed stop pulse signal DSTP catches up with the delayed start pulse signal DSTART, and the data output 420 of the count-mode flip-flop 418 drops to a low level, the negative data output 458 rises and triggers the clock input 456. The data input 460 of the reset flip-flop 454 receives a master reset signal RSTB, which is not used in normal operation and can be assumed to remain at a high ("1") level. The negative data output 462 of the reset flip-flop 454 causes the pulse generator 464 to reset the counter 428. When the next start pulse signal START and stop pulse signal STOP arrive, the pulse generator 466 resets the reset flip-flop 454. The master reset signal RSTB is provided to the other inputs of the first measurement circuit 400, as shown in Figure 4.

[0042]

[0052] Figure 6A is a logic circuit diagram showing details of a second measurement circuit 600, which may be a second measurement circuit 108 in the TDC circuit 102 of Figure 1. The second measurement circuit 600 receives a time residual TR from the first measurement circuit 104 (or the first measurement circuit 400 in Figure 4) and adds the time residual TR to the previously accumulated residual PAR to generate the current accumulated residual CAR. The second measurement circuit 600 generates a fractional indicator 110 based on the current accumulated residual CAR, which is added (e.g., by the adder 138 in Figure 1) to improve the resolution of the integer 106. The second measurement circuit 600 also calculates the next accumulated residual NAR. As described below, the next accumulated residual NAR generated in one cycle of the start pulse signal START and stop pulse signal STOP is fed back to become the previously accumulated residual PAR in the next cycle of the start pulse signal START and stop pulse signal STOP. In this way, all time residuals TR contribute to the accuracy of the TDC.

[0043]

[0053] The second measurement circuit 600 includes a time adder 602, an analog-to-digital converter (ADC) circuit 604, and a digital-to-analog converter (DAC) circuit 606, which are described individually. A detailed logic circuit diagram of the time adder 602 is provided in Figure 6B. As shown in Figure 6A, the time adder 602 receives a residual start signal RSTRT on a first residual input 608 and a residual stop signal RSTOP on a second residual input 610. The first residual input 608 may be coupled to the first residual output 434 of the first measurement circuit 400 in Figure 4, and the second residual input 610 may be coupled to the second residual output 435. The residual stop signal RSTOP rises after the residual start signal RSTRT with a temporal separation equal to the time residual TR of the period TP. The time adder 602 also receives previously accumulated residual PARs on a first PAR input 612 and a second PAR input 614. The temporal separation between the rising edge on the first PAR input 612 and the rising edge on the second PAR input 614 is equal to the previously accumulated residual PAR. As illustrated with reference to Figure 6B, the temporal residual TR and the previously accumulated residual PAR are summed by the time summing circuit 602.

[0044]

[0054] The time summing circuit 602 in Figure 6B includes a discharge circuit 616, a first capacitor 618, a second capacitor 620, a first sum flip-flop 622, and a second sum flip-flop 624. A detailed description of the time summing circuit 602 is first provided with reference to Figure 6B, and a detailed description of the operation of the time summing circuit 602 is provided with reference to both Figure 6B and the timing diagram in Figure 7.

[0045]

[0055] The discharge circuit 616 includes a first discharge control circuit 626 (including transistors 628A and 628B) for discharging the first capacitor 618 in response to an initialization reset signal RST_INI. Transistors 628A and 628B are connected in series between the first node 630P and the ground rail GND. The first discharge control circuit 626 also includes transistors 632A and 632B, similarly connected in series between the first node 630P and the ground rail GND. The control inputs 634A and 634B of transistors 632A and 632B are connected to a second PAR input 614 and a first residual input 608, respectively.

[0046]

[0056] The discharge circuit 616 also includes a second discharge control circuit 636 (including transistors 638A and 638B) for discharging the second capacitor 620 in response to an initialization reset signal RST_INI. Transistors 638A and 638B are coupled in series between the second node 630N and the ground rail GND. The second discharge control circuit 636 also includes transistors 639A and 639B, similarly coupled in series between the first node 630P and the ground rail GND. The control inputs 640A and 640B of transistors 639A and 639B are coupled to the first PAR input 612 and the second residual input 610, respectively. The first node 630P is coupled to the power rail PWR by a first switch (e.g., transistor) 642A, and the second node 630N is coupled to the power rail PWR by a second switch 642B. Both the first switch 642A and the second switch 642B are controlled by the residual start signal RSTRT. The first node 630P is coupled to the clock input 646A of the first sum flip-flop 622 via the first inverter 648A, and the second node 630N is coupled to the clock input 646B of the second sum flip-flop 624 via the second inverter 648B.

[0047]

[0057] The first residual input 608 (RSTRT) and the second residual input 610 (RSTOP) are at a low level before the time residual TR is provided. The low level of the residual start signal RSTRT controls the first switch 642A and the second switch 642B to open, coupling the first node 630P and the second node 630N to the power rail PWR, thereby charging both the first capacitor 618 and the second capacitor 620 to the first voltage VDD (which may be the power supply voltage). The first PAR input 612 and the second PAR input 614 are also at a low level initially, turning on transistor 632A in the first discharge control circuit 626 and transistor 638A in the second discharge control circuit 636. The low levels of the first residual input 608 and the second residual input 610 maintain the interruption of transistors 632B and 638B. Therefore, even if transistors 632A and 638A are turned on, the first capacitor 618 and the second capacitor 620 cannot be discharged through the first discharge control circuit 626 and the second discharge control circuit 636 in the initial state shown in Figure 7.

[0048]

[0058] At time t0 in the timing diagram of Figure 7, the rising edge of the first residual input 608 interrupts the first switch 642A and the second switch 642B. The rising edge of the first residual input 608 turns on transistor 632B, thereby enabling the discharge of the first capacitor 618, as indicated by the voltage at the first node 630P in Figure 7. Following the rising edge of the first residual input 608, at time t1, the rising edge of the second residual input 610 occurs, with an isolation time equal to the time residual TR. The rising edge of the second residual input 610 turns on transistor 638B, thereby enabling the discharge of the second capacitor 620, as indicated by the voltage at the second node 630N in Figure 7. The first capacitor 618 discharges for the duration of the residual time TR, and thereafter both the first capacitor 618 and the second capacitor 620 continue to discharge after the rise of the second residual input 610.

[0049]

[0059] Assuming that the first capacitor 618 and the second capacitor 620 discharge at the same rate, the difference between the voltage at the first node 630P and the voltage at the second node 630N at time t1 corresponds to the time residual TR. This difference remains constant because both the first capacitor 618 and the second capacitor 620 continue to discharge. At time t2, shortly after the rise of the second residual input 610 at t1, one of the first PAR input 612 and the second PAR input 614 occurs. In the first example of Figure 7, the first PAR input 612 rises at t2, shutting off transistor 638A, which stops the discharge of the second capacitor 620 (e.g., node 630N) from the first voltage VDD to the second reduced voltage V2, while the first capacitor 618 continues to discharge. At time t3 following time t2, with a time interval equal to the previously accumulated residual PAR, the second PAR input 614 also rises, shutting off transistor 632A and stopping the discharge of the first capacitor 618 (e.g., node 630P) from the first voltage VDD to the first reduced voltage V1. Thus, the discharge duration of the first capacitor 618 differs from the discharge duration of the second capacitor by a time interval equal to the time residual TR and the previously accumulated residual PAR. Since this time difference in discharge duration corresponds to a voltage difference based on the same discharge rate, the voltage difference between the first node 630P and the second node 630N at time t3 is related to the sum of the time residual TR and the previously accumulated residual PAR.

[0050]

[0060] At time t4, the reset signal RST (unrelated to the master reset signal RSTB mentioned above) resets the first sum signal SUM+ on the adder output 644A of the first sum flip-flop 622 and the second sum signal SUM- on the adder output 644B of the second sum flip-flop 624 to a low level. As shown in Figure 7, the voltages at the first node 630P and the second node 630N drop (which causes the inverters 648A and 648B to raise the voltages at the clock inputs 646A and 646B), but the first sum flip-flop 622 and the second sum flip-flop 624 are not triggered (e.g., by the clock). However, at time t5, both the first PAR input 612 and the second PAR input 614 transition to a low level, thereby turning on transistors 632A and 638A again and discharging both the first capacitor 618 and the second capacitor 620 at the same rate. The difference between the voltage at the first node 630P and the voltage at the second node 630N causes the first node 630P to first trigger a threshold voltage V, which is the clock input 646A of the first sum flip-flop 622. THR Below this threshold, the first sum signal SUM+ is set at time t6. Since the difference between the voltage at the first node 630P and the voltage at the second node 630N is related to the sum of the time residual TR and the previous cumulative residual PAR, the second node 630N discharges to the threshold voltage V THR The value falls below this threshold, thereby activating the clock input 646B and setting the second sum signal SUM- of the second sum flip-flop 624 at time t7. Thus, the time difference between the activation of the first sum signal SUM+ and the activation of the second sum signal SUM- is also equal to the sum of the time residual TR and the previously accumulated residual PAR, which is the current accumulated residual CAR.

[0051]

[0061] Referring again to Figure 6A, the first sum signal SUM+ and the second sum signal SUM- are outputs from the time summing circuit 602, which are coupled to the first input 650A and the second input 650B of the ADC circuit 604, respectively. The function of the ADC circuit 604 is to determine whether the magnitude of the current cumulative residual CAR (which can be positive or negative) is greater than a fraction of the time increment TI. In this example, the fraction is 1 / 2. The ADC circuit 604 includes a first T1 delay circuit 652 and a first T0 delay circuit 654, both of which are coupled to the first input 650A. The ADC circuit 604 also includes a second T0 delay circuit 656 and a second T1 delay circuit 658, both of which are coupled to the second input 650B. The first T1 delay circuit 652 and the second T1 delay circuit 658 have the same duration T1 delay as the first delay circuit 404. The first T0 delay circuit 654 and the second T0 delay circuit 656 have the same delay duration T0.

[0052]

[0062] For reasons explained below with reference to DAC circuit 606, the difference between T1 and T0 is half the difference between T1 and T2 in Figure 4. That is, the time increment TI used in the first measurement circuit 400 in Figure 4 (which determines the resolution of TDC circuit 102 in Figure 1) is twice the difference between T1 and T0, or T1-T0=(T1-T2) / 2. ADC circuit 604 generates a fractional indicator 660 corresponding to the fractional indicator 110 in Figure 1 to indicate whether the current cumulative residual CAR is greater than or equal to T1 / 2, and whether it is positive or negative.

[0053]

[0063] The ADC circuit 604 also includes a positive arbiter 662 and a negative arbiter 664. The first T1 delay circuit 652 is coupled to the data input DIN1 of the positive flip-flop 662, and the second T0 delay circuit 656 is coupled to the clock input CKIN1 of the first positive flip-flop 662. In the above example where the current cumulative residual CAR is a positive value, the rising edge of the second sum signal SUM- (output 644B) follows the rising edge of the first sum signal SUM+ (output 644A) after a time equal to the current cumulative residual CAR. In such an example, the rising edge of output 644A propagates through the first T1 delay circuit 652, and the rising edge on output 644B that arrives later propagates through the second T0 delay circuit. If the current cumulative delay CAR is greater than T1-T0, the rising edge propagating through the first T1 delay circuit 652 arrives at the data input DIN1 of the positive flip-flop 662 before the rising edge propagating through the second T0 delay circuit 656 arrives at the clock input CKIN1, and the data output DOUT1 of the positive flip-flop 662 is set to a high level ("1"). On the other hand, if the current cumulative delay CAR is less than T1-T0, the rising edge propagating through the second T0 delay circuit 656 arrives at the clock input CKIN1 before the rising edge propagating through the first T1 delay circuit 652 arrives at the data input DIN1 of the positive flip-flop 662, and the data output DOUT1 of the positive flip-flop 662 is set to a low level ("0").

[0054]

[0064] A current cumulative residual CAR with a negative value first generates a rising edge on output 644B, followed by a rising edge on output 644A. As described above, the rising edges propagating through the first T0 delay circuit 654 and the second T1 delay circuit 658 cause the data output DOUT2 of the negative flip-flop 664 to be set to "1" if the magnitude of the current cumulative residual CAR is greater than T1-T0, and to "0" otherwise. The fractional indicator 660 is determined by the positive flip-flop 662 and the negative flip-flop 664. In this example, the fractional indicator 660 may be a 2-bit binary value of 01, 00, or 10.

[0055]

[0065] As described above, the fractional indicator 660 may be the fractional indicator 110 in Figure 1, and the integer 448 in Figure 4 may be the integer 106. The fractional indicator 110 is used to effectively round up or round down the integer 106 based on the current cumulative residual CAR. By including the fractional indicator 110 together with the integer 106, the TDC circuit 102 improves accuracy compared to a TDC circuit that has only integer outputs and does not consider the residual. This adjustment is illustrated in the following example.

[0056]

[0066] In the first example, where the current cumulative residual CAR is +0.75(TI) (which is greater than TI / 2), the fractional indicator 660 causes the integer provided to DCO202 to increment by 1. As can be understood, this is an overadjustment in accordance with the actual time residual TR in a given cycle. However, the next cumulative residual NAR will be -0.25(TI) in the next cycle (or later) to compensate for the overadjustment.

[0057]

[0067] In the second example, the current cumulative residual CAR is any value between approximately +0.49(TI) and approximately -0.49(TI) (a small margin compared to 0.5 to account for possible device variations and jitter effects), the fractional indicator does not change the integer 106 in Figure 1, and the current cumulative residual CAR becomes the next cumulative residual NAR to be used in the next cycle.

[0058]

[0068] In the third example, since the current cumulative residual CAR is -0.82(TI), the fractional indicator 660 decrements the integer 106, giving +0.18(TI), which is the next cumulative residual NAR.

[0059]

[0069] Based on the above example, on average, the output clock C OUT and reference clock C REF It can be seen that the phase difference is significantly reduced.

[0060]

[0070] The purpose of the DAC circuit 606 is to provide the next accumulated residual NAR from the current cycle as the previously accumulated residual PAR in the next cycle. The DAC circuit 606 can use the output of the ADC circuit 604 to decide whether to add or subtract a time increment TI (=T1-T2) to the current accumulated residual CAR in order to generate the NAR. The DAC circuit 606 is first described structurally with reference to Figure 6A, and its operation is described again with further reference to Figure 7.

[0061]

[0071] The DAC circuit 606 includes a first T1 delay circuit 670 and a first T2 delay circuit 672, both of which are coupled to output 644A and to the first input 674A and second input 674B of multiplexer 676, respectively. The DAC circuit 606 also includes a second T1 delay circuit 680 and a second T2 delay circuit 682, both of which are coupled to output 644B and to the first input 684A and second input 684B of multiplexer 686, respectively. Outputs ERR+ and ERR- of multiplexer 676 are coupled to delay circuit 690.

[0062]

[0072] Referring again to Figure 7, the rising edges of the first sum signal SUM+ and the second sum signal SUM- are shown at times t5 and t6, respectively. The first sum signal SUM+ rises first, which occurs when the sign of the current cumulative residual CAR is positive. If it is negative, the rising edge of the second sum signal SUM- occurs before the rising edge of the first sum signal SUM+.

[0063]

[0073] At time t6, the rising edge of the output SUM+ is provided to the first T1 delay circuit 670 and the first T2 delay circuit 672. Based on the fractional indicator 660, the multiplexer 676 selects the first sum signal SUM+ delayed by T1 minutes, as provided by the output ERR+. At time t7, the rising edge of the second sum signal SUM- is provided to the second T1 delay circuit 680 and the second T2 delay circuit 682, and the multiplexer 686 selects the SUM- delayed by T2 minutes, as provided by the output ERR-. In this way, the time difference between the first sum signal SUM+ and the second sum signal SUM- is reduced by a time increment TI(T1-T2). This is the time difference between ERR+ and ERR-, which is the next accumulated residual NAR, shown at time t78 as the previously accumulated residual PAR in the next cycle. As shown in the figure, NAR is a negative amount equal to the current cumulative residual CAR minus (T1-T2). The delay circuit 690 delays ERR+ and ERR- by the same amount of time and is coupled to the first PAR input 612 and the second PAR input 614, where a one-cycle reference clock C REF The next accumulated residual NAR is stored and, in the next cycle, is provided as the previously accumulated residual PAR.

[0064]

[0074] Figure 8 shows a time resolution T including the first feedback circuit 402 and the second feedback delay circuit 410 of Figure 4. RESThis is a logic diagram of a calibration circuit 800 for calibrating the difference between the first delay period T1_P of the first feedback circuit 402 and the second delay period T2_P of the second feedback delay circuit 410. Details of the first feedback circuit 402 and the second feedback delay circuit 410 are provided above and will not be repeated here. The difference between T1_P and T2_P is determined when the first number or count value CNT1 of the first delay period T1_P is equal to the second number or count value CNT2 of the second delay period T2_P. This can be expressed by the following formula:

[0065]

[0075] CNT1 × T1_P = CNT2 × T2_P.

[0066]

[0076] For example, if CNT1=4 and CNT2=5, then (4)×T1_P=(5)×T2_P.

[0067]

[0077] T RES =T1_P-T2_P, therefore in this example, T RES It can be seen that = T1_P / 5.

[0068]

[0078] To reiterate, the first delay period T1_P in Figure 4 is based on the first delay T1 of the first delay circuit 404, the NOR gates R1 and R2, and the AND gate A1. The second delay period T2_P is based on the second delay T2 of the second delay circuit 412, the NOR gates R3 and R4, and the AND gate A2. Assuming that the NOR gates R1 to R4 all have the same delay and the AND gates A1 and A2 also have the same delay, the main difference between the first delay period T1_P and the second delay period T2_P is based on the difference between the first delay T1 and the second delay T2. The first delay T1 and the second delay T2 may be selected to satisfy the above equation, where T1_P = 10 ns and T2_P = 8 ns. However, since variations in propagation delay are unavoidable among all components, a calibration circuit 800 is provided to realize or approximate the above relationship CNT1 × T1_P = CNT2 × T2_P.

[0069]

[0079] The calibration operation of the calibration circuit 800, which may be performed in the calibration mode of the first measurement circuit 400, counts the number of CAL_IN iterations, determines whether CNT1 × T1_P = CNT2 × T2_P, and adjusts the second delay period T2_P. Alternatively, the calibration circuit 800 may adjust the first delay period T1_P, or both the first delay period T1_P and the second delay period T2_P. Such operation is described below following the description of the components of the calibration circuit 800.

[0070]

[0080] The first delay output 802 of the first delay feedback circuit 402 is coupled to the calibration counter 804 and the time delay 806. Both the calibration counter 804 and the time delay 806 are coupled to the AND gate 808. Similarly, the second delay output 810 of the second delay feedback circuit 410 is coupled to the inputs of the second calibration counter 812 and the time delay 814, both of which are further coupled to the AND gate 816.

[0071]

[0081] AND gates 808 and 816 have outputs 818A and 818B, respectively, which are coupled to a sequence determination circuit 820. The output 822 of the sequence determination circuit 820 is provided to an adjustment circuit 824, which can generate an adjustment signal ADJ on output 826. Output 826 is coupled to a variable capacitor 828, which is further coupled to a second delayed output 810 of a second delayed feedback circuit 410.

[0072]

[0082] In calibration mode, the input 830A of the first delay circuit 402 and the input 830B of the second delay circuit 410 are coupled to each other to simultaneously receive the calibration pulse signal CAL_IN, as shown in Figure 9. Calibration counter 804 counts the first number of iterations of the calibration pulse signal CAL_IN propagating through the first delay circuit 402 in the feedback loop, and calibration counter 812 counts the second number of iterations of the calibration pulse signal CAL_IN propagating through the second delay feedback circuit 410.

[0073]

[0083] When the count value CNT1 of the calibration counter 804 reaches a desired value (for example, 4 in the above example), the calibration counter 804 generates a first calibration pulse CP1 for the AND gate 808. The time delay 806 delays the CAL_IN pulse received from the first delay output 810 so as to synchronize the first calibration pulse CP1 with the AND gate 808. When the count value CNT2 of the calibration counter 812 reaches its desired value (for example, 5), a second calibration pulse CP2 is generated by the calibration counter 812 and provided to the AND gate 816, synchronized by the CAL_IN pulse propagating through the time delay 814.

[0074]

[0084] The sequence determination circuit 820 includes arbiter circuits 832A and 832B. A first calibration pulse CP1 is provided as data to arbiter circuit 832A via a first offset (delay) circuit 834P, and the first calibration pulse CP1 is also provided to clock arbiter circuit 832B without delay. Similarly, a second calibration pulse CP2 is provided as data to flip-flop circuit 832B via a second offset circuit 834N, and the second calibration pulse CP2 is also provided to clock arbiter circuit 832A without offset delay. The offset circuits 834P and 834N ensure that neither flip-flop circuits 832P nor 832N is set (e.g., to "1") unless the time difference between the first calibration pulse CP1 and the second calibration pulse CP2 is greater than the offset delay. The incrementer 836 generates an adjustment signal ADJ on output 826 as one of +1, 0, or -1, depending on the flip-flop circuits 832P and 832N.

[0075]

[0085] For example, if the flip-flop circuit 832P is set by the second pulse signal CP2 at the first clock input CK1, the second calibration pulse CP2 precedes the first calibration pulse CP1 by at least the offset delay of the offset circuit 834P. Therefore, if the first calibration pulse CP1 and the second calibration pulse CP2 are separated by more than the offset delay in time, the incrementer 836 generates either +1 or -1, whichever is appropriate, to increase the capacitance of the variable capacitor 828 in response to the adjustment signal ADJ (this increases the capacitance of the second delay output 810 and increases the second delay period T2_P). The variable capacitor 828 can be adjusted to increase or decrease its capacitance in response to the adjustment signal ADJ. The adjustment signal ADJ adjusts the capacitance of the variable capacitor 828 by an increment, and this operation is repeated until the first calibration pulse CP1 and the second calibration pulse CP2 separate below the offset delay, thereby making the adjustment signal ADJ "0". During normal operation other than calibration mode, the variable capacitor 828 is maintained at the determined capacitance value. By using the calibration circuit 800, the time increment TI may be within a range of less than 5% of T1_P. In some examples, the time increment TI may be less than 2% of T1_P.

[0076]

[0086] One operation of the calibration circuit 800 can be seen in the timing diagram 900 in Figure 9. After the arrival of the calibration pulse signal CAL_IN, both the count value CNT1 of counter 804 and the count value CNT2 of calibration counter 812 are incremented in response to the calibration pulse signal CAL_IN propagating to the first delayed output 802 and the second delayed output 810. The count value CNT1 is incremented each time the calibration pulse signal CAL_IN propagates to the first delayed output 802, and the count value CNT2 of calibration counter 812 is incremented each time the calibration pulse signal CAL_IN propagates to the second delayed output 810. Circuits 838, 840, 842, 844, and 846 are used to reset the calibration circuit 800 in preparation for the next calibration pulse signal CAL_IN.

[0077]

[0087] Figure 10 is a block diagram of an exemplary processor-based system 1000, which includes a processor 1002 (e.g., a microprocessor) with an instruction processing circuit 1004, the PLL 200 of Figure 2, and the TDC system 100 of Figure 1. Any of the processor-based system 1000, the processor 1002, and the instruction processing circuit 1004 may, for example, be the IC chip 101 of Figure 1. The processor-based system 1000 may be one or more circuits contained within an electronic circuit board card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer.

[0078]

[0088] In this example, processor 1002 represents one or more general-purpose processing circuits, such as a microprocessor or a central processing unit. Processor 1002 is configured to execute processing logic in instructions for performing the operations and steps described herein. In this example, processor 1002 includes an instruction cache 1006 for temporary high-speed access memory storage of instructions accessible by instruction processing circuit 1004. Instructions fetched or prefetched from memory, such as cache memory 1012, via the system bus 1010 are stored in the instruction cache 1006. Instruction processing circuit 1004 is configured to process the instructions fetched into the instruction cache 1006 and process the instructions for execution.

[0079]

[0089] The processor 1002 and cache memory 1012 are coupled to a system bus 1010, enabling interconnection of peripheral devices included in the processor-based system 1000. As is well known, the processor 1002 communicates with these other devices by exchanging address, control, and data information via the system bus 1010. For example, the processor 1002 can transmit bus transaction requests to a memory controller 1014 in the main memory 1008, as an example of a slave device. Although not shown in Figure 10, multiple system buses 1010 may be provided, each system bus constituting a different fabric. In this example, the memory controller 1014 is configured to provide memory access requests to a memory array 1016 in the main memory 1008. The memory array 1016 consists of an array of storage bit cells for storing data. The main memory 1008 may, in non-limiting examples, be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM)).

[0080]

[0090] Other devices can be connected to the system bus 1010. As shown in Figure 10, these devices may include, for example, main memory 1008, one or more input devices 1018, one or more output devices 1020, modem 1022, and one or more display controllers 1024. One or more input devices 1018 may include any type of input device, including (but not limited to) input keys, switches, voice processors, etc. Output devices 1020 may include any type of output device, including (but not limited to) audio, video, other visual indicators, etc. Modem 1022 may be any device configured to enable data exchange with network 1026. Network 1026 may be any type of network, including (but not limited to) wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth® networks, and the Internet. Modem 1022 may be configured to support any desired type of communication protocol. The processor 1002 may also be configured to access one or more display controllers 1024 via the system bus 1012 to control information transmitted to one or more displays 1028. The displays 1028 may include any type of display, including but not limited to cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma displays, etc. The input device 1018, modem 1022, and output device 1020 may be an IC chip 101, or otherwise include the TDC system 100.

[0081]

[0091] The processor-based system 1000 in Figure 10 may include a set of instructions 1030 executed by the processor 1002 for any desired application according to the instructions. The instructions 1030 may be stored in main memory 1008, the processor 1002, and / or the instruction cache 1006 as an example of a non-temporary computer-readable medium 1032. The instructions 1030 may also reside entirely or at least partially in main memory 1008 and / or the processor 1002 during execution. The instructions 1030 may also be transmitted or received over network 1026 via modem 1022 so that network 1026 includes computer-readable medium 1032, and although computer-readable medium 1032 is shown as a single medium in exemplary embodiments, the term “computer-readable medium” should be interpreted to include a single medium or multiple mediums (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more instruction sets. The term “computer-readable medium” shall also be interpreted to include any medium capable of storing, encoding, or transmitting a set of instructions for execution by a processing device, and causing a processing device to execute one or more of the methodologies of the embodiments disclosed herein. Accordingly, the term “computer-readable medium” shall be interpreted to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0082]

[0092] The embodiments disclosed herein include a variety of steps. The steps of the embodiments disclosed herein may be formed by hardware components or embodied by machine-executable instructions, which can be used to cause a general-purpose or dedicated processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0083]

[0093] Embodiments disclosed herein may be provided as computer program products or software that include a machine-readable medium (or computer-readable medium) storing instructions that can be used to program a computer system (or other electronic device) to perform a process in accordance with the embodiments disclosed herein. The machine-readable medium includes any mechanism for storing or transmitting information in a format readable by a machine (e.g., a computer). For example, the machine-readable medium includes machine-readable storage media (e.g., ROM, random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory, etc.).

[0084]

[0094] Unless otherwise stated, and as is evident from the above description, throughout this specification, any description using terms such as “process,” “calculate,” “determine,” and “display” refers to the operation and process of a computer system or similar electronic computing device that manipulates data and memory represented as physical (electronic) quantities in the registers of a computer system to convert them into other data similarly represented as physical quantities in the memory or registers of the computer system, or in other storage, transmission, or display devices of such information.

[0085]

[0095] Those skilled in the art will further understand that various exemplary logic blocks, modules, circuits, and algorithms described in relation to the embodiments disclosed herein may be implemented as instructions stored in electronic hardware, memory, or another computer-readable medium (any such instructions being executed by a processor or other processing device), or a combination of both. The devices and components described herein may, for example, be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memories disclosed herein may be of any type and size, and may be configured to store any desired type of information. To clearly demonstrate this compatibility, various exemplary components, blocks, modules, circuits, and steps are described above in general terms of functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. A skilled person may implement the described functionality in various ways for each specific application, but such implementation decisions should not be construed as resulting in a departure from the scope of this disclosure.

[0086]

[0096] Various exemplary logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or run by a processor, a digital signal processing device (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of the above designed to perform the functions described herein. The processor may be a microprocessor, but in alternative forms, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a DSP and a combination of a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0087]

[0097] The embodiments disclosed herein may be embodied in hardware and in instructions that are stored in hardware and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. In an alternative embodiment, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0088]

[0098] It should also be noted that the operational steps described in any of the exemplary embodiments of this specification are provided for the purpose of providing examples and explanations. The operations described may be performed in many different sequences other than those shown. Furthermore, the operations described in a single operational step may actually be performed in several different steps. Also, one or more operational steps described in the exemplary embodiments may be combined. It should be understood that the operational steps shown in the flowcharts may be subject to many different modifications, which will be readily apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of the various different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips which may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0089]

[0099] The above descriptions in this disclosure are provided to enable those skilled in the art to manufacture or use the disclosure. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Accordingly, this disclosure is not intended to be limited to the examples and designs described herein, but rather to be construed in the broadest sense in accordance with the principles and novel features disclosed herein.

Claims

1. The first measurement circuit (104) is, It receives a start pulse signal (START) and a stop pulse signal (STOP) that are separated in time by a period (TP), Determine the integer of the first consecutive time increment (TI) within the aforementioned period (TP), Determining the remaining time (TR) of the period (TP) that is less than one of the first time increments (TI), A first measurement circuit (104) configured to perform the following, The second measurement circuit (108) is, The aforementioned time remaining (TR) is added to the previously accumulated remaining (PAR) to generate the current accumulated remaining (CAR), To generate a fractional indicator that indicates whether the current cumulative residual is greater than half of the first time increment, In response to the fraction indicator (106) indicating that the magnitude of the current cumulative residual (CAR) exceeds half of the first time increment (TI), the next cumulative residual (NAR) is generated, which includes a first difference between the first time increment (TI) and the current cumulative residual (CAR). In response to the fraction indicator (106) indicating that the magnitude of the current cumulative residual (CAR) is less than half of the first time increment (TI), the next cumulative residual (NAR) is generated, which includes the current cumulative residual (CAR). A second measurement circuit (108) configured to perform the following: A time-to-digital converter (TDC) circuit (102) is provided.

2. The first measurement circuit, A first delay feedback circuit comprising a first delay circuit, wherein the first delay circuit is The first delayed input receives the start pulse signal, During the first delay period, the start pulse signal is delayed to generate a delayed start pulse signal at the first delayed output. The delayed start pulse signal is fed back from the first delayed output to the first delayed input, A first delay feedback circuit configured to perform the following: A second delay feedback circuit comprising a second delay circuit, wherein the second delay circuit is The second delayed input receives a stop pulse signal, The stop pulse signal is delayed for a second delay period shorter than the first delay period, and a delayed stop pulse signal is generated at the second delay output. The delayed stop pulse signal is fed back from the second delayed output to the second delayed input, A second delay feedback circuit configured to perform the following: It is a flip-flop circuit, Data output and, The data input coupled to the first delayed output, The clock input coupled to the second delay output described above, A flip-flop circuit equipped with, Equipped with, The aforementioned period includes the time from the leading edge of the start pulse signal to the leading edge of the stop pulse signal, The aforementioned time increment includes a second difference between the first delay period and the second delay period, and The TDC circuit according to claim 1, wherein the integer of the first time increment within the period includes the number of times the delayed start pulse signal is repeatedly propagated through the first delay feedback circuit and clocked from the data input to the data output of the flip-flop circuit in response to the delayed stop pulse signal being repeatedly propagated through the second delay feedback circuit to the clock input.

3. Each time the delayed stop pulse signal propagates through the second delay circuit in the second delay feedback circuit, the number of iterations is incremented. Before the delayed start pulse signal is received at the data input of the flip-flop circuit, the delayed stop pulse signal is received at the clock input of the flip-flop circuit, and in response, the integer is generated based on the number of iterations. The TDC circuit according to claim 2, further comprising a counter circuit configured to perform the following.

4. The first residual output and, The second residual output, Furthermore, In response to the generation of the integer, the remaining time is generated based on the time from when the delayed stop pulse signal is received at the clock input of the flip-flop circuit to when the delayed start pulse signal is received at the data input of the flip-flop circuit, and The time residual is the time between the first residual signal in the first residual output and the second residual signal in the second residual output. The TDC circuit according to claim 3.

5. In calibration mode, Receiving a calibration pulse signal, To determine whether the difference between the first number of iterations of the first delay period and the second number of iterations of the second delay period exceeds the offset delay, The second delay period is adjusted in response to the difference between the number of iterations of the first delay period and the number of iterations of the second delay period exceeding the offset delay. The TDC circuit according to any one of claims 2 to 4, further comprising a calibration circuit configured to perform the following.

6. A first calibration counter is configured to generate a first calibration pulse in response to counting the first number of repetitions of the calibration pulse signal passing through the first delay circuit, A second calibration counter is configured to generate a second calibration pulse in response to counting the second number of repetitions of the calibration pulse signal passing through the first and second circuits, It is a comparison circuit, Receiving the first calibration pulse and the second calibration pulse, In response to the first calibration pulse and the second calibration pulse being separated for a longer time than the offset delay, an adjustment signal is generated to adjust the second delay period. A comparison circuit configured to perform the following: The TDC circuit according to claim 5, further comprising:

7. The second measurement circuit, The first residual input and The second residual input and A time addition circuit, The time remaining is received from the first measurement circuit as the time between the first residual signal at the first residual input and the second residual signal at the second residual input, The remaining time is added to the previously accumulated remaining time, The current cumulative residue is generated as the time between the first sum signal at the output of the first adder and the second sum signal at the output of the second adder, A time summing circuit configured to perform the following: An analog-to-digital converter (ADC) circuit, The first adder output and the second adder output are coupled, To generate the fraction indicator that indicates whether the current cumulative residual is greater than half of the first time increment, An analog-to-digital converter (ADC) circuit configured to perform the following: A digital-to-analog converter (DAC) circuit, The first adder output and the second adder output are coupled, In response to the fraction indicator indicating that the current cumulative remainder is greater than half of the first time increment, the first sum signal is delayed by the duration of either the first or second delay period, and the second sum signal is delayed by the duration of the other delay period. In response to the fraction indicator indicating that the current cumulative residual is less than half of the first time increment, both the first sum signal and the second sum signal are delayed by the same amount of the first delay period and the second delay period. A digital-to-analog converter (DAC) circuit configured to perform the following: A TDC circuit according to any one of claims 1 to 6, comprising:

8. The TDC circuit according to any one of claims 1 to 7, wherein the fraction indicator indicates the polarity of the current cumulative residual.

9. The aforementioned time summing circuit It includes a first capacitor, a second capacitor, and a discharge circuit, The time addition circuit is configured to add the aforementioned remaining time to the previously accumulated remaining time, To reduce the first voltage in the first capacitor to a first voltage reduced from the power supply voltage, the first capacitor is discharged for a time equal to the remaining time, In response to the previously accumulated residual having a positive value, the first capacitor is further discharged for a time equal to the previously accumulated residual in order to further reduce the reduced first voltage. In response to the previously accumulated residue having a negative value, the second capacitor is discharged for a time equal to the previously accumulated residue in order to reduce the second voltage in the second capacitor to a second voltage reduced from the power supply voltage. The discharge circuit is configured to perform the following: The TDC circuit according to claim 7 or 8, wherein the current cumulative residual is determined based on the voltage difference between the reduced first voltage and the reduced second voltage.

10. The discharge circuit further discharges the first capacitor from the reduced first voltage and discharges the second capacitor from the reduced second voltage. In response to the first voltage across the first capacitor having a threshold voltage, the first sum flip-flop is activated to generate the first sum signal, The TDC circuit according to claim 9, configured to activate a second sum flip-flop to generate a second sum signal in response to the second voltage in the second capacitor having the threshold voltage.

11. The ADC circuit, A third delay circuit is configured to delay the first sum signal by the amount of the first delay period and generate a delayed first sum signal, A fourth delay circuit is configured to delay the second sum signal by the amount of the third delay period, thereby generating a delayed second sum signal. The second flip-flop circuit is, A second data input configured to receive the delayed first sum signal, A second clock input configured to receive the delayed second sum signal, The second data output, A second flip-flop circuit equipped with, Equipped with, The first delay period and the third delay period differ by half of the first time increment. In response to the current cumulative residual being greater than the difference between the first delay period and the third delay period, the delayed first sum signal is propagated to the second data output, and A one-bit fractional indicator is generated on the second data output of the second flip-flop circuit. The TDC circuit according to any one of claims 7 to 10.

12. The DAC circuit, A fifth delay circuit is configured to delay the first sum signal by the amount of the first delay period and generate a first delayed first sum signal, A sixth delay circuit is configured to delay the first sum signal by the amount of the second delay period to generate a second delayed first sum signal, A first multiplexer configured to select, based on the fractional indicator, the first delayed first sum signal or the second delayed first sum signal to propagate to the output of the first multiplexer, A seventh delay circuit is configured to delay the second sum signal by the amount of the first delay period to generate the first delayed second sum signal, An eighth delay circuit configured to delay the second sum signal by the amount of the second delay period and generate a second delayed second sum signal, A second multiplexer configured to select the first delayed second sum signal or the second delayed second sum signal for propagation to the second multiplexer output based on the fractional indicator, Equipped with, and A TDC circuit according to any one of claims 7 to 11, wherein the following cumulative residual is generated based on a selected one of the first delayed first sum signal and the second delayed first sum signal at the output of the first multiplexer and a selected one of the first delayed second sum signal and the second delayed second sum signal at the output of the second multiplexer.

13. The TDC circuit according to any one of claims 1 to 12, wherein the first time increment is less than 5% of the first delay period.

14. The TDC circuit according to any one of claims 1 to 13, wherein the integer is generated as a multi-bit binary value and the fractional indicator is generated as a 2-bit binary value.

15. A method for a time-digital circuit (TDC) (102), wherein the method is It receives a start pulse signal (START) and a stop pulse signal (STOP) that are separated in time by a period (TP), Determine the integer of the first time increment (TI) within the aforementioned period (TP), and the remaining time (TR) which is less than the first time increment (TI), The aforementioned time remaining (TR) is added to the previously accumulated remaining (PAR) to generate the current accumulated remaining (CAR), A fractional indicator (106) is generated that indicates whether the current cumulative remainder (CAR) differs from the first time increment (TI) by more than half of the first time increment (TI), In response to the fraction indicator (106) indicating that the current cumulative residual (CAR) differs from the first time increment (TI) by more than half the first time increment (TI), the next cumulative residual (NAR) is generated, which includes the difference between the first time increment (TI) and the current cumulative residual (CAR). In response to the fraction indicator (106) indicating that the current cumulative residual (CAR) differs from the first time increment (TI) by less than half of the first time increment (TI), the next cumulative residual (NAR) is generated based on the current cumulative residual (CAR), Methods that include...

16. The start pulse signal is received at the first delay input of the first delay circuit, During the first delay period, the start pulse signal is delayed to generate a delayed start pulse signal at the first delay output of the first delay circuit. The delayed start pulse signal is fed back from the first delayed output to the first delayed input, The stop pulse signal is received at the second delay input of the second delay circuit, The stop pulse signal is delayed for a second delay period shorter than the first delay period, and the delayed stop pulse signal is generated at the second delay output of the second delay circuit. The delayed stop pulse signal is fed back from the second delayed output to the second delayed input, The data input of the flip-flop circuit receives the delayed start pulse signal, The clock input of the flip-flop circuit receives the delayed stop pulse signal, It further includes, The aforementioned period includes the time from the start of the start pulse signal to the start of the stop pulse signal. The aforementioned time increment includes the difference between the first delay period and the second delay period, and The method according to claim 15, wherein the integer of the first time increment within the period includes the number of times the delayed start pulse signal propagates repeatedly through the first delay circuit to the data output of the flip-flop circuit in response to the delayed stop pulse signal repeatedly propagating through the second delay circuit to the clock input.

17. In calibration mode, Receiving a calibration pulse signal, To determine whether the difference between the first number of iterations of the first delay period and the second number of iterations of the second delay period exceeds the offset delay, The second delay period is adjusted in response to the difference between the number of iterations of the first delay period and the number of iterations of the second delay period exceeding the offset delay. The method according to claim 16, further comprising:

18. The time remaining is received as the time from the first residual signal to the second residual signal, The remaining time is added to the previously accumulated remaining time, The current cumulative residual is generated as the time from the first sum signal to the second sum signal, Based on the current cumulative residual, a fractional indicator is generated that indicates whether the magnitude of the current cumulative residual exceeds half of the first time increment. In response to the fraction indicator indicating that the current cumulative remainder is greater than half of the first time increment, the first sum signal is delayed by the duration of either the first or second delay period, and the second sum signal is delayed by the duration of the other delay period. In response to the fraction indicator indicating that the current cumulative residual is less than half of the first time increment, both the first sum signal and the second sum signal are delayed by the same amount of the first delay period and the second delay period. The method according to any one of claims 15 to 17, further comprising:

19. Adding the aforementioned remaining time to the previously accumulated remaining time is, To reduce the first voltage in the first capacitor to a first voltage reduced from the power supply voltage, the first capacitor is discharged for a time equal to the remaining time, In response to the previously accumulated residual having a positive sign, the first capacitor is further discharged for a time equal to the previously accumulated residual in order to further reduce the reduced first voltage. In response to the previously accumulated residue having a negative sign, the second capacitor is discharged for a time equal to the previously accumulated residue in order to reduce the second voltage in the second capacitor to a second voltage reduced from the power supply voltage. Including, The current cumulative residual is determined based on the voltage difference between the reduced first voltage and the reduced second voltage. The method according to claim 18, further comprising:

20. Digital controlled oscillator (DCO) (202), Loop filter circuit (212), Division circuit (204), A time-digital (TDC) system (208), Coarse TDC circuit (127), A miniature TDC circuit (102), It receives a start pulse signal (START) and a stop pulse signal (STOP) that are separated in time by a period (TP), Determine the integer of the first consecutive time increment (TI) within the aforementioned period (TP), Determining the remaining time (TR) of the period (TP) that is less than one of the first time increments (TI), A first measurement circuit (104) configured to perform the following, The aforementioned time remaining (TR) is added to the previously accumulated remaining (PAR) to generate the current accumulated remaining (CAR), A fractional indicator (106) is generated that indicates whether the current cumulative residual (CAR) is greater than half of the first time increment (TI), In response to the fraction indicator (106) indicating that the magnitude of the current cumulative residual (CAR) exceeds half of the first time increment (TI), the next cumulative residual (NAR) is generated, which includes the difference between the first time increment (TI) and the current cumulative residual (NAR). In response to the fraction indicator (106) indicating that the magnitude of the current cumulative residual (CAR) is less than half of the first time increment (TI), the next cumulative residual (NAR) is generated, which includes the current cumulative residual (CAR). A second measurement circuit (108) configured to perform the following: A fine TDC circuit (102) equipped with, A time-digital (TDC) system (208) equipped with, Range determination circuit (112), To determine whether the aforementioned period (TP) falls within the period range, In response to the determination that the aforementioned period (TP) exceeds the maximum period within the aforementioned period range, the coarse TDC circuit (127) generates the integer (132) corresponding to the aforementioned period (TP), In response to the determination that the aforementioned period (TP) is within the aforementioned period range, the fine TDC (102) generates the integer (125) corresponding to the aforementioned period, A range determination circuit (112) configured to perform the following, A phase-locked loop (PLL) circuit (200) is provided.

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