Analog-to-digital converter and signal processing device

Abstract

This application discloses an analog-to-digital converter and a signal processing device. In this solution, a low-power module in the analog-to-digital converter (i.e., ADC) can control whether the first-stage sub-ADC in the ADC should perform analog-to-digital conversion as usual, based on the received indication signal, and as a result, the processing bit width of the ADC can be adjusted. When the processing bit width of the ADC is reduced, the power consumption of the ADC is also reduced accordingly. Therefore, this application provides a solution for reducing the power consumption of an ADC by adjusting the processing bit width of the ADC.

Description

[Technical Field]

[0001] This application relates to the field of circuit design, and more particularly to analog-to-digital converters (ADCs) and signal processing devices. [Background technology]

[0002] Electronic devices deal with both digital and analog signals. Therefore, ADCs (analog-to-digital converters), which have analog-to-digital conversion capabilities, are a crucial part of electronic devices. Furthermore, ADCs are used as active components, and their power consumption constitutes a significant portion of the total power consumption of the electronic device.

[0003] As communication technology evolves, signal bandwidths continue to increase, leading to increasingly higher ADC rate requirements in the field of communications. A key indicator closely related to the ADC rate is the ADC's bit width, which significantly impacts its power consumption.

[0004] To ensure standardization and consistency, the processing bit width of electronic devices is fixed, typically 12 bits or 16 bits. For example, the data bit width of a base station in a 5th generation (5G) communication system is generally about 16 bits.

[0005] However, in the actual operation of electronic device processing services, bit width utilization is not high. As a result, the service data that needs to be processed by the ADC does not match the processing resources provided by the ADC, which leads to additional power consumption costs for the ADC. [Overview of the project]

[0006] This application provides an ADC and a signal processing device that adjust the processing bit width of the ADC, thereby reducing the power consumption of the ADC.

[0007] According to a first aspect, one embodiment of the present application provides an ADC. The ADC includes a first-stage sub-ADC, a second-stage sub-ADC, a first interstage amplifier, a digital control module, a low-power control module, and a first multiplexer, the functions of each module in the ADC being as follows: The low-power control module is configured to send a first control signal to the first-stage sub-ADC and a first selection signal to the first multiplexer based on a first indication signal received, or to send a second control signal to the first-stage sub-ADC and a second selection signal to the first multiplexer based on a second indication signal received, wherein the first control signal indicates that the first-stage sub-ADC will perform analog-to-digital conversion on a first input analog signal, the first selection signal indicates that the first multiplexer will select the signal input through the first input terminal, the second control signal indicates that the first-stage sub-ADC will skip performing analog-to-digital conversion on the first input analog signal, and the second selection signal indicates that the first multiplexer will select the signal input through the second input terminal.

[0008] The first stage sub-ADC is configured to, upon receiving a first control signal, perform analog-to-digital conversion on a first input analog signal based on the first control signal and a first reference analog signal to generate a first M-bit digital signal and send the first M-bit digital signal to a digital control module, correct the first input analog signal based on the first M-bit digital signal to generate a first corrected input analog signal, and send the first corrected input analog signal to the first input terminal of a first multiplexer. The first stage sub-ADC is further configured to skip performing analog-to-digital conversion on the first input analog signal based on the second control signal when it receives the second control signal. The first multiplexer is configured to receive a first corrected input analog signal from the first stage sub-ADC through a first input terminal, receive a first input analog signal through a second input terminal, and, upon receiving a first selection signal, select the signal input through the first input terminal as the second input analog signal based on the first selection signal, or, upon receiving a second selection signal, select the signal input through the second input terminal as the second input analog signal based on the second selection signal, and send the signal obtained by amplifying the second input analog signal to the first interstage amplifier. The first interstage amplifier is configured to amplify the received second input analog signal and to send the signal obtained by amplifying the second input analog signal to the second stage sub-ADC. The second stage sub-ADC is configured to perform analog-to-digital conversion on a second input analog signal based on a second reference analog signal to generate a first N-bit digital signal, and to send the first N-bit digital signal to a digital control module. The digital control module is configured to perform correction control on a received first M-bit digital signal and a received first N-bit digital signal to generate a first (M+N)-bit output digital signal, or to perform correction control on a received first N-bit digital signal to generate a first N-bit output digital signal, where M is a positive integer and N is a positive integer.

[0009] According to this solution, a low-power control module in the ADC can control whether the first-stage sub-ADC in the ADC should perform analog-to-digital conversion as usual, based on a received indication signal (first indication signal or second indication signal). When the first-stage sub-ADC is operating, the processing bit width of the ADC is M+N. When the first-stage sub-ADC is not operating, the processing bit width of the ADC is N. Therefore, the preceding module can adjust the processing bit width of the ADC by sending an indication signal to the ADC based on the amplitude of the service data or otherwise. In this way, the power consumption of the ADC is reduced after the processing bit width of the ADC is reduced.

[0010] In possible designs, the low-power control module is particularly configured to, in a first mode, send a first control signal to a first-stage sub-ADC and a first selection signal to a first multiplexer based on a received first indication signal, or, based on a received second indication signal, send a second control signal to a first-stage sub-ADC and a second selection signal to the first multiplexer. The low-power control module is further configured to send a third control signal to the first-stage sub-ADC in a second mode, the third control signal indicating that the first-stage sub-ADC should determine whether to perform analog-to-digital conversion on the first input analog signal based on the magnitude of the first input analog signal. The first stage sub-ADC compares the first input analog signal with a specified signal based on a third control signal, and if the first input analog signal is greater than the specified signal, performs analog-to-digital conversion on the first input analog signal based on a first reference analog signal to generate a second M-bit digital signal, sends the second M-bit digital signal to the digital control module, corrects the first input analog signal based on the second M-bit digital signal to generate a second corrected input analog signal, and sends the second corrected input analog signal to the first multiplexer. The system is further configured to send a signal to the input terminal of the first multiplexer, send a third selection signal to the first multiplexer, the third selection signal indicating that the first multiplexer will select the signal input through the first input terminal, or to skip performing analog-to-digital conversion on the first input analog signal when the first input analog signal is smaller than a specified signal, and send a fourth selection signal to the first multiplexer, the fourth selection signal indicating that the first multiplexer will select the signal input through the second input terminal. The first multiplexer is further configured to receive a second corrected input analog signal from the first stage sub-ADC through a first input terminal, receive a first input analog signal through the second input terminal, and, upon receiving a third selection signal, select the signal input through the first input terminal as the third input analog signal based on the third selection signal, or, upon receiving a fourth selection signal, select the signal input through the second input terminal as the third input analog signal based on the fourth selection signal, and send the signal obtained by amplifying the third input analog signal to the first interstage amplifier. The first interstage amplifier is further configured to amplify the received third input analog signal and to send the signal obtained by amplifying the third input analog signal to the second stage sub-ADC. The second stage sub-ADC is further configured to perform analog-to-digital conversion on a third input analog signal based on a second reference analog signal to generate a second N-bit digital signal, and to send the second N-bit digital signal to a digital control module. The digital control module is further configured to perform correction control on the received second M-bit digital signal and the received second N-bit digital signal to generate a second (M+N)-bit output digital signal, or to perform correction control on the received second N-bit digital signal to generate a second N-bit output digital signal.

[0011] According to this design, when the low-power control module in the ADC is in the second mode, the first-stage sub-ADC in the ADC can determine whether to perform analog-to-digital conversion as usual based on the magnitude of the input analog signal. When the first-stage sub-ADC is operating, the processing bit width of the ADC is M+N. When the first-stage sub-ADC is not operating, the processing bit width of the ADC is N. Therefore, when the low-power control module in the ADC is controlled to be in the second mode, the ADC can adaptively adjust the processing bit width of the ADC based on the magnitude of the analog signal input to the ADC. In this way, the power consumption of the ADC is reduced after the processing bit width of the ADC is reduced.

[0012] In a possible design, the value of a given signal is the value of the first reference analog signal × 1 / 2 M It is equal to.

[0013] In a possible design, the low-power control module includes a selection control module and a signal generation module. The signal generation module is configured to generate a third control signal in the second mode. The selection control module receives a first indication signal or a second indication signal through a first input terminal, and receives a third control signal from the signal generation module through a second input terminal. In the first mode, based on the first indication signal received through the first input terminal, send the first control signal to the first-stage sub-ADC and send the first selection signal to the first multiplexer, or, based on the second indication signal received through the first input terminal, send the second control signal to the first-stage sub-ADC and send the second selection signal to the first multiplexer, or In the second mode, it is configured to send the third control signal received through the second input terminal to the first-stage sub-ADC.

[0014] In a possible design, the selection control module is the second multiplexer, and the value of the first indication signal, the value of the first control signal, and the value of the first selection signal are the same, or the value of the second indication signal, the value of the second control signal, and the value of the second selection signal are the same, The second multiplexer is configured to select the signal input through the first input terminal in the first mode or select the signal input through the second input terminal in the second mode.

[0015] In a possible design, the first indication signal or the second indication signal is generated by the pre-stage module of the ADC based on the service data of the specified granularity, and the service data of the specified granularity is single sampled data or the service data received within the specified time.

[0016] In a possible design, the value of the first reference analog signal is the same as the value of the second reference analog signal, or the value of the second reference analog signal is equal to the value of the first reference analog signal × 1 / 2 K where K is a positive integer that may be less than or equal to M, and the operating parameters of the first inter-stage amplifier are set based on the value of the first reference analog signal and the value of the second reference analog signal.

[0017] In a possible design, the value of the second reference analog signal is equal to the value of the first reference analog signal × 1 / 2 M The specified signal is the second reference analog signal, and the first-stage sub-ADC includes a controller. When the controller receives the third control signal, it is configured to turn on the switch between the second reference analog signal and the first-stage sub-ADC.

[0018] According to this design, the first-stage sub-ADC may not need to generate the specified signal, and as a result, the power consumption caused by generating the specified signal is reduced.

[0019] According to a second aspect, an embodiment of the present application provides an ADC including a first-stage sub-ADC, a second-stage sub-ADC, a first inter-stage amplifier, a digital control module, a low-power control module, and a first multiplexer. The functions of each module in the ADC are as follows. The low-power control module is configured to send a first control signal to the first-stage sub-ADC, a first selection signal to the first multiplexer, and a second control signal to the second-stage sub-ADC based on the received first bit-width indication signal. The first control signal indicates that the first-stage sub-ADC performs m-bit analog-to-digital conversion, where m is a positive integer less than or equal to the maximum processing bit-width M of the first-stage sub-ADC. The first selection signal indicates that the first multiplexer selects the signal input through the first input terminal. The second control signal indicates that the second-stage sub-ADC performs N-bit analog-to-digital conversion, where N is the maximum processing bit-width of the second-stage sub-ADC. M is a positive integer, N is a positive integer, and the first bit-width indication signal is for indicating that the processing bit-width of the ADC is m + N. The first stage sub-ADC is configured to perform analog-to-digital conversion on a first input analog signal based on a received first control signal and a first reference analog signal to generate an m-bit digital signal and send the m-bit digital signal to a digital control module, correct the first input analog signal based on the m-bit digital signal to generate a first corrected input analog signal, and send the first corrected input analog signal to the first input terminal of a first multiplexer. The first multiplexer is configured to receive a first corrected input analog signal from the first stage sub-ADC through a first input terminal, receive a first input analog signal through a second input terminal, and, upon receiving a first selection signal, select the signal input through the first input terminal as the second input analog signal based on the first selection signal. The first interstage amplifier is configured to amplify the received second input analog signal and to send the signal obtained by amplifying the second input analog signal to the second stage sub-ADC. The second stage sub-ADC is configured to perform analog-to-digital conversion on a second input analog signal based on a second reference analog signal to generate an N-bit digital signal, and to send the N-bit digital signal to a digital control module. The digital control module is configured to perform correction control on the received m-bit digital signal and the received first N-bit digital signal to generate an (m+N)-bit output digital signal.

[0020] According to this solution, based on the received first bit width indication signal, the low-power control module in the ADC can adjust the real-time processing bit width of the first-stage sub-ADC to m and control the real-time processing bit width of the second-stage sub-ADC to the maximum processing bit width N, thereby performing analog-to-digital conversion as usual. In this method, the ADC can adjust its real-time processing bit width to m+N based on the first bit width indication signal. Thus, the preceding module can adjust the processing bit width of the ADC by sending the first bit width indication signal to the ADC based on the amplitude of the service data or otherwise. In this way, the power consumption of the ADC is reduced after the processing bit width of the ADC is reduced.

[0021] In a possible design, the low-power control module is further configured to send a third control signal to the first-stage sub-ADC, a second selection signal to the first multiplexer, and a fourth control signal to the second-stage sub-ADC, based on a received second bit-width indication signal, wherein the third control signal indicates that the first-stage sub-ADC will skip performing analog-to-digital conversion on the first input analog signal, the second selection signal indicates that the first multiplexer will select the signal input through the second input terminal, and the fourth control signal indicates that the second-stage sub-ADC will perform n-bit analog-to-digital conversion, where n is a positive integer less than or equal to N, and the second bit-width indication signal is to indicate that the processing bit width of the ADC is n. The first stage sub-ADC is further configured to skip performing analog-to-digital conversion on the first input analog signal based on the received third control signal. The first multiplexer is further configured to select the first input analog signal input through the second input terminal as the third input analog signal based on a second selection signal. The first interstage amplifier is further configured to amplify the received third input analog signal and to send the signal obtained by amplifying the third input analog signal to the second stage sub-ADC. The second stage sub-ADC is further configured to perform analog-to-digital conversion on a third input analog signal based on a second reference analog signal to generate an n-bit digital signal, and to send the n-bit digital signal to a digital control module. The digital control module is further configured to perform correction control on the received first n-bit digital signal to generate an n-bit output digital signal.

[0022] According to this design, based on a received second bit width indication signal, a low-power control module in the ADC can control the first-stage sub-ADC to not operate and adjust the real-time processing bit width of the second-stage sub-ADC to n. In this way, the ADC can adjust its real-time processing bit width to n based on the second bit width indication signal. Thus, the preceding module can adjust the processing bit width of the ADC by sending a second bit width indication signal to the ADC based on the amplitude of the service data or otherwise. In this way, the power consumption of the ADC is reduced after the processing bit width of the ADC is reduced.

[0023] In a possible design, the first bit width indication signal is a first bit sequence of H bits, the second bit width indication signal is a second bit sequence of H bits, and 2 H The decimal value of the first bit sequence is greater than or equal to M+N, and the decimal value of the second bit sequence is equal to m+N, and the decimal value of the second bit sequence is equal to n.

[0024] In a possible design, a first or second bit-width indication signal is generated by a pre-ADC module based on service data of a specified granularity, where the service data of a specified granularity is either a single sampled data or service data received within a specified time.

[0025] In possible designs, the value of the first reference analog signal is either the same as the value of the second reference analog signal, or the value of the second reference analog signal is half the value of the first reference analog signal. K The operating parameters of the first interstage amplifier are set based on the values ​​of the first reference analog signal and the second reference analog signal.

[0026] According to a third aspect, one embodiment of the present application provides an active module. Optionally, the active module may be an electrical energy-consuming component or device, such as a PA, chip, ADC, DAC, or ASIC. Optionally, the active module includes a low-power control module LPC and a plurality of functional modules. The LPC is configured to control all functional modules to operate normally based on a first indication signal received, or to control all functional modules to stop operating based on a second indication signal received, or to control a first functional module to operate normally and a second functional module to stop operating based on a third indication signal received. Furthermore, the LPC may further control a power supply module to stop supplying power to a functional module that has stopped operating.

[0027] According to this solution, the operating mode of the active module can be controlled and adjusted by configuring the LPC, and as a result, the active module can switch between no-load mode, low-load mode, and standard load mode. In this way, the wasted power consumption caused by continuous operation of the active module in standard load mode can be avoided.

[0028] According to a fourth aspect, one embodiment of the present application further provides a chip comprising an ADC provided in the first or second aspect, or an active module provided in the third aspect.

[0029] According to a fifth aspect, the present application further provides a signal processing device, which includes an ADC provided in the first or second aspect, or an active module provided in the third aspect.

[0030] According to a sixth aspect, the present application further provides a signal processing system, the system comprising a processing unit and an ADC provided in the first or second aspect, or an active module provided in the third aspect.

[0031] According to a seventh aspect, the application further provides an electronic device (for example, a communication device such as a base station). The electronic device includes an ADC provided in the first or second aspect, or an active module provided in the third aspect. [Brief explanation of the drawing]

[0032] [Figure 1A] This figure illustrates an example of statistical values ​​relating to the bit width ratio of service data when a base station is under full load, according to this application. [Figure 1B] This figure illustrates an example of statistical values ​​relating to the bit width ratio of service data when a base station is under low load, according to this application. [Figure 2]This is a flowchart of the basic operation process of the ADC according to this application. [Figure 3] This is a diagram illustrating the basic structure and operating principle of the ADC according to this application. [Figure 4] This is an illustrative diagram of the operation of a 3-bit ADC according to this application. [Figure 5] This is a diagram of the ADC architecture of a multi-stage sub-ADC according to this application. [Figure 6] This is an illustrative diagram of signal amplitude statistics in different system bandwidth scenarios according to this application. [Figure 7] This is a diagram showing the structure of an ADC according to one embodiment of this application. [Figure 8] This is a diagram showing the structure of an ADC according to one embodiment of this application. [Figure 9] This is a diagram showing the structure of an LPC according to one embodiment of this application. [Figure 10] This is a diagram showing the structure of an LPC according to one embodiment of this application. [Figure 11] This is a diagram showing the structure of an LPC according to one embodiment of this application. [Figure 12] This is a diagram showing the structure of an ADC according to one embodiment of this application. [Figure 13] This is a diagram of the structure of a conventional two-stage pipeline ADC. [Figure 14] This is a diagram showing the structure of a two-stage pipeline ADC example according to one embodiment of this application. [Figure 15] This is a pin diagram of a two-stage pipeline ADC example according to one embodiment of this application. [Figure 16] This is a diagram showing the structure of a two-stage pipeline ADC example according to one embodiment of this application. [Figure 17] This is a diagram showing the structure of a two-stage pipeline ADC example according to one embodiment of this application. [Figure 18] This is a diagram showing the structure of a two-stage pipeline ADC example according to one embodiment of this application. [Figure 19] This is a diagram of an ADC architecture having processing bit widths of multiple specifications according to one embodiment of the present application. [Figure 20] This diagram shows the processing bit widths for multiple specifications of a two-stage pipeline ADC according to one embodiment of this application. [Figure 21] This diagram shows the processing bit widths for multiple specifications of a three-stage pipeline ADC according to one embodiment of this application. [Figure 22] This is a diagram showing the structure of an ADC according to one embodiment of this application. [Figure 23] This is a diagram showing the structure of an ADC according to one embodiment of this application. [Figure 24] This is a diagram of different time units according to one embodiment of the present application. [Figure 25] This is a diagram showing the operating modes of an active module according to one embodiment of this application. [Figure 26] This is a diagram showing the structure of an active module according to one embodiment of this application. [Figure 27] This is a diagram of an active module in a standard load mode according to one embodiment of the present application. [Figure 28] This is a diagram of an active module in no-load mode according to one embodiment of the present application. [Figure 29] This is a diagram of an active module in low-load mode according to one embodiment of the present application. [Figure 30] This is a diagram of the structure of a conventional flash ADC. [Figure 31] This is a diagram showing the structure of a flash ADC according to one embodiment of this application. [Figure 32] This is a diagram showing the structure of a flash ADC according to one embodiment of this application. [Figure 33] This is a diagram showing the structure of a flash ADC according to one embodiment of this application. [Figure 34] This is a diagram showing the structure of a pipeline ADC according to one embodiment of this application. [Figure 35] This is a diagram showing the structure of a pipeline ADC according to one embodiment of this application. [Figure 36] This is a diagram showing the structure of a pipeline ADC according to one embodiment of this application. [Modes for carrying out the invention]

[0033] This application provides an ADC and a signal processing device that implements an ADC capable of adjusting its processing bit width, thereby reducing the power consumption of the ADC.

[0034] It should be noted that the links and connections described in the embodiments of this application may be direct connections or connections via at least one component. For example, A being connected to B (in other words, A being linked to B) may indicate that A is directly connected to B, or that A is connected to B via C. Furthermore, "and / or" describes the relationship between the related objects and indicates that three relationships may exist. For example, A and / or B may indicate the following: A exists alone, both A and B exist, and B exists alone. The letter " / " generally indicates an "or" relationship between the related objects.

[0035] Please note that in this application, “multiple” refers to two or more. “At least one” refers to one or more. “At least one of the following items (pieces)” or similar expressions means any combination of these items (pieces), including any single item (piece) or any combination of multiple items (pieces).

[0036] Furthermore, it should be understood that in the description of this application, words such as "first" and "second" are used solely to distinguish between descriptions and should not be understood as indicating or implying relative importance, or as indicating or implying a sequence. Before describing embodiments of this application, the ADC will be briefly described first.

[0037] The ADC is used as an active component, and the power consumption of the ADC is a significant part of the total power consumption of the electronic device. For illustrative purposes, the electronic device is a base station. Compared to conventional base stations, current base stations (e.g., 5G base stations) contain a large number of baseband processing units and radio frequency active components. This significantly increases the power consumption of the base station under low-load and no-load conditions. During normal power-on operation, the power consumption of the base station during off-peak service hours (e.g., early morning or night) is not significantly reduced compared to power consumption during peak service hours. This indicates that a large portion of the base station's power consumption is ineffective and does not positively impact the user experience. Therefore, reducing the power consumption of base stations under low-load and no-load conditions would result in significant commercial value and social contribution.

[0038] In mobile communication systems, base stations are devices that consume a significant amount of power. Within a base station, the power consumption of the active antenna unit (AAU) accounts for the majority of the base station's total power consumption. The AAU includes multiple active components, including an ADC (Analog Converter). Reducing the power consumption of the ADC when the base station is under low load and no load has a positive impact on reducing the base station's overall power consumption.

[0039] As mobile communication systems evolve, the frequency bands they support are increasing, and so is the signal bandwidth. Consequently, ADC rate requirements are becoming increasingly important. A key indicator closely related to the ADC rate is the processing bit width of the ADC, which significantly impacts the ADC's power consumption. Therefore, by reducing the processing bit width of the ADC when the base station is under low load and no load conditions, the ADC's power consumption can be reduced, and as a result, the base station's power consumption can be reduced.

[0040] For example, the current data bit width of a 5G base station is approximately 16 bits. In other words, the processing bit width of the ADC at the base station needs to be 16 bits. Figures 1A and 1B show statistics on the bit width ratio of service data when the base station is under full load and low load conditions.

[0041] Figure 1A(a) shows the data amplitude curve of service data when the base station is under full load, and Figure 1A(b) shows the data bit width actually required by the service data and determined based on the data amplitude of the service data in Figure 1A(a). As shown in the figure, in this case the bit width ratio of the service data is 74.5%.

[0042] Figure 1B(a) shows the data amplitude curve of service data when the base station is under low load, and Figure 1B(b) shows the data bit width actually required by the service data and determined based on the data amplitude of the service data in Figure 1B(a). As shown in the figure, in this case the bit width ratio of the service data is 53%.

[0043] Data analysis in Figures 1A and 1B reveals that bit width utilization is not high in the actual service processing process at base stations. However, to ensure standardization and consistency, the processing bit width of conventional ADCs is predetermined and cannot be adaptively adjusted. As a result, real-time service data processed by conventional ADCs does not match the processing resources provided by the ADC, resulting in additional power consumption costs for the ADC. Therefore, designing a solution that can adaptively adjust the processing bit width of the ADC is an urgent problem that needs to be solved in this field. The following describes the basic operating procedure of the ADC.

[0044] As shown in Figure 2, the basic operating procedure of an ADC includes steps such as sampling, holding, quantization, and encoding. The basic structure and operating principle of an ADC are shown in Figure 3. Assuming that the processing bit width of the ADC is N, an N-bit register in the ADC is configured to temporarily store an N-bit sequence, and in the initial state, all bits from the most significant bit (MSB) to the least significant bit (LSB) are low level (i.e., 0).

[0045] S1: After the input analog signal to be processed (which may be shown as Vin) is input to the ADC, the input analog signal to be processed is first held by a sample / hold circuit, which sends Vin to the first input terminal of the comparator.

[0046] S2: The controller sets the comparison bit of the N-bit register to high level (i.e., to 1). Note that initially, the comparison bit of the N-bit register is the most significant bit (MSB). In this case, the N-bit sequence currently temporarily stored in the N-bit register changes from a bit sequence where all N bits are 0 to a bit sequence where the most significant bit is 1 and the other bits are 0.

[0047] S3: The digital-to-analog converter (DAC) performs a digital-to-analog conversion on the N-bit sequence currently temporarily stored in the N-bit register based on the reference analog signal (Vref) to obtain the comparison analog signal Vdac, and transmits Vdac to the second input terminal of the comparator. In this case, the most significant bit of the N-bit sequence is 1 (where the other bits are 0), so Vdac = Vref / 2.

[0048] S4: The comparator compares Vin input through the first input terminal with Vdac input through the second input terminal, outputs a result signal based on the comparison result between Vin and Vdac, and transmits the result signal to the controller. The result signal is a high level (i.e., 1) or a low level (i.e., 0), that is, a 1-bit digital signal. When Vin≥Vdac, the result signal output by the comparator is at a high level. When Vin<Vdac, the result signal output by the comparator is at a low level.

[0049] S5: After receiving the result signal of the current comparison bit, the controller updates the value of the current comparison bit of the N-bit register based on the result signal. Specifically, when the result signal is at a high level (1), the current comparison bit remains unchanged, or when the result signal is at a low level (0), the current comparison bit is restored to a low level (i.e., the current comparison bit is cleared to 0). Then, the controller uses the next bit of the N-bit register as the comparison bit and repeats S2 to S5 until the controller updates the result signal of the LSB to the N-bit register.

[0050] S6: After the above processing is performed, the N-bit register outputs the temporarily stored N-bit sequence in a serial or parallel manner, and the N-bit sequence is the N-bit output digital signal (i.e., Dout) output by the ADC.

[0051] From the perspective of power consumption, as an analog-digital conversion unit and an analog circuit module in the ADC, the comparator occupies a large power consumption of the ADC in the operation process of the ADC.

[0052] Figure 4 is an illustrative diagram of the operation of a 3-bit ADC. In Figure 4, the circles represent Vdac during each comparison, D2 is the most significant bit of the 3-bit sequence, D1 is the second bit of the 3-bit sequence, and D0 is the least significant bit of the 3-bit sequence. From the above operating principle of the ADC and the example shown in Figure 4, it is clear that the value of the processing bit width of the ADC is equal to the number of data comparisons performed in the ADC.

[0053] Based on the operating principle of the ADC shown in Figure 3, multi-stage sub-ADC architectures are now available in the field of circuitry to extend the processing bit width of the ADC. See Figure 5. The multi-stage sub-ADCs in the ADC are connected in series. Each stage of sub-ADC is configured to perform at least one bit of analog-to-digital conversion on the input analog signal based on the processing bit width of the sub-ADC of each stage. The processing bit width of the ADC is the superposition of the processing bit widths of the multi-stage sub-ADCs. The processing bit widths of different stages of sub-ADCs may be the same or different. This is not limited to this application.

[0054] The circuit structure of each stage of the sub-ADC is a sample / hold circuit (i.e., Figure 5, as shown in the first stage sub-ADC) 5 It includes an internal S / H (Synthetic Harmonization) and sub-ADC circuitry, and further includes a differential circuit. Below, the function of each circuit module in the circuit structure of the first-stage sub-ADC will be explained using the first-stage sub-ADC as an example.

[0055] The sample / hold circuit is configured to sample and hold the analog signal (i.e., Vin) input to the first stage sub-ADC.

[0056] It is assumed that the processing bit width of the first-stage sub-ADC is N, where N is a positive integer. The sub-ADC circuit is configured to perform an N-bit analog-to-digital conversion on an input analog signal (Vin) to generate an N-bit digital signal (Dout1). See Figure 3 for the structure and operating principle of the sub-ADC circuit. Further details are not described herein.

[0057] A differential circuit is configured to perform differential processing on an analog signal (Vin) input to a first-stage sub-ADC based on an N-bit digital signal (Dout1) acquired by a sub-ADC circuit. As shown in Figure 3, the differential circuit may include a DAC and an operational amplifier. The DAC is configured to perform digital-to-analog conversion on the N-bit digital signal (Dout1) acquired by the sub-ADC circuit to obtain a corrected analog signal (Vc). The operational amplifier is configured to subtract the corrected analog signal (Vc) from the input analog signal (Vin) to obtain a difference signal (Vd1). The difference signal is sometimes called the corrected analog signal.

[0058] The difference signal acquired by the preceding sub-ADC is amplified by the interstage amplifier (i.e., RA in Figure 3), and the resulting signal is used as the analog signal (Vin') input to the next sub-ADC.

[0059] Finally, the digital control module receives digital signals from the sub-ADCs of those stages, performs processing on the digital signals such as timing matching and redundancy correction control, and combines those digital signals. Out It can be converted to a digital signal (Dout).

[0060] Assume the ADC includes two sub-ADCs. The first sub-ADC has a processing bit width of N, and the second sub-ADC has a processing bit width of M. In this case, the first sub-ADC performs an N-bit analog-to-digital conversion on the input analog signal, after which an N-bit digital signal (Dout1) is obtained. The second sub-ADC performs an M-bit analog-to-digital conversion on the input analog signal, after which an M-bit digital signal (Dout2) is obtained. After receiving Dout1 and Dout2, the digital control module performs processing such as timing matching and redundancy correction on Dout1 and Dout2, and combines Dout1 and Dout2 to obtain an (N+M) bit digital signal.

[0061] Optionally, the ADC architecture shown in Figure 5 is applicable to various types of ADCs. For example, pipeline ADCs (i.e., Pipeline-ADCs) and pipeline successive register (shift arithmetic right, SAR) ADCs (i.e., Pipeline-SAR ADCs) are all designed using the ADC architecture shown in Figure 5.

[0062] In the ADC architecture shown in Figure 5, the processing bit width of each sub-ADC is fixed to ensure standardization and consistency, and the processing bit width of the entire ADC is also fixed. However, collecting statistics on analog signals in mobile communication systems reveals that the proportion of sampling points for small amplitude signals acquired after the analog signal has been quantized is large.

[0063] Figure 6 is used as an example for illustrative purposes. In Figure 6, the first row is a graph of statistical values ​​of signal amplitudes corresponding to different frequencies in different system bandwidth scenarios in a mobile communication system. In each graph, the horizontal axis is the frequency distribution and the vertical axis is the signal amplitude. The second row is a histogram distribution of the amplitude of the I signal in different system bandwidth scenarios, and the third row is a histogram distribution of the amplitude of the Q signal in different system bandwidth scenarios. In the second and third rows, the horizontal axis is the signal amplitude and the vertical axis is the number of signal sampling points.

[0064] From the figures in the second and third rows of Figure 6, it can be seen that signal amplitudes closer to zero indicate a larger number of signal sampling points. In Figure 6, the signal sampling points in each black box account for the majority of the total signal sampling points.

[0065] In mobile communication systems, signals with small amplitudes account for a high proportion. If the ADC in the communication device still processes the signals by using a fixed processing bit width, the ADC incurs some additional power consumption costs.

[0066] The embodiments of this application will be described in detail below with reference to the attached drawings.

[0067] Embodiment 1

[0068] To implement adaptive adjustment of the processing bit width by the ADC in order to reduce the power consumption of the ADC, one embodiment of the present application provides an ADC based on the ADC architecture shown in Figure 5. See Figure 7. The ADC includes a first stage sub-ADC, a second stage sub-ADC, a first interstage amplifier (i.e., RA1 in Figure 7), a digital control module, a low power control module (low power controller, LPC) (i.e., LPC in Figure 7), and a first multiplexer (multiplexer, MUX) (i.e., MUX1 in Figure 7).

[0069] Figure 7 shows the connections between modules in the ADC. Note that the first and second input terminals of the first multiplexer are connected to the first stage sub-ADC and the first input analog signal (i.e., Vin1 in Figure 7), respectively, and the first multiplexer is configured to select a signal from either the first or second input terminal for output. The LPC is connected to the first stage sub-ADC and is configured to control the operating state of the first stage sub-ADC. The LPC is connected to the first multiplexer and is configured to control the first multiplexer to select a signal from a specific input terminal for output.

[0070] The following describes the functions of the modules in the ADC with reference to Figure 7. It is assumed that the processing bit width of the first stage sub-ADC is M, and the processing bit width of the second stage sub-ADC is N. M is a positive integer, and N is a positive integer.

[0071] The low-power control module is configured to send a first control signal to the first-stage sub-ADC and a first selection signal to the first multiplexer based on a first indication signal received, or to send a second control signal to the first-stage sub-ADC and a second selection signal to the first multiplexer based on a second indication signal received. The first control signal indicates that the first-stage sub-ADC will perform analog-to-digital conversion on a first input analog signal, the first selection signal indicates that the first multiplexer will select the signal input through the first input terminal, the second control signal indicates that the first-stage sub-ADC will skip performing analog-to-digital conversion on a first input analog signal (i.e., Vin1), and the second selection signal indicates that the first multiplexer will select the signal input through the second input terminal.

[0072] The first stage sub-ADC is configured to, upon receiving a first control signal, perform analog-to-digital conversion on a first input analog signal (Vin1) based on the first control signal and a first reference analog signal (i.e., Vref1 in Figure 7) to generate a first M-bit digital signal (i.e., D1_1 in Figure 7) and send the first M-bit digital signal to a digital control module; correct the first input analog signal based on the first M-bit digital signal (D1_1) to generate a first corrected input analog signal (i.e., Vd1 in Figure 7); and send the first corrected input analog signal (Vd1) to the first input terminal of the first multiplexer.

[0073] The first-stage sub-ADC is further configured to skip performing analog-to-digital conversion on the first input analog signal based on the second control signal when it receives the second control signal.

[0074] The first multiplexer is configured to receive a first corrected input analog signal (Vd1) from the first stage sub-ADC through a first input terminal, and a first input analog signal (Vin1) through a second input terminal. When it receives a first selection signal, it selects the signal input through the first input terminal as the second input analog signal (i.e., Vin2 in Figure 7) based on the first selection signal, or when it receives a second selection signal, it selects the signal input through the second input terminal as the second input analog signal (Vin2) based on the second selection signal, and sends the second input analog signal (Vin2) to the first interstage amplifier.

[0075] The first interstage amplifier is configured to amplify the received second input analog signal (Vin2) and to send the second input analog signal (Vin2) to the second stage sub-ADC.

[0076] The second stage sub-ADC is configured to perform analog-to-digital conversion on the second input analog signal (Vin2) based on the second reference analog signal (i.e., Vref2 in Figure 7) to generate the first N-bit digital signal (i.e., D2_1 in Figure 7), and to send the first N-bit digital signal (D2_1) to the digital control module.

[0077] The digital control module is configured to perform correction control on the received first M-bit digital signal (D1_1) and the received first N-bit digital signal (D2_1) to generate a first (M+N)-bit output digital signal (i.e., Dout1 in Figure 7), or to perform correction control on the received first N-bit digital signal (D2_1) to generate a first N-bit output digital signal (i.e., Dout1 in Figure 7).

[0078] From the above solution, it can be seen that a low-power control module in the ADC can control whether the first-stage sub-ADC in the ADC should perform analog-to-digital conversion as usual, based on the received indication signal (first indication signal or second indication signal). When the first-stage sub-ADC is operating, the processing bit width of the ADC is M+N. When the first-stage sub-ADC is not operating, the processing bit width of the ADC is N. Therefore, the preceding module can adjust the processing bit width of the ADC by sending an indication signal to the ADC based on the amplitude of the service data or otherwise. In this way, the power consumption of the ADC is reduced after the processing bit width of the ADC is reduced.

[0079] In this embodiment of the present application, please refer to the descriptions in Figures 3 and 5 for the operating principles and circuit structures of the first and second stage sub-ADCs. Further details will not be described again in this specification. The process by which the first stage sub-ADC corrects the first input analog signal based on the first M-bit digital signal (D1_1) to generate the first corrected input analog signal (Vd1) is a process in which the first stage sub-ADC acquires a difference signal by using a differential circuit. For specific processing, please refer to the description of the differential circuit in Figure 5.

[0080] In one implementation, the low-power control module may have two operating modes. In the first mode, the low-power control module may perform control based on a first or second indication signal received. In the second mode, the low-power control module may enable a mode in which the ADC adaptively adjusts the processing bit width. In this implementation, the first-stage sub-ADC may determine whether the first-stage sub-ADC needs to perform analog-to-digital conversion as usual based on the magnitude of the first input analog signal (Vin1).

[0081] Note that in this implementation, the first-stage sub-ADC may be connected to a first multiplexer and configured to control the first multiplexer to select a signal from a specific input terminal for output.

[0082] In this implementation, the low-power control module is: In the first mode, the system is particularly configured to send a first control signal to the first stage sub-ADC and a first selection signal to the first multiplexer based on a received first indication signal, or to send a second control signal to the first stage sub-ADC and a second selection signal to the first multiplexer based on a received second indication signal. For subsequent processing, please refer to Figure 7.

[0083] When the low-power control module is in the second mode, the module's functions and signal processing processes can be described with reference to Figure 8.

[0084] The low-power control module is In the second mode, a third control signal is sent to the first-stage sub-ADC, the third control signal being further configured to indicate that the first-stage sub-ADC should determine whether to perform analog-to-digital conversion on the first input analog signal (Vin1) based on the magnitude of the first input analog signal (Vin1).

[0085] The first sub-ADC is, Based on the third control signal, the first input analog signal (Vin1) is compared with the specified signal. When the first input analog signal (Vin1) is greater than the specified signal, the first input analog signal (Vin) is determined based on the first reference analog signal (Vref1). 1 The process involves performing analog-to-digital conversion on the first input analog signal (Vin1) to generate a second M-bit digital signal (i.e., D1_2 in Figure 8), sending the second M-bit digital signal (D1_2) to a digital control module, correcting the first input analog signal (Vin1) based on the second M-bit digital signal (D1_2) to generate a second corrected input analog signal (i.e., Vd3 in Figure 8), sending the second corrected input analog signal (Vd3) to the first input terminal of the first multiplexer, and sending a third selection signal to the first multiplexer, wherein the third selection signal indicates that the first multiplexer has selected the signal input through the first input terminal, or The system is further configured to skip performing analog-to-digital conversion on the first input analog signal (Vin1) when the first input analog signal is smaller than a specified signal, and to send a fourth selection signal to the first multiplexer, the fourth selection signal indicating that the first multiplexer selects the signal input through the second input terminal.

[0086] The first multiplexer is further configured to receive a second corrected input analog signal (Vd3) from the first stage sub-ADC through a first input terminal, receive a first input analog signal (Vin1) through a second input terminal, and, upon receiving a third selection signal, select the signal input through the first input terminal (i.e., Vd3) as the third input analog signal (i.e., Vin3 in Figure 8) based on the third selection signal, or, upon receiving a fourth selection signal, select the signal input through the second input terminal (i.e., Vin1) as the third input analog signal (Vin3) based on the fourth selection signal, and send the third input analog signal (Vin3) to the first interstage amplifier.

[0087] The first interstage amplifier is further configured to amplify the received third input analog signal (Vin3) and to send the third input analog signal (Vin3) to the second stage sub-ADC.

[0088] The second stage sub-ADC is further configured to perform analog-to-digital conversion on a third input analog signal (Vin3) based on a second reference analog signal (i.e., Vref2) to generate a second N-bit digital signal (i.e., D2_2 in Figure 8), and to send the second N-bit digital signal (D2_2) to the digital control module.

[0089] The digital control module is further configured to perform correction control on the received second M-bit digital signal (D1_2) and the received second N-bit digital signal (D2_2) to generate a second (M+N)-bit output digital signal (i.e., Dout2 in Figure 8), or to perform correction control on the received second N-bit digital signal (D2_2) to generate a second N-bit output digital signal (Dout2).

[0090] According to this implementation, when the low-power control module in the ADC is in the second mode, the first-stage sub-ADC in the ADC can decide whether to perform analog-to-digital conversion as usual based on the magnitude of the input analog signal. When the first-stage sub-ADC is operating, the processing bit width of the ADC is M+N. When the first-stage sub-ADC is not operating, the processing bit width of the ADC is N. Therefore, when the low-power control module in the ADC is controlled to be in the second mode, the ADC can adaptively adjust the processing bit width of the ADC based on the magnitude of the analog signal input to the ADC. In this way, the power consumption of the ADC is reduced after the processing bit width of the ADC is reduced.

[0091] In one implementation, the value of the specified signal is the value of the first reference analog signal (Vref1) × 1 / 2 M It is equal to.

[0092] In this embodiment of the present application, please refer to Figure 9. The low-power control module may include a selection control module and a signal generation module.

[0093] The signal generation module is configured to generate a third control signal when the low-power control module is in a second mode.

[0094] The selection control module receives a first indication signal or a second indication signal through a first input terminal, and receives a third control signal from the signal generation module through a second input terminal. When the low-power control module is in the first mode, it sends a first control signal to the first stage sub-ADC and a first selection signal to the first multiplexer based on a first indication signal received through the first input terminal, or it sends a second control signal to the first stage sub-ADC and a second selection signal to the first multiplexer based on a second indication signal received through the first input terminal, or When the low-power control module is in the second mode, it is configured to send a third control signal received through the second input terminal to the first-stage sub-ADC.

[0095] From the above description, it can be seen that the selection control module can generate a first control signal and a first selection signal based on a first indication signal received, or a second control signal and a second selection signal based on a second indication signal received.

[0096] For example, the selection control module is a second multiplexer, and the structure of the low-power control module is shown in Figure 10, where the second multiplexer is MUX2 in Figure 10. In this case, the value of the first indication signal, the value of the first control signal, and the value of the first selection signal are the same, or the value of the second indication signal, the value of the second control signal, and the value of the second selection signal are the same. The second multiplexer is configured to select a signal input through the first input terminal in the first mode, or to select a signal input through the second input terminal in the second mode.

[0097] Optionally, the operating mode of the low-power control module can be controlled via a mode signal (LP_mode). In this way, a user or a preceding module of the ADC can control the operating mode of the low-power control module in the ADC by sending a mode signal to the ADC, as shown in Figure 8. For example, this application further provides a structure for a low-power control module. See Figure 11. A mode signal is added based on the low-power control module shown in Figure 9. When the mode signal indicates a first mode, the select control module chooses to perform control based on a first or second indication signal input through a first input terminal, or when the mode signal indicates a second mode, the select control module chooses to perform control based on a third control signal input through a second input terminal.

[0098] Optionally, as shown in Figure 11, the signal generation module may trigger operation based on a mode signal. Specifically, when the signal generation module receives a mode signal indicating a first mode, it cannot generate a third control signal, or when the signal generation module receives a mode signal indicating a second mode, it begins generating a third control signal.

[0099] In possible implementations, a first or second indication signal is generated by a preceding module of the ADC based on service data of a specified granularity, where the service data of a specified granularity is either a single sampled data or service data received within a specified time. The specified time may include at least one time unit. Note that the specific form of the time unit is not limited in this application. The time unit may be a time unit in the field of communications, such as a symbol, slot, subframe, or wireless frame, or it may be a conventional time unit, such as a second, minute, hour, or day. For example, a specific setting form of the specified granularity may be any one of the time units shown in Figure 24.

[0100] This implementation allows the ADC to flexibly adjust the processing bit width based on the service data of a specified granularity. The smaller the specified granularity, the greater the potential power consumption gain of the ADC.

[0101] In possible implementations, the value of the first reference analog signal (Vref1) is the same as the value of the second reference analog signal (Vref2). In other words, the first and second stage sub-ADCs can perform analog-to-digital conversion using the same reference analog signal. In this case, the first interstage amplifier receives the received signal and converts it to digital. M It can be amplified twofold.

[0102] In another possible implementation, the value of the second reference analog signal (Vref2) is equal to the value of the first reference analog signal (Vref1) × 1 / 2 K where K is a positive integer that may be less than or equal to M, and the operating parameters of the first inter-stage amplifier are set based on the value of the first reference analog signal and the value of the second reference analog signal.

[0103] For example, when comparing the operating parameters of the first inter-stage amplifier when Vref2 = Vref1, when Vref2 = Vref1 / 2, the gain of the first inter-stage amplifier can be reduced by 6 dB in the design, and can the power consumption of the first inter-stage amplifier be reduced, or when Vref2 = Vref1 / 2 2 when the gain of the first inter-stage amplifier can be reduced by 12 dB in the design, and can the power consumption of the first inter-stage amplifier be further reduced, or when Vref2 = Vref1 / 2 M when the first inter-stage amplifier can be bypassed (i.e., the first inter-stage amplifier cannot operate).

[0104] In a possible implementation, the value of the second reference analog signal (Vref2) is equal to the value of the first reference analog signal (Vref1) × 1 / 2 M where the specified signal is the second reference analog signal (Vref2). In the second mode, the first-stage sub-ADC may compare the input first input analog signal (Vin1) with the second reference analog signal (Vref2) to determine whether analog-to-digital conversion needs to be performed on the first input analog signal (Vin1).

[0105] In this implementation, refer to FIG. 12. The first-stage sub-ADC includes a controller, and the controller is configured to turn on the switch between the second reference analog signal (Vref2) and the first-stage sub-ADC when receiving the third control signal. As a result, the first-stage sub-ADC can receive the second reference analog signal (Vref2).

[0106] It should be further noted that, compared to conventional ADCs, the ADC provided in this embodiment of the present application requires additional pins to receive a first indication signal or a second indication signal.

[0107] In the following, a two-stage pipelined ADC is used as an example for explanation. Please refer to Figure 13. The structure of a conventional two-stage pipelined ADC mainly consists of two sub-ADCs and an interstage amplifier (RA). For the structure and operating principle of each sub-ADC, please refer to the corresponding descriptions in Figures 3 and 5. Further details will not be described again in this specification. Each sub-ADC includes a DAC, a comparator (CM), and a controller. Registers are coupled to the controller.

[0108] As shown in Figure 13, the processing bit width of the first-stage sub-ADC is M. Therefore, the first-stage sub-ADC includes an M-bit DAC, a CM1, and a controller 1 coupled to an M-bit register. Similarly, the processing bit width of the second-stage sub-ADC is N. Therefore, the second-stage sub-ADC includes an N-bit DAC, a CM2, and a controller 2 coupled to an N-bit register.

[0109] In the operation of an ADC, the first-stage sub-ADC needs to perform a total of M comparisons of M bits from MSB to LSB to acquire an M-bit digital signal. Similarly, the second-stage sub-ADC needs to perform a total of N comparisons of N bits from MSB to LSB to acquire an N-bit digital signal. If the processing bit width of both sub-ADCs is 8, each of the two sub-ADCs needs to perform 8 comparisons.

[0110] Based on the solution provided in Embodiment 1 described above, this application provides Example 1 of a two-stage pipeline ADC. Please refer to Figure 14. Compared to the structure of a conventional two-stage pipeline ADC in Figure 13, the pipeline ADC in this example has two additional modules: a low-power control module (i.e., LPC in Figure 14) and a first multiplexer (i.e., MUX1 in Figure 14). Please note that this example is used as an example and does not imply any limitation to the solution in Embodiment 1. The following description will be made with reference to Figure 14.

[0111] The input to the LPC is a low-power indication signal (i.e., LP_flag in the diagram). LP_flag is generated and transmitted by the pre-ADC module. Optionally, in the ADC's package structure, LP_flag may be input through a separate input pin. The output of the LPC is connected to controller 1 and MUX1 of the first-stage sub-ADC.

[0112] MUX1 is positioned after the first-stage sub-ADC and before the RA. The two input terminals of MUX1 are configured to accept the original input analog signal Vin and the difference signal Vd1 obtained by correcting Vin by the first-stage sub-ADC, respectively, and the output terminal of MUX1 is connected to the input terminal of the RA. The following describes the functions of the two modules, namely LPC and MUX1.

[0113] (1) LPC

[0114] The LPC has two operating modes: a first mode (mode 1) and a second mode (mode 0). The operating mode of the LPC is controlled by using the LP mode signal (i.e., LP_mode in the diagram).

[0115] When LP_mode is equal to 1, the LPC's operating mode is mode 1. In this case, the LPC directly and transparently transmits the LP_flag input from the preceding module. When the value of LP_flag is 1, controller 1 controls the first stage sub-ADC so that it does not operate (i.e., the first stage sub-ADC does not perform analog-to-digital conversion and is directly bypassed). When the value of LP_flag is 0, controller 1 controls the first stage sub-ADC so that it operates normally and is not bypassed (i.e., the first stage sub-ADC performs M-bit analog-to-digital conversion as usual).

[0116] When LP_mode is equal to 0, the operating mode of the LPC is mode 0. In this case, the LPC indicates that the first-stage sub-ADC will decide whether it should operate (i.e., whether it should perform analog-to-digital conversion) based on the magnitude of Vin. For example, when LP_mode is equal to 0, the LPC sends a control signal to controller 1. Based on the control signal, controller 1 controls the least significant bit of the M-bit register to be set to a high level, and then the M-bit DAC may perform a digital-to-analog conversion on the M-bit sequence currently temporarily stored in the M-bit register based on the reference analog signal (Vref) to obtain a decision reference signal (Vj). In this case, Vj = Vref / 2 M That is the case.

[0117] CM1 compares Vj with Vin. If the result signal output by CM1 is 1, controller 1 restores the least significant bit of the M-bit register to a low level, and the first-stage sub-ADC performs the conventional analog-to-digital conversion procedure based on the control of controller 1. For specific processing of the analog-to-digital conversion procedure, please refer to the above description in Figure 3. Further details are not described herein. If the result signal output by CM1 is 0, controller 1 restores the least significant bit of the M-bit register to a low level and holds each bit of the M-bit register at a low level to ensure that the first-stage sub-ADC does not perform the analog-to-digital conversion procedure.

[0118] Note that in the scenario where LP_mode is equal to 0, if the result signal received by controller 1 from CM1 is 1, controller 1 may further send selection signal 0 to MUX1, or if the result signal received by controller 1 from CM1 is 0, controller 1 may further send selection signal 1 to MUX1.

[0119] (2) MUX1

[0120] MUX1 controls the input signal of RA based on the output signal of LPC or the selection signal sent by controller 1. When the output signal of LPC or the selection signal sent by controller 1 is 1, MUX1 selects Vin as the input signal of RA. When the output signal of LPC or the selection signal sent by controller 1 is 0, MUX1 selects the difference signal (Vd1) output by the M-bit DAC as the input signal of RA.

[0121] The second-stage sub-ADC performs analog-to-digital conversion based on the received analog signal, which has been amplified by the RA, as is typical. Specific processing is again not described herein.

[0122] The process of generating LP_flag needs further explanation. For example, LP_flag may be generated by a pre-ADC module or pre-ADC system based on real-time service data, and is intended to help control the operating state of sub-ADCs within the ADC.

[0123] Optionally, a preceding module or system may continuously generate LP_flag based on service data of a specified granularity. The service data of a specified granularity may be a single sampled data or service data received within a specified time period. The specified time period may include at least one time unit. The time unit may be a symbol, slot, subframe, radio frame, etc., or it may be a second, minute, hour, day, etc. This is not limited to the present application.

[0124] Compared to the hardware structure of conventional ADCs, the ADC provided in this embodiment of the present application requires the addition of a new pin to receive LP_flag. See Figure 15. The pin Pre_infoP is configured to receive LP_flag.

[0125] In the above example, a two-stage pipelined ADC is used as an example of the solution provided. This solution allows for the dynamic reduction of power consumption of each active component in the first-stage sub-ADC. Furthermore, this solution can be extended to multi-stage pipelined ADCs. When an N-stage pipelined ADC is designed using this solution, the power consumption of the active components in up to (N-1) stages of sub-ADCs can be reduced. The final power consumption gain of this solution is related to the probability distribution of the signal amplitude of the analog signal processed by the ADC.

[0126] Based on Example 1 shown in Figure 14, this application further provides Example 2 of another two-stage pipeline ADC. Please refer to Figure 16. This example provides the internal circuit structure of the LPC. Please note that this example is for illustrative purposes only and does not imply any limitation on the structure of the LPC.

[0127] Similar to Figure 9 or Figure 10, in this example the LPC may include an LSB controller and a second multiplexer (i.e., MUX2 in Figure 16). The LSB controller generates a control signal to indicate whether the first-stage sub-ADC should operate (i.e., perform analog-to-digital conversion) based on the magnitude of Vin. The functions of the LPC will be described in detail below with reference to Figure 16.

[0128] The LPC's two operating modes are controlled by using LP_mode. LP_mode can be sent to both the MUX2 and the LSB controller.

[0129] When LP_mode is equal to 1, the LSB controller does not operate, and MUX2 directly and transparently transmits the LP_flag input by the preceding module as the output of the LPC. In this way, the LPC can control MUX1 to select the signals that need to be output, based on the LP_flag, and to control whether the first-stage sub-ADC should operate normally. For details of the above control process, please refer to the corresponding description in Embodiment 1. Further details are not described herein.

[0130] When the LP_mode is equal to 0, the LSB controller starts to operate and outputs a control signal. MUX2 directly and transparently transmits the control signal as the output of the LPC. In this way, the controller 1 in the first-stage sub-ADC can determine whether the first-stage sub-ADC should operate (i.e., whether to perform analog-to-digital conversion) based on the control signal and the magnitude of Vin. For the process of how the first-stage sub-ADC determines whether and how to operate, please refer to the relevant description in Embodiment 1. Details will not be described again in this specification.

[0131] According to the solution provided in this case, the control signal generated by the LSB controller can be used to control the reduction of the number of sequential comparisons by the ADC. In this way, the power consumption of the ADC is reduced.

[0132] Still, a two-stage pipeline ADC is used for illustration. When the processing bit width of each stage of the sub-ADC is 8, the processing bit width of the ADC is 16. In the conventional solution, the ADC needs to perform 16 comparisons. After the solution in this case is used, when the first-stage sub-ADC determines that Vin < Vj, the ADC only needs to perform 9 comparisons (the first-stage sub-ADC performs 1 comparison, and the second-stage sub-ADC performs 8 comparisons, and 1 + 8 = 9). Therefore, the comparison operation by the ADC can be reduced by more than 40% in the solution of this case compared with that of the conventional ADC. When the ratio of the service data that is smaller than Vj and in the service data processed by the ADC is 30%, the comparison operation by the ADC can be reduced by 12% (40% × 30% = 12%) in this solution.

[0133] It should be further noted that the LPC and MUX1 may be connected via a switch. When LP_mode is equal to 0, the LPC or another component may switch off to prevent the MUX1 from receiving the LPC's control signals and consequently selecting the wrong signal for output.

[0134] Based on Examples 1 and 2, this application further provides Example 3. Unlike Examples 1 and 2, in Example 3, the two sub-ADCs in a two-stage pipeline ADC use different reference analog signals. See Figure 17. The reference analog signal for the first sub-ADC is Vref1, and the reference analog signal for the second sub-ADC is Vref2.

[0135] From the above explanation of the ADC structure shown in Figure 5, it can be seen that in an ADC, the pre-stage sub-ADC performs difference processing on the analog signal input to the pre-stage sub-ADC based on the digital signal acquired through analog-to-digital conversion, and the acquired difference signal is amplified by an interstage amplifier (i.e., RA), and the resulting signal is used as the analog signal input to the next-stage sub-ADC. When the processing bit width of the pre-stage sub-ADC is M, the RA amplifies the difference signal by 2 M It can be amplified by a factor of two.

[0136] It is clear that the operating parameters of the RA are related to the value of the reference analog signal of the two-stage sub-ADC.

[0137] Based on this, in this case, a multi-stage reference analog signal may be introduced to reduce the power consumption of the interstage amplifier RA.

[0138] For example, compared to the operating parameters of the RA when Vref2 = Vref1, when Vref2 = Vref1 / 2, the gain of the RA can be reduced by 6 dB in the design, and the power consumption of the RA can be reduced, or Vref2 = Vref1 / 2 2In this case, the gain of RA can be reduced by 12 dB in the design, and the power consumption of RA can be further reduced, or Vref2 = Vref1 / 2 M In this case, the RA can be bypassed (i.e., the RA cannot operate. In this case, the ADC may not have RA components, and MUX1 is directly connected to the second-stage sub-ADC).

[0139] The data above represents ideal data, without considering any errors or losses. Even if some non-ideal conditions are considered and additional correction algorithms need to be introduced into the ADC, the solution in this case still has a positive impact on reducing the ADC's power consumption compared to conventional solutions.

[0140] Based on Case 3, this application further provides Case 4. Vref2 = Vref1 / 2 M In this scenario, when the LPC's operating mode is mode 1, the first-stage sub-ADC makes a decision based on the control signal received by the LPC, using a reference signal Vj (Vj = Vref1 / 2 M A signal Vj is generated, Vj is compared with Vin, and based on the comparison result, it can be determined whether the first-stage sub-ADC needs to operate. In this scenario, it is clear that the value of the decision reference signal Vj is the same as the value of Vref2. Therefore, in this case, Vref2 can be introduced into the first-stage sub-ADC, and as a result, the first-stage sub-ADC does not need to generate Vj through digital-to-analog conversion. In this way, the power consumption caused when the DAC generates Vj in the first-stage sub-ADC is eliminated. Based on the above ideas, the present application provides the ADC architecture shown in Figure 18.

[0141] In this example, Vref2 may be connected to CM1 via a switch. Controller 1 controls the status of the switch.

[0142] When LP_mode is equal to 0, the LPC sends a control signal to controller 1. Controller 1 closes the switch based on the control signal, and as a result, CM1 compares Vref2 (Vj) with Vin. When the resulting signal output by CM1 is 1, controller 1 turns off the switch, and as a result, the first-stage sub-ADC can perform the conventional analog-to-digital conversion procedure based on Vref1 and the control of controller 1.

[0143] Building upon the solutions provided in Embodiment 1 and Examples 1 and 3, this application further provides Example 4, which may provide an architecture for an ADC having processing bit widths of multiple specifications. The position of each sub-ADC in the ADC may vary. Thus, based on the solutions provided in Embodiment 1 and Examples 1 to 3, the ADC may have processing bit widths of multiple specifications. For example, in the ADC, a multiplexer may be used to implement the positional variation of multi-stage sub-ADCs in the ADC. Still, a two-stage pipelined ADC is used as an example for illustrative purposes. The connection relationship between the two-stage sub-ADCs (i.e., sub-ADC0 and sub-ADC1) and two multiplexers (i.e., MUX0 and MUX1) in the ADC is shown in Figure 19. The ADC may further include a control module. The control module may control the output signals of MUX0 and MUX1 and adjust the relationship between sub-ADC0 and sub-ADC1. As shown in Figure 19, when the control module controls MUX0 to select the output signal of sub-ADC0 as the output signal, and controls MUX1 to select the output signal of sub-ADC1 as the output signal, sub-ADC0 is the first stage sub-ADC in the ADC, and sub-ADC1 is the second stage sub-ADC in the ADC. In this case, the signal transmission process is shown by the solid line in Figure 19.

[0144] When the control module controls MUX0 to select the input analog signal to be processed as the output signal, and controls MUX1 to select the output signal of sub-ADC0 as the output signal, sub-ADC1 is the first stage sub-ADC in the ADC, and sub-ADC0 is the second stage sub-ADC in the ADC. In this case, the signal transmission process is shown by the dashed line in Figure 19.

[0145] From the above explanation, it can be seen that when an ADC includes multiple sub-ADCs with different processing bit widths, the ADC may have multiple options for processing bit widths based on the positional changes of the sub-ADCs and the control of the above solution. The user or ADC can select the appropriate processing bit width based on the actual requirements.

[0146] In an example of a two-stage pipelined ADC, if the processing bit width of sub-ADC0 is M and the processing bit width of sub-ADC1 is N, the ADC can have processing bit widths of three rules, such as M, N, and M+N, as shown in Figure 20.

[0147] In an example of a three-stage pipelined ADC, if the processing bit width of sub-ADC0 is M, the processing bit width of sub-ADC1 is N, and the processing bit width of sub-ADC2 is K, then the ADC can have processing bit widths of six rules, such as M, N, K, M+N, M+K, N+K, and M+N+K, as shown in Figure 21.

[0148] Embodiment 2

[0149] To implement adaptive adjustment of the processing bit width by the ADC in order to reduce the power consumption of the ADC, one embodiment of the present application provides an ADC based on the ADC architecture shown in Figure 5. Please refer to Figure 22. The ADC includes a first stage sub-ADC, a second stage sub-ADC, a first interstage amplifier (i.e., RA1 in Figure 22), a digital control module, a low-power control module (i.e., LPC in Figure 22), and a first multiplexer (i.e., MUX1 in Figure 22).

[0150] Figure 22 shows the connections between modules in the ADC. Note that the first and second input terminals of the first multiplexer are connected to the first stage sub-ADC and the first input analog signal (i.e., Vin1 in Figure 22), respectively, and the first multiplexer is configured to select a signal from either the first or second input terminal for output. The LPC is connected to the first stage sub-ADC and the second stage sub-ADC and is configured to control the real-time processing bit width of the first stage sub-ADC and the second stage sub-ADC. The LPC is further connected to the first multiplexer. The LPC is connected to the first multiplexer and is configured to control the first multiplexer to select a signal from a specific input terminal for output.

[0151] In the following, 22 The functions of the modules in the ADC will be explained while referring to the following. It is assumed that the maximum processing bit width of the first-stage sub-ADC is M, and the maximum processing bit width of the second-stage sub-ADC is N. M is a positive integer, and N is a positive integer. The fact that the maximum processing bit width of the first-stage sub-ADC is M indicates that the components such as registers and DACs in the first-stage sub-ADC are M bits. The fact that the maximum processing bit width of the second-stage sub-ADC is N indicates that the components such as registers and DACs in the second-stage sub-ADC are N This indicates that it is a bit.

[0152] The low-power control module is configured to send a first control signal to the first-stage sub-ADC, a first selection signal to the first multiplexer, and a second control signal to the second-stage sub-ADC, based on a first bit width indication signal received, where the first control signal indicates that the first-stage sub-ADC will perform m-bit analog-to-digital conversion, where m is a positive integer less than or equal to the maximum processing bit width M of the first-stage sub-ADC; the first selection signal indicates that the first multiplexer will select the signal input through the first input terminal; the second control signal indicates that the second-stage sub-ADC will perform N-bit analog-to-digital conversion, where N is the maximum processing bit width of the second-stage sub-ADC, M is a positive integer, and N is a positive integer; and the first bit width indication signal is for indicating that the processing bit width of the ADC is m+N.

[0153] The first stage sub-ADC is configured to perform analog-to-digital conversion on a first input analog signal (i.e., Vin1 in Figure 22) based on a received first control signal and a first reference analog signal (i.e., Vref1 in Figure 22) to generate an m-bit digital signal (i.e., D1_1 in Figure 22) and send the m-bit digital signal (D1_1) to a digital control module, correct the first input analog signal (Vin1) based on the m-bit digital signal (D1_1) to generate a first corrected input analog signal (i.e., Vd1 in Figure 22), and send the first corrected input analog signal (Vd1) to the first input terminal of a first multiplexer.

[0154] The first multiplexer is configured to receive a first corrected input analog signal (Vd1) from the first stage sub-ADC through a first input terminal, and a first input analog signal (Vin1) through a second input terminal, and, upon receiving a first selection signal, to select the signal input through the first input terminal (Vd1) as the second input analog signal (i.e., Vin2 in Figure 22) based on the first selection signal.

[0155] The first interstage amplifier (RA1) is configured to amplify the received second input analog signal (Vin2) and to send the second input analog signal (Vin2) to the second stage sub-ADC.

[0156] The second stage sub-ADC is configured to perform analog-to-digital conversion on the second input analog signal (Vin2) based on the second reference analog signal (i.e., Vref2 in Figure 22) to generate an N-bit digital signal (i.e., D2_1 in Figure 22), and to send the N-bit digital signal (D2_1) to the digital control module.

[0157] The digital control module receives the received m-bit digital signal (D1_1) and the received taN The system is configured to perform correction control on the bit digital signal (D2_1) to generate an (m+N) bit output digital signal (i.e., Dout1 in Figure 22).

[0158] According to this solution, in the first-stage sub-ADC, the real-time processing bit width of the first-stage sub-ADC can be adjusted to m based on the first control signal. Note that for the process by which the first-stage sub-ADC performs analog-to-digital conversion, refer to the above explanation in Figure 3. The difference is that controller 1 in the first-stage sub-ADC uses the first bit of the last m bits in the M-bit register as the first comparison bit, and after each comparison is completed, uses the bit following the current comparison bit as the new comparison bit until all comparisons for the last m bits are completed.

[0159] From the above solution, it can be seen that, based on the received first bit width indication signal, the low-power control module in the ADC can adjust the real-time processing bit width of the first-stage sub-ADC to m and control the real-time processing bit width of the second-stage sub-ADC to the maximum processing bit width N, thereby performing analog-to-digital conversion as usual. According to this method, the ADC can adjust its real-time processing bit width to m+N based on the first bit width indication signal. Therefore, the preceding module can adjust the processing bit width of the ADC by sending the first bit width indication signal to the ADC based on the amplitude of the service data or otherwise. In this way, the power consumption of the ADC is reduced after the processing bit width of the ADC is reduced.

[0160] In one implementation, the ADC may further adjust its real-time processing bit width to n based on a second bit width indication signal, where n is a positive integer less than or equal to N. This will be explained below with reference to Figure 23.

[0161] The low-power control module is further configured to send a third control signal to the first-stage sub-ADC, a second selection signal to the first multiplexer, and a fourth control signal to the second-stage sub-ADC, based on a received second bit-width indication signal, wherein the third control signal indicates that the first-stage sub-ADC will skip performing analog-to-digital conversion on the first input analog signal, the second selection signal indicates that the first multiplexer will select the signal input through the second input terminal, and the fourth control signal indicates that the second-stage sub-ADC will perform n-bit analog-to-digital conversion, where n is a positive integer less than or equal to N, and the second bit-width indication signal is for indicating that the processing bit width of the ADC is n.

[0162] The first-stage sub-ADC is further configured to skip performing analog-to-digital conversion on the first input analog signal based on the received third control signal.

[0163] The first multiplexer is further configured to select, based on a second selection signal, a first input analog signal input through the second input terminal (i.e., Vin1 in Figure 23) as a third input analog signal (i.e., Vin3 in Figure 23).

[0164] The first interstage amplifier (RA1 in Figure 23) is further configured to amplify the received third input analog signal (Vin3) and to send the third input analog signal (Vin3) to the second stage sub-ADC.

[0165] The second stage sub-ADC is further configured to perform analog-to-digital conversion on a third input analog signal (Vin3) based on a second reference analog signal (Vref2 in Figure 23) to generate an n-bit digital signal (i.e., D2_2 in Figure 23), and to send the n-bit digital signal (D2_2) to a digital control module.

[0166] The digital control module receives tan The system is further configured to perform correction control on the bit digital signal (D2_2) to generate an n-bit output digital signal (i.e., Dout2 in Figure 23).

[0167] According to this implementation, based on the received second bit width indication signal, the low-power control module in the ADC can control the first-stage sub-ADC to not operate and adjust the real-time processing bit width of the second-stage sub-ADC to n. In this way, the ADC can adjust its real-time processing bit width to n based on the second bit width indication signal. Thus, the preceding module can adjust the processing bit width of the ADC by sending a second bit width indication signal to the ADC based on the amplitude of the service data or otherwise. In this way, the power consumption of the ADC is reduced after the processing bit width of the ADC is reduced.

[0168] In this embodiment of the present application, the first bit width indication signal is a first bit sequence of H bits, and the second bit width indication signal is a second bit sequence of H bits, and 2 H The decimal value of the first bit sequence is greater than or equal to M+N, and the decimal value of the second bit sequence is equal to m+N, and the decimal value of the second bit sequence is equal to n.

[0169] For example, if M+N=16, the first bit width indication signal and the second Bit width The indication signal can be a 4-bit bit sequence.

[0170] Similar to the first or second indication signal in Embodiment 1, in this embodiment, the first or second bit-width indication signal is generated by a pre-ADC module based on service data of a specified granularity, where the service data of a specified granularity is a single sampled data or service data received within a specified time. The specified time may include at least one time unit. Note that the specific form of the time unit is not limited in this application. The time unit may be a time unit in the field of communications, such as a symbol, slot, subframe, or wireless frame, or it may be a conventional time unit, such as a second, minute, hour, or day. For example, a specific setting form of the specified granularity may be any one of the time units shown in Figure 24.

[0171] This implementation allows the ADC to flexibly adjust the processing bit width based on the service data of a specified granularity. The smaller the specified granularity, the greater the potential power consumption gain of the ADC.

[0172] Similar to Embodiment 1, the value of the first reference analog signal is the same as the value of the second reference analog signal, or the value of the second reference analog signal is the value of the first reference analog signal × 1 / 2 K Equal to M, where K is a positive integer less than or equal to M, the operating parameters of the first interstage amplifier are set based on the values ​​of the first reference analog signal and the second reference analog signal. For a description of the first and second reference analog signals, see the description in Embodiment 1. Further details are not described herein.

[0173] It should be noted that the embodiments and examples described above are illustrated using examples with two-stage or three-stage sub-ADCs. However, the embodiments and examples described above do not limit the scope of application of the solution provided in this embodiment of the present application. The solution is applicable to various ADCs having multi-stage sub-ADCs.

[0174] Embodiment 3

[0175] To reduce the power consumption of active components in electronic devices, one embodiment of this application provides an active module. The active module may be an electrical energy-consuming component or device such as a power amplifier (PA), chip, ADC, DAC, or ASIC. As shown in Figure 25, the active module has the following three operating modes and supports stable switching between the three modes.

[0176] Mode 1 is the no-load mode (extreme power consumption with power supply cut off). Active components do not operate and can transparently transmit signals input to them.

[0177] Mode 2 is a low-load mode (low power consumption, where power supply or clock interruption depends on load changes).

[0178] Mode 3 is the standard load mode (typical power consumption where power supply and clock are not interrupted).

[0179] In one implementation, please refer to Figure 26 for the structure of the active module. The active module contains multiple functional modules (for example, functional modules 1 through L in Figure 26). These multiple functional modules work together to complete the standard operation of the active module.

[0180] After an input signal (for example, Sin in Figure 26) is input to the active module, each of the functional modules within the active module processes the input signal and can then output the resulting output signal (i.e., Sout in Figure 26) through its output interface.

[0181] Optionally, the active module may further include an LPC. After receiving an indication signal, the LPC may, based on the indication signal, control the operating state of each of the functional modules in the active module (for example, controlling whether any one of the functional modules completes a conventional operation, and / or controlling the operating gear of any one of the functional modules). In this way, the operating mode of the active module can be controlled.

[0182] In one implementation, the LPC controls all functional modules in the active module to operate normally based on the first indication signal received. In this case, the operating mode of the active module is the standard load mode. See Figure 27.

[0183] In another implementation, the LPC may control all functional modules in the active module to cease operation based on a received second indication signal, and the power supply module may cease supplying power to each of the functional modules. In this case, the active module's operating mode is no-load mode. See Figure 28. In this operating mode, the active module may transparently transmit the received signal, i.e., Sout = Sin. Alternatively, the active module may not output a signal. Specific schemes may be designed specifically based on system requirements and actual scenarios, and are not limited to those described herein.

[0184] In yet another implementation, the LPC may, based on a received third command signal, control the first functional module in the active module to operate normally and the second functional module to stop operating, and the power supply module directly cuts off the power to the second functional module. In this case, the operating mode of the active module is the low-load mode. See Figure 29. Note that there may be one or more first functional modules; this is not limited to this embodiment of the present application.

[0185] Based on the solution provided in Embodiment 3, this application further provides the following examples.

[0186] Case 1: The structure of a conventional flash ADC is shown in Figure 30, and mainly includes a voltage divider circuit, multiple comparators (e.g., CM0 to CM N-1 shown in Figure 30), a latch decoding module, an output module, and a clock control logic circuit. For the functions and operating principles of the modules, please refer to conventional design solutions for flash ADCs. Details are not described herein. Based on the conventional architecture shown in Figure 30, in this case, the power consumption of the ADC can be reduced by using the following two solutions.

[0187] Solution 1: Directly control the blocking of a portion of the comparator based on the bit_info information of the preceding module.

[0188] Solution 2: Based on the low-power indication generated by the gear control circuit, shut off a portion of the comparator.

[0189] The implementation of Solution 1 will be explained below with reference to Figure 31.

[0190] The pre-ADC module can send an indication signal (for example, bit_info in Figure 31) to the ADC, which can independently control the activation and deactivation of each comparator. For example, in the case of an N-bit flash ADC, when the input bit_info is a 2-bit bit sequence, the ADC can deactivate comparators other than the first and second comparators, as well as the associated decoding links, based on bit_info. In this way, the power consumption of the flash ADC is reduced.

[0191] The implementation of Solution 2 will be explained below with reference to Figures 32 and 33.

[0192] In Solution 2, the operating state of the ADC can be divided by a gear via a gear control circuit, and data prediction is performed based on the gear. If the input analog signal is greater than the signal corresponding to the gear, the ADC operates normally. If the input analog signal is less than the signal corresponding to the gear, submodules such as comparators are shut off if the signal level exceeds the gear. In this way, the overall operating power consumption of the ADC is reduced.

[0193] Figure 32 shows the ADC operating state divided by two gears. As shown in Figure 32, the control signal output by the gear control circuit enables only the comparator corresponding to bit X. This is equivalent to dividing the ADC operating state by two gears, where bits 0 through X-1 belong to one gear, and bits above X belong to the other gear. When the output of the comparator corresponding to bit X is 0, only the comparators corresponding to bits 0 through X-1 are enabled, and the other comparators corresponding to bits above X are blocked. When the output of the comparator corresponding to bit X is 1, all comparators operate normally in conventional mode.

[0194] Figure 32 shows only the case where the ADC is divided by two gears. Based on the principle described above, this example can be further extended to more gears, such as three gears, and can be designed based on a gear control circuit. Figure 33 is a diagram of the ADC's operating state divided by three gears, and other or more gears are not shown.

[0195] Please refer to Figure 33. When the ADC is divided by three gears, the gear control circuit first activates the comparators corresponding to two bits, namely the comparator corresponding to bit X and the comparator corresponding to bit Y.

[0196] When the ADC operates, data determination begins with the comparator corresponding to bit X. If the output of the comparator corresponding to bit X is 0, only the comparators corresponding to bits 0 through X-1 are enabled, and the other comparators corresponding to bits above X are blocked. If the output of the comparator corresponding to bit X is 1, the comparator corresponding to bit Y continues to perform data determination.

[0197] If the output of the comparator corresponding to bit Y is 0, only the comparators corresponding to bits 0 through Y-1 ​​are enabled, and the other comparators corresponding to bits above Y are blocked. If the output of the comparator corresponding to bit Y is 1, all comparators in the ADC operate normally in conventional mode.

[0198] Case 2:

[0199] Similar to Example 1, the SAR ADC also performs sequential comparisons for each bit. Therefore, the ADC can also perform energy savings for some submodules, such as comparators, via the bit_info signal of the preceding module or gear control circuit. For details, please refer to the explanation in Example 1. Further details will not be explained again in this specification.

[0200] Case 3: A pipelined ADC includes a multi-stage sub-ADC. A differential configuration is used, where a 1-bit analog-to-digital conversion is performed in each stage, and the differential signal is then transmitted to the next stage. See Figure 34 for the structure of the pipelined ADC. The ADC includes a multi-stage sub-ADC (i.e., multiple stages, e.g., S1 to Sn in Figure 34). For the function and operating principle of the module, see the conventional design solutions for pipelined ADCs. Details are not described herein.

[0201] Similar to Case 1, in this case, the power consumption of the ADC can also be reduced by using two solutions.

[0202] Solution 1: The ADC can directly control the shutdown of one or more stages of sub-ADCs in a multi-stage sub-ADC via the bit_info of the preceding module. See Figure 35. For a specific implementation of Solution 1, see the description of Solution 1 in Example 1. Further details are not provided herein.

[0203] Solution 2: Based on the low-power indication generated by the gear control circuit, shut off a portion of the sub-ADC. See Figure 36. For a specific implementation of Solution 2, see the description of Solution 2 in Example 1. Further details are not provided herein.

[0204] According to the embodiments and examples described above, the present application further provides a chip comprising at least one of the ADCs or active modules provided in the embodiments or examples described above.

[0205] According to the embodiments and examples described above, the present application further provides a board or active device, which includes at least one of the ADCs or active modules provided in the embodiments or examples described above.

[0206] According to the embodiments and examples described above, the present application further provides a signal processing apparatus, which includes at least one of the ADCs or active modules provided in the embodiments or examples described above.

[0207] According to the embodiments and examples described above, the present application further provides a signal processing system. The system includes a processing unit and at least one of the ADCs or active modules provided in the embodiments or examples described above. The processing unit is configured to control, manage, and modulate the processing bit width of the ADC or the operating mode of the active module. For example, the processing unit is configured to generate a first indication signal or a second indication signal, or a first bit-width indication signal or a second bit-width indication signal, or to generate bit_info, or to generate low-power indication, and so on.

[0208] According to the embodiments and examples described above, this application further provides electronic devices (for example, communication devices such as base stations). The electronic devices include at least one of the ADCs or active modules provided in the embodiments or examples described above.

[0209] Those skilled in the art will understand that embodiments of this application may be provided as methods, systems, or computer program products. Accordingly, embodiments of hardware only, software only, or a combination of software and hardware may be used in this application. Furthermore, embodiments of computer program products that include computer-usable program code and are implemented on one or more computer-usable storage media (including, but not limited to, disk memory, CD-ROM, optical memory, etc.) may be used in this application.

[0210] This application will be described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products relating to this application. It should be understood that computer program instructions may be used to implement each step and / or block in the flowcharts and / or block diagrams, as well as combinations of steps and / or blocks in the flowcharts and / or block diagrams. Computer program instructions may be provided for a processor of a general-purpose computer, a dedicated computer, an embedded processor, or another programmable data processing device for generating machines, and as a result, instructions executed by the processor of the computer or another programmable data processing device will generate a device configured to implement one or more steps in the flowchart and / or one or more blocks in the block diagrams.

[0211] Computer program instructions can, alternatively, be stored in computer-readable memory, which can instruct a computer or another programmable data processing device to operate in a specific manner. As a result, instructions stored in computer-readable memory generate an artifact that includes an instruction unit. The instruction unit implements the functions specified in one or more steps in a flowchart and / or one or more blocks in a block diagram.

[0212] Computer program instructions may, alternatively, be loaded onto a computer or another programmable data processing device, resulting in a series of operational steps being performed on the computer or another programmable device to generate computer implementation processing, and consequently, the instructions executed on the computer or another programmable device provide steps for implementing a function specified in one or more steps in a flowchart and / or one or more blocks in a block diagram.

[0213] It is clear that a person skilled in the art can make various changes and modifications to this application without departing from the scope of protection of this application. In this way, if the changes and modifications to this application fall within the scope of the claims of this application and the equivalent art thereto, then this application shall also include such changes and modifications.

Claims

1. An analog-to-digital converter (ADC) comprising a first-stage sub-ADC, a second-stage sub-ADC, a first interstage amplifier, a digital control module, a low-power control module, and a first multiplexer, The low-power control module is configured to send a first control signal to the first-stage sub-ADC and a first selection signal to the first multiplexer based on a received first indication signal, or to send a second control signal to the first-stage sub-ADC and a second selection signal to the first multiplexer based on a received second indication signal, wherein the first control signal indicates that the first-stage sub-ADC will perform analog-to-digital conversion on a first input analog signal, the first selection signal indicates that the first multiplexer will select a signal input through the first input terminal, the second control signal indicates that the first-stage sub-ADC will skip performing analog-to-digital conversion on the first input analog signal, and the second selection signal indicates that the first multiplexer will select a signal input through the second input terminal. The first stage sub-ADC is configured to, upon receiving the first control signal, perform analog-to-digital conversion on the first input analog signal based on the first control signal and the first reference analog signal to generate a first M-bit digital signal, send the first M-bit digital signal to the digital control module, correct the first input analog signal based on the first M-bit digital signal to generate a first corrected input analog signal, and send the first corrected input analog signal to the first input terminal of the first multiplexer. The first stage sub-ADC is further configured to skip performing analog-to-digital conversion on the first input analog signal based on the second control signal when it receives the second control signal. The first multiplexer is configured to receive the first corrected input analog signal from the first stage sub-ADC through the first input terminal, receive the first input analog signal through the second input terminal, and, upon receiving the first selection signal, select the signal input through the first input terminal as the second input analog signal based on the first selection signal, or, upon receiving the second selection signal, select the signal input through the second input terminal as the second input analog signal based on the second selection signal, and send the signal obtained by amplifying the second input analog signal to the first interstage amplifier. The first interstage amplifier is configured to amplify the received second input analog signal and to send the signal obtained by amplifying the second input analog signal to the second stage sub-ADC. The second stage sub-ADC is configured to perform analog-to-digital conversion on the second input analog signal based on the second reference analog signal to generate a first N-bit digital signal, and to send the first N-bit digital signal to the digital control module. The digital control module is configured to perform correction control on the received first M-bit digital signal and the received first N-bit digital signal to generate a first (M+N)-bit output digital signal, or to perform correction control on the received first N-bit digital signal to generate a first N-bit output digital signal, where M is a positive integer and N is a positive integer. Analog-to-digital converter (ADC).

2. The low-power control module is In the first mode, based on the received first indication signal, the first control signal is sent to the first stage sub-ADC and the first selection signal is sent to the first multiplexer, or based on the received second indication signal, the second control signal is sent to the first stage sub-ADC and the second selection signal is sent to the first multiplexer. It is specifically configured to do so, The low-power control module is In the second mode, a third control signal is sent to the first stage sub-ADC, the third control signal indicating that the first stage sub-ADC should determine whether to perform analog-to-digital conversion on the first input analog signal based on the magnitude of the first input analog signal. It is further configured to do the following: The aforementioned first stage sub-ADC is Based on the third control signal, the first input analog signal is compared with a specified signal. When the first input analog signal is greater than the specified signal, the process involves performing analog-to-digital conversion on the first input analog signal based on the first reference analog signal to generate a second M-bit digital signal, sending the second M-bit digital signal to the digital control module, correcting the first input analog signal based on the second M-bit digital signal to generate a second corrected input analog signal, sending the second corrected input analog signal to the first input terminal of the first multiplexer, and sending a third selection signal to the first multiplexer, wherein the third selection signal indicates that the first multiplexer has selected the signal input through the first input terminal. Do or When the first input analog signal is smaller than the specified signal, the analog-to-digital conversion of the first input analog signal is skipped, and a fourth selection signal is sent to the first multiplexer, the fourth selection signal indicating that the first multiplexer selects the signal input through the second input terminal. It is further configured to do the following: The first multiplexer is further configured to receive the second corrected input analog signal from the first stage sub-ADC through the first input terminal, receive the first input analog signal through the second input terminal, and, upon receiving the third selection signal, select the signal input through the first input terminal as the third input analog signal based on the third selection signal, or, upon receiving the fourth selection signal, select the signal input through the second input terminal as the third input analog signal based on the fourth selection signal, and send the signal obtained by amplifying the third input analog signal to the first interstage amplifier. The first interstage amplifier is further configured to amplify the received third input analog signal and to send the signal obtained by amplifying the third input analog signal to the second stage sub-ADC. The second stage sub-ADC is further configured to perform analog-to-digital conversion on the third input analog signal based on the second reference analog signal to generate a second N-bit digital signal, and to send the second N-bit digital signal to the digital control module. The ADC according to claim 1, wherein the digital control module is further configured to perform correction control on the received second M-bit digital signal and the received second N-bit digital signal to generate a second (M+N)-bit output digital signal, or to perform correction control on the received second N-bit digital signal to generate a second N-bit output digital signal.

3. The value of the specified signal is the value of the first reference analog signal × 1 / 2 Ｍ The ADC according to claim 2, which is equivalent to the ADC according to claim 2.

4. The low-power control module comprises a selection control module and a signal generation module. The signal generation module is configured to generate the third control signal in the second mode. The selection control module receives the first indication signal or the second indication signal through the first input terminal, and receives the third control signal from the signal generation module through the second input terminal. In the first mode, based on the first indication signal received through the first input terminal, the first control signal is sent to the first stage sub-ADC and the first selection signal is sent to the first multiplexer, or based on the second indication signal received through the first input terminal, the second control signal is sent to the first stage sub-ADC and the second selection signal is sent to the first multiplexer. In the second mode, the third control signal received through the second input terminal is sent to the first stage sub-ADC. The ADC according to claim 2 or 3, configured to perform the following:

5. The selection control module is a second multiplexer, wherein the value of the first indication signal, the value of the first control signal, and the value of the first selection signal are the same, or the value of the second indication signal, the value of the second control signal, and the value of the second selection signal are the same. The ADC according to claim 4, wherein the second multiplexer is configured to select a signal input through the first input terminal in the first mode, or to select a signal input through the second input terminal in the second mode.

6. The ADC according to any one of claims 1 to 5, wherein the first indication signal or the second indication signal is generated by a preceding module of the ADC based on service data of a specified granularity, and the service data of the specified granularity is a single sampled data or service data received within a specified time.

7. The value of the first reference analog signal is either the same as the value of the second reference analog signal, or the value of the second reference analog signal is the value of the first reference analog signal × 1 / 2 Ｋ It is equal to and K is a positive integer less than or equal to M, The ADC according to any one of claims 1 to 6, wherein the operating parameters of the first interstage amplifier are set based on the value of the first reference analog signal and the value of the second reference analog signal.

8. The value of the second reference analog signal is the value of the first reference analog signal × 1 / 2 Ｍ Equal to the above, the specified signal is the second reference analog signal, The ADC according to claim 2, wherein the first-stage sub-ADC includes a controller, and the controller is configured to turn on a switch between the second reference analog signal and the first-stage sub-ADC when it receives the third control signal.

9. An analog-to-digital converter (ADC) comprising a first-stage sub-ADC, a second-stage sub-ADC, a first interstage amplifier, a digital control module, a low-power control module, and a first multiplexer, The low-power control module is configured to send a first control signal to the first-stage sub-ADC, a first selection signal to the first multiplexer, and a second control signal to the second-stage sub-ADC based on a received first bit width indication signal, wherein the first control signal indicates that the first-stage sub-ADC will perform m-bit analog-to-digital conversion, where m is a positive integer less than or equal to the maximum processing bit width M of the first-stage sub-ADC; the first selection signal indicates that the first multiplexer will select the signal input through the first input terminal; the second control signal indicates that the second-stage sub-ADC will perform N-bit analog-to-digital conversion, where N is the maximum processing bit width of the second-stage sub-ADC, M is a positive integer, and N is a positive integer; and the first bit width indication signal is for indicating that the processing bit width of the ADC is m + N. The first stage sub-ADC is configured to perform analog-to-digital conversion on a first input analog signal based on the received first control signal and first reference analog signal to generate an m-bit digital signal and send the m-bit digital signal to the digital control module, correct the first input analog signal based on the m-bit digital signal to generate a first corrected input analog signal, and send the first corrected input analog signal to the first input terminal of the first multiplexer. The first multiplexer is configured to receive the first corrected input analog signal from the first stage sub-ADC through the first input terminal, receive the first input analog signal through the second input terminal, and, upon receiving the first selection signal, select the signal input through the first input terminal as the second input analog signal based on the first selection signal. The first interstage amplifier is configured to amplify the received second input analog signal and to send the signal obtained by amplifying the second input analog signal to the second stage sub-ADC. The second stage sub-ADC is configured to perform analog-to-digital conversion on the second input analog signal based on the second reference analog signal to generate an N-bit digital signal, and to send the N-bit digital signal to the digital control module. The digital control module is an analog-to-digital converter (ADC) configured to perform correction control on the received m-bit digital signal and the received first N-bit digital signal to generate an (m+N)-bit output digital signal.

10. The low-power control module is further configured to send a third control signal to the first-stage sub-ADC, a second selection signal to the first multiplexer, and a fourth control signal to the second-stage sub-ADC, based on a received second bit-width indication signal, wherein the third control signal indicates that the first-stage sub-ADC will skip performing analog-to-digital conversion on the first input analog signal, the second selection signal indicates that the first multiplexer will select the signal input through the second input terminal, and the fourth control signal indicates that the second-stage sub-ADC will perform n-bit analog-to-digital conversion, where n is a positive integer less than or equal to N, and the second bit-width indication signal is for indicating that the processing bit width of the ADC is n. The first stage sub-ADC is further configured to skip performing analog-to-digital conversion on the first input analog signal based on the received third control signal. The first multiplexer is further configured to select the first input analog signal input through the second input terminal as a third input analog signal based on the second selection signal, The first interstage amplifier is further configured to amplify the received third input analog signal and to send the signal obtained by amplifying the third input analog signal to the second stage sub-ADC. The second stage sub-ADC is further configured to perform analog-to-digital conversion on the third input analog signal based on the second reference analog signal to generate an n-bit digital signal, and to send the n-bit digital signal to the digital control module. The ADC according to claim 9, wherein the digital control module is further configured to perform correction control on a received first n-bit digital signal to generate an n-bit output digital signal.

11. The first bit width indication signal is a first bit sequence of H bits, and the second bit width indication signal is a second bit sequence of H bits, 2 Ｈ is greater than or equal to M + N, and The ADC according to claim 10, wherein the decimal value of the first bit sequence is equal to m + N, and the decimal value of the second bit sequence is equal to n.

12. The ADC according to claim 10 or 11, wherein the first bit width indication signal or the second bit width indication signal is generated by a preceding module of the ADC based on service data of a specified granularity, and the service data of the specified granularity is a single sampled data or service data received within a specified time.

13. The value of the first reference analog signal is the same as the value of the second reference analog signal, or the value of the second reference analog signal is the value of the first reference analog signal × 1 / 2 Ｋ It is equal to and K is a positive integer less than or equal to M, The ADC according to any one of claims 9 to 12, wherein the operating parameters of the first interstage amplifier are set based on the value of the first reference analog signal and the value of the second reference analog signal.

14. ADC according to any one of claims 1 to 13 A chip equipped with this feature.

15. ADC according to any one of claims 1 to 13 A signal processing device equipped with the following features.

16. A signal processing system comprising a processing unit and an ADC according to any one of claims 1 to 13, The processing unit is configured to generate a first indication signal or a second indication signal. Signal processing system.

17. A signal processing system comprising a processing unit and an ADC according to any one of claims 1 to 13, The processing unit is configured to generate a first bit width indication signal or a second bit width indication signal. Signal processing system.

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