An ultra-high energy-efficient time-domain analog-to-digital converter based on a gated ring oscillator

Abstract

The application discloses a kind of based on super high energy efficiency time domain analog-digital converter of gate type ring oscillator, comprising: voltage-time conversion circuit, pulse generation circuit, self-tracking sampling clock generation circuit, gate ring oscillator circuit, comparator quantization circuit, counter quantization circuit and sampling decoding circuit;Gate ring oscillator circuit includes N-stage gate delay unit, N-stage gate delay unit is cascaded to form cross-coupled positive feedback circuit, gate delay unit is controlled under the control of external reset voltage to the internal node of gate delay unit Voltage reset, positive feedback resistor is connected on the positive feedback path of gate delay unit;The positive feedback path of gate delay unit and gate inverter are controlled by the gate signal generated by pulse generation circuit.This application simplifies subsequent decoding logic, while effectively reducing the delay of gate delay unit, improves the oscillation frequency and time resolution of the overall ring oscillator, and greatly improves the energy efficiency ratio of ADC.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit technology, specifically relating to an ultra-high energy efficiency time-domain analog-to-digital converter based on a gated ring oscillator. Background Technology

[0002] Time-domain ADCs (A / D converters) represent a promising new architecture for high-speed and high-efficiency applications, holding significant importance and research value for realizing high-performance, ultra-high-speed communication systems. The core component determining the performance of a time-domain ADC lies in the time-to-digital converter (TDC). Due to the inherent time-domain folding characteristics of ring oscillators, their complexity is significantly reduced compared to delay-line TDCs and vernier TDCs. While simple free-oscillating TDCs are easy to implement, they consume considerable power. Gated ring oscillators, on the other hand, adapt their operating time to the input signal magnitude, resulting in higher energy efficiency for TDCs. However, analog-to-digital converters still suffer from complex decoding logic, high quantization power consumption, and relatively low oscillation frequency and time resolution, leading to relatively low energy efficiency. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this invention provides an ultra-high energy efficiency time-domain analog-to-digital converter based on a gated ring oscillator. The technical problem to be solved by this invention is achieved through the following technical solution:

[0004] An ultra-high energy efficiency time-domain analog-to-digital converter based on a gated ring oscillator includes: a voltage-to-time conversion circuit, a pulse generation circuit, a self-tracking sampling clock generation circuit, a gated ring oscillator circuit, a comparator quantization circuit, a counter quantization circuit, and a sampling decoding circuit;

[0005] The output terminal of the voltage-to-time conversion circuit is connected to the input terminal of the pulse generation circuit and the input terminal of the self-tracking sampling clock generation circuit, respectively.

[0006] The output of the self-tracking sampling clock generation circuit is connected to the input of the sampling decoding circuit;

[0007] The output terminal of the gated ring oscillator circuit is connected to the input terminal of the counter quantization circuit and the input terminal of the comparator quantization circuit.

[0008] The output terminals of the counter quantization circuit and the comparator quantization circuit are both connected to the input terminal of the sampling decoding circuit.

[0009] The gated ring oscillator circuit includes N-stage gated delay units, which are cascaded to form a cross-coupled positive feedback circuit. Under the control of an external reset voltage, the internal nodes of the gated delay units are voltage reset. A positive feedback resistor is connected to the positive feedback path of the gated delay units. The positive feedback path of the gated delay units and the gated inverter are controlled by the gated signal generated by the pulse generation circuit.

[0010] In one embodiment of the present invention, the gated delay unit includes: a gated inverter, a node reset switch, a gated switch, and the positive feedback resistor;

[0011] One end of the positive feedback resistor is connected to the input terminal of the gated inverter, and the other end is connected to one end of the node reset switch and one end of the gated switch; the other end of the node reset switch is connected to the reset voltage.

[0012] The other end of the gate switch is connected to the output of the gate inverter of another gate delay unit; wherein, the input of the gate inverter, the positive feedback resistor, and the connection between the gate switch and the output of the gate inverter of another gate delay unit form the positive feedback path;

[0013] The gated inverter and the gated switch are controlled by the gated signal.

[0014] In one embodiment of the present invention, the output terminal of the gated ring oscillator circuit is connected to the input terminal of the comparator quantization circuit and the input terminal of the counter quantization circuit through a first-stage interpolation circuit.

[0015] In one embodiment of the present invention, each stage of the interpolation circuit includes two inverters with their output terminals shorted together, and the input terminals of the two inverters are respectively connected to the output terminal and the input terminal of the gated ring oscillator circuit.

[0016] In one embodiment of the present invention, the self-tracking sampling clock generation circuit includes: an AND gate circuit, a first delay circuit, a second delay circuit, and a NAND gate circuit;

[0017] The first time signal and the second time signal output from the output terminal of the voltage-time conversion circuit are input to the two input terminals of the AND gate circuit. The output terminal of the AND gate circuit is connected to the input terminal of the first delay circuit. The output terminal of the first delay circuit is connected to the input terminal of the second delay circuit and the first input terminal of the NAND gate circuit. The output terminal of the second delay circuit is connected to the second input terminal of the NAND gate circuit. The output terminal of the NAND gate circuit is connected to the input terminal of the sampling decoding circuit.

[0018] In one embodiment of the present invention, the sampling and decoding circuit includes: a trigger sampling circuit and a decoding circuit; the trigger sampling circuit acquires quantization information of the gated ring oscillator circuit under the control of the sampling clock output by the NAND gate circuit;

[0019] The output of the first-stage interpolation circuit is connected to the input of the comparator quantization circuit and the input of the counter quantization circuit.

[0020] The output of the comparator quantization circuit is connected to the input of the flip-flop sampling circuit;

[0021] The output of the counter quantization circuit is connected to the input of the trigger sampling circuit;

[0022] The input terminal of the trigger sampling circuit is also connected to the output terminal of the self-tracking sampling clock generation circuit, and the output terminal of the trigger sampling circuit is connected to the input terminal of the decoding circuit.

[0023] The beneficial effects of this invention are:

[0024] Before each cycle transition, the N-stage gated delay unit of this invention resets the voltage of its internal nodes under the control of a reset voltage signal. Therefore, the initial state for each transition is determined, significantly simplifying subsequent decoding logic. The gated inverter and positive feedback path are directly controlled by the gate signal en, operating only when en is high, thus saving quantization power consumption. Simultaneously, the positive feedback path implemented through the positive feedback resistor effectively reduces the delay of the gated delay unit, thereby improving the overall ring oscillator's oscillation frequency and time resolution, and significantly enhancing the ADC's energy efficiency ratio.

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0026] Figure 1 A circuit block diagram of an ultra-high efficiency time-domain analog-to-digital converter based on a gated ring oscillator is provided for an embodiment of the present invention.

[0027] Figure 2 A schematic diagram of the structure of a 4-stage gated ring oscillator circuit provided in an embodiment of the present invention;

[0028] Figure 3 A circuit diagram of the gated delay unit provided in an embodiment of the present invention;

[0029] Figure 4 This is a circuit diagram of a gated inverter provided in an embodiment of the present invention;

[0030] Figure 5A schematic diagram of the first-stage interpolation circuit provided in an embodiment of the present invention;

[0031] Figure 6 for Figure 2 A schematic diagram of the corresponding M-bit counter quantization circuit;

[0032] Figure 7 A schematic diagram of a self-tracking sampling clock generation circuit provided in an embodiment of the present invention;

[0033] Figure 8 Timing diagram for generating a self-tracking sampling clock provided in an embodiment of the present invention;

[0034] Figure 9 A schematic diagram of a sampling decoding circuit provided in an embodiment of the present invention;

[0035] Figure 10 This is a schematic diagram of a 6.5-bit TDC circuit provided for an embodiment of the present invention. Detailed Implementation

[0036] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0037] like Figure 1 and Figure 2 As shown, an ultra-high energy efficiency time-domain analog-to-digital converter based on a gated ring oscillator includes: a voltage-to-time conversion circuit, a pulse generation circuit, a self-tracking sampling clock generation circuit, a gated ring oscillator circuit, a comparator quantization circuit, a counter quantization circuit, and a sampling decoding circuit.

[0038] The output of the voltage-to-time conversion circuit is connected to the input of the pulse generation circuit and the input of the self-tracking sampling clock generation circuit, respectively. The first input signal V... inp Second input signal V inn The input terminal of the voltage-to-time conversion circuit processes the signal and outputs the first time signal T. P Second time signal T N First time signal T P Second time signal T N The input is processed by the self-tracking sampling clock generation circuit and the pulse generation circuit, and the self-tracking sampling clock generation circuit outputs the sampling clock CLK. DFF The pulse generation circuit outputs a gate signal en.

[0039] The output of the self-tracking sampling clock generation circuit is connected to the input of the sampling decoding circuit;

[0040] The output of the gated ring oscillator circuit is connected to the inputs of the counter quantization circuit and the comparator quantization circuit; the outputs of both the counter quantization circuit and the comparator quantization circuit are connected to the input of the sampling decoder circuit; the gate signal en is input to the gated ring oscillator circuit, and the output signal of the gated ring oscillator circuit is input to the counter quantization circuit and the comparator quantization circuit. After processing by the comparator quantization circuit, the sampling decoder circuit outputs the signal at CLK. DFF Under the control of the system, the quantization information of the gated ring oscillator circuit and the quantization information of the counter quantization circuit are acquired, and then the binary quantization result is generated through the sampling decoding circuit.

[0041] The gated ring oscillator circuit includes N-stage gated delay units, which are cascaded to form a cross-coupled positive feedback circuit. Under the control of an external reset voltage rst, the gated delay units perform voltage reset on their internal nodes. A positive feedback resistor is connected to the positive feedback path of the gated delay units. The positive feedback path of the gated delay units and the gated inverter are controlled by a gate signal en generated by a pulse generation circuit.

[0042] In this embodiment, the N-stage gated delay unit constitutes an N-stage gated ring oscillator circuit. The analog-to-digital converter uses a gated ring oscillator and a comparator quantization circuit for fine quantization, and a gated ring oscillator and a counter quantization circuit for coarse quantization. Unlike a free-oscillating ring oscillator, the operating time of the gated ring oscillator (GRO) depends on the amplitude of the input signal. The operating time of the gated ring oscillator is positively correlated with the magnitude of the input voltage signal, thus exhibiting higher energy efficiency and significantly improving the energy efficiency ratio. By resetting the initial phase of the gated ring oscillator to a defined state before oscillation, the decoding logic is effectively simplified. The delay unit employs cross-coupled positive feedback technology, approximately doubling the oscillation frequency.

[0043] Before each cycle transition, the N-stage gated delay unit resets the internal nodes under the control of the reset voltage rst signal. Therefore, the initial state for each transition is determined, significantly simplifying subsequent decoding logic. The gated inverter and positive feedback path are directly controlled by the gate signal en, operating only when en is high, thus saving quantization power consumption. Simultaneously, the positive feedback path implemented through the positive feedback resistor R effectively reduces the delay of the gated delay unit, thereby improving the overall ring oscillator's oscillation frequency and time resolution, and significantly enhancing the ADC's energy efficiency ratio.

[0044] The reset voltage rst is a fixed voltage provided by an external clock module.

[0045] Furthermore, the gated delay unit includes: a gated inverter 10, a node reset switch sj, a gated switch sm, and a positive feedback resistor R;

[0046] One end of the positive feedback resistor R is connected to the input terminal of the gated inverter 10, and the other end of the positive feedback resistor R is connected to one end of the node reset switch sj and one end of the gated switch sm; the other end of the node reset switch sj is connected to the reset voltage rst.

[0047] The other end of the gate switch sm is connected to the output of the gate inverter 10 of another gate delay unit; wherein, the connection between the input of the gate inverter 10, the positive feedback resistor R, the gate switch sm and the output of the gate inverter 10 of another gate delay unit forms a positive feedback path; the gate inverter 10 and the gate switch sm are controlled by the gate signal en.

[0048] In this embodiment, as Figure 2 , Figure 3 and Figure 4 The diagram shows the case when N=4 of the N-stage gated delay unit. Before each cycle transition, the gated ring oscillator circuit resets the internal nodes under the control of the reset voltage rst signal. Therefore, the initial state of each transition is determined, significantly simplifying the subsequent decoding logic. During the transition, the oscillation state is controlled by the gate signal en. With N=4, it can be divided into 8 phases in one oscillation cycle, achieving a 3-bit time quantization resolution. The gated inverter 10 and the positive feedback path are directly controlled by the gate signal en, operating only when en is high, thus saving quantization power consumption. Reset switches are added to both sides of the positive feedback resistor R, effectively improving reset efficiency. Simultaneously, the addition of the positive feedback resistor R effectively reduces the delay of the delay unit, thereby improving the overall ring oscillator's oscillation frequency and time resolution.

[0049] Furthermore, the output of the gated ring oscillator circuit is connected to the input of the comparator quantization circuit and the input of the counter quantization circuit through a first-stage interpolation circuit. Each interpolation stage includes two inverters 20 with their outputs shorted. Specifically, the gated ring oscillator circuit has two inputs, namely the first differential input φ. k Second differential input terminal The gated ring oscillator circuit has two output terminals, namely the first differential output terminal. Second differential output terminal φ k+1 The first differential input terminal φ of the gated ring oscillator circuit k Second differential output terminal φ k+1 Connect to the two input terminals of the two inverters 20 respectively, or to the second differential input terminal of the gated ring oscillator circuit. and the first differential output terminal Each inverter 20 is connected to one of its two input terminals. The output terminals of the two inverters 20 are connected to the input terminals of the comparator quantization circuit and the counter quantization circuit, respectively.

[0050] In this embodiment, as Figure 2 and Figure 5 As shown, with I=1 and N=4, interpolating the output node of the gated ring oscillator using an interpolation circuit can further improve its overall quantization resolution. The interpolation circuit can be constructed from an inverter 20 with its output shorted. Under ideal interpolation accuracy, an I-stage interpolation circuit can improve the overall quantization resolution of the gated ring oscillator by I bits. Figure 6 This is the embodiment of the present invention and Figure 2 The corresponding M-bit counter quantization circuit (M=2) is mainly composed of flip-flops.

[0051] Furthermore, such as Figure 7 and Figure 8 As shown, the self-tracking sampling clock generation circuit includes: an AND gate circuit, a first delay circuit, a second delay circuit, and a NAND gate circuit;

[0052] The first time signal T output by the voltage-to-time conversion circuit P Second time signal T N The AND gate has two input terminals. The output terminal of the AND gate is connected to the input terminal of the first delay circuit. The output terminal of the first delay circuit is connected to the input terminal of the second delay circuit and the first input terminal of the NAND gate. The output terminal of the second delay circuit is connected to the second input terminal of the NAND gate. The output terminal of the NAND gate is connected to the input terminal of the sampling and decoding circuit.

[0053] In this embodiment, the first time signal T is first selected by an AND gate circuit. P Second time signal T N The signal that lags behind the input signal T S0 Among them, T S1 and T S2 The input signal T S0 The signals, after being delayed by t1 by the first delay circuit and by t1+t2 by the second delay circuit, are ultimately used to generate the sampling clock CLK through a NAND gate circuit. DFF The gate signal en is the first time signal T. P Second time signal T N The pulse signal obtained by performing an XOR operation in the pulse generation circuit has a pulse generation delay of t. pgSince sampling only occurs after the gated ring oscillator circuit stops oscillating, conversion power consumption is reduced, ensuring the stability of sampling and conversion. Furthermore, the sampling clock is synchronized with the moment oscillation stops, effectively suppressing the impact of leakage current in the gated ring oscillator circuit on quantization performance.

[0054] Among them, t pg If it is less than t1, t1 and t2 can be set as needed.

[0055] Furthermore, such as Figure 9 As shown, the sampling and decoding circuit includes: a flip-flop sampling circuit and a decoding circuit; the sampling clock CLK output by the flip-flop sampling circuit and the NAND gate circuit. DFF The acquisition of quantization information of the gated ring oscillator circuit under control;

[0056] The output of the first-stage interpolation circuit is connected to the input of the comparator quantization circuit and the input of the counter quantization circuit; the output of the comparator quantization circuit is connected to the input of the flip-flop sampling circuit.

[0057] The output of the counter quantization circuit is connected to the input of the flip-flop sampling circuit;

[0058] The input of the trigger sampling circuit is also connected to the output of the self-tracking sampling clock generation circuit, and the output of the trigger sampling circuit is connected to the input of the decoding circuit.

[0059] In one feasible implementation method Figure 10 This is a schematic diagram of a 6.5-bit TDC circuit. The overall structure of the TDC circuit consists of a 4.5-bit fine quantization path implemented by a 6-stage gated delay unit and a 2-bit coarse quantization path implemented by a 2-bit counter quantization circuit. In the fine quantization section, a 6-stage fully differential gated delay unit is used, which can generate 12 quantization phases per oscillation cycle, corresponding to a 3.5-bit quantization resolution. Simultaneously, this embodiment performs interpolation between each phase of the gated ring oscillator circuit, doubling the resolution. Therefore, the entire fine quantization module can achieve a 4.5-bit quantization bit depth. The phase information is sampled and decoded by comparators and flip-flops to complete the conversion from the time domain to the digital domain. The coarse quantization section consists of a 2-bit counter.

[0060] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0061] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0062] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0063] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0064] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0065] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-efficiency time-domain analog-to-digital converter based on a gated ring oscillator, characterized in that, include: Voltage-to-time conversion circuit, pulse generation circuit, self-tracking sampling clock generation circuit, gated ring oscillator circuit, comparator quantization circuit, counter quantization circuit, and sampling decoding circuit; The output terminal of the voltage-to-time conversion circuit is connected to the input terminal of the pulse generation circuit and the input terminal of the self-tracking sampling clock generation circuit, respectively. The output of the self-tracking sampling clock generation circuit is connected to the input of the sampling decoding circuit; The self-tracking sampling clock generation circuit includes: an AND gate circuit, a first delay circuit, a second delay circuit, and a NAND gate circuit; The first time signal and the second time signal output from the output terminal of the voltage-time conversion circuit are input to the two input terminals of the AND gate circuit. The output terminal of the AND gate circuit is connected to the input terminal of the first delay circuit. The output terminal of the first delay circuit is connected to the input terminal of the second delay circuit and the first input terminal of the NAND gate circuit. The output terminal of the second delay circuit is connected to the second input terminal of the NAND gate circuit. The output terminal of the NAND gate circuit is connected to the input terminal of the sampling decoding circuit. The sampling and decoding circuit includes: a trigger sampling circuit and a decoding circuit; the trigger sampling circuit acquires the quantization information of the gated ring oscillator circuit under the control of the sampling clock output by the NAND gate circuit. The output of the first-stage interpolation circuit is connected to the input of the comparator quantization circuit and the input of the counter quantization circuit. The output of the comparator quantization circuit is connected to the input of the flip-flop sampling circuit; The output of the counter quantization circuit is connected to the input of the trigger sampling circuit; The input terminal of the trigger sampling circuit is also connected to the output terminal of the self-tracking sampling clock generation circuit, and the output terminal of the trigger sampling circuit is connected to the input terminal of the decoding circuit. The output terminal of the gated ring oscillator circuit is connected to the input terminal of the counter quantization circuit and the input terminal of the comparator quantization circuit. The output terminals of the counter quantization circuit and the comparator quantization circuit are both connected to the input terminal of the sampling decoding circuit. The gated ring oscillator circuit includes N-stage gated delay units, which are cascaded to form a cross-coupled positive feedback circuit. Under the control of an external reset voltage, the internal nodes of each gated delay unit are voltage reset. A positive feedback resistor is connected to the positive feedback path of each gated delay unit. The positive feedback path of the gated delay unit and the gated inverter are controlled by a gate signal generated by the pulse generation circuit. The gated delay unit includes: a gated inverter, a node reset switch, a gated switch, and the positive feedback resistor; One end of the positive feedback resistor is connected to the input terminal of the gated inverter, and the other end is connected to one end of the node reset switch and one end of the gated switch; the other end of the node reset switch is connected to the reset voltage. The other end of the gate switch is connected to the output of the gate inverter of another gate delay unit; wherein, the input of the gate inverter, the positive feedback resistor, and the connection between the gate switch and the output of the gate inverter of another gate delay unit form the positive feedback path; The gated inverter and the gated switch are controlled by the gated signal.

2. The ultra-high efficiency time-domain analog-to-digital converter based on a gated ring oscillator according to claim 1, characterized in that, The output of the gated ring oscillator circuit is connected to the input of the comparator quantization circuit and the input of the counter quantization circuit through an I-stage interpolation circuit; where I represents the number of interpolation circuits.

3. The ultra-high efficiency time-domain analog-to-digital converter based on a gated ring oscillator according to claim 1, characterized in that, Each interpolation circuit includes two inverters with their outputs shorted together. The inputs of the two inverters are connected to the output and input of the gated ring oscillator circuit, respectively.

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