Multiple Instruction Multiple Data Processing Unit

Abstract

A processing unit comprising multiple modules is provided. Each of the multiple modules is configured to receive a first number of inputs and compute an output, and the multiple modules are divided into N module subsets connected in series. The N module subsets are connected in series from the first subset to the Nth subset. Each module subset is configured to process each total number of inputs received by the module subset. Each module in the module subset is configured to process a first number of inputs from each total number of inputs received by the module subset in parallel with the other modules in the module subset, compute the module's output, and transmit the module's output as input to each subsequent module subset connected in series, in parallel with the other modules in the module subset. The processing unit may be a MIMD processing unit and may further include interfaces for receiving inputs and weights, and may further include output subsets for executing one or more activation functions on one or more received outputs.

Description

[Technical Field]

[0001] This disclosure relates to a computer architecture. Specifically, this disclosure relates to a multiple instruction multiple data (MIMD) computer architecture, and to the design and implementation of a MIMD processing unit. [Background technology]

[0002] The demand for computing power is constantly increasing, particularly due to the expanding use of artificial intelligence and machine learning. Traditional processing units, such as arithmetic logic units (ALUs) or multiplication and integration units (MACs), can only apply one operation to two operands in a single processing step. This is called single-instruction, single-data (SISD) processing. More advanced processing units, such as graphics processing units (GPUs), Advanced Vector Extensions (AVX), and Streaming SIMD Extensions (SSEs), can apply one operation to multiple operands simultaneously in a single processing step. This is called single-instruction, multiple-data (SIMD) processing. However, operations on the same operand are executed sequentially. Therefore, traditional processing units cannot apply multiple operations to multiple operands simultaneously in a single processing step. Furthermore, existing processing units have many drawbacks, including structural complexity, scalability limitations, long buses, and increasing cache sizes.

[0003] Existing algorithms related to artificial neural networks, string comparison, and finite impulse response (FIR) filters all perform summation operations on weighted inputs. Some implementations of these algorithms use MAC cores within field-programmable gate arrays (FPGAs). Other implementations, such as Google's Tensor Processing Unit (TPU), use condensed arrays with MAC units containing activation units on each node. Some other implementations of the above algorithms use MACs within Accumulated Matrix Products (AMPs), such as Graphcore's Intelligence Processing Unit (IPU). By using MACs, these implementations can only perform one loop pass per clock cycle to compute a single weighted input.

[0004] Analog in-memory implementations of these algorithms also exist. For example, Mythic AI uses a digital-to-analog converter (DAC) to convert the neuron's output into an analog signal, which is then amplified and added by an adjustable register. The resulting current is then converted back into a digital signal by an analog-to-digital converter (ADC). However, these techniques share the commonality that the neuron's output is exchanged via a bus, which becomes a bottleneck and limits performance. Furthermore, all of these approaches do not consider data exchange within their architecture, and therefore lack scalability.

[0005] US2017 / 0357891, which discloses one or more bit-series tiles for performing bit-series operations, describes a system in which each bit-series tile receives input neurons and synapses and transmits output neurons. It also includes activation memory for storing neurons, as well as a dispatcher and a reducer. The dispatcher reads neurons and synapses from memory and transmits them to one or more bit-series tiles in a bit-series manner. The reducer receives output neurons from one or more tiles and transmits them to the activation memory. However, this system has the problem that weighted input summation is performed in a bit-parallel manner, and that the use of a dispatcher, reducer, and activation memory increases its complexity.

[0006] The systems described in US2019 / 0228307 and US2020 / 0371745 disclose a data processing method that includes generating weight data by encoding multiple weights of an artificial neural network filter using inverted two's complement fixed-point form, and performing operations on the weight data and input activation data using a bit-series method to control when the activation function is executed with respect to the weight data and input activation data. However, these systems suffer from increased complexity due to the bit-parallel operation of the weighted inputs and the use of input registers.

[0007] Therefore, the current processing architecture needs to be simplified and scalable, especially to enable real-time MIMD processing. Furthermore, the enhanced processing architecture should ideally enable high-speed computation without requiring a bus to transmit intermediate calculation results or a cache to store results. It is also desirable to provide an enhanced architecture that enables point-to-multipoint communication through routing rather than addressing. Moreover, it is desirable to provide an architecture that exhibits constant processing time, rather than processing time that depends on the number of loops, as in conventional architectures. Furthermore, real-time performance determined by the design is desired, rather than real-time performance that depends on the operating system, as in the current architecture. In addition, it is desirable to be able to implement a smaller IC structure by using more layers and increasing the number of processing units per layer within the same chip area. This is impossible in the current architecture because increasing the number of cores requires a longer bus and more cache. [Overview of the project]

[0008] According to one aspect of the present invention, a processing unit comprising a plurality of modules is provided. Each of the plurality of modules is configured to receive a first number of inputs and calculate an output, the first number of inputs being 2 or more, the plurality of modules are divided into N module subsets, the N module subsets are connected in series from the first subset to the Nth subset, and each module subset is configured to process each total number of inputs received by the subset. Each module in the module subset is configured to process the first number of inputs from each total number of inputs received by the module subset in parallel with the other modules in the module subset, calculate the module's output, and transmit the module's output as an input to each subsequent module subset connected in series, in parallel with the other modules in the module subset.

[0009] Each module is configured to receive a first number of inputs (2 or more) and compute one output. N module subsets are connected in series from the first subset to the Nth subset, providing a tree-structured architecture in which the first subset simultaneously receives the total number of inputs and the Nth subset simultaneously generates one output.

[0010] By configuring each module in a module subset to process a first number of inputs in parallel with the other modules in the module subset and calculate the module's output, simultaneous processing of all possible inputs becomes possible.

[0011] For example, starting with the first subset of modules, during one clock cycle, one bit of each input of the first number of inputs of the modules in that particular subset is processed simultaneously (e.g., added), and the output (e.g., the intermediate sum of the input bits of the first number of inputs) is calculated in parallel with the other modules in the subset. Thus, a module in a particular subset can process all its inputs simultaneously and calculate its output (e.g., the intermediate sum of all input bits) during one clock cycle.

[0012] By sending the output of a module in parallel with other modules in a module subset as input to each subsequent module subset connected in series, there is no need for a cache to store the output (e.g., intermediate sum) or a bus to transmit the output. This enables point-to-multipoint communication via routing rather than addressing, significantly reducing the complexity of the processing unit architecture.

[0013] In this configuration, transmitted outputs are processed by each subsequent subset until the Nth module subset calculates the final output (e.g., the sum of all input bits). While outputs are transmitted from the first module subset and processed by subsequent module subsets connected in series, new inputs (e.g., the next bit of the operand) are simultaneously processed by modules in the first module subset. This makes it possible to process all inputs bit by bit simultaneously, achieving real-time MIMD processing.

[0014] In a particular embodiment, the first subset may comprise a first number of modules equal to the value obtained by dividing the total number of each input received by the first subset by the first number of inputs, and the total number of each input received by the subset may be an integer multiple of the first number of inputs.

[0015] In some embodiments, each subsequent module subset may contain a number of modules equal to the number of outputs calculated by the module subset preceding the subsequent module subset divided by the number of inputs in the first module subset. Thus, the total number of modules in N subsets may be equal to the total number of inputs received by the first subset minus 1. Modules in a module subset may be configured to transmit their outputs bitwise in series, starting from the least significant bit and LSB first, as inputs to the corresponding modules in each subsequent module subset. This eliminates the need for a cache to store outputs and a bus to transmit outputs, significantly reducing architectural complexity.

[0016] Therefore, by simultaneously receiving all inputs or operands sequentially from the LSB, simultaneously processing all received input bits sequentially from the LSB to generate their respective outputs, and simultaneously transmitting each generated output as input to a subsequent module connected in series, while simultaneously processing all new input bits to generate new outputs, the proposed bit-series architecture, unlike conventional bit-parallel architectures, enables the simultaneous and distributed processing of all inputs or operands, thereby compensating for the additional clock cycles required. Existing bit-parallel architectures cannot process all inputs or operands simultaneously. These architectures are limited to processing only two inputs or operands simultaneously in one clock cycle.

[0017] In some embodiments, the processing unit may further comprise a subset of module interfaces configured to receive a total number of inputs and a number of weights equal to the number of inputs for each total number, and to calculate a weighted output. The inputs for each total number may be received bitwise in series from the processing unit for each total number or from the parallel-to-serial converter for each total number. The inputs for each total number may be synchronized by one or more input synchronization signals received from the processing unit for each total number or from the parallel-to-serial converter for each total number. The weights may be provided by control logic.

[0018] In some embodiments, a subset of interfaces may comprise a number of modules equal to the total number of inputs received by the subset of the module interfaces. Each module in the subset of interfaces may be configured to receive each of the total number of inputs and their corresponding weights, and to compute an output. Each module in the subset of the module interfaces may be configured to send its weighted output as input to the corresponding module in the first subset of modules, bitwise serial and LSB-first. A subset of interfaces may be configured to receive each of the total number of inputs bitwise and LSB-first, and to receive the corresponding number of weights bitwise in parallel or bitwise serial and LSB-first.

[0019] In some embodiments, the processing unit may further comprise an output module subset configured to receive one or more outputs of a module subset and perform one or more operations on the received one or more outputs to compute the output of the processing unit. The one or more operations may include applying one or more activation functions to the received outputs. The one or more activation functions may include one or more of the following: binary step function, linear function, sigmoid function, tanh function, normalized linear function, ReLU, leaky ReLU, parameterized ReLU, exponential linear function, swish function, unit sample function, carry function, One function, modulo function, 1 / n function, and Softmax function. The activation functions may be configured to be implemented using fixed lookup tables (LUTs) and / or programmable LUTs. The processing unit may further comprise control logic. The control logic may be configured to select one of fixed LUTs or programmable LUTs. The processing unit may be a MIMD processing unit.

[0020] According to another aspect of the present invention, a processing method is provided which includes the step of receiving a total number of inputs by each subset of a plurality of modules contained in a processing unit. The processing unit comprises a plurality of modules divided into N module subsets. The module subsets are connected in series from the first subset to the Nth subset. Each module is configured to receive a first number of inputs and calculate an output. The first number of inputs is 2 or more. The processing method includes the step of processing the total number of inputs received by each subset by each module subset contained in the processing unit. Each module of the module subset processes the first number of inputs from the total number of inputs received by each subset of modules in parallel with the other modules of the module subset and calculates the output of the module. The output of the module is transmitted in parallel with the other modules of the module subset as an input to each subsequent module subset connected in series.

[0021] The first subset may comprise a first number of modules equal to the total number of each input received by the first subset divided by the first number of inputs, and the total number of each input received by the subset may be a multiple of the first number of inputs. Each subsequent module subset may comprise a number of subsequent modules equal to the number of outputs calculated by the preceding module subset divided by the first number of inputs.

[0022] This method may further include the step of each module in a module subset transmitting an output, in bit-serial and LSB-first fashion, as an input to a corresponding module in each subsequent module subset. The step of each module subset included in the processing unit processing each respective total number of inputs received by the subset may include processing each respective total number of inputs in bit-serial and LSB-first fashion, or may include processing each respective total number of inputs partially in bit-serial and LSB-first fashion. The processing unit may be a MIMD processing unit. The processing unit may be configured to perform discontinuous processing in a processing network.

[0023] The following detailed description and the accompanying drawings provide a more detailed understanding of the nature and advantages of the present invention.

Brief Description of the Drawings

[0024] The accompanying drawings are incorporated into the specification to explain the principles of the embodiments and constitute a part of the specification. The drawings do not mean that the embodiments are limited to the manufacturing and use methods illustrated and described. Further features and advantages will become apparent hereinafter, particularly from the description of the embodiments shown in the accompanying drawings.

[0025] [Figure 1] A processing unit according to one embodiment is shown. [Figure 2] A processing unit according to one embodiment is shown. [Figure 3] A processing unit according to an embodiment is shown, including a subset of module interfaces and a subset of module outputs. [Figure 4] An example of synchronization of a processing unit according to an embodiment is shown. [Figure 5] A module with carry clear logic according to one embodiment is shown. [Figure 6] A processing unit showing the flow of synchronization signals according to an embodiment is shown. [Figure 7]This shows a combination of processing units that implement a processing network according to one embodiment. [Figure 8] This is a flowchart showing a method for processing input received by a processing unit according to one embodiment. [Figure 9] This is a flowchart illustrating a method for processing received input by a combination of processing units that implement a processing network, according to one embodiment. [Modes for carrying out the invention]

[0026] This specification describes systems and methods for the design and implementation of MIMD processing units. For illustrative purposes, numerous examples and specific details are provided to fully understand the embodiments described. Embodiments defined by the claims may include some or all of the features included in these examples, either individually or in combination with other features described later, and may also include variations and equivalents of the features and concepts described herein. Exemplary embodiments are described with reference to the drawings, where elements and structures are indicated by reference numerals. Furthermore, where an embodiment is a method, the steps and elements of the method may be performed in a combination of parallel or sequential execution. All embodiments described below can be combined with one another, as long as they do not conflict.

[0027] Figure 1 shows a processing unit 100 according to one embodiment. The processing unit comprises a plurality of modules 120. Each module 120 is configured to receive a first number as input and to calculate an output. The first number of input is 2 or greater. The plurality of modules are divided into N subsets of modules 1, 2, 3, ..., N. The N module subsets are connected in series from the first subset to the Nth subset. Each module subset is configured to process each total number input received by that subset. Each module in a module subset is configured to process the first number input from each total number input received by the module subset and to calculate the module's output in parallel with the other modules in the module subset. Each module in a module subset is further configured to transmit the module's output as input to each subsequent module subset connected in series, in parallel with the other modules in the module subset. Processing the first number input from each total number input received by the module subset by each module may include processing each bit of the first number input simultaneously by each module and calculating the module's output. Each input of the first number may be represented using M bits.

[0028] The first subset may comprise a first number of modules equal to the total number of inputs received by the first subset divided by the first number of inputs, and the total number of inputs received by the subset may be an integer multiple of the first number of inputs. Each subsequent module subset may comprise a number of modules equal to the number of outputs computed by the module subset preceding the subsequent module subset divided by the first number of inputs. Modules in a module subset may be configured to transmit their outputs bitwise in series and sequentially from the least significant bit (LSB) as inputs to the corresponding modules in each subsequent module subset. Computing the module's output in parallel with other modules in the subset includes each module in the module subset computing its output simultaneously with other modules in the subset. Transmitting the module's output in parallel with other modules in the module subset as inputs to subsequent module subsets connected in series includes transmitting the module's output simultaneously with other modules in the module subset as inputs to subsequent module subsets connected in series.

[0029] Each subsequent subset of a series-connected module may be the subset immediately following the series-connected module. Each input of the total number of inputs received by the subset may be an operand. Each input of the total number of inputs received by the subset may be represented using M bits. Each input of the total number of inputs received by the subset may be represented in two's complement form.

[0030] The total number of inputs in each subset are evenly divided among the modules of the module subset so that the sum of the first number of inputs in a subset is equal to the total number of inputs in each subset. Each module subset may be further configured to process the total number of inputs in bitwise serial and LSB-first, or partially in bitwise serial and LSB-first. Processing the total number of inputs in bitwise serial and LSB-first by a module subset includes processing the first number of inputs in bitwise serial and LSB-first by each module of the module subset. Processing the total number of inputs in bitwise serial and LSB-first by a module subset may include each module of the module subset performing a serial-to-parallel conversion on each input of the first number of inputs to produce a converted first number of inputs having a bitwise parallel form, performing bitwise parallel processing on the converted first number of inputs to compute the bitwise parallel processing result, and performing a parallel-to-serial conversion on the bitwise parallel processing result to produce the module's output.

[0031] Each module in the module subset may include one or more arithmetic logic circuits, each including at least one of the following: adder, subtractor, multiplier, AND, OR, NAND, NOR, NOT, and XOR. Each module in the module subset is configured to process a first number of inputs by using the module's one or more arithmetic logic circuits to perform one or more operations on a first number of inputs and compute an output.

[0032] Figure 2 shows a processing unit 200 according to one embodiment. In this embodiment, the processing unit 200 is an example of the processing unit 100 shown in Figure 1. In this embodiment, the first number of inputs received by each module 120 is 2. Multiple modules are divided into N subsets of modules, where N is equal to 3. The three subsets of module 1, module 2, and module 3 are connected in series from the first subset to the third subset. The total number of inputs received by the first subset is 8. The total number of modules in the three module subsets is 7.

[0033] Each subset of the module is configured to process the respective total number of inputs received by that subset. In this embodiment, the first subset processes a total of 8 inputs, the second subset processes a total of 4 inputs, and the third subset processes a total of 2 inputs.

[0034] Each module in the module subset is configured to process a first number of inputs, which in this embodiment are 2, from the total number of inputs received by the module subset, and to calculate the module's output in parallel with the other modules in the module subset, and to transmit the module's output as an input to each subsequent module subset connected in series, in parallel with the other modules in the module subset.

[0035] Each input of the total number of inputs received by a module subset may be an operand represented using M bits. For example, starting with the first subset of modules, during one clock cycle, one bit of each of the two inputs of a module in a particular subset is processed simultaneously (e.g., added), and the output (e.g., the intermediate sum of the two input bits of the two operands) is calculated in parallel with the other modules in the subset. Thus, a module in a particular subset can process all its inputs simultaneously and calculate its output (e.g., the intermediate sum of all input bits) during one clock cycle.

[0036] The transmitted output is processed by a second successor module subset, which calculates four successor outputs (e.g., successor intermediate sums). The four successor outputs are then sent to a third module subset for processing, which calculates the final output (e.g., the sum of all eight input bits of the eight operands).

[0037] The output is transmitted from the first module subset and processed by subsequent module subsets connected in series. Meanwhile, subsequent inputs (in this embodiment, the next eight input bits of the eight operands) are processed simultaneously by the modules of the first module subset. Once all M bits of all inputs have been processed by the first module subset, a total of each (in this embodiment, the total of each new operand) new inputs may be received for processing by the first module subset.

[0038] Depending on the configuration, a module in a module subset may be configured to transmit its output bitwise in series, starting from the least significant bit (LSB), as input to the corresponding module in each subsequent module subset. Each module in a module subset computing its output in parallel with other modules in the subset includes each module in the module subset computing its output simultaneously with other modules in the subset. Transmitting the module's output in parallel with other modules in the module subset as input to a subsequent module subset connected in series includes transmitting the module's output simultaneously with other modules in the module subset as input to a subsequent module subset connected in series. Each subsequent subset of a series-connected module may be the subset immediately following the series-connected module. Each input of the total number of inputs received by the module subset may be represented in two's complement form. The processing unit may be a MIMD processing unit.

[0039] Figure 3 shows a processing unit 300 according to an embodiment. The processing unit 300 includes an interface subset 340 of module 320 and an output subset 380 of module 360. The processing unit 300 may further include an interface subset 340 of module 320 configured to receive a total number of inputs and a number of weights equal to the number of total inputs, and to calculate a weighted output.

[0040] Each total number of inputs received by the interface subset of the processing unit's module may correspond to the output of each total number of processing units. Each total number of inputs received by the interface subset 340 of module 320 of processing unit 300 may also correspond to the output of each total number of processing units included in the preceding layer of the processing network. Each total number of inputs received by the interface subset of the processing unit's module may also correspond to the output of each total number of parallel-serial converters 720. The corresponding number of weights may be provided by the control logic 620. The control logic 620 may be included in the processing unit.

[0041] Each of the total number of inputs received by the module's interface subset may be synchronized by an input synchronization signal. The input synchronization signal may be received from each of the total number of processing units 300 included in the preceding layer of the processing network, or from each of the total number of parallel-serial converters 720, or from the bus.

[0042] Each input of each total number input received by the interface subset 340 of module 320 may be an operand represented using M bits. Each weight of the corresponding total number weight received by the module's interface subset may be an operand represented using M bits.

[0043] The interface subset 340 may comprise a number of modules 320 equal to the total number of inputs received by the module interface subset. Each module 320 of the interface subset 340 may be configured to receive each input of the total number of inputs and the corresponding weights of the corresponding number of weights, and to compute an output.

[0044] Interface subset 340 may be configured to receive each total number of inputs bitwise and LSB-first, and the corresponding number of weights bitwise in parallel or bitwise and LSB-first. If the corresponding number of weights are received in bitwise parallel format, a parallel-to-serial converter may be used to convert the bitwise parallel format to bitwise serial format. Each module in the module interface subset may be configured to send its weighted output bitwise and LSB-first as input to the corresponding module in its subsequent module subset. Each subsequent module subset may be the first subset 1 of module 120.

[0045] Each module 320 of the interface subset 340 may be configured to perform a bitwise serial multiplication operation on its input from its total number of inputs and the corresponding weight from the corresponding number of weights, simultaneously with the other modules of the interface subset, to calculate a weighted output. Therefore, since the logic circuitry required for a bitwise serial multiplier is much smaller than that for a bitwise parallel multiplier, all the necessary multipliers can be implemented on the same chip of the processing unit, thereby enabling high-speed parallel processing of all inputs.

[0046] As shown in Figure 3, the processing unit may further include an output subset 380 of module 360. The output subset of a module may be configured to receive one or more outputs of the module subset and to process the received one or more outputs. The output subset 380 may include one module 360. The output module is configured to receive the output of the Nth subset N of the module and to process the received output. Processing the received output of the Nth module subset may include bit serial processing of the received output, or partial bit serial processing of the received output and LSB-first processing. Partial bit serial and LSB-first processing of the received output may include performing a serial-to-parallel conversion on the received output to generate a converted output in parallel format. Partial bit serial and LSB-first processing of the received output may include performing one or more operations on the converted output to calculate the result, and performing a parallel-to-serial conversion on the result to generate the output of the output module.

[0047] One or more operations may include applying one or more activation functions to one or more transformed outputs. The one or more activation functions may include one or more of the following: binary step function, linear function, sigmoid function, tanh function, normalized linear function, ReLU, leaky ReLU, parameterized ReLU, exponential linear function, swish function, unit impulse function, carry function, One function, modulo function, 1 / n function, and Softmax function.

[0048] One or more activation functions may be implemented using fixed lookup tables (LUTs) and / or programmable LUTs. The control logic (620) included in the processing unit is configured to select either a fixed LUT or a programmable LUT to apply to one or more converted outputs and to calculate the result.

[0049] Modules 340 and 120 in each module subset 340, 1, 2, 3, ..., N may be configured to send a start bit to the corresponding module in each subsequent module subset 1, 2, 3, ..., N, 380, simultaneously with the other modules in the subset. The start bit may be sent simultaneously to the corresponding module in a first period preceding a second period. The second period may be a period in which the least significant bit (LSB) of each total number input is sent simultaneously to the corresponding module in each subsequent module subset for processing. The start bit indicates the start of processing of each total number input by the module subset. Each input of each total number input received by the module subset may be represented using M bits. The period may include one or more clock cycles.

[0050] According to any of the embodiments described above, each module subset 340, 1, 2, 3, ..., N, 380 may be further configured to transmit an input synchronization signal to its respective subsequent module subset to identify a first period during which a start bit is simultaneously transmitted to the corresponding module in each subsequent module subset. The input synchronization signal of the module interface subset is received from an output module subset of a preceding or other processing unit, or from a bus. The simultaneously transmitted start bit may be activated or turned ON during the first period in which the input synchronization signal is active or ON, thereby clearing any overflow or carry within the module subset. The input synchronization signal may be deactivated or turned OFF after the first period. This shortens the carry chain and reduces both the logic load and the wiring load. It also enables higher clock frequencies. The logic circuit implementing this overflow or carry clear logic is described below with reference to Figure 5.

[0051] According to any of the embodiments described above, each module subset may be configured to synchronize the outputs of the module subset based on an output synchronization signal. The output synchronization signal may be active in a third period following a second period. The second period may be the period during which the modules of the module subset process the LSB of each total number of inputs, as described above. The time at which the third period begins is a function of the time required for module subsets 340, 1, 2, 3, ..., N, 380 to process each total number of inputs. The time required for a module interface subset to process each total number of inputs is an integer multiple of a clock cycle. The time required for module interface subset 340 to process each total number of inputs may be different from the time required for any of the first to Nth subsets of the module 1, 2, 3, ..., N to process each total number of inputs. The time required for a module output subset 380 to process one or more outputs of a module subset may be different from the time required for other module subsets in the processing unit to process them.

[0052] According to any of the embodiments described above, each module 120 in the first to N subsets of the module subset may be further configured to process the input of a first number by performing one or more operations on the input of a first number. One or more operations may include, in a second period (following a first period in which the start bit is received), simultaneously receiving the bits of each input of the first number input, starting from the LSB. One or more operations may further include, in a third period following the aforementioned second period, performing an addition operation on the received bits to calculate an output, and in a third period following the second period, simultaneously receiving the subsequent bits of each input of the first number input. If a carry occurs in the addition operation, the carry is added to the bits received in the fourth period following the third period to calculate an output. If the bit received in a particular period is the start bit and the input synchronization signal is active or ON during that particular period, the carry is cleared using carry clear logic. The carry clear logic may be implemented as described with reference to Figures 4 and 5.

[0053] Each module subset according to any of the embodiments described above may be configured to synchronize the outputs of the module subset based on an output synchronization signal. The output synchronization signal is active in a third period following a second period. The time at which the third period begins is a function of the time required for each module subset to process its respective total number of inputs. The time required for a module interface subset to process its respective total number of inputs and compute a weighted output may differ from the time required for other module subsets in the processing unit. Similarly, the time required for an output module subset to process one or more outputs of the module subset and compute a processing unit output may differ from the time required for other subsets in the processing unit. This is because the module output subset arranges a series-parallel converter to convert the received one or more outputs into a parallel format, applies one or more activation functions as described above to the converted one or more outputs to generate a result, and converts the generated result back into a bit-serial format using a parallel-serial converter.

[0054] The output subset 380 of module 360 ​​of processing unit 300 may be configured to synchronize its output with one or more inputs of one or more interface modules 340 associated with one or more subsequent processing units 300 using an input synchronization signal. Alternatively, the input synchronization signal may be transmitted from the bus to one or more interface modules 340 associated with one or more subsequent processing units 300. The output subset of the module subset is transmitted as input to one or more corresponding interface modules 340 associated with one or more subsequent processing units 300, in bit-series and LSB-first. One or more subsequent processing units may be located in subsequent layers of the computing network. The processing units may be MIMD processing units. Each processing unit may be configured to perform discontinuous processing in the processing network. The processing units may be implemented using application-specific integrated circuits (ASICs). These ASICs can replace FPGAs, CPUs, and GPUs.

[0055] Figure 4 shows an example of synchronization of module 120 of any subset of the first to N module subsets according to an embodiment. In this example, a binary representation of numbers is used. The number of first inputs received by any module is 2. In Figure 4, the inputs are shown as x0 and x1. Each input may be an operand. Each input is represented by M bits. The M bits are processed LSB first.

[0056] Figure 4 shows Sync x iThe input synchronization signal, indicated as such, is transmitted from the preceding module subset or control logic and identifies a first period. During the first period, a start bit is simultaneously transmitted to the corresponding module in each subsequent module subset, including the module that processes the illustrated inputs x0 and x1. This first period is shown in Figure 4 as the period corresponding to clock cycle 0. The simultaneously transmitted start bit is activated or turned ON during the first period when the input synchronization signal is active or ON, thereby clearing any overflow or carry within the module subset. This shortens the carry chain and reduces both the logic load and the wiring load. A logic circuit implementing this carry clear logic is shown in Figure 5.

[0057] Each module in the module subset may be configured to process the input of a first number by performing one or more operations on the input of the first number. One or more operations may include, in a second period (corresponding to clock cycle 1 in Figure 4), starting from the LSB and simultaneously receiving the bits of each input of the input of the first number.

[0058] One or more operations may further include, in a third period following the second period described above (corresponding to clock cycle 2 in Figure 4), performing an addition operation on the received bits to calculate the output, and in a third period following the second period, simultaneously receiving the subsequent bits of each input of the first number.

[0059] One or more operations may further include determining whether the addition operation generates a carry, and if the addition operation generates a carry, in the fourth period following the third period (corresponding to, for example, clock cycle 3 in Figure 5), adding the carry to the bits received in the fourth period and calculating the output. This process involves a new start bit and the input synchronization signal x i This process continues in the same manner during the next period (clock cycles 4 to 16) until the module receives a new start bit and input sync signal Sync x. iWhen the module receives the new start bit and the input synchronization signal Sync x, one or more of the above operations are repeated. i When the module receives the data, any remaining carries or overflows within the module are cleared, as described above. This shortens the carry chain, reducing both the logic load and the wiring load.

[0060] The proposed bit-series architecture differs from conventional bit-parallel architectures in that it allows for the simultaneous and distributed processing of all inputs or operands in multiplication and addition, thereby compensating for the additional clock cycles required. This is achieved by an interface subset that simultaneously receives all of each total number of inputs or operands in LSB-first, processes all of each total number of input bits simultaneously in LSB-first (multiplying by the corresponding weights) to calculate a weighted output, and simultaneously transmits the generated weighted output as an input to be processed (simultaneously added) by each subsequent module connected in series, while simultaneously receiving and processing all of each new total number of bits to calculate a new weighted output. Existing bit-parallel architectures cannot process all inputs or operands simultaneously. These architectures are limited to processing only two inputs or operands simultaneously per clock cycle. In bit-parallel architectures, bits belonging to two operands are processed in one clock cycle. The duration of the carry transmission determines the maximum clock frequency. In the proposed bit serial processing, while M bits belonging to the same input or operand are transmitted in M ​​clock cycles, the processing is distributed, multiplication and addition occur simultaneously, and processing begins as soon as the LSB of the input or operand is received. The start of the input or operand is marked by an additional start bit prior to the LSB. This start bit is active while the input synchronization signal is active. This shortens the carry chain, reduces both logic and wiring loads, and enables higher clock frequencies. All of this compensates for the additional clock cycles required to process all M bits of the input or operand.

[0061] Figure 5 shows a module with carry-clear logic according to one embodiment. Module 120 of any of the first to N module subsets 1, 2, 3, ..., N according to any of the embodiments described above includes carry-clear logic and may be implemented as described with reference to Figure 5. In this embodiment, the first number of inputs received by the module is 2. This is shown by the two inputs x0 and x1 in Figure 5. The module includes a full adder 520, an AND gate 540, and two D flip-flops. The module is configured to process the two inputs by performing one or more operations. One or more operations include receiving each bit of the two inputs sequentially from the LSB simultaneously by the full adder 520, and performing an addition operation on the bits received by the full adder 520 to calculate the sum. If the addition operation generates a carry c_out, the carry is added by the full adder to the next bit received in a subsequent addition operation.

[0062] As shown in Figure 5, the output sum S of the full adder becomes the input to the D flip-flop 560. The output Q of the D flip-flop is the output of the module. The output carry c_out constitutes the input to the logic circuit 540. Synchronization signal Sync x i This signal is first inverted by a NOT gate and then input to logic circuit 540. Logic circuit 540 may also be an AND gate. The output of logic circuit 540 becomes input D of D flip-flop 560. The output Q of D flip-flop is supplied to the carry input c_in of the full adder. If the output carry is active or ON and the synchronization signal is inactive or OFF, the output generated by logic circuit 540 is active or ON. The output of this logic circuit is input to D flip-flop 560. Therefore, the output Q of the D flip-flop corresponding to the carry becomes active or ON, and the carry is supplied to the carry input c_in of the full adder and added to the bits received in the next period. The next period may be the subsequent clock cycle.

[0063] Output carry is active or ON, and sync signal Sync x i If is also active or ON (indicating that either of the two receiving inputs x0 or x1 is the start bit), the output generated by logic circuit 540 is deactivated or OFF. The output of this logic circuit is fed into D flip-flop 560. Thus, the output Q of the D flip-flop is deactivated or OFF, thereby clearing any overflow or carry present in the module. This shortens the carry chain, reducing both the logic design and routing loads and enabling higher clock frequencies.

[0064] Figure 6 shows a processing unit illustrating the flow of synchronization signals according to an embodiment. The embodiment described above with reference to Figure 3 may be implemented as described with reference to Figure 6. Figure 6 shows a processing unit 600 including an interface subset 340 of module 320, two module subsets 1 and 2, an output subset 380 including module 360, and control logic 620, along with the flow of synchronization signals entering and leaving each subset. The interface subset 340 includes four modules 320 configured to receive four inputs (X0, X1, X2, X3) with a total number of inputs and weights (W0, W1, W2, W3) corresponding to the total number of inputs, and to calculate a weighted output.

[0065] The four inputs received by the module interface subset of the processing unit 600 may be the outputs of four processing units included in the front layer of the computing network, or they may be the outputs of four parallel-serial converters 720. The corresponding number of weights (W0, W1, W2, W3) are provided by the control logic 620.

[0066] Each of the total number of inputs received by the module's interface subset is the input synchronization signal Sync x iIt may be synchronized by Sync x. The input synchronization signal is shown in the graph at the top of each module subset. In this graph, the lower signal represents the clock signal, and the middle signal represents the input synchronization signal Sync x. i The upper signal represents the input, which is represented by 16 bits. The upper signal also indicates an additional bit (start bit) that precedes the LSB bit b0 of the input. Each input may also be an operand. Each of the four inputs (X0, X1, X2, X3) is represented by 16 bits. Each of the four weights (W0, W1, W2, W3) is represented by 16 bits.

[0067] Input synchronization signals for the module interface subset 340 are received from each of the total number of processing units 300 included in the preceding layer of the processing network, or from each of the total number of parallel-serial converters 720, or from the bus, as shown for interface subset 340. Input synchronization signals for the first to Nth module subsets and the output module subset may be received from preceding module subsets or control logic, as shown in Figure 6.

[0068] The interface subset 340 of module 320 is configured to receive four inputs (X0, X1, X2, X3) bitwise in series and LSB-first, and four corresponding weights (W0, W1, W2, W3) bitwise in parallel or bitwise in series and LSB-first. If the four corresponding weights are received in series, a parallel-serial converter is used to convert the series-serial format. Each module 320 in the module's interface subset may be configured to transmit its weighted output bitwise in series and LSB-first as input to the corresponding module in its subsequent module subset. Each subsequent module subset is the first subset 1 of the module.

[0069] Each module 320 of the four modules in the interface subset 340 of the module subset may be configured, simultaneously with the other modules of the interface subset, to compute a weighted output by multiplying the input bits of the four inputs (X0, X1, X2, X3) by one of the four corresponding weights (W0, W1, W2, W3), starting from the LSB. The weighted output is sent to the subsequent module subset, while the new input bits from the four inputs are received and processed by the interface subset. The weighted output is received and added by module 120 of the subsequent module subset.

[0070] The processing unit 600 may include an output subset 380 of module 360 ​​configured to receive and process the output of the Nth subset, where N is equal to 2. Processing the received output of the Nth or 2nd subset of the module includes bitwise serial and LSB-first processing of the received output, or partial bitwise serial and LSB-first processing. Partial bitwise serial and LSB-first processing of the received output may include performing a serial-to-parallel conversion on the received output to produce a converted output in parallel form. Partial bitwise serial and LSB-first processing of the received output may include performing one or more operations on the converted output to compute the result, and performing a parallel-to-serial conversion on the result to produce the output of the output module subset, which is the output of the processing unit. One or more operations performed on the converted output may include applying one or more activation functions to the converted output, as described above.

[0071] The time required for the output module subset to process the output of the second module subset and compute the processing unit output includes the time required to transform the received output and generate a transformed output in parallel format, the time required to apply one or more activation functions to the transformed output as described above to generate the result, and the time required to convert the generated result back to bit serial format using a parallel-serial converter.

[0072] As can be seen by comparing the graph showing output O of the output subset shown in Figure 6 with the graph showing the Nth or second module subset, the time required for the output module subset to process a 16-bit input is 18 clock cycles. The output module subset according to any of the embodiments described above may be configured to accommodate longer or shorter delays depending on the implementation or application. However, within a given implementation, the delay is always kept constant.

[0073] As shown in Figure 6, modules 340 and 120 in module subsets 340, 1, and 2 may further be configured to transmit a start bit to the corresponding module in their respective subsequent module subsets 1, 2, and 380, simultaneously with the other modules in their module subsets. The start bit may be transmitted simultaneously to the corresponding module in a first period preceding a second period. The second period is a period in which the least significant bit of each total number input is transmitted simultaneously to the corresponding module in each subsequent module subset. Each of the total number inputs may be represented using M bits, without including a start bit. The start bit is an additional bit that indicates the start of processing of each total number input by the module subset. The period may include one or more clock periods.

[0074] According to any of the embodiments described above, an input or operand of a module subset does not need to immediately follow another input or operand based on the input synchronization signal. In other words, the input synchronization signal may be transmitted to and / or received by the module subset immediately after a number of clock cycles equal to the number of bits representing the input or operand has elapsed. In Figure 6, this number of clock cycles is 17. Alternatively, the input synchronization signal may be transmitted to and / or received by the module subset after more clock cycles (more than the number of bits representing the input), or it may be stopped or not transmitted at all. This enables discontinuous processing, which is an essential feature of the digital signal processing design of the processing unit.

[0075] As described above, each module subset may be configured to synchronize the output of the module subset based on an output synchronization signal. Each module 120 of module subsets 1 and 2 shown in Figure 6 may be configured to process the input of the first number (2) by performing one or more operations on the input of the first number (2), as described above.

[0076] According to any of the embodiments described above, each module subset 340, 1, 2 may be further configured to transmit an input synchronization signal to its respective subsequent module subset to identify a first period during which start bits are simultaneously transmitted to the corresponding modules of each subsequent module subset. The input synchronization signal of the module interface subset may be transmitted from the output module subset of the preceding processing unit or from the bus.

[0077] The output subset 380 of module 360 according to any of the foregoing embodiments may be configured to synchronize its output O with one or more respective inputs of one or more respective interface modules 340 associated with one or more subsequent processing units 300 using an input synchronization signal. The input synchronization signal sync of the output module subset is the input synchronization signal Sync x of one or more respective interface subsets of module 340 i and becomes. Alternatively, the input synchronization signal may be transmitted from the bus to one or more respective interface subsets of module 340.

[0078] The output O of the output module subset may be transmitted as an input to one or more respective interface module subnets 340 associated with one or more subsequent processing units 300 in bit-serial and LSB-first. One or more subsequent processing units may be included in a subsequent layer of the computing network. Processing unit 600 may be a MIMD processing unit. Processing unit 600 may be implemented using application-specific integrated circuits ASICs. These ASICs may replace FPGAs, CPUs, and GPUs.

[0079] Figure 7 shows a combination of processing units 300 implementing a processing network according to an embodiment. The processing network in Figure 7 may be used to implement an artificial neural network. The processing network may be used to implement one or more string comparison functions. The processing network shown in Figure 7 includes five vertical layers. The leftmost vertical layer of the processing network is a converter layer containing eight parallel-serial converters 720. The first leftmost vertical layer following the leftmost vertical layer may be the input layer of the processing network, containing eight processing units 300. The rightmost vertical layer may be the output layer of the processing network, also containing eight processing units 300. The remaining two intermediate vertical layers may be hidden layers of the processing network. Each processing unit may correspond to a processing unit 300 based on the embodiments described with respect to Figures 3 to 6. The output of each output module subset of each processing unit in a layer may be connected to the respective inputs of each interface module subset of each processing unit in each subsequent layer in the processing network. Each processing unit in a given layer may be configured to synchronize its output with the connected inputs of the respective interface subsets of each processing unit in subsequent layers of the processing network, using an input synchronization signal. The input synchronization signal may be transmitted from a preceding processing unit, a preceding parallel-serial converter 720, or a bus. The output of each processing unit within a layer is transmitted LSB-first and becomes an input to the corresponding interface subset of each processing unit in subsequent layers of the processing network. The processing network may be configured to process data continuously or discontinuously. The processing units shown in Figure 7 may be implemented using application-specific integrated circuits (ASICs). These ASICs can replace FPGAs, CPUs, and GPUs.

[0080] Figure 8 is a flowchart of a method 800 for processing inputs received by a processing unit according to one embodiment. The processing unit may be a MIMD processing unit. The processing unit enables real-time MIMD processing of the inputs received in its interface module subset. This method begins in step 810, where the interface module subset of the processing unit receives each total number input and the corresponding number weights. Each total number input and the corresponding number weights may be received bitwise in serial and LSB-first.

[0081] In step 820, each module in the processing unit's interface module subset performs a bitwise serial multiplication operation between its input from the total number of inputs and the corresponding weight from the corresponding number of weights to compute a weighted output, while simultaneously step 810 is repeated.

[0082] In step 830, each module in the interface module subset, simultaneously with modules in other interface module subsets, sends its weighted output in bit-series and LSB-first as input to the corresponding module in the first module subset, while step 820 is repeated simultaneously.

[0083] In step 840, the first module subset processes the inputs transmitted simultaneously and calculates the corresponding outputs, while step 830 is repeated at the same time.

[0084] In step 850, the output of the first module subset is processed sequentially by subsequent module subsets, and the output is calculated by the Nth module subset. Meanwhile, step 840 is repeated.

[0085] In step 860, the output calculated by the Nth module subset is received by the output module subset. The output module subset applies one or more activation functions to the calculated output to generate the output of the processing unit. Meanwhile, step 850 is repeated.

[0086] Figure 9 is a flowchart of a method 900 for processing inputs received by a combination of processing units that implement a processing network according to an embodiment shown in Figure 7. The combined processing units enable a real-time MIMD implementation of the processing network. The method begins in step 910, where each interface module subset of each processing unit associated with the input layer of the processing network receives a corresponding total number of inputs from a parallel-series converter and a corresponding number of weights from control logic.

[0087] In step 920, each processing unit associated with the input layer of the processing network processes the total number of inputs and calculates an output, as described in Figures 3-6.

[0088] In step 930, the outputs of all processing units in the input layer are sent bitwise in serial and LSB-first to the respective interface subsets of each processing unit in the first hidden layer of the processing network. Meanwhile, step 920 is repeated.

[0089] In step 940, the processing unit of the first hidden layer processes the input received from the input layer and the corresponding number of weights received from the control logic, and calculates the corresponding output. Meanwhile, step 930 is repeated.

[0090] In step 950, the corresponding output of the first hidden layer is simultaneously transmitted as input to each interface subset of each processing unit in the second hidden layer of the processing network, bitwise serial and LSB-first. Meanwhile, step 940 is repeated.

[0091] In step 960, the processing unit of the second hidden layer processes the input received from the first hidden layer and the corresponding number of weights received from the control logic, and calculates the corresponding output. Meanwhile, step 950 is repeated.

[0092] In step 970, the corresponding output of the second hidden layer is sent as input to each interface subset of each processing unit in the output layer of the processing network. Meanwhile, step 960 is repeated.

[0093] In step 980, the output layer processing unit processes the input received from the second hidden layer and the respective number of weights received from the control logic to compute the corresponding output of the processing network. Meanwhile, step 970 is repeated.

[0094] The aforementioned specific embodiments and examples outline the invention but do not limit it. It should be understood that other embodiments of the invention may even be created, and that the aforementioned specific embodiments and examples are not exhaustive.

Claims

1. A processing unit comprising multiple modules, Each of the aforementioned plurality of modules is configured to receive a first number of inputs and calculate an output, The number of the first inputs is 2 or more. The aforementioned plurality of modules are divided into N module subsets, The N module subsets are connected in series from the first subset to the Nth subset. Each module subset is configured to process the respective total number of inputs received by the module subset. Each module in the aforementioned module subset is: In parallel with the other modules of the module subset, the first number of inputs is processed from the total number of inputs received by the module subset, and the output of the module is calculated. The output of the module is transmitted in parallel with the other modules of the module subset as input to each subsequent module subset connected in series. It is configured in such a way. Processing unit.

2. The first subset comprises a first number of modules equal to the value obtained by dividing the total number of inputs received by the first subset by the number of first inputs, The total number of inputs received by each subset is an integer multiple of the number of the first inputs. The processing unit according to claim 1.

3. The processing unit according to claim 1 or 2, wherein each subsequent module subset includes a number of modules equal to the number of outputs calculated by the module subset preceding the subsequent module subset divided by the number of first inputs.

4. The processing unit according to any one of claims 1 to 3, wherein the module of the module subset is configured to transmit the output in series bits and in order from the least significant bit to the corresponding module of each subsequent module subset.

5. The processing unit according to any one of claims 1 to 4, further comprising a subset of module interfaces configured to receive the total number of each input and a number of weights equal to the total number of each input, and to calculate a weighted output.

6. The subset of the interface comprises a number of modules equal to the total number of inputs received by the subset of the interface of the module, Each module of the subset of the interface is configured to receive each input of the respective total number and the corresponding weight of the corresponding number, and to calculate an output. The processing unit according to claim 5.

7. The processing unit according to claim 5 or 6, wherein each module in the subset of the interface of the module is configured to transmit the weighted output bitwise in series and sequentially from the least significant bit to the corresponding module in the first subset of the module as input.

8. The processing unit according to any one of claims 5 to 7, wherein a subset of the interface is configured to receive the respective total number of inputs bitwise in series and sequentially from the least significant bit, and to receive the corresponding number of weights bitwise in parallel or bitwise in series and sequentially from the least significant bit.

9. The processing unit according to any one of claims 5 to 8, wherein each module of the subset of the interface is configured to perform a bitwise serial multiplication operation between the input from the respective total number of inputs and the corresponding weight from the corresponding number of weights, simultaneously with the other modules of the subset of the interface, in order to calculate the weighted output.

10. Each module in the module subset is configured to transmit a start bit to the corresponding module in the respective subsequent module subset, simultaneously with the other modules in the module subset. The aforementioned start bit is transmitted simultaneously to the corresponding module during the first period preceding the second period. The second period is the period during which the least significant bit of each of the total number of inputs is simultaneously transmitted to the corresponding module of each subsequent module subset. The period includes one or more clock cycles. A processing unit according to any one of claims 1 to 9.

11. The processing unit according to claim 10, wherein each module subset is further configured to transmit an input synchronization signal to the respective subsequent module subset to identify the first period during which the start bit is simultaneously transmitted to the corresponding module of the respective subsequent module subset.

12. The processing unit according to claim 11, wherein the simultaneously transmitted start bit is active during the first period while the input synchronization signal is active, and overflows in the module subset are cleared.

13. Each module subset is configured to synchronize the output of the module subset based on an output synchronization signal. The output synchronization signal is active in the third period following the second period. The time at which the third period begins is a function of the time required for each of the module subsets to process the respective total number of inputs. A processing unit according to any one of claims 10 to 12.

14. Each module in the module subset is configured to process the input of the first number of inputs by performing one or more operations on the input of the first number of inputs, The above one or more operations are, Starting from the least significant bit, the bits of each input of the first input number are received simultaneously, The process involves performing addition, subtraction, multiplication, division, logical operations, or activation function operations on the received bits to calculate the output, Simultaneously, the following bits of each input of the first input number are received, including, A processing unit according to any one of claims 1 to 13.

15. The processing unit according to claim 14, wherein if the operation performed is an addition operation and the addition operation generates a carry, the carry is added to the subsequent bits.

16. The processing unit according to any one of claims 1 to 15, wherein the total number of inputs for each of the module subsets is evenly divided among the modules of the module subset, and the sum of the number of first inputs within the module subset is equal to the total number of inputs for each of the module subsets.

17. The processing unit according to any one of claims 1 to 16, further comprising an output module subset configured to receive one or more outputs of the module subset and to perform one or more operations on the received outputs to calculate the output of the processing unit.

18. The processing unit according to claim 17, wherein the one or more operations described above include applying one or more activation functions to the received output.

19. The processing unit according to claim 18, wherein the one or more activation functions include one or more of the following: binary step function, linear function, sigmoid function, tanh function, normalized linear function, ReLU, leaky ReLU, parameterized ReLU, exponential linear function, swish function, unit impulse function, carry function, One function, modulo function, 1 / n function, and Softmax function.

20. The processing unit according to claim 18 or 19, wherein the one or more activation functions are configured to be implemented using a fixed lookup table, a LUT, and a programmable LUT.

21. Further equipped with control logic, The control logic is configured to select either a fixed LUT or a programmable LUT to be applied to the one or more received outputs of the module subset. The processing unit according to claim 20.

22. The processing unit according to any one of claims 1 to 21, wherein each module subset is configured to process the respective total number of inputs bitwise in series and sequentially from the least significant bit, or partially in series and sequentially from the least significant bit.

23. Each processing unit is configured to perform discontinuous processing in the processing network, according to any one of claims 1 to 22.

24. The processing unit according to any one of claims 1 to 23, wherein each module of the module subset includes one or more arithmetic logic circuits, and the one or more arithmetic logic circuits include at least one of an adder, a subtractor, a multiplier, AND, OR, NAND, NOR, NOT, and XOR.

25. The processing unit according to claim 24, wherein each module of the module subset is configured to process the inputs of the first number of inputs by performing one or more operations on the inputs of the first number of inputs using the one or more arithmetic logic circuits of the module and calculating an output.

26. A processing method, The processing unit includes a step in which each subset of multiple modules receives its respective total number of inputs, The processing unit comprises a plurality of modules, which are divided into N module subsets. The module subsets are connected in series from the first subset to the Nth subset, Each module receives a first input and calculates an output. The number of the first inputs is 2 or more. The processing method includes the step of processing the respective total number of inputs received by each module subset included in the processing unit, Each module of the module subset processes the first number of inputs from the total number of inputs received by the module subset in parallel with the other modules of the module subset, and calculates the output of the module. The output of the module is transmitted in parallel with the other modules of the module subset as an input to each subsequent module subset connected in series. Processing method.

27. The first subset comprises a first number of modules equal to the value obtained by dividing the total number of inputs received by the first subset by the number of first inputs, The total number of inputs received by each subset is a multiple of the number of the first inputs. The processing method according to claim 26.

28. The processing method according to claim 26 or 27, wherein each subsequent module subset includes a number of subsequent modules equal to the number of outputs calculated by the preceding module subset divided by the number of first inputs.

29. The processing method according to any one of claims 26 to 28, further comprising the step of each module of the module subset transmitting the output bitwise in series and in order from the least significant bit to the corresponding module of the respective subsequent module subset.

30. The processing method according to any one of claims 26 to 29, wherein each module subset included in the processing unit processes each of the total number of inputs received by each module subset, the step of processing each of the total number of inputs bitwise in series and from the least significant bit, or processing each of the total number of inputs partially bitwise in series and from the least significant bit.

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