Three-dimensional NOR memory array of thin-film ferroelectric memory transistors performing partial polarization

Abstract

This disclosure provides a memory device including a NOR memory string and a method of operating the same. The memory device of this disclosure implements partial polarization to provide a reference signal for read operations. The reference signal realizes a third logic state in a ferroelectric memory transistor that is distinguishable from a first logic state and a second logic state (e.g., a logic state associated with a write state and an erase state). The memory device of this disclosure provides a reference signal for read operations by averaging a first signal associated with the write state and a second signal associated with the erase state of the ferroelectric memory transistor. The memory device of this disclosure also provides a multilevel memory cell that stores multiple logic bits in each memory cell by implementing one or more partial polarization states.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a method of operating the same. More specifically, the present invention relates to a three-dimensional memory array of thin-film ferroelectric memory transistors that perform partial polarization to provide additional polarization states that can be applied for use as a reference signal or additional data bits. [Background technology]

[0002] High-density memory arrays, such as a three-dimensional array of NOR-type memory strings ("three-dimensional NOR-type memory array"), are disclosed, for example, in U.S. Patent No. 10,121,553 (Patent Document 1), filed on 26 August 2016 and issued on 6 November 2018, entitled "Capacitively Coupled Non-Volatile Thin-Film Transistor NOR String in a Three-Dimensional Array." The entire disclosure of Patent Document 1 is incorporated herein by reference for any purpose. The storage transistors or memory transistors of Patent Document 1 are configured as a three-dimensional array of NOR-type memory strings formed on the upper side of a semiconductor substrate plane. The NOR memory string disclosed in Patent Document 1 comprises a number of thin-film storage transistors that share a common bit line and a common source line. In one embodiment, the storage transistors in the NOR memory string are arranged along a direction substantially parallel to the plane of the semiconductor substrate ("horizontal direction"). In such a three-dimensional array, NOR memory strings are arranged on multiple planes (e.g., eight or sixteen planes) on a semiconductor substrate, and the NOR memory strings on each plane are arranged in a matrix along two mutually orthogonal horizontal directions. Data is stored in the charge trap layer of each storage transistor (e.g., a triple layer of silicon oxide-silicon nitride-silicon oxide). Each storage transistor in a NOR memory string is read, written, or erased by appropriately biasing the word line connected to it and a common bit line shared with other storage transistors in the NOR memory string.

[0003] Such a three-dimensional NOR-type memory array, in addition to providing high memory density and capacity, can provide a memory circuit with a highly desirable speed comparable to conventional memory circuits, such as dynamic random access memory ("DRAM"), which have much lower circuit density and significantly higher power consumption. Furthermore, the memory circuit of Patent Document 1 is also called "quasi-volatile memory" or "QV memory." Each memory cell of QV memory stores data bits as charge in a charge storage material (e.g., ONO), similar to the memory cells of non-volatile memory (NVM). Due to the properties of the charge storage layer, typical QV memory cells have a much longer data retention time than DRAM cells, and therefore a lower refresh rate than DRAM cells. For example, a typical DRAM system is designed to refresh every 64 milliseconds, while a QV memory with equivalent effective access performance only needs to refresh every 10 minutes. This reduction in refresh rate provides QV memory with significant advantages, such as reduced power consumption, reduced heat dissipation, and improved memory availability, thereby improving host performance.

[0004] Advances in electrically polarizable materials ("ferroelectric materials"), particularly those used in semiconductor manufacturing processes, suggest new potential applications in ferroelectric memory circuits. A high-density memory array realized using a three-dimensional array of NOR memory strings of ferroelectric memory transistors is disclosed, for example, in U.S. Patent Application No. 17 / 936,320 (Patent Document 2), filed September 28, 2022, entitled "Memory Structure Including a Three-Dimensional NOR Memory String of a Junctionless Ferroelectric Memory Transistor and Method for Manufacturing the Same." The entire disclosure of Patent Document 2 is incorporated herein by reference for all purposes. Patent Document 2 describes a memory structure comprising randomly accessible ferroelectric memory transistors configured as horizontal NOR memory strings. The ferroelectric memory transistors include a polarizable ferroelectric material as a gate dielectric layer. The NOR memory strings are formed on a semiconductor substrate within a plurality of scalable memory stacks of thin-film memory transistors. In some examples, this three-dimensional memory stack is manufactured using a method that includes the steps of forming operational trenches for vertical local word lines and forming auxiliary trenches by back-side selective etching to facilitate back-array metal replacement and channel isolation. A three-dimensional array of NOR-type memory strings of thin-film ferroelectric transistors is disclosed, for example, in U.S. Patent Application No. 17 / 812,375, “Three-Dimensional Memory String Array of Thin-Film Ferroelectric Transistors” (Patent Document 3), filed July 13, 2022. The entire disclosure of Patent Document 3 is incorporated herein by reference.

[0005] The performance of a memory device can be improved by optimizing various modes of read, write, or erase operations for NOR memory strings. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] U.S. Patent No. 10,121,553 [Patent Document 2] U.S. Patent Application No. 17 / 936,320 [Patent Document 3] U.S. Patent Application No. 17 / 812,375 [Overview of the Initiative] [Means for solving the problem]

[0007] This disclosure provides a memory device and a method of operating the same, including a three-dimensional array of NOR memory strings of junctionless ferroelectric memory transistors. This disclosure is substantially described with reference to, for example, at least one figure and is more fully described in the claims.

[0008] In some embodiments of the present disclosure, a memory device is provided. The memory device of the present disclosure is an array of memory strings, each memory string comprising a thin-film ferroelectric memory transistor having a drain terminal connected to a common bit line, a source terminal connected to a common source line, and a gate terminal connected to a corresponding word line, wherein each ferroelectric memory transistor in a plurality of memory strings vertically aligned in the array is connected to a common word line, and each ferroelectric memory transistor comprises a ferroelectric gate dielectric layer that is polarizable in response to the application of a bias voltage to the drain terminal, source terminal, and gate terminal. The ferroelectric memory transistor provides the ferroelectric gate dielectric layer with a first polarization state associated with a first threshold voltage value in response to being driven by a first set of bias voltages, and provides the ferroelectric gate dielectric layer with a second polarization state associated with a second threshold voltage value greater than the first threshold voltage value in response to being driven by a second set of bias voltages. At least one memory transistor in a first memory string is designated as a reference memory transistor, which, in response to being driven by a third set of bias voltages, provides the ferroelectric gate dielectric layer of the reference memory transistor with a third polarization state associated with a third threshold voltage value between a first threshold voltage value and a second threshold voltage value, and having a polarization level between a first polarization state and a second polarization state.

[0009] Another embodiment of the present disclosure provides a method for retrieving data in a memory device. The memory device is implemented as an array of memory strings of ferroelectric memory transistors ("memory cells"). Each memory string includes a thin-film ferroelectric memory transistor having a drain terminal connected to a common bit line, a source terminal connected to a common source line, and a gate terminal connected to a corresponding word line, each ferroelectric memory transistor including a ferroelectric gate dielectric layer that is polarizable in response to the application of a bias voltage to the drain terminal, source terminal, and gate terminal. The method of the present disclosure includes the steps of: biasing one or more ferroelectric memory transistors using a first set of bias voltages to provide a first polarization state in the ferroelectric gate dielectric layer associated with a first threshold voltage value; biasing one or more ferroelectric memory transistors using a second set of bias voltages to provide a second polarization state in the ferroelectric gate dielectric layer associated with a second threshold voltage value greater than the first threshold voltage value; designating at least one ferroelectric memory transistor in a first memory string as a reference memory transistor; and biasing the reference memory transistor using a third set of bias voltages to provide a third polarization state in the ferroelectric gate dielectric layer of the reference memory transistor having a polarization level between the first polarization state and the second polarization state, associated with a third threshold voltage value between the first threshold voltage value and the second threshold voltage value.

[0010] In yet another embodiment of the present disclosure, a memory device is provided. The memory device of the present disclosure is an array of memory strings, each memory string comprising a thin-film ferroelectric memory transistor having a drain terminal connected to a common bit line, a source terminal connected to a common source line, and a gate terminal connected to a corresponding word line, wherein each ferroelectric memory transistor in a plurality of memory strings vertically aligned in the array is connected to a common word line, and each ferroelectric memory transistor comprises a ferroelectric gate dielectric layer that is polarizable in response to the application of bias voltages to the drain terminal, source terminal, and gate terminal. The ferroelectric memory transistor is driven by a first set of bias voltages to provide the ferroelectric gate dielectric layer with a first polarization state associated with a first threshold voltage value, and is driven by a second set of bias voltages to provide the ferroelectric gate dielectric layer with a second polarization state associated with a second threshold voltage value greater than the first threshold voltage value. A first ferroelectric memory transistor in the array is designated as the first reference memory transistor, and a second ferroelectric memory transistor in the array is designated as the second reference memory transistor. The first reference memory transistor is driven to a first polarization state by the bias voltage of the first set, and the second reference memory transistor is driven to a second polarization state by the bias voltage of the second set. A bit line signal indicating the first polarization state of the first reference memory transistor and a bit line signal indicating the second polarization state of the second reference memory transistor are combined to generate a reference signal for reading memory data stored in the ferroelectric memory transistors and determining the logical state of that memory data.

[0011] In other embodiments of the present invention, the reference polarization state in a reference memory transistor can be polarized in response to the application of a bias voltage from the drain terminal to the gate terminal of the ferroelectric memory transistor, which is different from the bias voltage from the source terminal to the gate terminal of the ferroelectric memory transistor. The difference in bias voltage can be realized as a difference in the applied voltage value or a difference in the duration of the applied bias voltage. In this way, multiple reproducible polarization states can be established in the same ferroelectric memory transistor, thereby enabling the construction of a ferroelectric multilevel cell. In some embodiments, the polarizable states can be formed as a continuous ferroelectric analog memory cell.

[0012] In another embodiment, a dual-bit ferroelectric memory cell is formed by applying a first bias voltage from the drain terminal to the gate terminal and a second bias voltage different from the first bias voltage from the source terminal to the gate terminal. This makes it possible to form two distinctly different polarization states within the memory cell, namely a first polarization state at the drain terminal of the memory cell and a second polarization state at the source terminal of the memory cell. Two-bit readout from the same memory cell can be performed in two steps, for example, by first reading from the source terminal to the drain terminal, then inverting and reading from the drain terminal to the source terminal, thereby detecting the polarization of the ferroelectric layer adjacent to the drain terminal, and then detecting the polarization of the ferroelectric layer adjacent to the source terminal. In this specification, reading from the source terminal to the drain terminal means detecting the cell current flowing from the source terminal to the drain terminal by biasing the source terminal of the memory transistor, and reading from the drain terminal to the source terminal means detecting the cell current flowing from the drain terminal to the source terminal by biasing the drain terminal of the memory transistor.

[0013] In embodiments of the present invention, the reference signal scheme is described as providing a reference signal for read operations in a three-dimensional memory array of ferroelectric memory transistors. The reference signal scheme can be readily applied to a two-dimensional memory array to provide a reference signal for read operations. For example, the reference signal scheme of this disclosure can be applied to a planar array of ferroelectric memory cells, including memory transistors built on a memory substrate.

[0014] The above and other advantages, aspects and novel features of the present invention, as well as details of the exemplary embodiments thereof, will be better understood by referring to the following description and accompanying drawings. [Brief explanation of the drawing]

[0015] Various embodiments of the present invention are disclosed in the following detailed description and accompanying drawings. While the drawings depict various embodiments of the present invention, the present invention is not limited to the embodiments depicted. It should be understood that in the drawings, similar reference numerals indicate similar structural elements. Furthermore, it should be understood that the depictions in the drawings are not necessarily drawn to a fixed scale.

[0016] [Figure 1] Figure 1 is a schematic diagram of a memory device including a three-dimensional array of NOR-type memory strings according to an embodiment of the present disclosure. [Figure 2] Figure 2 is a schematic diagram showing exemplary support circuits connected to the bit lines of the NOR type memory string of the memory device of Figure 1 in an embodiment of the present disclosure. [Figure 3] Figure 3 is a perspective view of a memory device showing an array of NOR-type memory strings in a three-dimensional array in several embodiments. [Figure 4] Figure 4 shows configurations for locating a reference memory transistor within a reference plane in several embodiments. [Figure 5]Figure 5 shows configurations for providing a reference memory transistor within a reference stack in several embodiments. [Figure 6] Figure 6 shows configurations for providing a reference memory transistor within a reference slice in several embodiments. [Figure 7] Figure 7 is a schematic diagram of a memory array including a memory stack of NOR-type memory strings in an embodiment of the present disclosure. [Figure 8] Figures 8(a) and 8(b) are timing diagrams showing the voltage and timing conditions for executing erase and program operations in order to realize positive and negative polarization states in the memory transistors of a memory device in an embodiment of the present disclosure. [Figure 9] Figures 9(a) and (b) are timing diagrams showing the voltage and timing conditions for performing a partial polarization operation to realize a partial polarization state in the reference memory transistor of the memory device in an embodiment of the present disclosure. [Figure 10] Figures 10(a) and (b) are timing diagrams showing the voltage and timing conditions for performing a partial polarization operation to realize a partial polarization state in a reference memory transistor of a memory device in another embodiment of the present disclosure. [Figure 11] Figures 11(a) and (b) are timing diagrams showing the voltage and timing conditions for performing a partial polarization operation to realize a partial polarization state in a reference memory transistor of a memory device in another embodiment of the present disclosure. [Figure 12] Figures 12(a) and (b) are timing diagrams showing the voltage and timing conditions for performing a partial polarization operation to realize a partial polarization state in a reference memory transistor of a memory device in another embodiment of the present disclosure. [Figure 13] Figures 13(a) and (b) are timing diagrams showing the voltage and timing conditions for performing a partial polarization operation to realize a partial polarization state in a reference memory transistor of a memory device in another embodiment of the present disclosure. [Figure 14] Figure 14 shows an exemplary threshold voltage distribution in a memory device, illustrating three polarization states in several embodiments. [Figure 15A] Figure 15A is a plot showing the generation of bit line signals during readout operations in several embodiments. [Figure 15B] Figure 15B is a plot showing the operation of a sense amplifier using a reference cell reference signal to determine the latch time of the sense amplifier output signal in several embodiments. [Figure 16] Figure 16 is a schematic diagram of a sense amplifier circuit in which a reference signal is used as a sense amplifier latch signal in several embodiments. [Figure 17] Figure 17 is a schematic diagram of a sense amplifier circuit, including a differential sense amplifier that uses a reference signal as a sense amplifier reference, in several embodiments. [Figure 18A] Figure 18A is a schematic diagram of a memory circuit in an embodiment of the present disclosure, which includes a reference memory transistor in a reference slice. [Figure 18B] Figure 18B is a timing diagram showing a sequential reading method in an embodiment of the present disclosure. [Figure 19A] Figure 19A is a plot showing the generation of a reference signal for readout operation using an averaging method in several embodiments. [Figure 19B] Figure 19B is a schematic diagram showing the implementation of the averaging scheme in several embodiments. [Figure 20] Figure 20 is a cross-sectional view of a pair of ferroelectric memory transistors that can be used in some embodiments to form memory transistors in the memory arrays of Figures 1 and 7. [Modes for carrying out the invention]

[0017] In embodiments of the present disclosure, a semiconductor memory device including a three-dimensional array of NOR-type memory strings of thin-film ferroelectric memory transistors implements a partial polarization scheme to provide a reference signal for improving read operation. In some embodiments, the partial polarization scheme is implemented to reduce the memory window in the ferroelectric memory transistor, thereby reducing electrical stress on the ferroelectric memory transistor and improving the erase and write endurance cycle of the memory transistor. In some other embodiments, the partial polarization scheme is implemented to realize a multi-bit ferroelectric memory transistor configured to store two or more binary memory bits in each ferroelectric memory transistor. That is, by using the partial polarization scheme of the present disclosure, each ferroelectric memory transistor can be configured to store two or more writable memory states, thereby allowing 1.5 bits, 2.0 bits, or more bits to be stored in each memory transistor.

[0018] In a first aspect of this disclosure, a partial polarization scheme is applied to provide a reference signal (also referred to herein as a reference bit line signal or reference source line signal). This reference signal realizes a third logic state in a ferroelectric memory transistor that is distinguishable from a first logic state and a second logic state (e.g., logic states associated with the write and erase states of a ferroelectric memory transistor in normal single-bit memory operation). In some embodiments, the reference bit line signal is generated by partially polarizing (i.e., partially writing or partially erasing) one or more ferroelectric memory transistors designated as reference memory transistors. This partial polarization can be achieved, for example, by changing the write voltage or erase voltage applied to achieve fully positive and fully negative polarization states in normal single-bit memory operation. Alternatively, this partial polarization can be achieved, for example, by changing the write time or erase time used to achieve fully positive and fully negative polarization states in normal single-bit memory operation. In embodiments of this disclosure, partial polarization is achieved by setting the polarization level of the ferroelectric dielectric layer of the ferroelectric memory transistor to a polarization level between the polarization level of the ferroelectric memory transistor in the write state and the polarization level of the ferroelectric memory transistor in the erase state.

[0019] With this configuration, the partial polarization state of the writable reference memory transistor is normally maintained as long as the fully written and fully erased states of the memory transistor are maintained. If the write and erase polarization states shift due to, for example, an increase in ambient temperature, the reference memory transistor also shifts accordingly, thereby enabling the reading of the correct write and erase states from the memory array. In all embodiments of this disclosure, the ferroelectric reference memory transistor can be periodically refreshed, for example, every few minutes or hours, to maintain a reference voltage threshold with respect to the written or erased threshold voltage values.

[0020] It should be noted that the partial polarization scheme of this disclosure allows any one or more ferroelectric memory transistors in a three-dimensional array of NOR-type memory strings to be designated as one or more reference memory transistors. That is, the reference memory transistors are implemented using the same thin-film ferroelectric memory transistors used for data storage. No additional processing or different materials are required to provide the reference memory transistors.

[0021] According to another aspect of the present disclosure, a semiconductor memory device including a three-dimensional array of NOR-type memory strings of thin-film ferroelectric memory transistors provides a reference signal for read operations by averaging a first signal associated with the write state of the ferroelectric memory transistors and a second signal associated with the erase state. This reference signal has a value distinguishable from threshold voltage values ​​for the write and erase states of the ferroelectric memory transistors and can be effectively applied in read operations to determine the logic state of the ferroelectric memory transistors.

[0022] In some embodiments, a reference signal is connected to a reference sense amplifier to generate a read reference signal that can be used as a latch signal for latching data read from an active bit line. In one example, during a read operation, the memory transistor to be accessed is selected by activating a word line and an active bit line connected to the selected memory transistor. The active bit line is connected to a sense amplifier to generate a sense amplifier output signal. In one embodiment, the read reference signal generated from the reference bit line signal determines the timing for latching the sense amplifier output signal, and the latched sense amplifier output signal is provided as read data for the selected memory transistor. In other embodiments, the sense amplifier connected to the active bit line is implemented as a differential sense amplifier, and the reference signal is connected to the differential sense amplifier to be used as a detection reference signal for detecting a signal on the active bit line.

[0023] In other embodiments, a reference signal is applied during a write operation to set the threshold voltage value of a selected memory transistor to a desired voltage value for a write or erase state. In some embodiments, the reference signal is applied during a calibration step, such as during a wafer sorting process, to set the write conditions for the write and erase states. For example, a reference memory transistor is read out to obtain a reference signal or the voltage indicated by the reference signal. To write a selected memory transistor to the write state, a reference signal is applied to set the threshold voltage value of the ferroelectric memory transistor to a voltage value greater than the reference signal. To write a selected memory transistor to the erase state, a reference signal is applied to set the threshold voltage value of the ferroelectric memory transistor to a voltage value lower than the reference signal. In some embodiments, the conditions for the erase or write operation of each memory transistor are set to closely follow the reference memory transistors adjacent to them.

[0024] In this specification, the terms “semiconductor memory die,” “memory die,” “semiconductor memory device,” or “memory device” are used interchangeably to refer to a memory circuit of memory transistors or storage transistors formed on or above a semiconductor substrate. In embodiments of this disclosure, a semiconductor memory device includes a three-dimensional array of storage transistors. In embodiments of this disclosure, a semiconductor memory device includes a three-dimensional array of storage transistors. In some embodiments, a semiconductor memory device is constructed using a three-dimensional array of NOR-type memory strings formed on a semiconductor substrate, as described in Patent Document 1. Furthermore, in other embodiments, a semiconductor memory device is configured using a three-dimensional array of NOR-type memory strings of ferroelectric memory transistors formed on a semiconductor substrate, as described in Patent Document 2. In embodiments of this disclosure, a three-dimensional array of NOR-type memory strings of ferroelectric memory transistors can be applied to realize a non-volatile memory device or a quasi-volatile memory device. For example, a quasi-volatile memory may have an average retention time of more than 100 ms, such as about 10 minutes or several hours, while a non-volatile memory device may have a minimum data retention time of several days or several years. In the case of quasi-volatile memory, the ferroelectric storage transistor needs to be refreshed from time to time to restore a predetermined written or erased polarization state. For example, the ferroelectric storage transistor is refreshed every few minutes or hours. Specifically, the ferroelectric storage transistor of this disclosure can realize a quasi-nonvolatile memory device with a refresh interval of approximately several hours to several days. This refresh interval of the ferroelectric storage transistor of this disclosure is significantly longer than the refresh interval of DRAM, which requires very frequent refreshes of tens of milliseconds or so.

[0025] In this specification, a NOR-type memory string includes storage transistors formed on a plane of a semiconductor substrate that share a common source region and a common drain region, and each storage transistor can be individually addressed and accessed. In some examples, a three-dimensional array can be formed by providing NOR-type memory strings on multiple planes (e.g., eight or sixteen planes) on a semiconductor substrate and arranging the NOR-type memory strings on each plane in a row. In this specification, the term “memory device” may also refer to a single memory die or a set of memory dies connected to a memory controller.

[0026] In this specification, the term “storage transistor” is used interchangeably with “memory transistor” to refer to a data storage structure formed on a memory die as described herein. In some examples, a semiconductor memory device of the present disclosure, including a NOR-type memory string of randomly accessible storage transistors (or memory transistors), can have applications in a computer system as main memory where data storage locations are directly accessible by the computer system's processor, in a role previously played by conventional random-access memory (RAM), such as dynamic RAM (DRAMS) and static RAM (SRAM). For example, the memory structure of the present disclosure can be applied to a computer system to function as random-access memory to support the operation of a microprocessor, a graphical processor, and an artificial intelligence processor. In other examples, the memory structure of the present disclosure can also be applied to form a storage system, such as a solid-state drive, or to replace a hard drive, to provide long-term data storage in a computer system.

[0027] In embodiments of this disclosure, a semiconductor memory device is formed using a ferroelectric field-effect transistor as a memory transistor. More specifically, a ferroelectric field-effect transistor (hereinafter also referred to as a ferroelectric transistor or FeFET) is formed by using a ferroelectric material as the gate dielectric layer between the gate conductor and the channel of the field-effect transistor. The ferroelectric transistor realizes memory functionality by storing data in a polarized state in the ferroelectric gate dielectric layer (also referred to as the "ferroelectric dielectric layer"). Specifically, when a voltage greater than the cosicant field of the ferroelectric material is applied to the gate conductor, electric polarization is induced in the ferroelectric dielectric layer, and this electric polarization can be reversed by applying a voltage of the opposite polarity. Specifically, the polarization of the ferroelectric material can be reversed by applying a voltage greater than the cosicant field of the ferroelectric material. The polarization state induced in the ferroelectric gate dielectric layer changes the threshold voltage of the ferroelectric storage transistor. By utilizing the change or shift in the threshold voltage of the ferroelectric storage transistor due to different polarization states, data in different logic states can be represented. For example, two logic states (e.g., "0" and "1") can be represented by high and low threshold voltage values ​​of a ferroelectric transistor, resulting from two electrically polarized states induced in a ferroelectric dielectric layer. Multiple logic states (e.g., three states for 1.5 logic bits, four states for 2 logic bits) can be achieved by modulating the electric field to realize additional electrically polarized states (or polarization levels) between the 0 and 1 polarization states. In some cases, the polarization states between the 0 and 1 polarization states are continuous, allowing the stored data to be an analog signal.

[0028] In actual operation, the potential difference between the gate, source, and drain of a ferroelectric transistor is used to generate an electric dipole in the ferroelectric dielectric layer, depending on the influence of the electric field. In one example, the potentials of the source and drain are fixed, and the polarization direction of the electric dipole changes with the gate potential. Furthermore, the polarization direction of the electric dipole directly determines the type of majority carrier in the channel of the ferroelectric transistor. For example, when the potential applied to the gate is positive (+V), the electric dipole becomes negative on the side closer to the gate and positive on the side closer to the channel. Due to the attractive force of the positive electrode of the electric dipole, the majority carriers in the channel become electrons. When the potential applied to the gate is negative (-V), the electric dipole becomes positive on the side closer to the gate and negative on the side closer to the channel. Due to the attractive force of the negative electrode of the electric dipole, the majority carriers in the channel become holes (vacancies). In this specification, the polarization state of the ferroelectric layer where the positive electrode of the electric dipole is close to the channel is referred to as the positive polarization state (+P) or the first polarization state. On the other hand, the polarization state of a ferroelectric layer in which the negative electrode of an electric dipole is close to the channel is called the negative polarization state (-P) or the second polarization state.

[0029] For example, a ferroelectric transistor is an n-type transistor. When a positive bias voltage is applied to the gate, the majority carriers in the channel become electrons, and the threshold voltage of the ferroelectric transistor decreases. Conversely, when a negative bias voltage is applied to the gate, the majority carriers in the channel become holes, and the threshold voltage of the ferroelectric transistor increases. The level of the threshold voltage of a ferroelectric transistor corresponding to the polarization state of the ferroelectric dielectric layer can be used to indicate different logic states of a memory cell.

[0030] In some embodiments, the ferroelectric dielectric layer is a doped hafnium oxide layer. In some examples, the doped hafnium oxide layer comprises one or more of the following hafnium oxides: zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and zirconium impurities.

[0031] In embodiments of this disclosure, a three-dimensional array of NOR-type memory strings is formed as a junction-less ferroelectric memory transistor. That is, the ferroelectric storage transistor does not contain a p / n junction as a drain or source region within the channel. Instead, the drain and source regions are formed by conductive layers such as a metal layer, and the semiconductor channel region is formed by an amorphous oxide semiconductor material such as indium gallium zinc oxide (IGZO). In some examples, the source / drain conductive layer can be formed from a metal layer or a low-resistance metallic conductive material, such as molybdenum (Mo), tungsten (W), tungsten nitride (WN), ruthenium, or titanium-tungsten alloy (TiW). In some examples, the semiconductor channel region may be formed from other oxide semiconductor materials, such as indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO). The ferroelectric memory transistor includes a source region and a drain region (both formed from a metallic conductive material) that are in electrical contact with the oxide semiconductor channel region. The ferroelectric memory transistor configured in this way is a junction-less transistor that does not contain a p / n junction in its channel. The threshold voltage changes due to the polarization of the ferroelectric dielectric layer, thereby modulating the mobile carriers in the semiconductor channel layer. Each ferroelectric memory transistor in the NOR-type memory string is controlled by an individual control gate electrode formed within the local word line structure, which allows each memory transistor to be addressed and accessed individually.

[0032] As used herein, the term “semiconductor oxide layer” (also referred to as “oxide semiconductor layer” or “metal oxide semiconductor layer”) refers to a thin-film semiconductor material made from a conductive metal oxide such as zinc oxide or indium oxide, or any suitable conductive metal oxide having a charge carrier with electron mobility that can be modified or regulated by appropriate preparation or inclusion of appropriate impurities.

[0033] In this description, for the sake of facilitating reference to the drawings, a Cartesian coordinate system is used, as shown in the figures, in which the Z direction is perpendicular to the plane of the semiconductor surface, and the X and Y directions are perpendicular to the Z direction. Furthermore, the drawings provided herein are idealized depictions for illustrating embodiments of the present disclosure and are not intended to be actual depictions of any particular component, structure, or apparatus. The drawings are not drawn to a constant scale, and some layer thicknesses and dimensions may be exaggerated for clarity. Deformations from the illustrated shapes are also expected. For example, areas depicted as box shapes may generally have rough and / or nonlinear features. Illustrated acute angles may be rounded. Similar reference numerals refer to similar components throughout.

[0034] Figure 1 is a schematic diagram of a memory device including a three-dimensional array of NOR memory strings in an embodiment of the present disclosure. Referring to Figure 1, the memory device 200 of this specification includes a plurality of NOR memory strings 212 configured in a three-dimensional array to form a high-density memory structure. The three-dimensional array of NOR memory strings is configured as a memory stack 215 of NOR memory strings 212, within each memory stack 215, the NOR memory strings 212 are stacked in a first direction (e.g., the Z direction). Figure 1 shows three memory stacks 215: memory stack 0, memory stack 1, and memory stack 2. The three-dimensional array of NOR memory strings is also configured as a row of NOR memory strings 212 arranged in a second direction (e.g., the X direction) that forms a plane, with each row of NOR memory strings 212 located in one or more planes parallel to each other along the first direction (Z direction). Each memory string 212 includes a series of memory transistors 202 in a NOR configuration connected in parallel to each other between a common bit line 204 and a common source line 206. The memory transistors form a horizontal NOR-type memory string (also referred to as an "HNOR-type memory string") extending in a third direction (e.g., the Y direction). In this embodiment, the memory transistors 202 are thin-film ferroelectric field-effect transistors (also referred to as "ferroelectric memory transistors"). Furthermore, in some embodiments, the memory transistors 202 are junction-less ferroelectric memory transistors formed using oxide semiconductor channels.

[0035] Each ferroelectric memory transistor 202 in each memory string 212 has a drain terminal connected to its corresponding common bit line BLx (e.g., BL0, BL1, BL2, ...) and a source terminal connected to its corresponding common source line SLx (e.g., SL0, SL1, SL2, ...). Thus, each ferroelectric memory transistor 202 in each memory string 212 is connected in parallel with its corresponding common bit line 204 and common source line 206 to form a NOR-type memory string. Each ferroelectric memory transistor 202 within each memory string 212 further has a gate terminal connected to its corresponding word line WLx (e.g., WL0, WL1, WL2, ...). Each ferroelectric memory transistor 202 vertically aligned across multiple memory strings 212 in the memory stack 215 is connected to its corresponding common word line 208 (also referred to as "local word line 208"). Each local word line 208 corresponding to each memory transistor horizontally aligned in a second direction (X direction) is connected to a common global word line GWLx (e.g., GWL0, GWL1, GWL2, ...).

[0036] In some embodiments, the common source line 206 is electrically floating (i.e., not connected to any potential), and the source voltage is applied from the common bit line 204 using a precharge transistor (not shown). In other embodiments, both the common bit line 204 and the common source line 206 are electrically biased or driven by a control circuit connected to the memory device 200 via hardwire connections. Using an electrically floating source line eliminates the need for hardwire connections, which has the advantage of reducing the density of connector wires required in the stepped structure (not shown) of the three-dimensional array.

[0037] The ferroelectric memory transistors of this disclosure offer high durability, long data retention periods, and relatively low-voltage operation in both erase (e.g., less than 5.0 volts) and write (e.g., less than -5.0 volts) operations. By combining ferroelectric or polarization properties with three-dimensional structures (e.g., thin-film NOR memory strings), memory devices of the ferroelectric memory transistors of this disclosure offer the further advantage of realizing high-density, low-cost memory arrays while retaining the advantages of high-speed random-access memory circuits (low read latency).

[0038] In embodiments of this disclosure, a three-dimensional array of NOR memory strings of the memory device 200 is formed on a semiconductor substrate. To complete the memory circuit, various types of circuits to support the operation of the NOR memory strings formed on the semiconductor substrate are formed inside or on the surface of the semiconductor substrate. Such circuits are referred to as “under-array circuits” (“CuA”) and may include digital and analog circuits such as decoders, drivers, sense amplifiers, sequencers, state machines, logic gates, memory caches, multiplexers, voltage level shifters, voltage sources, latches, registers, and connectors. These circuits perform iterative local operations on the memory array formed on the semiconductor substrate, such as processing random addresses and executing commands for activation, erase, write, read, or refresh. In some embodiments, the transistors within the CuA are constructed using processes optimized for control circuits (e.g., advanced manufacturing processes optimized for forming low-voltage and high-speed logic circuits). In some embodiments, the CuA are constructed using fin-type field-effect transistors (FinFETs) or gate-all-around field-effect transistors (GAAFETs) to achieve a compact circuit layer and improved transistor performance.

[0039] In some embodiments, CuA provides data paths to and from the memory array, and further, to and from a memory controller located on the same semiconductor substrate as CuA. Alternatively, the memory controller may be located on a separate semiconductor substrate, in which case CuA and its associated data paths are electrically connected to the memory controller using various bonding techniques. In some examples, the memory controller includes a control circuit for accessing and operating memory transistors in the memory array to which it is connected, to perform other memory control functions such as data routing and error correction, and to provide an interface function with a system that interacts with the memory array.

[0040] In the memory device 200, each memory transistor 202 in the NOR-type memory string 212 can perform read, write, or erase operations by appropriately biasing its corresponding common word line 208 (WLx) and a common bit line 204 (BLy) shared with other memory transistors 202 in the NOR-type memory string 212. The word line corresponding to each memory transistor 202 is shared with memory transistors in other NOR-type memory strings in a different plane, aligned with that memory transistor along a first direction (Z-direction or "vertical direction"). Although not shown in Figure 1, each word line is also shared between two memory transistors in two adjacent NOR-type memory strings in the same plane (XY plane). In some embodiments, the common source line is typically electrically floating, i.e., not hardwired to any potential. During read, write, or erase operations, the common source line of a NOR-type memory string is typically subjected to a relatively constant voltage, maintained by a voltage source or the charge of an associated capacitor ("virtual ground"), such as the parasitic capacitance of the common source line. For example, the common source line of a NOR-type memory string is biased to a given voltage by a pre-charge operation that provides a desired voltage to the common bit line and transfers the voltage on the common bit line to the common source line via one or more pre-charge transistors. For example, to write to or erase a selected memory transistor, a sufficient voltage difference (e.g., 3V for a ferroelectric memory transistor) is applied between the word line and at least the common bit line. To avoid interference with unselected memory transistors, unintended erasure or writing to unselected memory transistors can be prevented by applying a predetermined voltage difference between the word line associated with the unselected memory transistor and the common bit line that is significantly lower than the voltage required for writing or erasing.To read the selected memory transistor, a read voltage (e.g., 1V for a ferroelectric memory transistor) is applied to the word line, and the bit line is biased to a positive voltage (e.g., approximately 0.05V to 0.9V) to allow current to flow between the drain and source terminals of the selected memory transistor. The current on the bit line is detected by a sense amplifier via a bit line selector, thereby determining the logic state or stored data of the selected memory transistor.

[0041] Figure 2 is a schematic diagram showing exemplary support circuitry connected to the bit lines of the NOR memory string of the memory device in Figure 1 in an embodiment of the present disclosure. Specifically, Figure 2 shows a sense amplifier circuit and associated circuit elements for performing a memory read operation. For simplicity of explanation, additional circuit elements and control signals are omitted. In this specification, a slice in the memory device 200 (Figure 1) refers to a memory transistor connected to the same global word line GWLx within the memory device 200. In other words, a slice in the memory device refers to a memory transistor located in the XZ plane of the three-dimensional memory array in Figure 1. In this embodiment, each slice of memory transistor consists of p+1 memory pages, and each memory page contains n+1 bits or n+1 bit lines. In this specification, each memory access from the host is performed on a unit of memory data access. This unit of access is referred to as a page of memory data or memory page. For example, each slice of memory transistor contains 32 memory pages, and each memory page contains 512 bits or 512 bit lines. The bit lines within the memory device 200 (Figure 1) are connected to support circuits for performing memory read operations. For example, the support circuits are formed in the under-array circuits within the semiconductor substrate of the memory device. Figure 2 shows an exemplary support circuit for performing read operations in the memory device. Referring to Figure 2, the bit lines of the NOR type memory strings in the memory array are connected to bit line selectors 220. Specifically, each bit line selector 220 is connected to p+1 bit lines and selects one bit line from among the p+1 bit lines to be detected by the sense amplifier (SA) 222 corresponding to each bit line selector 220. For example, each bit line selector 220 receives a selection signal BL_SEL, which selects one bit line (e.g., Bly) from among the p+1 bit lines to be detected by the sense amplifier 222 as the bit line Blyx. The selection signal BL_SEL can be a multi-bit signal. Each group of bit lines 218 contains bit lines associated with the same data bits across p+1 memory pages.For example, bit line BL0 is associated with data bit 0 across memory pages P0 to Pp, forming a group of bit lines 218. To select one bit line from each group of bit lines 218, each group of bit lines 218 is connected to its corresponding bit line selector 220. Thus, each of the n+1 bit line selectors 220 selects n+1 bit lines BL0x to BLnx in response to the selection signal BL_SEL for detection at the corresponding sense amplifier 222. In one example, a memory page representing a unit of memory data access contains 512 bits (or 64 bytes) of memory data, and 512 bit line selectors are provided to select the bit lines BL0x to BLnx of the memory page selected for access. Additional bits in the memory data may be included for error correction bits or other management functions. The selected global word line activates p+1 memory pages (e.g., 32 memory pages), and the bit line selector corresponding to each sense amplifier selects the bit lines associated with the memory page selected for access.

[0042] At the output of each bit line selector 220, the selected bit lines (BL0x~BLnx) are connected to the sense amplifier 222 corresponding to each bit line selector 220. In a read operation, the sense amplifier 222 detects a voltage signal indicating the bit line current on the selected bit line to determine the logic state of the selected memory transistor. In response to this detection, it generates a sense amplifier output signal SAOUT. In this embodiment, each sense amplifier output signal SAOUT is connected to a data latch 224. The data latch 224 stores the sense amplifier output signal SAOUT as read data exchanged with the memory controller. The data latch 224 may be further used to store write data received from the memory controller, which is written to the selected memory transistor in a memory write operation. The memory device's support circuitry includes additional data latches (not shown) for storing memory data for other operations, for example, locally storing read data for a refresh operation. Note that the circuit configuration shown in Figure 2 is illustrative and not intended to limit the invention. In another embodiment, the sense amplifier 222 may be equipped with a data latch function so that it can function as a data latch for storing read data.

[0043] During a read operation, the sense amplifier 222 detects a voltage signal on the selected bit line. This voltage signal indicates the bit line current associated with the erase or write state of the selected memory transistor. The sense amplifier 222 uses a reference signal REF to determine the erase or write state of the selected memory transistor. The sense amplifier 222 generates a sense amplifier output signal SAOUT, which contains a logic state indicating the detected bit line voltage signal. For example, in response to a read voltage applied to the selected word line of the selected memory transistor, the erase state of the memory transistor is associated with a conductive memory transistor, and the write state of the memory transistor is associated with a non-conductive memory transistor. During operation, the sense amplifier 222 uses the reference signal REF to distinguish between conductive and non-conductive memory transistors. In a multilevel ferroelectric memory cell, the bit line signal is compared with multiple written reference signals REF1, REF2, etc., to determine the stored data value associated with one of the multiple polarization levels.

[0044] In one embodiment, the sense amplifier 222 is implemented as a single-ended sense amplifier circuit. In this case, the sense amplifier 222 detects the bit line current of the selected bit line and, each time a bit line signal is generated, uses a reference signal REF to determine when the sense amplifier output signal should be latched as a valid output signal. In other words, the reference signal REF indicates when the bit line signal has risen sufficiently, and the reference signal REF triggers the latching of the sense amplifier output signal to the data latch 224. In another embodiment, the sense amplifier 222 is implemented as a differential sense amplifier circuit. In this case, the differential sense amplifier circuit triggers the sense amplifier output signal by comparing the bit line signal of the selected memory transistor with the reference signal REF.

[0045] Embodiments of this disclosure relate to a device structure and method for providing a reference signal for memory read operations in a memory device of a three-dimensional NOR-type memory string of ferroelectric memory transistors. Specifically, embodiments of this disclosure utilize the ferroelectric polarization characteristics of ferroelectric memory transistors to generate a reference signal using the partial polarization of a reference ferroelectric memory transistor. A partial polarization state is realized in one or more reference ferroelectric memory transistors that are distinguishable from the erase or write state of the ferroelectric memory transistors. This partial polarization state can be effectively used as a reference signal for distinguishing the erase or write state of the ferroelectric memory transistors. This is made possible by the observation that electrically writable partially polarized ferroelectric transistors exhibit stable threshold stability in the partial polarization state and therefore can be used as writable reference memory transistors for long periods of time, even when exposed to high temperatures. During a memory refresh operation, the reference memory transistor itself can be refreshed to return to its initial partially polarized / depolarized state in order to compensate for the drift of the written reference transistor.

[0046] In embodiments of this disclosure, a reference signal is generated using one or more ferroelectric memory transistors designated as reference memory transistors in a memory array. In some embodiments, the reference memory transistors are selected to be physically close to the memory transistors being accessed in normal memory operation, so that the reference memory transistors share the same elemental fluctuations as the memory transistors. Thus, the reference signal follows the fluctuations of the bit line signal of the memory transistor being accessed, resulting in a highly accurate and reliable reference signal. In embodiments of this disclosure, the reference memory transistors are designated in a reference plane, reference stack, or reference slice, as will be described in detail later.

[0047] Figure 3 is a perspective view of a memory device showing an array of NOR-type memory strings in a three-dimensional array in several embodiments. More specifically, the memory structure 230 in Figure 3 realizes a part of the memory device 200 of Figure 1 and shows a three-dimensional array 232 of NOR-type memory strings 234 arranged on a semiconductor substrate 245. In the illustration of Figure 3, each NOR-type memory string 234 is represented by a rectangular box having a ferroelectric memory transistor arranged within the NOR-type memory string and a bit line of the NOR-type memory string extending in the Y direction. The three-dimensional array 232 shown in Figure 3 includes NOR-type memory strings formed in eight planes arranged vertically (Z direction). In each plane (planes 0 to 7), NOR-type memory strings 234 are arranged in columns along the X direction. NOR-type memory strings 234 aligned vertically in the Z direction across multiple planes are referred to herein as a memory stack. In this embodiment, each memory stack includes eight memory strings stacked along the YZ plane. As described above, the semiconductor substrate 245 includes logic circuits (referred to as array sub-circuits) for operating the memory transistors. For example, the array sub-circuits may include a bit line selector 240 and a sense amplifier 242.

[0048] A global word line 236 is formed above the three-dimensional array 232 and extends in a direction perpendicular to the direction in which the NOR-type memory string 234 extends, i.e., in the X direction. In this embodiment, local word lines (not shown) connected to each global word line are formed vertically. The local word lines are provided between memory stacks (in the sidewall transistor configuration) or within the memory stack (in the channel-all-around transistor configuration). Along each memory stack, each local word line is arranged in the Y direction to connect to each global word line 236.

[0049] During operation, a given global word line 236 is activated, and a section of memory transistors connected to each local word line across each plane and all memory stacks of each NOR-type memory string 234 (also referred to as a "memory transistor slice") is selected. As described above, a memory transistor slice contains p+1 memory pages, and each memory operation selects one memory page from the p+1 pages for access. Each memory page represents the access unit of a memory operation. The bit line BL associated with the selected memory page in the memory transistor slice is selected to perform the memory operation. Specifically, bit lines corresponding to the same data bits in the p+1 memory pages of the slice (e.g., the group of bit lines shown in the dotted box 238) are connected to each bit line selector 240 in the array-under-circuit formed on the semiconductor substrate 245. The bit line selector 240 selects one bit line from the p+1 bit lines. In a memory read operation, the selected bit line is connected to the corresponding sense amplifier 242 to detect the bit line current and determine the logic state of the memory transistor being accessed. For example, a slice of memory transistor may contain 32 memory pages. In this case, the 32 bit lines included in bit line group 238 are connected to the corresponding bit line selector 240 to read one bit of data during a read operation. The other bit line groups corresponding to the remaining n data bits are also connected to their corresponding bit line selectors and sense amplifiers.

[0050] The memory structure 230 in Figure 3 shows a portion of a memory array of NOR-type memory strings. In some examples, the memory structure 230 in Figure 3 forms a tile of memory transistors, and a large-capacity memory device can be realized by constructing a memory device using a two-dimensional array of these tiles. Figures 4 to 6 show the configuration of a memory array for providing a reference signal for memory read operations in embodiments of this disclosure. Similar elements in Figures 3 to 6 are given the same reference numerals and similar elements are not described further. For example, Figures 4 to 6 show a tile of memory transistors in a memory device composed of a two-dimensional array of tiles.

[0051] Figure 4 shows configurations for providing a reference memory transistor in a reference plane in several embodiments. Referring to Figure 4, the memory structure 250 includes eight memory planes, one of the memory planes in the memory array is designated as a reference plane 255, on which the memory transistors operate to provide a reference signal for read operations. The reference plane 255 includes some or all of a NOR-type memory string arranged in the same plane (e.g., plane 3). In a memory read operation, a bit line selector 240 selects one bit line from a group of bit lines (shown in dotted box 238) for access, and the selected bit line is connected to its corresponding sense amplifier 242. Also, a reference signal generated by one or more reference memory transistors in the reference plane 255 is provided to the sense amplifier 242 for use in detecting the bit line signal of the selected bit line. In some embodiments, the bit lines of the reference memory transistors are connected, with or without, to one or more dedicated sense amplifiers, referred herein as “reference sense amplifiers”. The reference sense amplifier generates a reference signal, such as a reference voltage signal (REF), which is provided to the sense amplifier 242 for reading data from selected memory transistors, such as bit line group 238, during memory read operations.

[0052] In some examples, by providing a reference plane for a reference memory transistor, a reference signal can be provided from a memory transistor located in the same stack as the selected bit line, thereby reducing fluctuations in the reference signal relative to the bit line signal and improving detection accuracy. In some embodiments, one or more reference memory transistors located in a reference plane 255 within the bit line group 238 are used to provide a reference signal for the data bits read from the bit line group 238.

[0053] Figure 5 shows configurations for providing a reference memory transistor within a reference stack in several embodiments. Referring to Figure 5, the memory structure 260 includes multiple memory stacks, one of which in the memory array is designated as the reference stack 265, and its memory transistors operate to provide a reference signal for read operations. The reference stack 265 includes NOR-type memory strings arranged in the same stack across some or all of the memory planes from plane 0 to plane 7. In a memory read operation, a bit line selector 240 selects one bit line from the group of bit lines (shown in the dotted box 238) for access, and the selected bit line is connected to its corresponding sense amplifier 242. Also, a reference signal generated by one or more reference memory transistors in the reference stack 265 is provided to the sense amplifier 242 for use in detecting the bit line signal of the selected bit line. In some embodiments, the bit lines of the reference memory transistors are connected, with or without, to one or more dedicated sense amplifiers, referred herein as “reference sense amplifiers”. The reference sense amplifier generates a reference signal, such as a reference voltage signal (REF), which is connected to the sense amplifier 242 to read data from selected memory transistors, such as bit line group 238, during memory read operations.

[0054] Specifically, the reference signal is detected periodically and stored in a reference sense amplifier or a latch connected thereto. Alternatively, the reference signal can be detected during a memory read operation, simultaneously with the detection of the read data. In some examples, by providing a reference stack of reference memory transistors, the reference signal can be provided from memory transistors located in the same memory plane as the selected bit line, thereby minimizing fluctuations in the reference signal relative to the bit line signal and improving detection accuracy. More specifically, in some embodiments, the bit lines of the reference memory transistors in the reference stack 265 are connected to a bit line selector. The bit line selector selects the bit lines of reference memory transistors located in the same plane as the memory transistors selected for the read operation. The selected bit lines are provided to a reference sense amplifier to generate a reference signal. In this way, the reference signal generated by the selected reference memory transistors can closely track fluctuations in the bit line signals of the memory transistors selected for the memory read operation.

[0055] Figure 6 shows configurations for providing a reference memory transistor within a reference slice in several embodiments. Referring to Figure 6, the memory structure 270 includes memory transistors within a plurality of memory slices, each memory slice connected to a single global word line. One of the memory slices within the memory structure 270 is designated as the reference slice 275, and its memory transistors operate to provide a reference signal for read operations. The global word line 277 connected to the reference slice 275 is referred to herein as the reference global word line. The reference slice 275 includes reference memory transistors arranged across the entire memory stack and across some or all of the memory planes 0 to 7. In a memory read operation, a bit line selector 240 selects one bit line from a group of bit lines (shown in the dotted box 238) for access, and the selected bit line is connected to its corresponding sense amplifier 242. Also, a reference signal generated by one or more reference memory transistors in the reference slice 275 is provided to the sense amplifier 242 for use in detecting the bit line signal of the selected bit line. In some embodiments, the reference memory transistor is located within the same memory string as the selected memory transistor to be accessed, and two read operations are performed sequentially: reading the bit line signal from the selected memory transistor and reading the reference signal from the reference memory transistor (details will be described later).

[0056] In other embodiments, the bit lines of a reference memory transistor are connected, with or without a bit line selector, to one or more dedicated sense amplifiers, referred herein as “reference sense amplifiers.” The reference sense amplifiers generate a reference signal, such as a reference voltage signal (REF), which is connected to a sense amplifier 242 to read data from selected memory transistors, such as bit line group 238, during memory read operations.

[0057] By providing a reference slice for the reference memory transistor, a reference signal can be provided from a memory transistor located within the same memory string as the selected bit line. This minimizes fluctuations in the reference signal relative to the bit line signal, thereby improving detection accuracy.

[0058] Figure 7 is a schematic diagram of a memory array including a memory stack of NOR-type memory strings in an embodiment of the present disclosure. For example, the memory array 280 in Figure 7 realizes a part of the memory device 200 in Figure 1. The memory array 280 in Figure 7 also shows a stack of NOR-type memory strings of ferroelectric memory transistors and the arrangement of precharge transistors provided on each memory string. Referring to Figure 7, the memory array 280 includes a plurality of memory strings 212 that are stacked on top of each other to form a memory stack. Each memory string 212 includes a series of memory transistors 202 connected in parallel to each other between a common bit line 204 and a common source line 206. The memory strings 212 are also called NOR-type memory strings because the memory transistors are connected in parallel to each other in a NOR configuration. The NOR-type memory strings 212 of memory transistors constitute a basic building block for forming a two-dimensional or three-dimensional array of memory transistors. That is, a plurality of strings of memory transistors can be used to form a two-dimensional array of memory transistors, such as a planar or stack of memory transistors. A three-dimensional array of memory transistors can be formed by stacking multiple planes of two-dimensional arrays of memory transistors on top of each other. In this specification, a semiconductor memory device is realized by an array of strings of memory transistors. The exact configuration or arrangement of the strings of memory transistors is not important to the implementation of this disclosure.

[0059] Each memory transistor 202 is a thin-film memory transistor having a drain terminal connected to a common bit line 204, a source terminal connected to a common source line 206, a gate terminal or control terminal connected to a local word line 208, and a data storage film that stores data for the memory transistor. In this embodiment, the data storage film is a ferroelectric dielectric layer provided between the gate conductor layer that forms the gate terminal and the channel layer. The drain terminal and source terminal are in electrical contact with the channel layer. In the memory array configuration shown in Figure 7, the gate terminal of a memory transistor 202 is driven by its corresponding word line (WLx) 208. Each word line WLx activates one storage transistor 202 in one NOR-type memory string 212, and simultaneously activates other memory transistors in other NOR-type memory strings, such as other NOR-type memory strings in the same memory stack. With this configuration, when a word line WL is selected, all storage transistors 202 connected to that word line (e.g., WLn) are activated. During operation, the selected word line activates p+1 memory pages, each memory page containing n+1 memory transistors associated with n+1 NOR-type memory strings. The bit lines belonging to the selected memory page are selected for memory operation. Thus, by selecting a memory page using the selected word line and the selected bit line, it is possible to access n+1 storage transistors within the selected memory page.

[0060] In embodiments of this disclosure, a memory device includes a ferroelectric memory transistor (or “memory cell”) that can be read from, written to, or erased. Write operations and erase operations may be collectively referred to as write operations. The memory device performs memory operations that include read operations, which read data from the memory transistors, and write operations, which write data to the storage transistors. The memory device may perform other operations, such as refresh operations, but these are not described herein. In this specification, a write operation includes two operations or two phases: an erase operation or erase phase and a write operation or write phase. In these embodiments, the erase operation is associated with writing a first logical state (e.g., logical value “1”) to the memory cell, and the write operation is associated with writing a second logical state (e.g., logical value “0”) to the memory cell. Note that the specific logical states assigned to an erase operation or write operation are arbitrary and not important to the implementation of this disclosure. In other embodiments, the erase step is associated with writing a logical value “0” to the memory cell, and the write step is associated with writing a logical value “1” to the memory cell.

[0061] Furthermore, in this specification, a first logical state (e.g., erase state) is used to identify a first polarization state in the ferroelectric dielectric layer of a ferroelectric memory transistor, and a second logical state (e.g., write state) is used to identify a second polarization state in the ferroelectric dielectric layer of a ferroelectric memory transistor. For example, the first polarization state can be associated with a positive polarization state having a lower threshold voltage value and a conductive memory cell in response to a read voltage applied to the gate terminal of the memory transistor. On the other hand, the second polarization state can be associated with a negative polarization state having a higher threshold voltage value and a non-conductive memory cell in response to a read voltage applied to the gate terminal of the memory transistor. As used herein, a positive polarization state (first polarization state) and a negative polarization state (second polarization state) refer to polarization states in which the polarization directions of electric dipoles in the ferroelectric dielectric layer are opposite to each other. For example, a positive polarization state is associated with an erase state, and a negative polarization state is associated with a written state.

[0062] To write to or erase a ferroelectric memory transistor, a large voltage difference (e.g., 3V in the case of a ferroelectric memory transistor) is applied between the word line and the common bit line and common source line. In one embodiment, to erase a memory cell, a positive voltage is applied between the word line and the common bit line and common source line. For example, a positive voltage (+3V) is applied to the word line, and the common bit line and common source line are set to 0V. On the other hand, to write to a memory cell, a negative voltage is applied between the word line and the common bit line and common source line. For example, if the word line is set to 0V and a positive voltage (+3V) is applied to the common bit line and common source line, a voltage of -3V is applied to the word line relative to the common bit line and common source line. To avoid interference with unselected memory transistors, unintended erasure or writing to unselected memory transistors can be prevented by applying a predetermined voltage difference between the word line and the common bit line / common source line associated with the unselected memory transistor, which is significantly smaller than the voltage required for writing or erasing.

[0063] In embodiments of this disclosure, both write and erase operations can be achieved without requiring positive and negative bias voltages by, for example, switching a positive voltage (in this example, +3V) between the word line or common bit line / common source line and applying 0V to other transistor nodes. In these embodiments, since the ferroelectric memory transistors are built on a three-dimensional stack that does not share a common ground within the substrate, applying positive voltages to different transistor nodes is easily done. Furthermore, by not requiring positive and negative voltages on the same die, manufacturing costs can be reduced and the complexity of the device can be decreased. In addition, for example, the triple-well process flow commonly used when positive and negative voltages are required to bias the memory transistors is not required.

[0064] To read stored data from a selected memory transistor, a read voltage is applied to the selected word line to activate the selected memory transistor, and a bit line voltage Vbit is applied to the common bit line. In one example, the read voltage is 1-2V and the voltage Vbit is 0.5V. The selected memory transistor can then modulate the common bit line based on its conductivity state. In some embodiments, the bit line voltage is generated as a result of the logic state of the selected memory transistor, and the read data is latched or recorded after the period in which the bit line voltage is generated. After the period in which the bit line voltage is generated, a sense amplifier connected to the bit line of the selected memory transistor detects the bit line current or voltage indicating the stored data.

[0065] In some embodiments, the common source line 206 is typically electrically floating, i.e., not hardwired to any potential. During read, write, or erase operations, the common source line 206 of a NOR-type memory string is set to a desired voltage (e.g., ground voltage) by a precharge operation using one or more precharge transistors 285 formed along the memory string. After the precharge operation, the common source line 206 is left electrically floating. The precharge voltage on the common source line 206 is maintained by the parasitic capacitance of the common source line and is also referred to as the "virtual ground" voltage. Specifically, the precharge operation sets the common bit line 204 to a desired voltage and then transfers the bit line voltage to the source line by momentarily turning on the precharge transistor 285 to short-circuit the common bit line 204 to the common source line 206. As a result, the common source line 206 is charged from the voltage on the common bit line 204 to a voltage equal to the bit line voltage. After the precharge operation is complete, the precharge transistor 285 is turned off. The common source line 206 is maintained at a relatively constant voltage by parasitic capacitance at the source terminal, such as the parasitic capacitance between the source terminal of the memory transistor in the NOR-type memory string 212 and the gate terminal of the numerous local word lines.

[0066] In some embodiments, each memory string 212 includes one or more precharge transistors 285 distributed throughout the memory string. The precharge transistors 285 are connected to a precharge word line PCH_WL. This precharge word line is momentarily asserted to turn on the precharge transistors, electrically short-circuiting the associated common bit line to a common source line. Turning off the precharge word line PCH_WL allows another voltage to be applied to the common bit line without disturbing the voltage established on the common source line. In this embodiment, the precharge word line PCH_WL is asserted to activate the precharge transistors 285 in the memory stack. In embodiments of this disclosure, the precharge transistors 285 are preferably non-memory field-effect transistors. In another embodiment, the common source line 206 is configured to be hardwired to a voltage source for biasing it to a desired voltage for read, write, and erase operations. For example, the voltage source for the common source line may be located in the circuitry below the array.

[0067] In embodiments of this disclosure, one or more ferroelectric memory transistors in a memory device are designated as reference memory transistors for providing a programmable reference signal for read operations. In Figure 7, one memory transistor 202 in a memory string is designated as a reference memory transistor 282 (also referred to as a reference memory cell or reference cell). In practice, to improve the quality of the reference signal, multiple memory transistors, such as all memory transistors in a memory string, are designated as reference memory transistors. Specifically, a final reference signal with a desired narrow voltage distribution can be generated by averaging the individual reference signals generated by multiple reference memory transistors. In some embodiments, the final reference signal can be generated by averaging the individual reference signals generated by, for example, six, twelve, or eighteen reference memory transistors.

[0068] In one embodiment, a memory string can be designated as a reference string. In this case, all memory transistors within the reference string are used as reference memory transistors to provide a reference signal. For example, a reference memory transistor 282 connected to word line WL2 can provide a reference signal to a memory transistor 202 in the same memory stack that is also connected to word line WL2. In this way, local variations (variations) can be minimized, and the reference signal provided by the reference memory transistor 282 can be used to more accurately detect read signals from selected memory transistors vertically aligned within the same memory stack. As described above, various configurations can be used to provide a reference memory transistor. For example, Figure 4 shows an example where the plane of the memory string is designated as the reference plane of the reference memory transistor. In another example, Figure 5 shows an example where the stack of the memory string is designated as the reference stack of the reference memory transistor. In yet another example, Figure 6 shows an example where a slice of memory transistor is designated as the reference slice of the reference memory transistor.

[0069] In some embodiments, a reference signal is generated by partially polarizing a reference memory transistor. Partial polarization, as used herein, refers to biasing a ferroelectric memory transistor to a polarization level in the ferroelectric dielectric layer that falls between the positive and negative polarization states associated with the erase and write states of the ferroelectric memory transistor. As described above, the positive and negative polarization states in the ferroelectric dielectric layer refer to polarization states where the polarization directions of the electric dipoles in the ferroelectric dielectric layer are opposite to each other. The term “polarization state” is used herein to refer to the polarization direction of the electric dipoles in the ferroelectric dielectric layer, which refers to the positive or negative polarization state associated with the erase or write state of the ferroelectric memory transistor. Furthermore, the term “polarization level” refers to different polarization levels achieved in the ferroelectric dielectric layer, associated with different threshold voltage values ​​induced by polarization. A given polarization level is associated with a positive or negative polarization state in the ferroelectric dielectric layer. For example, a first polarization level associated with a negative polarization state may induce a different threshold voltage value than that induced by a second polarization level associated with a negative polarization state. In the following description, the terms “polarization state” and “polarization level” are used interchangeably to refer to the different threshold voltage values ​​induced by the polarization of the ferroelectric dielectric layer. In this case, the polarization can be in the positive or negative direction.

[0070] During operation, the polarization state and polarization level correspond to different threshold voltage values ​​within the ferroelectric memory cell. In some embodiments, during an erase operation, a positive bias is applied to the drain and source terminals of the gate terminal of the ferroelectric memory transistor to induce a positive polarization state in the ferroelectric dielectric layer. As a result, the memory transistor is set to a first threshold voltage value (VTH1). On the other hand, in some embodiments, during a write operation, a negative bias is applied to the drain and source terminals of the gate terminal of the ferroelectric memory transistor to induce a negative polarization state in the ferroelectric dielectric layer. As a result, the memory transistor is set to a second threshold voltage value (VTH2). In this embodiment, the second threshold voltage value VTH2 has a voltage greater than the first threshold voltage value VTH1. In some embodiments, by reading the stored data using a reference voltage between the first and second threshold voltage values, it is possible to distinguish between an erased memory cell in a conductive state and a written memory cell in a non-conductive state.

[0071] In embodiments of this disclosure, during partial erase or partial write operations, a reference memory transistor is partially polarized to set the threshold voltage of the reference memory transistor to a third threshold voltage value (VTH3) that is between a first threshold voltage value and a second threshold voltage value. In other words, the reference signal generated by the reference memory transistor has a voltage that is associated with, or indicates, a third threshold voltage value (VTH3) that is between a first threshold voltage value and a second threshold voltage value. In one embodiment, the reference memory transistor is half-polarized to generate a reference signal having a voltage (VTH3) that is an intermediate value between a first threshold voltage value and a second threshold voltage value. That is, the third threshold voltage value VTH3 is an intermediate value between a first threshold voltage value and a second threshold voltage value (VTH3 = VTH1 + (VTH2 - VTH1) / 2). In other embodiments, the third threshold voltage value (VTH3) is close to VTH1 or VTH2 and does not necessarily have to be an intermediate value between VTH1 and VTH2.

[0072] In embodiments of this disclosure, a ferroelectric memory transistor is said to be partially polarized if the ferroelectric dielectric layer of the memory transistor has a polarization level between a positive polarization state induced by an erase operation and a negative polarization state induced by a write operation. By performing a partial polarization operation, the polarization direction of the electric dipoles in the ferroelectric dielectric layer is changed to set the polarization level of the ferroelectric dielectric layer to a polarization level between the positive polarization state and the negative polarization state. That is, the partially polarized ferroelectric layer contains electric dipoles in both polarization directions, thereby modulating the mobile carriers in the channel layer to set the threshold voltage value of the partially polarized memory transistor to a voltage level between the positive polarization state and the negative polarization state.

[0073] Figures 8(a) and (b) are timing diagrams showing the voltage and timing conditions for performing erase and write operations to achieve positive and negative polarization states in the memory transistors of the memory device in embodiments of the present disclosure. In Figures 8(a) and (b), curve 302 represents the word line voltage V applied to the word line WLx of the memory transistor selected for access. WL This is shown. Curve 304 shows the word line voltage V applied to the word line of an unselected memory transistor that shares the same common bit line as the selected memory transistor (i.e., on the same memory string). WL_UnSel This shows the word line voltage V (also called the "forbidden voltage"). Curve 306 shows the word line voltage V applied to the word line of the precharge transistor associated with the selected memory transistor. WL_PCH This shows that curve 308 represents the bit line voltage V of the common bit line associated with the selected memory transistor. BL This shows that curve 310 represents the source line voltage V of the common source line associated with the selected memory transistor. SL This indicates that. Additionally, to avoid interference with data stored in the unselected memory transistors, a prohibition voltage may be applied to unselected bit lines that share the same word line as the selected memory transistor, if necessary.

[0074] Referring to FIG. 8(a), to perform an erase operation, the voltage of the word line of the selected memory transistor is biased to a positive voltage (e.g., 3V) with respect to the bit line and source line voltages. In one example, to perform an erase operation to set the selected memory transistor to a positive polarization state, the gate terminal (word line) of the selected memory transistor is biased to 3V, and the drain terminal (bit line) and source terminal (source line) are biased to 0V. The erase operation starts from a setup period from time T0 to time T1, and during this setup period, a precharge operation is performed to set the word line voltage. For example, during this setup period, the word line voltage V WL of the selected memory transistor is raised to an intermediate voltage (e.g., 1V), and the word line voltage V WL_UnSel of the unselected memory transistors is raised to an erase inhibit voltage VINH_E (e.g., 1 - 1.5V). To perform the precharge operation, the word line voltage V WL_PCH for precharge operation is raised to a voltage sufficient to turn on the precharge transistor (e.g., 2 - 3V), and the bit line voltage V BL is set to 0V. Thereby, the common bit line of the selected memory string is electrically connected to the common source line via one or more activated precharge transistors. By the precharge operation, the source line voltage V SL is set to the same voltage as the bit line voltage (i.e., 0V). At time T1, the word line voltage V WL_PCH for precharge operation is deasserted to 0V or the like, whereby the precharge transistor turns off. When the common source line is electrically floating, the source line voltage V SL is held at 0V or virtual ground by the parasitic capacitance between the common source line and the gate terminals of the memory transistors in the memory string. In another embodiment, the word line voltage V WL_PCH for precharge operation is held at the turn-on voltage (2 - 3V) as shown by the dashed line of curve 306, whereby the source line is actively biased to the bit line voltage throughout the erase period.

[0075] By setting it in this way, at time T2, the erasure period (Te) is equal to the word line voltage V WL The process starts with the erase voltage VER (e.g., 3V) raised. Word line voltage V WL The erase voltage VER is maintained until time T3. When a positive erase voltage is applied between the gate, drain, and source terminals of the selected memory transistor, the ferroelectric dielectric layer of the selected memory transistor is induced to a first polarization state (positive polarization state) in response to the applied positive bias, thereby setting the memory transistor to a first threshold voltage value VTH1. At the end of the erase period (Te) (time T3), the word line voltage V WL and word line voltage V WL_UnSel The voltage drops to 0V. Word line voltage V for pre-charge operation. WL_PCH The bit line voltage and source line voltage rise momentarily (from time T3 to time T4) to equalize. This prepares the memory device for the next memory operation.

[0076] Referring to Figure 8(b), to perform a write operation, the word line voltage of the selected memory transistor is biased to a negative voltage (e.g., -3V) relative to the bit line and source line. In one example, to perform a write operation to set the selected memory transistor to a negatively polarized state, the gate terminal (word line) of the selected memory transistor is biased to 0V, and the drain terminal (bit line) and source terminal (source line) are biased to 3V. Thus, a negative voltage is not required to perform the write operation. The write operation starts from a setup period from time T0 to T1, during which a precharge operation is performed to set the bit line voltage and source line voltage to an intermediate voltage (e.g., 1.5V). That is, the word line voltage for the precharge operation V WL_PCH Assert (for example, 2-3V) to turn on the precharge transistor. This will change the bit line voltage V BL It is set to an intermediate voltage (e.g., 1.5V), and the source line voltage VSL The bit line voltage V BL This becomes equal to the word line voltage V for pre-charge operation at time T1. WL_PCH It is deasserted to 0V. Alternatively, the word line voltage V for precharging is used. WL_PCH As shown by the dashed line in curve 306, the source line is held at the turn-on voltage (2-3V), thereby actively biasing the source line to the bit line voltage throughout the entire writing period.

[0077] By setting it this way, at time T2, the write period (Tp) is set to the word line voltage V of the unselected transistor. WL_UnSel The process starts with the write-protect voltage VINH_P (e.g., 1.5~2V) raised. In this embodiment, the write-protect voltage VINH_P is set to 1.5V. Bit line voltage V BL The write-protect voltage VINH_P rises due to the connection between the gate terminals of all unselected memory transistors in the memory string and the common bit line. As a result, the bit line voltage V BL The voltage rises to the write voltage VPR (3V), which is the sum of the intermediate voltage (1.5V) and the write-protect voltage VINH_P (1.5V). Meanwhile, the source line voltage V SL The write voltage rises to 3V by connecting to the gate terminal of an unselected memory transistor, or by being actively biased to the bit line voltage via a precharge transistor.

[0078] When a negative write voltage is applied between the gate, drain, and source terminals of the selected memory transistor, the ferroelectric dielectric layer of the selected memory transistor is induced to a second polarization state (negative polarization state) in response to the applied negative bias, thereby setting the memory transistor to a second threshold voltage value VTH2. At the end of the write period (Tp) (time T3), the word line voltage V WL_UnSel and the word line voltage V for pre-charge operation WL_PCHThe voltage drops to 0V. The bit line voltage and source line voltage are also discharged to 0V. This prepares the memory device for the next memory operation.

[0079] In this embodiment, the erase period Te and the write period Tp are both described as the period from time T2 to time T3. However, the erase period Te and the write period Tp may or may not have the same duration. Times T1 to T4 are used only to indicate relative durations and are not intended to indicate precise durations.

[0080] In embodiments of the present disclosure, the reference signal for read operations is primarily generated by performing a partial polarization operation on a reference memory transistor. Partial polarization can be performed by partially erasing or partially writing to the reference memory transistor. Several schemes can be applied to perform the partial polarization operation of the reference memory transistor. For convenience of explanation, in the following description, the drain terminal and source terminal of the ferroelectric memory transistor are referred to as the "current terminals" of the transistor. In some embodiments, the drain terminal and source terminal of the ferroelectric memory transistor in the memory device of the present disclosure have interchangeable symmetrical structures in the transistor structure. In the following description, the drain terminal is the first current terminal and is connected to a common bit line, and the source terminal is the second current terminal and is connected to a common source line.

[0081] In some embodiments, partial polarization operation is performed by performing an erase or write operation on only one current terminal (either the drain or source terminal) of the reference ferroelectric memory transistor. The other current terminal is prohibited from being erased or written to. In the following description, partial polarization operation may also be referred to as partial erase operation or partial write operation. In further embodiments, partial polarization operation is achieved by performing an erase or write operation on one current terminal with a shortened erase / write duration. In other embodiments, partial polarization operation is achieved by performing a weak erase or weak write operation on one current terminal. As a result, the ferroelectric dielectric layer of the reference ferroelectric memory transistor is erased or written to a partially polarized state having a polarization level between the positive polarization state of the erase operation and the negative polarization state of the write operation. Consequently, the reference memory transistor has a third threshold voltage value (VTH3) between a first threshold voltage value and a second threshold voltage value associated with the positive and negative polarization states.

[0082] In another embodiment, partial polarization operation is achieved by performing a weak erase or weak write operation on both current terminals (drain and source) of a reference ferroelectric memory transistor.

[0083] It should be noted that before performing a partial polarization operation, the reference memory transistor may be pre-conditioned to the opposite polarization state. For example, the reference memory transistor may first be erased by an erase operation and then partially written by a partial polarization operation. Alternatively, the reference memory transistor may first be written by a write operation and then partially erased by a partial polarization operation. Furthermore, it should be noted that a partially polarized reference memory transistor is periodically refreshed to ensure that the partially polarized state is maintained. Preconditioning or refreshing of the reference memory transistor can be carried out in various ways, as will be understood by those skilled in the art.

[0084] In some embodiments, the reference memory transistor can be partially erased or written during the manufacturing process (so-called one-time writeable) or in the field. In large memory arrays, statistical distributions and manufacturing variations are expected to affect transistor parameters across long bit lines, long word lines, each die, each wafer, or wafer lot, resulting in variations in threshold voltage, on / off current range, and sensitivity to temperature fluctuations. In some embodiments, the reference memory transistor is constructed identically to the memory transistor and is electrically written to or erased to an intermediate state between the write and erase states of the memory transistor. Furthermore, in some embodiments, it is preferable that the reference memory transistor be located as physically close as possible to the memory transistor. By configuring it in this way, the reference memory transistor can track variations in the memory transistor across manufacturing process variations and operating temperature variations. The reference memory transistor in embodiments of this disclosure utilizes the stability of the write and erase polarization states of each memory transistor. Such stability ensures that the written or erased transistor state is maintained for relatively long periods (typically minutes, hours, days, weeks, or longer) even while operating over a wide temperature range. In some embodiments, the reference memory transistor of the present disclosure is periodically refreshed by read operations and subsequent erase / write operations as necessary to compensate for threshold voltage drift that may occur over time.

[0085] Figures 9(a) and (b) are timing diagrams showing the voltage and timing conditions for performing a partial polarization operation to achieve a partial polarization state in the reference memory transistor of the memory device in embodiments of the present disclosure. Specifically, Figures 9(a) and (b) show the voltage and timing conditions that can be used to perform a partial polarization operation by performing an erase operation on only one current terminal, and further by shortening the erase / write period. In Figures 9(a) and (b), curve 312 represents the word line voltage V applied to the word line WLx of the reference memory transistor selected as the access target. WL Curve 314 shows the word line voltage V applied to the word line of an unselected memory transistor that shares the same common bit line as the selected reference memory transistor (i.e., on the same memory string). WL_UnSel This is shown. Curve 316 shows the word line voltage V applied to the word line of the precharge transistor associated with the selected reference memory transistor. WL_PCH This shows that curve 318 represents the bit line voltage V of the common bit line associated with the selected memory transistor. BL_REF This shows that curve 320 represents the source line voltage V of the common source line associated with the selected memory transistor. SL_RE This indicates that, if necessary, a prohibition voltage may be applied to the unselected bit lines that share the same word lines of the selected memory transistors to avoid interference with the data stored in the unselected memory transistors.

[0086] Figure 9(a) shows a partial erase operation, which in some embodiments is achieved by performing an erase operation on the drain terminal (bit line) of a selected reference memory transistor. Referring to Figure 9(a), in order to perform an erase operation on the drain terminal to achieve a partial erase operation, the voltage of the word line of the selected reference memory transistor is biased to a positive voltage (e.g., 3V) relative to the bit line. On the other hand, the source line is biased to a voltage that prevents an erase operation on the source terminal of the selected reference memory transistor. In one example, the selected reference memory transistor has its gate terminal (word line) biased to 3V, its drain terminal (bit line) biased to 0V, and its source terminal (source line) biased to 1-1.5V. The partial erase operation starts from a setup period from time T0 to time T1, during which a precharge operation is performed to set the word line voltage. During this setup period, the word line voltage V of the selected memory transistor WL Increase the voltage to an intermediate voltage (e.g., 1V), and the word line voltage of the unselected memory transistor V WL_UnSel Increase the erase disable voltage VINH_E (for example, 1 to 1.5V).

[0087] To perform the precharge operation, the word line voltage V for the precharge operation must be used. WL_PCH This is raised to a voltage sufficient to turn on the precharge transistor (e.g., 2-3V). In order to perform the erase operation to the drain terminal, the precharge operation raises the source line voltage of the reference memory transistor V SL_REF This is set to a VHP voltage that prohibits the erase operation, i.e., setting the ferroelectric dielectric layer to the first polarization state. In this embodiment, the VHP voltage is 1 to 1.5V. When the precharge operation is performed, the precharge transistor is turned on, and the bit line voltage of the reference memory transistor V BL_REF The voltage rises to VHP, and the source line voltage V SL_REF The bit line voltage V BL_REF This is equal to the source line voltage V. SL_REF It rises to VHP voltage.

[0088] Then, at time T1, the word line voltage V for pre-charge operation is WL_PCH It is deasserted to 0V. The common source line is electrically floating, and the source line voltage V SL_REF This is held at the VHP voltage by the parasitic capacitance between the common source line and the gate terminal of the memory transistor in the memory string. After the pre-charge operation is complete (i.e., after time T1), the bit line voltage of the reference memory transistor V BL_REF It discharges to 0V or ground.

[0089] By setting it in this way, at time T2, the erasure period (Te) is equal to the word line voltage V WL The process starts with the erase voltage VER (e.g., 3V) raised. Word line voltage V WL The erase voltage VER is maintained until time T3. A positive erase voltage is applied only between the gate and drain terminals of the selected reference memory transistor. Thus, the ferroelectric dielectric layer of the selected reference memory transistor is partially polarized by setting only the vicinity of the drain terminal to a first polarization state. Erasing to the source terminal is prohibited, and the polarization state is maintained in the opposite polarization state (e.g., a second polarization state) set by preconditioning. In this way, the selected reference memory transistor is set to a third threshold voltage value VTH3. At the end of the erase period Te (time T3), the word line voltage V WL and word line voltage V WL_UnSel The voltage drops to 0V. Word line voltage V for pre-charge operation. WL_PCH The bit line voltage rises instantaneously (from time T3 to time T4) to equalize the source line voltage. As a result, the source line voltage V SL_REF The voltage drops to 0V. This prepares the memory device for the next memory operation.

[0090] In other embodiments, partial erasure is further improved by shortening the erasure period at the drain terminal (bit line). In one embodiment, the erasure period is as shown by the dashed line 319 in Figure 9(a), starting after time T2, with the bit line voltage V BL_REF This is shortened by holding the erase-prohibited VHP voltage for tHP time. Bit line voltage V BL_REF By holding the erase-prohibition voltage VHP for a tHP time, the erase of the drain terminal can be prohibited for a tHP time. The erase period is the bit line voltage V BL_REF The process begins when the voltage finally drops to 0V and continues until time T3. That is, the erasure period Te from time T2 to time T3 is shortened by the amount of tHP time. Shortening the erasure period causes partial polarization of the ferroelectric dielectric layer at the drain terminal, which allows the third threshold voltage value VTH3 of the reference memory transistor to be set to a value between the first threshold voltage value and the second threshold voltage value.

[0091] Figure 9(b) shows a partial erase operation, which in some embodiments is achieved by performing an erase operation on the source terminal (source line) of a selected reference memory transistor. Referring to Figure 9(b), in order to perform an erase operation on the source terminal to achieve a partial erase operation, the voltage of the word line of the selected reference memory transistor is biased to a positive voltage (e.g., 3V) relative to the source line. On the other hand, the bit line is biased to a VHP voltage that prevents the erase operation on the drain terminal of the selected reference memory transistor. In one example, the selected reference memory transistor has its gate terminal (word line) biased to 3V, its source terminal (source line) biased to 0V, and its drain terminal (bit line) biased to 1-1.5V. The partial erase operation starts from a setup period from time T0 to time T1, during which a precharge operation is performed to set the word line voltage. During the setup period, the word line voltage of the selected memory transistor V... WL Increase the voltage to an intermediate voltage (e.g., 1V), and the word line voltage of the unselected memory transistor V WL_UnSelIncrease the erase disable voltage VINH_E (for example, 1 to 1.5V).

[0092] To perform the precharge operation, the word line voltage V for the precharge operation must be used. WL_PCH This is raised to a voltage sufficient to turn on the precharge transistor (e.g., 2-3V). In order to perform the erase operation to the source terminal, the precharge operation raises the source line voltage of the reference memory transistor V SL_REF Set the voltage to 0V. When the bit line voltage of the reference memory transistor is set to 0V and the precharge transistor is turned on, the source line voltage V SL_REF The bit line voltage V BL_REF , that is, it becomes equal to 0V.

[0093] Then, at time T1, the word line voltage V for pre-charge operation is WL_PCH The voltage is deasserted to 0V. The common source line becomes electrically floating, and the source line voltage V SL This is held at 0V or virtual ground by parasitic capacitance between the common source line and the gate terminal of the memory transistor in the memory string. At time T2, the bit line voltage V of the reference memory transistor BL_REF The voltage rises to VHP (e.g., 1V), which prevents the erase operation at the drain terminal of the reference memory transistor.

[0094] By setting it in this way, at time T2, the erasure period (Te) is equal to the word line voltage V WL The process starts with the erase voltage VER (e.g., 3V) raised. Word line voltage V WLThe erase voltage VER is maintained until time T3. A positive erase voltage is applied only between the gate and source terminals of the selected reference memory transistor. Thus, the ferroelectric dielectric layer of the selected reference memory transistor is partially polarized by setting only the vicinity of the source terminal to a first polarization state. Erasing to the drain terminal is prohibited, and the polarization state is maintained in the opposite polarization state (e.g., a second polarization state) set by preconditioning. In this way, the selected reference memory transistor is set to a third threshold voltage value VTH3. At the end of the erase period Te (time T3), the word line voltage V WL and word line voltage V WL_UnSel It drops to 0V. Also, the bit line voltage V of the reference memory transistor BL_REF It also drops to 0V. Word line voltage V for pre-charge operation WL_PCH The bit line voltage rises instantaneously (from time T3 to time T4) to equalize the source line voltage. As a result, the source line voltage V SL_REF This is set to 0V. This prepares the memory device for the next memory operation.

[0095] In other embodiments, partial erasure can be achieved by shortening the erasure period at the source terminal (source line). In one embodiment, a pre-charge word line voltage V is used before time T3. WL_PCH The erasure period can be shortened by asserting and ending the erasure period before time T3. For example, dashed line 317d, word line voltage V for precharge operation. WL_PCH By asserting this, the source erasure period can be terminated earlier by the amount of the tHP time. When the precharge transistor is turned on, the source line voltage V of the reference memory transistor is activated. SL_REF The bit line voltage V is set to the erase-prohibition voltage VHP. BL_REF This becomes equal to the source line voltage V. SL_REFThe voltage rises to VHP, and the erase operation to the source terminal is completed. By shortening the erase time, the ferroelectric dielectric layer at the source terminal becomes partially polarized, which allows the third threshold voltage value VTH3 of the reference memory transistor to be set to a value between the first threshold voltage value and the second threshold voltage value.

[0096] Figures 10(a) and (b) are timing diagrams showing voltage and timing conditions for performing a partial polarization operation to achieve a partially polarized state in a reference memory transistor of a memory device in another embodiment of the present disclosure. Similar elements in Figures 9(a), 9(b), 10(a), and 10(b) are denoted by the same reference numerals and will not be described further. Specifically, Figures 10(a) and (b) show voltage and timing conditions that can be used to achieve a partial polarization operation by performing a weak erase operation on only one current terminal of the reference memory transistor. For example, Figure 10(a) shows a partial erase operation that, in some embodiments, is achieved by performing a weak erase operation on the drain terminal (bit line) of a selected reference memory transistor. The weak erase operation on the drain terminal is performed in a similar manner to the partial erase operation on the drain terminal, as described above with reference to Figure 9(a). Referring to Figure 10(a), in order to perform a weak erase operation on the drain terminal, after the end of the precharge period (i.e., after time T1), the bit line voltage V BL_REF Instead of reducing it to 0V as shown in Figure 9(a), it is reduced to a weaker erase voltage VWER that is greater than 0V. For example, a weaker erase voltage VWER is 0.5V. In this way, during the erase period, the voltage applied across the reference memory transistor (between the gate terminal and the drain terminal) is set to a weaker erase voltage VWER of 2.5V, which is lower than the complete erase voltage VER of 3V. By configuring it in this way, the amount of polarization of the ferroelectric dielectric layer at the drain terminal is reduced, and the reference memory transistor is set to a third threshold voltage value VTH3, which is between the first threshold voltage value VTH1 and the second threshold voltage value VTH2.

[0097] Figure 10(b) shows a partial erase operation, which in some embodiments is achieved by performing a weak erase operation on the source terminal (source line) of a selected reference memory transistor. The weak erase operation on the source terminal is performed in a similar manner to the partial erase operation on the source terminal, as described above with reference to Figure 9(b). In Figure 9(b), the bit line voltage V BL_REF The source line voltage V SL_REF To make it equal to 0V, it is set to 0V during the precharge period. Referring to Figure 10(b), in order to achieve a weak erase operation on the source terminal, the bit line voltage V is set to 0V during the precharge period (between time T0 and time T1). BL_REF The source line voltage VWER is set to a weak erase voltage greater than 0V (e.g., 0.5V). SL_REF The bit line voltage V BL_REF , that is, it becomes equal to a weak erase voltage (e.g., 0.5V). After the precharge period ends (after time T1), the bit line voltage V BL_REF The erase disable voltage is raised to VHP (e.g., 1V), preventing erasure to the drain terminal. In this way, during the erasure period, the voltage applied across the reference memory transistor (between the gate terminal and the source terminal) is set to a weaker erasure voltage VWER of 2.5V, which is lower than the full erasure voltage VER of 3V. By configuring it in this way, the polarization of the ferroelectric dielectric layer at the source terminal is reduced, and the reference memory transistor is set to a third threshold voltage value VTH3, which is between the first threshold voltage value VTH1 and the second threshold voltage value VTH2.

[0098] Figures 11(a) and (b) are timing diagrams showing voltage and timing conditions for performing a partial polarization operation to achieve a partially polarized state in a reference memory transistor of a memory device in another embodiment of the present disclosure. Similar elements in Figures 9(a), 9(b), 11(a), and 11(b) are denoted by the same reference numerals and are not described further. Specifically, Figures 11(a) and (b) show voltage and timing conditions that can be used to achieve a partial polarization operation by performing a write operation to only one current terminal of the reference memory transistor.

[0099] FIG. 11(a) shows a partial write operation realized by performing a write operation to the drain terminal (bit line) of a selected reference memory transistor in some embodiments. Referring to FIG. 11(a), in order to perform a write operation to the drain terminal to realize the partial write operation, the word line voltage of the selected reference memory transistor is biased to a negative voltage (e.g., -3V) with respect to the bit line. On the other hand, the source line is biased to a voltage that prohibits a write operation to the source terminal of the selected reference memory transistor. In one example, for the selected reference memory transistor, the gate terminal (word line) is biased to 0V, the drain terminal (bit line) is biased to 3V, and the source terminal (source line) is biased to 1.5V. The write operation starts from a setup period from time T0 to time T1, and during this setup period, the word line voltage V WL_PCH (e.g., 3V) is asserted to turn on the precharge transistor and start the precharge operation. By the precharge operation, the bit line voltage V BL_REF is set to a set voltage VSET that is lower than an intermediate voltage (e.g., 1.5V) used in the write operation. For example, the voltage VSET can be 0V. The source line voltage V SL_REF becomes equal to the bit line voltage V BL_REF by turning on the precharge transistor. And at time T1, the word line voltage V WL_PCH for the precharge operation is deasserted to 0V. After the end of the precharge operation, the bit line voltage V BL_REF rises to the intermediate voltage (e.g., 1.5V). On the other hand, the source line voltage V SL_REF is held at the set voltage VSET (e.g., 0V).

[0100] By setting it in this way, at time T2, the write period (Tp) is the word line voltage V of the unselected transistor WL_UnSelIt starts in a state where it has risen to the write inhibit voltage VINH_P (for example, 1.5 to 2 V). In this embodiment, the write inhibit voltage VINH_P is set to 1.5 V. The bit line voltage V of the reference memory transistor BL_REF rises by the amount of the write inhibit voltage VINH_P due to the connection between the common bit line and the gate terminals of all unselected memory transistors in the memory string. As a result, the bit line voltage V BL_REF rises to a write voltage VPR of 3 V, which is the sum of the intermediate voltage (1.5 V) and the write inhibit voltage VINH_P (1.5 V). On the other hand, the source line voltage rises from the VSET voltage (0 V) to the write inhibit voltage VINH_P (for example, 1.5 V) due to the connection with the gate terminals of the unselected memory transistors. As a result, writing to the source terminal is prohibited, and writing to the reference memory transistor is performed only at the drain terminal. In this way, the ferroelectric dielectric layer of the selected reference memory transistor is partially polarized by setting only the vicinity of the drain terminal to the second polarization state. In this way, the selected reference memory transistor is set to the third threshold voltage value VTH3. At the end of the write period Tp (time T3), the word line voltage V WL_UnSel and the bit line voltage V BL_REF drop to 0 V. When the word line voltage V WL_PCH for precharge operation is asserted to turn on the precharge transistor, the source line voltage V SL_REF becomes equal to the bit line voltage V BL_REF . Thereby, the memory device is ready for the next memory operation.

[0101] In other embodiments, the partial write operation is further improved by shortening the write period to the drain terminal (bit line). In one embodiment, the write period is shortened by reducing the bit line voltage V BL_REF to the write inhibit voltage VINH_P (1.5 V) over a tHP time before time T3, as shown by the dashed line 324 in FIG. 11(a). The bit line voltage V BL_REFBy reducing the voltage to a write-protected voltage over a tHP time, writing to the drain terminal can be prohibited for tHP time. That is, the writing period Tp from time T2 to time T3 is shortened by the amount of tHP time. Shortening the writing period causes partial polarization of the ferroelectric dielectric layer at the drain terminal, thereby setting the third threshold voltage value VTH3 of the reference memory transistor to a value between the first threshold voltage value and the second threshold voltage value.

[0102] Figure 11(b) illustrates a partial write operation, which in some embodiments is achieved by performing a write operation on the source terminal (source line) of a selected reference memory transistor. Referring to Figure 11(b), in order to perform a write operation on the source terminal to achieve a partial write operation, the voltage of the word line of the selected reference memory transistor is biased to a negative voltage (e.g., -3V) relative to the source line. On the other hand, the bit line is biased to a write-block voltage to prevent a write operation on the drain terminal of the selected reference memory transistor. In one example, the selected reference memory transistor is biased to 0V at the gate terminal (word line), 3V at the source terminal (source line), and 1.5V at the drain terminal (bit line). The write operation starts from a setup period from time T0 to T1, during which the word line voltage V for pre-charge operation is applied. WL_PCH Assert (for example, 3V) to turn on the precharge transistor and start the precharge operation. The precharge operation causes the bit line voltage V BL_REF This is set to an intermediate voltage (e.g., 1.5V). By turning on the precharge transistor, the source line voltage V SL_REF The bit line voltage V BL_REF This becomes equal to the word line voltage V for pre-charge operation at time T1. WL_PCH The bit line voltage V is deasserted to 0V, etc. After the precharge operation is complete, the bit line voltage V BL_REF The voltage drops to a set voltage VSET (e.g., 0V) which is lower than the intermediate voltage (1.5V). On the other hand, the source line voltage V SL_REFIt is maintained at an intermediate voltage (for example, 1.5V).

[0103] By setting it this way, at time T2, the write period (Tp) is set to the word line voltage V of the unselected transistor. WL_UnSel The process starts with the write-protect voltage VINH_P (e.g., 1.5~2V) rising. In this embodiment, the write-protect voltage VINH_P is set to 1.5V. The bit line voltage V of the reference memory transistor BL_REF The connection between the gate terminals of all unselected memory transistors in the memory string and the common bit line causes the VSET voltage to rise by the amount of the write-protect voltage VINH_P. As a result, the bit line voltage V BL_REF The voltage rises to the write-protect voltage VINH_P (e.g., 1.5V). Meanwhile, the source line voltage V SL_REF The connection to the gate terminal of the unselected memory transistor causes the voltage to rise from the intermediate voltage (1.5V) to the write voltage VPR, which is the sum of the intermediate voltage (1.5V) and the write-protect voltage VINH_P (1.5V), resulting in a write voltage of 3V. As a result, writing to the drain terminal is prohibited, and writing to the reference memory transistor is performed only at the source terminal. In this way, the ferroelectric dielectric layer of the selected reference memory transistor is partially polarized by setting only the vicinity of the source terminal to a second polarized state. The selected reference memory transistor is set to a third threshold voltage value VTH3. At the end of the writing period Tp (time T3), the word line voltage V WL_UnSel and bit line voltage V BL_REF The voltage drops to 0V. Word line voltage V for pre-charge operation. WL_PCH Asserting this and turning on the precharge transistor results in a source line voltage V SL_REF The bit line voltage V BL_REF This becomes equal to . This prepares the memory device for the next memory operation.

[0104] In other embodiments, partial writing operations are further improved by shortening the writing period at the source terminal (source line). In one embodiment, the writing period is as shown by the dashed line 326 in Figure 11(b), with a word line voltage V for pre-charging operation over a period of tHP before time T3. WL_PCH This is shortened by asserting (for example, 3V). This turns on the precharge transistor and the source line voltage V SL_REF The bit line voltage V BL_REF This becomes equal to (1.5V write-protect voltage). As a result, the source line voltage V SL_REF The source line voltage V drops to 1.5V, as shown by the dashed line 328 in Figure 11(b). SL_REF By reducing the voltage to the write-protected voltage over the tHP time, writing to the source terminal can be prohibited for the tHP time. That is, the writing period Tp from time T2 to time T3 is shortened by the amount of the tHP time. Shortening the writing period causes partial polarization of the ferroelectric dielectric layer at the source terminal, thereby setting the third threshold voltage value VTH3 of the reference memory transistor to a value between the first threshold voltage value and the second threshold voltage value.

[0105] Figures 12(a) and (b) are timing diagrams showing voltage and timing conditions for performing a partial polarization operation to achieve a partially polarized state in a reference memory transistor of a memory device in another embodiment of the present disclosure. Similar elements in Figures 9(a), 9(b), 12(a), and 12(b) are denoted by the same reference numerals and will not be described further. Specifically, Figures 12(a) and (b) show voltage and timing conditions that can be used to achieve a partial polarization operation by performing a weak write operation to only one current terminal of the reference memory transistor. For example, Figure 12(a) shows a partial write operation that, in some embodiments, is achieved by performing a weak write operation to the drain terminal (bit line) of a selected reference memory transistor. The weak write operation to the drain terminal is performed in a similar manner to the partial write operation to the drain terminal, as described above with reference to Figure 11(a). Referring to Figure 12(a), in order to perform a weak write operation to the drain terminal, at the end of the precharge period (i.e., after time T1), the bit line voltage V BL_REF Instead of setting the intermediate voltage to 1.5V as shown in Figure 11(a), it is set to an intermediate voltage lower than the intermediate voltage shown in Figure 11(a) (for example, 1V). In this way, during the writing period, the voltage applied across the reference memory transistor (between the gate terminal and the drain terminal) is set to a weaker writing voltage of -2.5V, which is lower than the full writing voltage VPR of -3V. By configuring it in this way, the polarization of the ferroelectric dielectric layer at the drain terminal is reduced, and the reference memory transistor is set to a third threshold voltage value VTH3, which is between the first threshold voltage value VTH1 and the second threshold voltage value VTH2.

[0106] Figure 12(b) shows a partial write operation, which in some embodiments is achieved by performing a weak write operation to the source terminal (source line) of a selected reference memory transistor. The weak write operation to the source terminal is performed in a similar manner to the partial write operation to the source terminal, as described above with reference to Figure 11(b). In Figure 11(b), the bit line voltage VBL_REF The source line voltage V SL_REF To make it equal to 1.5V, the intermediate voltage is set to 1.5V during the precharge period. Referring to Figure 12(b), in order to achieve a weak write operation to the source terminal, the bit line voltage V is set during the precharge period (between time T0 and time T1). BL_REF The source line voltage V is set to a lower intermediate voltage (e.g., 1V) than the intermediate voltage (1.5V) shown in Figure 11(b). SL_REF The bit line voltage V BL_REF , that is, it becomes equal to the intermediate voltage (for example, 1V). After the end of the pre-charge period (after time T1), the bit line voltage V BL_REF The voltage drops to a set voltage VSET (e.g., 0V). In this way, during the writing period, the voltage applied across the reference memory transistor (between the gate terminal and the source terminal) is set to a weaker write voltage VWPR of -2.5V, which is lower than the full write voltage VPR of -3V. By configuring it in this way, the polarization of the ferroelectric dielectric layer at the source terminal is reduced, and the reference memory transistor is set to a third threshold voltage value VTH3, which is between the first threshold voltage value VTH1 and the second threshold voltage value VTH2.

[0107] Figures 13(a) and (b) are timing diagrams showing voltage and timing conditions for performing a partial polarization operation to achieve a partially polarized state in a reference memory transistor of a memory device in another embodiment of the present disclosure. Similar elements in Figures 9(a), 9(b), 13(a), and 13(b) are denoted by the same reference numerals and are not described further. Specifically, Figures 13(a) and (b) show voltage and timing conditions that can be used to achieve a partial polarization operation by performing a weak erase or weak write operation on both current terminals of a reference memory transistor. For example, Figure 13(a) shows a partial erase operation that, in some embodiments, is achieved by performing a weak erase operation on the drain and source terminals (bit line and source line) of a selected reference memory transistor. The weak erase operation on the drain and source terminals is performed in a similar manner to the partial erase operation on the drain terminal, as described above with reference to Figure 9(a) or Figure 10(a). Referring to Figure 13(a), in order to achieve a weak erase operation on the drain and source terminals, the bit line voltage V is set during the precharge period (from time T0 to time T1). BL_REF Increase the source line voltage VWER to a weak erase voltage less than the erase-prohibition voltage VINH_E. For example, a weak erase voltage VWER is 0.5V. SL_REF The bit line voltage V BL_REF To make it equal to the original, it is similarly biased to a weaker erase voltage VWER. At the end of the precharge period (i.e., after time T1), the word line voltage VWL_PCH for precharge operation is either discharged or left asserted (dashed line). During the erase period (between time T2 and time T3), the voltage applied across the reference memory transistor (between the gate, drain, and source terminals) is set to a weaker erase voltage VWER of 2.5V, which is lower than the full erase voltage VER of 3V. By configuring it in this way, the polarization level of the ferroelectric dielectric layer at the drain and source terminals is reduced, and the reference memory transistor is set to a third threshold voltage value VTH3, which is between the first threshold voltage value VTH1 and the second threshold voltage value VTH2.

[0108] Figure 13(b) shows a partial write operation, which in some embodiments is achieved by performing a weak write operation on the drain and source terminals (bit line and source line) of a selected reference memory transistor. The weak write operation on the drain and source terminals is performed in a similar manner to the partial write operation on the source terminal, as described above with reference to Figure 11(b). Referring to Figure 13(b), in order to achieve the weak write operation on the drain and source terminals, the bit line voltage V is set during the precharge period (from time T0 to time T1). BL_REF The source line voltage V is set to a lower intermediate voltage (e.g., 1V) than the intermediate voltage (1.5V) shown in Figure 11(b). SL_REF The bit line voltage V BL_REF , that is, it becomes equal to the intermediate voltage (e.g., 1V). After the end of the precharge period (after time T1), unlike in Figure 12(b), the bit line voltage V BL_REF The word line voltage V of the unselected transistors does not decrease. Instead, the connection between the bit line and source line and the gate terminal of all unselected memory transistors in the memory string causes the word line voltage V of the unselected transistors to decrease at the start of the write period (time T2). WL_UnSel The write-protect voltage VINH_P (for example, 1.5V) rises, and the bit line voltage V BL_REF and source line voltage V SL_REF Both voltages rise from an intermediate voltage (1V) to a weak write voltage (e.g., 2.5V), which is the sum of the intermediate voltage and the write-protect voltage VINH_P (1.5V).

[0109] In this way, during the writing period, the voltage applied across the reference memory transistor (between the gate, drain terminal, and source terminal) is set to a weaker write voltage VWPR of -2.5V, which is lower than the full write voltage VPR of -3V. By configuring it in this way, the polarization of the ferroelectric dielectric layer at the drain and source terminals is reduced, and the reference memory transistor is set to a third threshold voltage value VTH3, which is between the first threshold voltage value VTH1 and the second threshold voltage value VTH2.

[0110] In embodiments of this disclosure, the memory device uses the partial polarization operation described above to set one or more reference storage transistors to a partially polarized state having a threshold voltage value between the threshold voltage value of an erased storage transistor and the threshold voltage value of a written storage transistor. In this specification, a partially polarized state refers to a state in which the ferroelectric dielectric layer has a polarization level between a positive polarization state associated with the erase state and a negative polarization state associated with the write state. The partially polarized state of the reference memory transistor is used as a reference signal for reading stored memory data from the memory transistor. Figure 14 shows an exemplary threshold voltage distribution in a memory device, illustrating three polarization states in several embodiments. Referring to Figure 14, curve 340 represents the distribution of erased memory cells, which have a threshold voltage near the erase threshold voltage VTH-erase. Curve 344 represents the distribution of written memory cells, which have a threshold voltage near the write threshold voltage VTH-program. Specifically, the erase threshold voltage VTH-erase and the write threshold voltage VTH-program represent the erase and write operations for achieving positive and negative polarization states in a ferroelectric memory transistor. Curve 342 represents the distribution of partially erased or partially written memory cells. These partially polarized memory cells have threshold voltages near the reference threshold voltage VTH-reference. Specifically, the partially polarized memory cells have polarization levels between positive and negative polarization states in the ferroelectric dielectric layer. By appropriately partially erasing or partially writing the reference memory transistor, a reference threshold voltage can be set sufficiently far from the erase and write threshold voltages. This makes it possible to use the reference threshold voltage as a reference signal in the read operation to distinguish between the erased and written states of the memory transistor.

[0111] The partial writing and erasing of memory transistors in this disclosure can be used to store two or more binary bits of information per memory transistor. For example, intermediate memory states associated with threshold voltages VTH1 (e.g., Vth-erase), VTH2 (e.g., Vth-program), and VTH3 (e.g., Vth-reference) can present 1.5 bits of information, thereby increasing memory density by 50%. This is possible because each of the three polarization states VTH1, VTH2, and VTH3 is relatively stable. Similarly, ferroelectric memory transistors in embodiments of this disclosure can store two or more bits of information per transistor by adjusting the pulse width (time) or pulse amplitude, as long as all states fall within the polarization window of the memory transistor. In some embodiments, ferroelectric memory transistors can be erased or written with precision to provide a semi-analog memory device.

[0112] Alternatively, the durability of a single-bit ferroelectric memory transistor (the maximum number of erase / write operations for each memory transistor) can be improved by avoiding polarization and depolarization up to the full memory window of the memory transistor. For example, if the fully polarized memory polarization window is in the range of 0.0V to 1.0V, operating the memory transistor in the range of 0.2V to 0.8V reduces polarization stress, thereby extending the transistor's durability and mitigating other adverse conditions of ferroelectrics, such as memory layer imprinting.

[0113] Next, a circuit and method for using a reference signal generated by partial polarization operation in readout operation will be described. Specifically, the reference signal is used by the sense amplifier circuit of the memory device to distinguish between erased memory cells and written memory cells.

[0114] In the first embodiment, the memory device uses this reference signal as a timing signal to determine when to latch the bit line signal detected by the sense amplifier circuit as a valid sense amplifier output signal. In embodiments of the present disclosure, memory transistors in the memory device are read by applying a read voltage (e.g., 2V) to the word line of a selected memory transistor and charging the common bit line to a predetermined voltage Vbit (e.g., 0.5V). The selected memory transistor can then modulate the common bit line based on the conductivity state of the memory transistor. The bit line signal is generated on the common bit line and detected as read data by the associated sense amplifier. Figure 15A is a plot showing the generation of bit line signals during read operation in several embodiments. Referring to Figure 15A, curve 350 shows a bit line signal associated with a written memory cell, which has a higher threshold voltage value and becomes non-conductive in response to the read voltage applied to the gate terminal. In this specification, a written memory cell is also referred to as an "off-cell" to indicate that the memory cell becomes non-conductive in response to the read voltage applied to the gate terminal. Ideally, to deconduct a memory cell, the off-cell bit line signal should be at a constant voltage level Vbit. However, in reality, as shown by curve 350 in Figure 15A, the off-cell bit line signal decreases over time due to leakage current.

[0115] In Figure 15A, curve 354 shows the bit line signal associated with an erased memory cell. This memory cell has a lower threshold voltage value and becomes conductive in response to a read voltage applied to its gate terminal. In this specification, the erased memory cell is also referred to as the "on-cell" to indicate that it becomes conductive in response to a read voltage applied to its gate terminal. When a read voltage is applied to the gate terminal, the conductive on-cell discharges its bit line, and the on-cell bit line signal decreases at a first rate over time, as shown by curve 354 in Figure 15A. Over a given signal generation period, a voltage difference is generated between the erased memory cell (on-cell) and the written memory cell (off-cell).

[0116] Figure 15A further shows the bit line signal (curve 352) from a reference memory transistor (reference cell) that has been partially erased or partially written using one or more of the partial polarization operations described above. The bit line signal of the reference cell has a threshold voltage between the erased memory cell and the written memory cell in response to the read voltage applied to the gate terminal. When the read voltage is applied to the gate terminal, the reference cell discharges its bit line, and the bit line signal of the reference cell decreases at a second rate over time, as shown in curve 352 in Figure 15A. Specifically, the bit line signal of the reference cell decreases at a slower rate than the on-cell bit line signal and at a faster rate than the off-cell bit line signal. As a result, over a predetermined signal generation period, the bit line signal of the reference cell has a signal value between the bit line signal of the erased memory cell and the bit line signal of the written memory cell, and can be used as a reference signal to distinguish between the erased state and the written state of the memory cell.

[0117] Figure 15B is a plot illustrating the sense amplifier operation using a reference cell reference signal to determine the latch time of the sense amplifier output signal in several embodiments. Referring to Figure 15B, in the detection phase of a read operation, the sense amplifier input node detects the bit line signal, and when the bit line signal reaches a given detection threshold, the sense amplifier output signal (SAOUT) changes or flips the logic state. For an erased memory cell with bit line current conducting, the sense amplifier output signal SAOUT_ON (curve 364) changes the state at an earlier timing compared to a written memory cell with no bit line current conducting. The sense amplifier output signal SAOUT_OFF (curve 360) of a written cell eventually changes the state due to leakage current that discharges the bit line signal.

[0118] Figure 15B further illustrates the sense amplifier output signal SAOUT_REF (curve 362) of the reference cell. The partially polarized reference cell discharges the bit lines at a slower rate than the erase cell. Therefore, the sense amplifier output signal SAOUT_REF changes state after the signal SAOUT_ON and before the signal SAOUT_OFF. In embodiments of this disclosure, the logical state of the sense amplifier output signal SAOUT_REF is used as a reference signal for latching the sense amplifier output of the memory cell. That is, the sense amplifier circuit of the memory device latches the logical value of the memory cell to be read in response to a change in the logical state of the sense amplifier output signal SAOUT_REF. In an erased memory cell, the state of the sense amplifier output signal changes, but in a written memory cell, the state of the sense amplifier output signal does not yet change.

[0119] Figure 16 is a schematic diagram of a sense amplifier circuit in several embodiments that uses a reference signal as a sense amplifier latch signal. Referring to Figure 16, the sense amplifier circuit includes a sense amplifier 422 connected to a bit line 404, such as a bit line selected by each bit line selector 220 (Figure 2). During operation, the memory transistor to be accessed is activated by its associated word line signal. The bit line associated with the memory transistor to be accessed is selected by the bit line selector in response to the bit line selection signal. Each sense amplifier 422 detects its corresponding bit line 404 and generates a sense amplifier output signal SAOUT, such as output signals SAOUT0 to SAOUTn. The generated sense amplifier output signals SAOUT are provided to each data latch 424. Each data latch 424 latches its corresponding sense amplifier output signal SAOUT in response to a latch signal and generates data output signals DO (e.g., DO0 to DOn).

[0120] A sense amplifier 416 ("reference sense amplifier") is provided to detect a reference signal RBLx (node ​​414) generated by one or more reference memory transistors. The reference memory transistors are partially polarized to have a threshold voltage between the erase threshold voltage and the write threshold voltage of the memory transistors. During operation, the reference memory transistors are activated for access by their associated reference word line signals. Reference bit line signals are provided to their associated common bit lines. In some embodiments, multiple reference memory transistors are used, and the reference signal RBLx is generated by averaging a combination of bit line signals from multiple reference memory transistors. For example, multiple reference memory transistors are partially polarized to a third threshold voltage value between the erase threshold voltage and the write threshold voltage of the memory transistors and activated for access by asserting their corresponding reference word lines. In this embodiment, reference bit lines REF_BL0 to REF_BLm associated with multiple reference memory transistors are connected to a bit line selector 420. The bit line selector 420, in response to the reference selection signal RBL_SEL, selects multiple reference bit lines from bit lines REF_BL0 to REF_BLm and connects all selected reference bit lines to the reference signal node 414. When multiple reference bit lines are activated and connected to the reference signal node 414, charge sharing occurs among the activated reference bit lines, and an average signal is obtained as the reference signal RBLx. Averaging multiple reference bit lines has the advantage of generating a more accurate reference signal.

[0121] Using the reference signal RBLx (node ​​414) generated in this manner, the reference sense amplifier 416 generates a sense amplifier output signal (node ​​418) which is used as the latch signal TREF of the data latch 424. Specifically, the reference sense amplifier 416 detects the reference signal RBLx. The output signal TREF then changes the logic state according to the partial polarization state of the reference memory transistor selected (by the bit line selector 420). The output signal TREF is used by the data latch 424 to indicate the timing for latching the sense amplifier output signal SAOUT and generating the data output signal DO (e.g., DO0~DOn).

[0122] In the embodiment shown in Figure 16, the sense amplifier 422 is implemented as a single-ended sense amplifier, and the reference signal is used as a timing signal to latch the sense amplifier output signal at a given timing after the start of generation of the bit line signal. In other embodiments, the sense amplifier can be implemented as a differential sense amplifier, in which case a reference signal is used as a sense amplifier reference for comparison with the detected bit line signal.

[0123] Figure 17 is a schematic diagram of a sense amplifier circuit in several embodiments, including a differential sense amplifier that uses a reference signal as a sense amplifier reference signal (voltage). Referring to Figure 17, the sense amplifier circuit includes a sense amplifier 442 connected to a bit line 404 (e.g., a bit line selected by each bit line selector 220 (Figure 2)). Each sense amplifier 442 is a differential sense amplifier, with the signal of its corresponding bit line 404 as its first input and the sense amplifier reference voltage VREF as its second input. Each sense amplifier 442 detects the signal of its corresponding bit line 404 and generates a sense amplifier output signal SAOUT (e.g., output signals SAOUT0 to SAOUTn) by comparing the detected bit line signal with the sense amplifier reference signal. The generated sense amplifier output signals SAOUT are provided to each data latch 444. Each data latch 444 latches or holds its corresponding sense amplifier output signal SAOUT and outputs it as a data output signal DO (e.g., DO0 to DOn).

[0124] In this embodiment, the sense amplifier reference voltage VREF is generated from a reference signal RBLx. The reference signal RBLx is a reference signal generated from one or more reference memory transistors that are partially polarized to have a threshold voltage between the erase threshold voltage and the write threshold voltage of the memory transistors. In some embodiments, as described above with reference to Figure 16, multiple reference memory transistors are used, and the reference signal RBLx is generated by averaging a combination of bit line signals from the multiple reference memory transistors. For example, reference bit lines REF_BL0~REF_BLm associated with multiple reference memory transistors are connected to a bit line selector 420. In response to a reference selection signal RBL_SEL, the bit line selector 420 selects multiple reference bit lines from the bit lines REF_BL0~REF_BLm and connects all selected reference bit lines to a reference signal node 434. Once the multiple reference bit lines are activated and connected to the reference signal node 434, charge sharing occurs between the activated reference bit lines, and the average signal is obtained as the reference signal RBLx.

[0125] In this embodiment, the reference signal RBLx (node ​​434) is buffered or amplified by the operational amplifier circuit 440 to generate a copy of the reference signal used as the sense amplifier reference voltage VREF. In some embodiments, the operational amplifier circuit 440 includes an operational amplifier 436 that receives the reference signal RBLx at its non-inverting input terminal. The inverting input terminal is connected to a negative feedback loop. The operational amplifier 436 drives the gate terminal of an NMOS transistor 438. The drain terminal (node ​​435) of the NMOS transistor 438 is biased by a current source 439 connected to a positive supply voltage Vdd. The current source 439 supplies current I REF The source terminal of the NMOS transistor 438 is connected to a negative supply voltage Vss or ground voltage. The drain terminal (node ​​435) of the NMOS transistor 438 provides a reference signal VREF, which is input to the inverting input terminal of the operational amplifier 436 via a feedback loop. This reference signal VREF is duplicated or distributed to the second input terminals of multiple sense amplifiers 442 that detect the bit line signals of memory transistors selected for reading.

[0126] In the embodiments described above, the reference memory transistor can be formed from one or more memory strings, such as a memory string provided on a reference plane (Figure 4) or a memory string provided on a reference stack (Figure 5). In these cases, the common bit line associated with the reference memory string becomes a dedicated reference bit line connected only to the reference memory transistor. In some embodiments, the reference memory transistor is formed as a reference slice (Figure 6) in which one or more memory transistors in the memory string are designated as reference memory transistors. In this case, the memory string includes both memory transistors and reference memory transistors, and the memory transistors and reference memory transistors on the same memory string share the same common bit line. In some embodiments, a sequential read method is used to access the memory transistors and reference memory transistors that share the same common bit line.

[0127] Figure 18A is a schematic diagram of a memory circuit in which a reference memory transistor is included in a reference slice in an embodiment of the present disclosure. Figure 18B is a timing diagram showing a sequential read method in an embodiment of the present disclosure. Referring to Figure 18A, in the reference slice configuration, the memory string 512 of memory transistor 502 includes one or more memory transistors designated as reference memory transistor 516 (also referred to as the “reference memory cell”). Thus, the reference memory cell 516 shares the same bit lines 504 and source lines 506 as memory transistor 502. Each memory transistor is accessed by its associated word line 508 (e.g., WL0, WL1, WL2, ...). The reference memory transistor is accessed by the reference word line REF_WL518.

[0128] The common bit line 504 is connected to the bit line selector 520. Specifically, the bit line selector 520 is connected to all bit lines associated with the same data bit across p+1 memory pages (e.g., memory pages P0 to Pp). In response to the selection signal BL_SEL, the bit line selector 520 selects one bit line as the selected bit line signal BL0x and connects it to the sense amplifier circuit for sensing. In this embodiment, the sense amplifier circuit is implemented as a differential sense amplifier 522, which generates the sense amplifier output signal SAOUT0 on the output node 524.

[0129] In embodiments of this disclosure, a reference signal for a read operation is read sequentially along with the memory data in a sequential read operation. Specifically, the reference memory transistor is partially polarized using the partial erase or partial write operation described above so that the partial polarization state of the reference memory transistor can be used as a reference signal for read operations of other memory transistors in the same memory string. The read operation of the sequential read method will be described with reference to Figure 18B. In the example shown in Figure 18B, the read operation sequentially reads the reference memory transistor and then the selected memory transistor. For example, the reference memory transistor may be read first, followed by the selected memory transistor. The read order in Figure 18B is an example and is not intended to limit it. In other embodiments, the read operation is performed by first reading one or more memory transistors, followed by reading the reference memory transistor.

[0130] In the sequential read operation shown in Figure 18B, the memory device first accesses the reference memory transistor 516 by asserting the associated word line REF_WL (curve 538). A bit line signal is generated as a result of partial polarization of the reference memory transistor (curve 540). The bit line selector 520 selects the bit line BL0 to be accessed, and the sense amplifier 522 detects the bit line signal. The detected data value is stored in the sense amplifier circuit 522 as the sense amplifier reference signal VREF. For example, the sense amplifier reference signal VREF is stored in one of the differential input nodes of the differential sense amplifier 522.

[0131] Next, the word line REF_WL (curve 538) is deasserted, and the word line WLx associated with the selected memory transistor 502 is asserted, as shown in curve 532. As a result, a bit line signal is generated. In the case of a written memory transistor, the bit line is discharged only by leakage current, and the bit line signal (curve 534) has a small downward slope. In the case of an erased memory transistor, the bit line is discharged by the conductive memory transistor, and the leakage current and bit line signal (curve 536) have a larger downward slope. After the generation of the bit line signal, the sense amplifier 522 detects the bit line signal and compares the detected bit line signal with the sense amplifier reference signal VREF already stored in the sense amplifier to generate the sense amplifier output signal SAOUT. The sense amplifier output signal SAOUT is provided to the data latch 524. The data latch 524 latches or holds the sense amplifier output signal SAOUT and provides it as a data output signal DO.

[0132] It should be noted that the sense amplifier reference signal VREF does not need to be read out each time a memory transistor in the memory string 512 is read. The read sense amplifier reference signal VREF is stored in the sense amplifier 522, and the sense amplifier reference signal VREF stored in the sense amplifier 522 is used to compare with the detected bit line signals of multiple memory transistors. In addition, the reference signal VREF stored in the sense amplifier 522 is updated periodically, such as when the reference memory transistor is periodically refreshed.

[0133] Furthermore, in some embodiments, a memory transistor near the bit line selector within the memory string may be designated as the reference memory transistor. By doing so, reading the bit line signal from the reference memory transistor becomes faster than reading the bit line signal from memory transistors further down the memory string, thereby reducing the latency of sequential read operations.

[0134] Average signal as reference signal

[0135] In another aspect of the present disclosure, a semiconductor memory device including a three-dimensional array of NOR-type memory strings of thin-film ferroelectric memory transistors generates a reference signal for read operations by averaging a first signal related to the write state of the ferroelectric memory transistors and a second signal related to the erase state of the ferroelectric memory transistors. The reference signal has a value distinguishable from the write state threshold voltage and the erase state threshold voltage of the ferroelectric memory transistors and can be effectively applied to determine the logic state of the ferroelectric memory transistors in read operations.

[0136] Figure 19A is a plot showing the generation of a reference signal for read operations using an averaging method (averaging scheme) in several embodiments. Figure 19B is a schematic diagram showing the implementation of the averaging scheme in several embodiments. Referring to Figure 19A, in the averaging scheme, a reference signal for read operations can be generated by averaging one or more written memory cells and one or more erased memory cells. In some embodiments, the same number of written and erased memory cells are used. For example, a first group of memory transistors including one or more memory transistors is designated as a reference memory transistor and written to. A second group of memory transistors including one or more memory transistors is designated as a reference memory transistor and erased. When a written reference memory transistor is read, a bit line signal shown in curve 552 is generated. When an erased reference memory transistor is read, a bit line signal shown in curve 554 is generated. By averaging the written bit line signal and the erased bit line signal, a reference signal RBL (curve 556) having an intermediate signal value between the written bit line signal value and the erased bit line signal value can be generated. By using the reference signal RBL as the reference signal for the read operation, it is possible to reliably distinguish between the write memory transistor and the erase memory transistor. For example, as described above, the reference signal RBL is applied to a single-ended sense amplifier circuit configuration (Figure 16) or a differential sense amplifier circuit configuration (Figure 17), thereby enabling the detection of the bit line signal of the memory transistor to be accessed.

[0137] Figure 19B illustrates how an averaging scheme is implemented using a bit line selector. Referring to Figure 19B, the bit line selector 580 is connected to a first group of bit lines 560 (bit lines REF_BL0 to REF_BL2) associated with a designated reference memory transistor that is in the write state. The bit line selector 580 is also connected to a second group of bit lines 562 (bit lines REF_BL3 to REF_BL5) associated with a designated reference memory transistor that is in the erase state. In this embodiment, each group of bit lines contains three bit lines. The bit line selector 580 selects some or all of the bit lines connected to it in response to a selection signal BL_SEL. Specifically, to implement the averaging scheme, the bit line selector 580 receives a selection signal BL_SEL which selects or activates at least one written bit line from the first group of bit lines 560 and at least one erased bit line from the second group of bit lines 562. When two bit lines are selected and connected to output node 582, charge sharing occurs between the two bit lines, and the average signal of the written bit line and the erased bit line is generated as the reference signal RBLx on node 582.

[0138] In practice, multiple bit lines are selected from each bit group to improve the accuracy of the reference signal and reduce variability in the reference signal value. For example, the selection signal BL_SEL instructs the bit line selector 580 to select three bit lines from the first bit line group 560 and three bit lines from the second bit line group 562 for averaging. In one embodiment, the same number of written and erased bit lines are used to generate a reference signal having signal values ​​intermediate between the signal values ​​of the written bit lines and the signal values ​​of the erased bit lines. In other embodiments, different ratios of written and erased bit lines can be used to generate a reference signal that is close to either the signal values ​​of the written bit lines or the signal values ​​of the erased bit lines.

[0139] As described above, by applying the reference signal RBLx to a single-ended sense amplifier circuit configuration (Figure 16) or a differential sense amplifier circuit configuration (Figure 17), detection of the bit line signal of the memory transistor to be accessed can be achieved.

[0140] Reduce the memory window

[0141] According to yet another aspect of this disclosure, a ferroelectric memory transistor can operate such that its memory window is smaller than the saturated (or fully polarized) memory window between the written and erased states of the ferroelectric memory transistor. In this specification, the term “memory window” refers to the difference in threshold voltages between the write and erased states of a ferroelectric memory transistor. For example, the memory window (MW) of a ferroelectric memory transistor is given by MW = VT(write) - VT(erase), where VT(write) is the threshold voltage of the ferroelectric memory transistor in the write state (e.g., negative polarization) and VT(erase) is the threshold voltage of the ferroelectric memory transistor in the erase state (e.g., positive polarization). Typically, the memory window is defined by the erase threshold voltage at the lower limit of the voltage window and the write threshold voltage at the upper limit of the voltage window. In normal operation, a large memory window is desirable, and the memory window is extended as much as possible by fully polarizing the ferroelectric dielectric layer, for example, by exposing the ferroelectric dielectric layer to a relatively high write or erase voltage. In other words, memory transistors are typically written to achieve the highest possible write threshold voltage and erased to achieve the lowest possible erase threshold voltage. However, doing so may place excessive stress on the polarization phase of the ferroelectric dielectric material or require the use of an excessively high erase voltage to erase the memory transistor. Using an excessively high erase or write voltage may expose the memory cell to excessive electric field stress, limiting the durability of the memory device. In this specification, the “durability” of a memory transistor refers to the number of erase-write cycles before the ferroelectric memory transistor can no longer maintain its polarization cycle. Excessive electric fields applied to a memory transistor may result in a phenomenon called “imprint,” which alters the memory operation.

[0142] Embodiments of the present disclosure provide a novel operating mode for ferroelectric memory transistors, which has the advantage of mitigating or avoiding degradation of ferroelectric memory transistors due to excessive stress. In a standard operating mode, a ferroelectric memory transistor is either erased to an erase state (e.g., an erase polarization state) or written to a write state (e.g., a write polarization state), storing memory data in two logical states. In embodiments of the present disclosure, a novel operating mode is used to bias a ferroelectric memory transistor to a write state or an erase polarization state, thereby allowing different levels of polarization within a given polarization state to represent different stored data values. In other words, different polarization levels associated with a given polarization state (write polarization state or erase polarization state) are used to represent different binary states of a memory cell, such as a first logical value and a second logical value of stored data. The threshold voltage values ​​associated with the different polarization levels fall within the memory window generated by the erase polarization state and the write polarization state. In this specification, different polarization levels associated with a given polarization state (write or erase polarization state) are also referred to as weak polarization state and strong polarization state, and the terms weak polarization state and strong polarization state are used to indicate different polarization levels within a given polarization state. The polarization level is retained in the memory cell for a sufficiently long period of time, provided that care is taken to avoid interference from erase or write operations in adjacent cells in the memory array.

[0143] Basically, the binary state of a memory cell (e.g., logical values ​​"0" and "1") is established by first erasing the memory cell and then writing it to a weakly polarized state (e.g., logical value "0") or a strongly polarized state (e.g., logical value "1"). For example, if the polarization threshold voltage between the gate and drain or source (or both drain and source) is 1.5V, a weakly polarized state (0) can be formed by a short pulse of 2.0V between the gate and drain / source, and a strongly polarized state (1) can be formed by a short pulse of 3.0V between the gate and drain / source. Alternatively, the magnitude of the pulse may be the same for both 0 and 1 (e.g., 2.5V), and the pulse duration may be, for example, 0.5 microseconds for weak polarization (thus resulting in a low signal (0)) and 1 microsecond for strong polarization (thus resulting in a large signal (1)). Long-term retention of a 0 or 1 signal may require periodic read / refresh operations, such as every 10 minutes, every hour, or once a day.

[0144] Multilevel cell

[0145] According to another aspect of this disclosure, a multibit ferroelectric memory transistor (also referred to as a multilevel cell or MLC) can be realized by applying a partial polarization scheme. Herein, a single-bit memory cell (or single-level cell) refers to a memory cell configured to store one binary bit of memory data associated with two different ferroelectric polarization states (typically represented by logical values ​​0 and 1) of the memory cell. A multibit memory cell, on the other hand, refers to a memory cell configured to store multiple binary bits of memory data, such as 1.5 bits or 2 bits or more, associated with three or more different ferroelectric polarization states or polarization levels (e.g., represented by logical values ​​00, 01, and 10) within the memory cell. To write to a multilevel cell, the memory transistor is polarized to one of several writable polarization levels corresponding to one or more polarization states using a partial polarization scheme. To read from a multilevel cell, the bit line current of the memory transistor is compared with a set of reference signals to determine the stored data value of the memory transistor. In one embodiment, the reference signal set is generated by multiple reference memory transistors, each partially polarized to a writable reference polarization level, used to distinguish between multiple writable polarization levels or sub-division states of the memory transistors. For example, the stored data value of a 1.5-bit memory cell can be determined by comparing the bit line current from a multilevel cell with two reference signals. This principle can also be extended to a continuous range of writable analog states.

[0146] In embodiments of this disclosure, multilevel ferroelectric memory transistors are implemented using a partial polarization scheme to support two or more binary bits per memory cell. For example, three polarization states (or polarization levels) stored in one memory transistor represent 1.5 bits of information, and four polarization states (or polarization levels) stored in a memory transistor represent two bits per memory cell. In some embodiments, multiple polarization levels can be realized by writing or erasing at only one current terminal of the ferroelectric memory transistor according to the partial polarization scheme described above.

[0147] In one exemplary embodiment, three polarization states in the same ferroelectric memory transistor are achieved by (1) to (3) below: (1) The first polarization state is achieved by applying a 3V pulse to the gate and 0V to both the drain and source. (2) The second polarization state is achieved by applying 0V to the gate and 3V pulses to both the drain and source. (3) The third polarization state is achieved by applying a 3V pulse to the gate and one current terminal (drain or source) and 0V to the other current terminal (source or drain). In other words, the third polarization state is achieved by performing an erase operation on only one current terminal (source or drain) and prohibiting the erase operation on the other current terminal.

[0148] In some embodiments, multiple copies of a reference signal can be generated to support read operations in a multilevel ferroelectric memory transistor, which are used to distinguish between the various polarization states realized in the memory transistor. For example, when using the single-ended detection shown in Figure 16, additional instances of the bit line selector 420 and the reference sense amplifier 416 are provided to generate reference latch signals TREF at different signal levels. For example, different reference latch signals TREF are generated from reference bit lines associated with reference memory transistors having different polarization levels. Reference latch signals TREF with different signal values ​​are provided to distinguish between multiple logical states of a multilevel cell. Specifically, the reference latch signals TREF are provided to the data latch 424 to detect the sense amplifier output values ​​at different time intervals. More specifically, each data latch 424 latches the sense amplifier output values ​​at different time intervals indicated by the reference latch signal TREF and generates encoded data as output data. The encoded multi-bit data represents the signal level of the multilevel memory transistor being accessed in the read operation.

[0149] In another example, when using differential detection as shown in Figure 17, additional instances of the bit line selector 420 and the operational amplifier circuit 440 are provided to generate an additional reference voltage signal VREF. For example, different reference voltage signal levels are generated from reference bit lines associated with reference memory transistors having different polarization levels. The reference voltage signals VREF with different signal levels are provided to the sense amplifier 442 to detect different polarization states of the multilevel cell during a memory read operation. More specifically, each sense amplifier 442 compares its corresponding bit line signal BLx (node ​​414) with a group of reference voltage signals VREF having different reference signal levels to generate encoded data as a sense amplifier output signal. The generated sense amplifier output signal is stored in the data latch 444. The encoded multi-bit data represents the signal level of the multilevel memory transistor being accessed during a read operation.

[0150] In another exemplary embodiment, a 2-bit memory transistor per cell can be realized by applying strong (00), weak (01), weaker (10), and nearly zero (11) polarization fields to the drain and source of the memory transistor channel. Typically, the polarization field is strongest in the ferroelectric dielectric layer between the gate and drain, and between the gate and source. To a relatively small degree, the fringe fields adjacent to the drain and adjacent to the source both play a major role in providing partial polarization over the transistor channel region. If only one of the sources or drains of a ferroelectric memory transistor contributes to the fringe field polarization, the memory window becomes smaller, resulting in a change in the threshold voltage level of the memory transistor and the detected read current. Therefore, by carefully controlling the voltage modulation of the bit line or source line relative to the gate, or both, it becomes possible to write / erase the memory cell to a separate threshold voltage level detectable by the transistor's read current. In some embodiments, reading multibit stored data can be performed in two stages: first, detecting the channel adjacent to the drain, and then detecting the channel adjacent to the source by switching the source and drain to detect two different memory bits within the same transistor. More specifically, a channel adjacent to the drain can be detected by biasing the drain terminal or common bit line to a slightly positive voltage (e.g., 0.5V) and detecting the cell current flowing from the drain terminal to the source terminal of the memory transistor. Alternatively, a channel adjacent to the source can be detected by biasing the source terminal or common source line to a slightly positive voltage (e.g., 0.5V) and detecting the cell current flowing from the source terminal to the drain terminal of the memory transistor.

[0151] Figure 20 is a cross-sectional view of a pair of ferroelectric memory transistors that can be used in some embodiments to form memory transistors in the memory arrays of Figures 1 and 7. Specifically, Figure 20 shows a memory structure 50 including a pair of memory transistors 20a and 20b (collectively referred to as “memory transistors 20”) arranged in two adjacent planes of a memory stack. Referring to Figure 20, the memory transistor 20 (transistor 20a or 20b) includes a first conductive layer 22 forming a drain terminal (common drain line or common bit line) and a second conductive layer 24 forming a source terminal (common source line), the first conductive layer 22 and the second conductive layer 24 being separated from each other by a channel spacer dielectric layer 23. The memory transistor 20 further includes a channel layer 26 formed perpendicularly along the sidewall of the memory stack and in contact with both the first conductive layer 22 and the second conductive layer 24. A ferroelectric gate dielectric layer 27 and a gate conductor layer 28 are formed on the sidewall of the channel layer 26. The gate conductor layer 28 may include a conductive adhesive layer 28a such as a titanium nitride layer and a bulk conductive layer 28b such as tungsten. Optionally, an interface layer 25 may be provided between the channel layer 26 and the ferroelectric gate dielectric layer 27. The memory transistor 20 is isolated from adjacent storage transistors in the stack by an interlayer isolation layer 15. With this configuration, memory transistors sharing a common source line and a common bit line along the active strip (Y direction) form a NOR-type memory string (also referred to herein as a "horizontal NOR-type memory string" or "HNOR-type memory string").

[0152] In embodiments of this disclosure, the common bit line 22 and common source line 24 of the memory transistor 20 are interchangeable, and either one can operate as the drain or source of the memory transistor. As a result, the drain / source interchangeability makes it possible to implement ferroelectric polarization via electrical fringes in only the channel region 26 adjacent to the drain (shown by the dotted circle 30 in Figure 20), only the channel region 26 adjacent to the source (shown by the dotted circle 32 in Figure 20), or via fringe fields adjacent to both the drain and source (dotted circles 30 and 32). In practice, as long as the drain and source are held at the same voltage with respect to their gate conductor layers 28, the memory window MW1 (i.e., the threshold voltage difference between the write and erase states of the memory transistor) generated by the fringe field 30 and the memory window MW2 generated by the fringe field 32 can have approximately the same width. In this case, both the source and drain are activated, and the total polarization window MWTOT is MWTOT = MW1 + MW2. If only the source provides the fringe field and the drain is held at a forbidden voltage, such as the same voltage as the gate, the total polarization window becomes MW2, which is half of MWTOT. Thus, as shown in this embodiment, by partially polarizing or heparing a ferroelectric memory transistor according to the partial polarization scheme of the present disclosure, an intrinsic reference polarization state close to half of the total polarization state can be realized.

[0153] Alternatively, both the source and drain channel regions can be polarized to different degrees. For example, by setting the fringe field at the drain (dotted box 30) to a 3.0V maximum polarization pulse and the fringe field at the source (dotted box 32) to a 1.5V polarization-blocking pulse, it is possible to avoid applying all 3 volts between the drain and source of the memory transistor. In contrast, in normal write and erase operations, 3V or 0V is typically applied to both the bit line and the source line to achieve the maximum memory window. In normal write and erase operations, the width of the memory window (MW) is twice the width of the memory window when only the source or only the drain is biased. One advantage of the source and drain lines independently contributing to the ferroelectric reference polarization is that any ferroelectric transistor in the memory array can be electrically written to one of the intermediate reference polarization states. This intermediate reference polarization state has a relatively long retention time. Another advantage of the writable intermediate reference polarization state in a memory transistor is that the memory transistor can be used not only as a reference signal for read operations but also as a reference signal for write operations, and the erase threshold voltage and write threshold voltage can be set relative to the reference signal.

[0154] Another advantage of operating the source fringe magnetic field independently of the drain fringe magnetic field is that it can provide each ferroelectric memory transistor with the following four different polarization states: (1) a polarization state that reads the drain acting as the drain, (2) a polarization state that reads the source acting as the drain, (3) a polarization state that reads both the source and drain at 0V, and (4) a polarization state that reads both the source and drain at 3V. These four different polarization states can be read by reading each ferroelectric memory transistor twice in a row, and correspond to two different bits (corresponding to 00, 01, 10, and 11).

[0155] In this specification, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” are used to facilitate the description of the relationship between one component and another as shown in the drawings. It should be understood that such spatially relative terms are intended to encompass various orientations or settings of the device in use or operation, in addition to the directions or settings shown in the drawings. For example, if the device in the drawing is turned upside down, a component described as being located “below” or “directly below” another component would be located “above” the other component. Therefore, the exemplary term “below” can encompass both the “above” and “below” directions or settings. Furthermore, the device may be oriented in other settings (e.g., rotated 90 degrees, or any other orientation), and the spatially relative terms used herein shall be interpreted accordingly.

[0156] When it is stated that one component or layer is “placed on,” “connected to,” or “joined” another component or layer, it should be understood that it may be “directly” “placed on,” “connected to,” or “joined” the other component or layer, or there may be an intermediary component or layer between the two components or layers. In contrast, when it is stated that one component or layer is “directly placed on,” “directly connected to,” or “directly joined” another component or layer, there is no intermediary component or layer between the two components or layers.

[0157] In this detailed description, process steps described in one embodiment may be used in another embodiment even if they are not explicitly described in another embodiment. Where this specification refers to a method including two or more defined steps, the defined steps may be performed in any order or simultaneously, unless the context indicates or specific instructions are otherwise provided herein. Furthermore, unless the context indicates or specific instructions are otherwise provided, the method may also include one or more other steps performed before any defined step, between two defined steps, or after all defined steps.

[0158] In this detailed description, various embodiments or examples of the present invention can be carried out in various forms, such as processes, apparatus, systems, and compositions of materials. A detailed description of one or more embodiments of the present invention is provided above, along with accompanying drawings illustrating the principles of the present invention. Although the present invention has been described in relation to such embodiments, the present invention is not limited to any embodiment. Various modifications and variations are possible within the scope of the present invention. The scope of the present invention is limited only by the appended claims, and the present invention encompasses various alternative forms, modifications, and equivalents. In order to provide a complete understanding of the present invention, numerous specific details are described herein. These details are provided for illustrative purposes only, and the present invention can be carried out in accordance with the claims without some or all of these specific details. For clarity, technical matters known in the art relating to the present invention are not described in detail so as not to unnecessarily obscure the present invention. The present invention is defined by the appended claims.

Claims

1. A memory device, An array of memory strings, each memory string comprising a thin-film ferroelectric memory transistor having a drain terminal connected to a common bit line, a source terminal connected to a common source line, and a gate terminal connected to a corresponding word line, wherein each ferroelectric memory transistor of a plurality of memory strings vertically aligned in the array is connected to a common word line, and each ferroelectric memory transistor comprises a ferroelectric gate dielectric layer that is polarizable in response to the application of a bias voltage to the drain terminal, the source terminal, and the gate terminal, the array of memory strings, The ferroelectric memory transistor, in response to being driven by a first set of bias voltages, provides the ferroelectric gate dielectric layer with a first polarization state associated with a first threshold voltage value, and in response to being driven by a second set of bias voltages, provides the ferroelectric gate dielectric layer with a second polarization state associated with a second threshold voltage value greater than the first threshold voltage value. A memory device in which at least one memory transistor in a first memory string is designated as a reference memory transistor, and in response to the reference memory transistor being driven by a third set of bias voltages, provides the ferroelectric gate dielectric layer of the reference memory transistor with a third polarization state having a polarization level between the first and second polarization states, associated with a third threshold voltage value between the first and second threshold voltage values.

2. A memory device according to claim 1, The first polarization state includes a positive polarization state in the ferroelectric gate dielectric layer. The second polarization state includes a negative polarization state in the ferroelectric gate dielectric layer. The memory device wherein the third polarization state has a polarization level between the positive polarization state and the negative polarization state in the ferroelectric gate dielectric layer.

3. A memory device according to claim 2, The first polarization state is associated with memory data of a first logical state stored in the corresponding ferroelectric memory transistor. The second polarization state is associated with memory data of a second logical state stored in the corresponding ferroelectric memory transistor. A memory device in which a reference signal indicating the third polarization state in the reference memory transistor is provided for reading memory data stored in other ferroelectric memory transistors and determining the logical state of the memory data.

4. A memory device according to claim 2, The bias voltage of the first set includes a positive bias applied to the drain terminal and the source terminal of the ferroelectric memory transistor to induce the first polarization state in the ferroelectric gate dielectric layer. A memory device wherein the bias voltage of the second set includes a negative bias to the drain terminal and the source terminal, applied to the gate terminal of the ferroelectric memory transistor to induce the second polarization state in the ferroelectric gate dielectric layer.

5. A memory device according to claim 4, A memory device wherein the bias voltage of the second set includes a positive bias to the gate terminal, applied to the drain terminal or the source terminal of the ferroelectric memory transistor to induce the second polarization state in the ferroelectric gate dielectric layer.

6. A memory device according to claim 1, Multiple memory transistors within one or more memory strings are designated as the reference memory transistors. Each of the aforementioned reference memory transistors is driven by the bias voltage of the third set to provide the ferroelectric gate dielectric layer with the third polarization state. A memory device that combines signals indicating the third polarization state in each of the aforementioned reference memory transistors to generate a reference signal for reading memory data stored in other ferroelectric memory transistors and determining the logical state of that memory data.

7. A memory device according to claim 6, The signal indicating the third polarization state in each of the reference memory transistors includes the bit line signal from each of the reference memory transistors. A memory device in which the bit line signals are combined and averaged to generate the reference signal.

8. A memory device according to claim 6, The array of memory strings includes a three-dimensional array of memory strings, which includes memory strings stacked vertically on each other to form a memory stack, and memory strings arranged in a first horizontal row to form a memory plane. The ferroelectric memory transistors are arranged within each memory string along a second horizontal direction perpendicular to the first horizontal direction. A memory device in which the ferroelectric memory transistors, arranged in the vertical and first horizontal planes across a three-dimensional array of the memory strings, form a memory slice.

9. A memory device according to claim 8, The first memory plane in the three-dimensional array of the memory string is designated as the reference memory plane. A memory device in which the ferroelectric memory transistors in the memory string of the first memory plane are driven by the bias voltage of the third set to provide a reference signal indicating the third polarization state, which is used to read memory data stored in the ferroelectric memory transistors in other memory strings and to determine the logical state of the memory data.

10. A memory device according to claim 8, The first memory stack in the three-dimensional array of the memory string is designated as the reference memory stack. A memory device in which the ferroelectric memory transistors in the memory string of the first memory stack are driven by the bias voltage of the third set to provide a reference signal indicating the third polarization state, which is used to read memory data stored in the ferroelectric memory transistors in other memory strings and to determine the logical state of the memory data.

11. A memory device according to claim 8, The first memory slice in the three-dimensional array of the memory string is designated as the reference memory slice. A memory device in which the ferroelectric memory transistors in the memory string of the first memory slice are driven by the bias voltage of the third set to provide a reference signal indicating the third polarization state, which is used to read memory data stored in the ferroelectric memory transistors in other memory strings and to determine the logical state of the memory data.

12. A memory device according to claim 1, The common bit line of the array of memory strings connected to the ferroelectric memory transistor is connected to a plurality of sense amplifiers. Each sense amplifier receives a bit line signal associated with the memory transistor to be accessed in order to read the data stored in the memory transistor to be accessed, and generates a sense amplifier output signal indicating the data stored in the memory transistor. The reference memory transistor provides a reference bit line signal indicating the third polarization state. The aforementioned reference bit line signal is provided to a reference sense amplifier to generate a read reference signal. A memory device wherein the read reference signal is applied to latch a sense amplifier output signal generated by the sense amplifier connected to a bit line associated with the memory transistor to be accessed, selected by the corresponding word line.

13. A memory device according to claim 1, The common bit line of the array of memory strings connected to the ferroelectric memory transistor is connected to a plurality of differential sense amplifiers. Each of the differential sense amplifiers receives a bit line signal and a sense amplifier reference signal related to the memory transistor to be accessed, and generates a sense amplifier output signal indicating the data stored in the memory transistor. The reference memory transistor provides a reference bit line signal indicating the third polarization state. The aforementioned reference bit line signal is provided to each of the differential sense amplifiers as the sense amplifier reference signal in a memory device.

14. A memory device according to claim 13, A memory device in which the reference bit line signal is read from the reference memory transistor and stored in the differential sense amplifier for comparison with the bit line signal associated with the memory transistor to be accessed.

15. A memory device according to claim 1, One or more of the ferroelectric memory transistors in the first memory string are designated as the reference memory transistors, and the common bit line of the first memory string is connected to the first sense amplifier. The reference memory transistor on the first memory string is selected as the access target, and a reference bit line signal is provided to the first sense amplifier to generate a reference signal, which is stored in the first differential input terminal of the first sense amplifier. A second memory transistor on the first memory string is selected as the access target, and a bit line signal is provided to the second differential input terminal of the first sense amplifier. The first sense amplifier is a memory device that generates a sense amplifier output signal by comparing the bit line signal with the reference signal stored in the first sense amplifier.

16. A memory device according to claim 5, A memory device wherein the bias voltage of the third set includes a positive bias to the drain and source terminals of the reference memory transistor, applied to the gate terminal to induce the third polarization state in the ferroelectric gate dielectric layer.

17. A memory device according to claim 16, The bias voltage of the first set includes a first voltage value that is a positive bias to the drain terminal and the source terminal, applied to the gate terminal of the ferroelectric memory transistor to induce the first polarization state in the ferroelectric gate dielectric layer. A memory device wherein the bias voltage of the third set includes a second voltage value smaller than the first voltage value, which is applied to the gate terminal of the reference memory transistor, to induce the third polarization state in the ferroelectric gate dielectric layer, and which is a positive bias to the drain terminal and the source terminal.

18. A memory device according to claim 5, The bias voltage of the first set includes a positive bias applied over a first duration. A memory device wherein the bias voltage of the third set includes a positive bias to the drain and source terminals of the reference memory transistor, applied to the gate terminal for a second duration shorter than the first duration, in order to induce the third polarization state in the ferroelectric gate dielectric layer.

19. A memory device according to claim 5, A memory device wherein the bias voltage of the third set includes a positive bias to the gate terminal, applied to the drain terminal or the source terminal of the ferroelectric memory transistor to induce the third polarization state in the ferroelectric gate dielectric layer.

20. A memory device according to claim 19, The bias voltage of the second set includes a third voltage value that is a positive bias with respect to the gate terminal, applied to the drain terminal or the source terminal of the ferroelectric memory transistor in order to induce the second polarization state in the ferroelectric gate dielectric layer. A memory device wherein the bias voltage of the third set includes a fourth voltage value smaller than the third voltage value, which is a positive bias to the gate terminal and is applied to the drain terminal or the source terminal of the reference memory transistor to induce the third polarization state in the ferroelectric gate dielectric layer.

21. A memory device according to claim 5, The bias voltage of the second set includes a positive bias to the gate terminal, applied to the drain terminal or the source terminal of the ferroelectric memory transistor for a third duration, in order to induce the second polarization state in the ferroelectric gate dielectric layer. A memory device wherein the bias voltage of the third set includes a positive bias to the gate terminal, applied to the drain terminal or the source terminal of the reference memory transistor for a fourth duration shorter than the third duration, in order to induce the third polarization state in the ferroelectric gate dielectric layer.

22. A memory device according to claim 5, The bias voltage of the first set includes a first voltage value that is a positive bias to the drain terminal and the source terminal, applied to the gate terminal of the ferroelectric memory transistor to induce the first polarization state in the ferroelectric gate dielectric layer. A memory device wherein the bias voltage of the third set includes a second voltage value smaller than the first voltage value, which is applied to the gate terminal of the reference memory transistor, to induce the third polarization state in the ferroelectric gate dielectric layer, and which is a positive bias to the drain terminal and the source terminal.

23. A memory device according to claim 5, The bias voltage of the second set includes a third voltage value that is a positive bias with respect to the gate terminal, applied to the drain terminal or the source terminal of the ferroelectric memory transistor in order to induce the second polarization state in the ferroelectric gate dielectric layer. A memory device wherein the bias voltage of the third set includes a fourth voltage value smaller than the third voltage value, which is a positive bias to the gate terminal and is applied to the drain terminal or the source terminal of the reference memory transistor to induce the third polarization state in the ferroelectric gate dielectric layer.

24. A memory device according to claim 1, A memory device in which the third threshold voltage value associated with the third polarization state follows fluctuations in the first threshold voltage value and the second threshold voltage value associated with the first and second polarization states, respectively, due to temperature changes.

25. A method for detecting data in a memory device implemented as an array of memory strings of ferroelectric memory transistors, Each memory string includes a thin-film ferroelectric memory transistor having a drain terminal connected to a common bit line, a source terminal connected to a common source line, and a gate terminal connected to a corresponding word line, and each ferroelectric memory transistor includes a ferroelectric gate dielectric layer that is polarizable in response to the application of a bias voltage to the drain terminal, the source terminal, and the gate terminal. This method is The steps include: biasing one or more ferroelectric memory transistors using a first set of bias voltages to provide the ferroelectric gate dielectric layer with a first polarization state associated with a first threshold voltage value; The steps include: biasing one or more of the ferroelectric memory transistors using a second set of bias voltages to provide the ferroelectric gate dielectric layer with a second polarization state associated with a second threshold voltage value greater than the first threshold voltage value; The steps include designating at least one of the ferroelectric memory transistors in the first memory string as a reference memory transistor, A method comprising the steps of: biasing the reference memory transistor using a third set of bias voltages to provide a third polarization state in the ferroelectric gate dielectric layer of the reference memory transistor having a polarization level between the first polarization state and the second polarization state, associated with a third threshold voltage value between the first threshold voltage value and the second threshold voltage value.

26. The method according to claim 25, The first polarization state includes a positive polarization state in the ferroelectric gate dielectric layer and is associated with memory data of a first logical state stored in the corresponding ferroelectric memory transistor. The second polarization state includes a negative polarization state in the ferroelectric gate dielectric layer and is associated with memory data of a second logical state stored in the corresponding ferroelectric memory transistor. This method is The steps include generating a reference signal indicating the third polarization state in the reference memory transistor, A method comprising the step of using the reference signal to read memory data stored in another ferroelectric memory transistor and determining the logical state of the memory data.

27. The method according to claim 25, The step of biasing the one or more ferroelectric memory transistors using the bias voltage of the first set includes the step of applying a positive bias to the drain terminal and the source terminal of the ferroelectric memory transistor to induce a first polarization state in the ferroelectric gate dielectric layer, A method comprising the step of biasing the one or more ferroelectric memory transistors using the second set of bias voltages, the step of applying a positive bias to the drain terminal or the source terminal of the ferroelectric memory transistor with respect to the gate terminal in order to induce the second polarization state in the ferroelectric gate dielectric layer.

28. The method according to claim 25, The step of designating at least one of the ferroelectric memory transistors in the first memory string as the reference memory transistor includes the step of designating a plurality of the ferroelectric memory transistors as the reference memory transistors, This method is The steps include: biasing the reference memory transistor using the bias voltage of the third set to induce the third polarization state in the ferroelectric gate dielectric layer of the reference memory transistor; A method further comprising the step of combining signals indicating the third polarization state in each of the reference memory transistors to generate a reference signal for reading memory data stored in other ferroelectric memory transistors and determining the logical state of the memory data.

29. The method according to claim 28, The step of combining the signals indicating the third polarization state in each of the reference memory transistors includes the step of combining the bit line signals from each of the reference memory transistors. This method is A method further comprising the step of averaging the bit line signals to generate the reference signal.

30. The method according to claim 28, The aforementioned array of memory strings includes a three-dimensional array of memory strings, The step of designating a plurality of ferroelectric memory transistors as the reference memory transistors is, A method comprising the step of designating a plurality of ferroelectric memory transistors in a memory plane, including a first horizontally arranged memory string within the three-dimensional array, as the reference memory transistors.

31. The method according to claim 28, The aforementioned array of memory strings includes a three-dimensional array of memory strings, The step of designating a plurality of ferroelectric memory transistors as the reference memory transistors is, A method comprising the step of designating a plurality of ferroelectric memory transistors in a memory stack, which includes memory strings arranged vertically within the three-dimensional array, as the reference memory transistors.

32. The method according to claim 28, The aforementioned array of memory strings includes a three-dimensional array of memory strings, The step of designating a plurality of ferroelectric memory transistors as the reference memory transistors is: A method comprising the step of designating a plurality of ferroelectric memory transistors in a memory slice, which includes memory transistors in a three-dimensional array of memory strings arranged in a vertical and a first horizontal plane, as the reference memory transistors.

33. The method according to claim 25, The steps include selecting the memory transistor to be accessed from a second memory string, The steps include: detecting the bit line signal associated with the selected memory transistor using a sense amplifier in order to read the data stored in the selected memory transistor; The reference memory transistor comprises the step of generating a reference signal indicating the third polarization state, and A method further comprising the step of latching the detected data value of the selected memory transistor at the output node of the sense amplifier in response to the reference signal.

34. The method according to claim 25, The steps include generating a reference signal indicating the third polarization state in the reference memory transistor, The steps include selecting the memory transistor to be accessed from a second memory string, The steps include providing a reference signal and a bit line signal associated with the selected memory transistor to a differential sense amplifier in order to read the data stored in the selected memory transistor, A method further comprising the step of generating a sense amplifier output signal indicating the data stored in the selected memory transistor.

35. The method according to claim 27, The step of biasing the reference memory transistor using the bias voltage of the third set is: A method comprising the step of applying a second voltage value, less than or equal to a first voltage value, with a positive bias to the drain terminal and the source terminal, to the gate terminal of the reference memory transistor in order to induce the third polarization state in the ferroelectric gate dielectric layer.

36. The method according to claim 35, A method further comprising the step of preconditioning the reference memory transistor by applying a predetermined set of bias voltages to set the reference memory transistor to a polarization state opposite to the third polarization state, before biasing the reference memory transistor to the third set of bias voltages.

37. The method according to claim 35, The step of applying the positive bias of the first voltage value includes applying the first voltage value of a positive bias to the drain terminal and the source terminal of the ferroelectric memory transistor for a first duration in order to induce the first polarization state in the ferroelectric gate dielectric layer, A method comprising the step of applying the positive bias of the second voltage value, wherein the step of applying the second voltage value, which is a positive bias to the drain terminal and the source terminal, to the gate terminal of the reference memory transistor for a second duration shorter than the first duration, in order to induce the third polarization state in the ferroelectric gate dielectric layer.

38. The method according to claim 27, The step of biasing the reference memory transistor using the bias voltage of the third set is: A method comprising the step of applying a fourth voltage value, less than or equal to a third voltage value, with a positive bias to the gate terminal, to the drain terminal or the source terminal of the reference memory transistor in order to induce the third polarization state in the ferroelectric gate dielectric layer.

39. The method according to claim 38, A method further comprising the step of preconditioning the reference memory transistor by applying a predetermined set of bias voltages to set the reference memory transistor to a polarization state opposite to the third polarization state, before biasing the reference memory transistor to the third set of bias voltages.

40. The method according to claim 38, The step of applying the third voltage value with a positive bias to the gate terminal to the drain terminal and the source terminal of the ferroelectric memory transistor includes the step of applying the third voltage value with a positive bias to the gate terminal to the drain terminal or the source terminal of the ferroelectric memory transistor for a third duration in order to induce the first polarization state in the ferroelectric gate dielectric layer, A method comprising the step of applying the fourth voltage value, which is a positive bias to the gate terminal, to the drain terminal or the source terminal of the reference memory transistor, for a fourth duration shorter than the third duration, in order to induce the third polarization state in the ferroelectric gate dielectric layer.

41. The method according to claim 27, The step of biasing the one or more ferroelectric memory transistors using the first set of bias voltages includes the step of applying a first positive bias voltage value to the drain terminal and the source terminal of the ferroelectric memory transistor to induce a first polarization state in the ferroelectric gate dielectric layer, A method comprising the step of biasing the reference memory transistor using the third set of bias voltages, the step of applying a second voltage value to the gate terminal of the reference memory transistor, which is less than the first voltage value and positively biased to the drain terminal and the source terminal, in order to induce the third polarization state in the ferroelectric gate dielectric layer.

42. The method according to claim 27, The step of biasing the one or more ferroelectric memory transistors using the second set of bias voltages includes the step of applying a third voltage value that is a positive bias relative to the gate terminal to the drain terminal or the source terminal of the ferroelectric memory transistor in order to induce the second polarization state in the ferroelectric gate dielectric layer, A method comprising the step of biasing the reference memory transistor using the third set of bias voltages, the step of applying a fourth voltage value, which is positively biased to the gate terminal and smaller than the third voltage value, to the drain terminal or the source terminal of the reference memory transistor in order to induce the third polarization state in the ferroelectric gate dielectric layer.

43. The method according to claim 25, A method further comprising the step of periodically applying the bias voltage of the third set to the reference memory transistor to set the ferroelectric gate dielectric layer to the third polarization state.

44. A memory device, An array of memory strings, each memory string comprising a thin-film ferroelectric memory transistor having a drain terminal connected to a common bit line, a source terminal connected to a common source line, and a gate terminal connected to a corresponding word line, wherein each ferroelectric memory transistor of a plurality of memory strings vertically aligned in the array is connected to a common word line, and each ferroelectric memory transistor comprises a ferroelectric gate dielectric layer that is polarizable in response to the application of a bias voltage to the drain terminal, the source terminal, and the gate terminal, the array of memory strings, The ferroelectric memory transistor is driven by a first set of bias voltages to provide the ferroelectric gate dielectric layer with a first polarization state associated with a first threshold voltage value, and is driven by a second set of bias voltages to provide the ferroelectric gate dielectric layer with a second polarization state associated with a second threshold voltage value greater than the first threshold voltage value. The first ferroelectric memory transistor in the array is designated as the first reference memory transistor. A second ferroelectric memory transistor in the array is designated as a second reference memory transistor. The first reference memory transistor is driven to the first polarization state by the bias voltage of the first set, The second reference memory transistor is driven to the second polarization state by the bias voltage of the second set, A memory device that generates a reference signal for reading memory data stored in a ferroelectric memory transistor and determining the logical state of the memory data by combining a bit line signal indicating the first polarization state of the first reference memory transistor and a bit line signal indicating the second polarization state of the second reference memory transistor.

45. A memory device according to claim 44, The bit line signals from the first reference memory transistor and the second reference memory transistor are connected to the bit line selector. The bit line selector, in response to the bit line selection signal, selects and activates bit line signals from both the first reference memory transistor and the second reference memory transistor to generate an average bit line signal representing the reference signal. The average bit line signal indicates the reference signal in the memory device.

46. A memory device according to claim 44, A plurality of first ferroelectric memory transistors designated as the first reference memory transistor, The system further includes a plurality of second ferroelectric memory transistors designated as the second reference memory transistor, A memory device that generates a reference signal by combining bit line signals indicating the first polarization state of the first plurality of reference memory transistors and bit line signals indicating the second polarization state of the second plurality of reference memory transistors.

47. A memory device according to claim 46, The bit line signals from the first set of reference memory transistors and the second set of reference memory transistors are connected to a bit line selector. The bit line selector, in response to a bit line selection signal, selects and activates bit line signals from the first plurality of reference memory transistors and the second plurality of reference memory transistors to generate an average bit line signal. The average bit line signal indicates the reference signal in the memory device.

48. A method for storing data in a memory device implemented as an array of memory strings of ferroelectric memory transistors, Each memory string includes a thin-film ferroelectric memory transistor having a drain terminal connected to a common bit line, a source terminal connected to a common source line, and a gate terminal connected to a corresponding word line, and each ferroelectric memory transistor includes a ferroelectric gate dielectric layer that is polarizable in response to the application of a bias voltage to the drain terminal, the source terminal, and the gate terminal. This method is The steps include: biasing one or more ferroelectric memory transistors using a first set of bias voltages to provide the ferroelectric gate dielectric layer with a first polarization level associated with a first threshold voltage value; The steps include: biasing one or more of the ferroelectric memory transistors using a second set of bias voltages to provide the ferroelectric gate dielectric layer with a second polarization level associated with a second threshold voltage value greater than the first threshold voltage value; A method wherein both the first polarization level and the second polarization level are associated with a first polarization state in the ferroelectric gate dielectric layer.

49. The method according to claim 48, The first polarization state includes a positive polarization state in the ferroelectric gate dielectric layer. A method wherein the first polarization level and the second polarization level are associated with different polarization levels in the positive polarization state.

50. The method according to claim 48, The first polarization state includes a negative polarization state in the ferroelectric gate dielectric layer. A method wherein the first polarization level and the second polarization level are associated with different polarization levels in the negative polarization state.

51. A memory device, An array of memory strings, each memory string comprising a thin-film ferroelectric memory transistor having a drain terminal connected to a common bit line, a source terminal connected to a common source line, and a gate terminal connected to a corresponding word line, wherein each ferroelectric memory transistor of a plurality of memory strings vertically aligned in the array is connected to a common word line, and each ferroelectric memory transistor comprises a ferroelectric gate dielectric layer that is polarizable in response to the application of a bias voltage to the drain terminal, the source terminal, and the gate terminal, the array of memory strings, The ferroelectric memory transistor is driven by a bias voltage and stores memory data at three or more polarization levels in a first polarization state and a second polarization state. Each of the three or more polarization levels is associated with a predetermined threshold voltage value. A memory device in which the threshold voltage values ​​of three or more of the above polarization levels are different from each other.

52. A memory device according to claim 51, The first polarization state includes a negative polarization state in the ferroelectric gate dielectric layer. The second polarization state includes a positive polarization state in the ferroelectric gate dielectric layer. A memory device in which each of the three or more polarization levels is associated with a different polarization level in the negative polarization state or the positive polarization state.

53. A memory device according to claim 51, The ferroelectric memory transistor is driven by a bias voltage and stores memory data at a first polarization level, a second polarization level, and a third polarization level. A memory device in which the first polarization level, the second polarization level, and the third polarization level are applied to encode 1.5 logic bits of memory data stored in the ferroelectric memory transistor.

54. A memory device according to claim 53, A memory device in which the first polarization level, the second polarization level, and the third polarization level of the first ferroelectric memory transistor and the first polarization level, the second polarization level, and the third polarization level of the second ferroelectric memory transistor are applied to encode three logic bits of memory data stored in the first ferroelectric memory transistor and the second ferroelectric memory transistor.

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