Formation of silicon and metal-containing materials for hard masks

Abstract

An exemplary method for semiconductor processing may include providing a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may include a silicon- and halogen-containing precursor and a metal-containing precursor. A substrate may be housed within the processing area. The method may include generating plasma emissions of the deposition precursor. The method may include forming layers of silicon- and metal-containing material on the substrate.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Patent Application No. 18 / 197,528, filed on May 15, 2023, entitled "FORMATION OF SILICON - AND - METAL - CONTAINING MATERIALS FOR HARDMASK APPLICATIONS", which is hereby incorporated by reference in its entirety.

[0002]

[0002] This technology relates to semiconductor processes and equipment. More specifically, this technology relates to a method for depositing silicon - and - metal - containing materials that can be used as hardmask materials.

Background Art

[0003]

[0003] Integrated circuits are realized by a process of creating intricately patterned material layers on a substrate surface. To create a patterned structure on a substrate, a controlled method of forming and removing exposed materials is required. As device miniaturization progresses and structures become more complex, material properties can affect subsequent processes. For example, hardmask materials can affect not only the ability to develop structures but also the ability to selectively remove materials.

[0004]

[0004] Therefore, improved systems and methods that can be used to create high - quality devices and structures are needed. These needs and others are addressed by this technology.

Summary of the Invention

[0005]

[0005] An exemplary method of semiconductor processing may include providing a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may include a silicon and halogen-containing precursor and a metal-containing precursor. A substrate may be housed within the processing area. The method may include generating plasma emissions of the deposition precursor. The method may include forming layers of silicon and metal-containing material on the substrate.

[0006]

[0006] In some embodiments, the silicon and halogen-containing precursor comprises silicon tetrafluoride (SiF4). The metal-containing precursor may comprise one or more of tungsten, molybdenum, cobalt, tantalum, ruthenium, titanium, rhenium, hafnium, or zirconium. The metal-containing precursor may further comprise halogens. The deposition precursor may further comprise one or more of boron-containing precursors, carbon-containing precursors, or nitrogen-containing precursors. The method may include making the flow rate of the deposition precursor cyclic. The flow rate of the metal-containing precursor may be greater than the flow rate of the silicon and hydrogen-containing precursor during the first period. The flow rate of the metal-containing precursor may be less than the flow rate of the silicon and hydrogen-containing precursor during the second period. The layer of silicon and metal-containing material may feature a metal concentration greater than or about 20 at.%. The method may include pre-treating the substrate before forming the layer of silicon and metal-containing material. Pre-treatment of the substrate may include providing a nitrogen-containing precursor to the processing area of ​​the semiconductor processing chamber, generating plasma emissions of the nitrogen-containing precursor, and bringing the substrate into contact with the plasma emissions of the nitrogen-containing precursor. The method may also include forming a seed layer on the substrate after pre-treatment. The seed layer may be or include an amorphous boron-containing material.

[0007]

[0007] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include providing a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may include a silicon and halogen-containing precursor and a metal-containing precursor. A substrate may be housed within the processing area. The method may include generating plasma emissions of the deposition precursor. The plasma emissions of the deposition precursor may be generated with a plasma output of more than 200 W or about 200 W. The method may include forming layers of silicon and metal-containing material on a substrate.

[0008]

[0008] In some embodiments, the plasma emissions of the deposition precursor may be generated with a plasma output of less than 2,000 W or about 2,000 W. The silicon and metal-containing material layers may not contain fluorine, oxygen, or both. The method may include pre-treating the substrate to form a seed layer on the substrate before providing the deposition precursor. The temperature in the processing area may be maintained at less than 600°C or about 600°C. The pressure in the processing area may be maintained at less than 50 Torr or about 50 Torr.

[0009]

[0009] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include providing silicon-containing precursors and metal-containing precursors to a processing area in a semiconductor processing chamber. A substrate may be housed within the processing area. The method may include forming layers of silicon and metal-containing material on the substrate. The layers of silicon and metal-containing material may be characterized by a metal concentration greater than or about 20 at.%.

[0010]

[0010] In some embodiments, the silicon-containing precursor may be or may contain silicon tetrafluoride (SiF4). The metal-containing precursor may be or may contain tungsten hexafluoride (WF6). Layers of silicon and metal-containing materials may be formed at a rate greater than or about 500 Å / m.

[0011]

[0011] Such technologies may offer a number of advantages over conventional systems and techniques. For example, the process may produce silicon and metal-containing materials that may feature a wide range of metal concentrations. Furthermore, the process may utilize deposition precursors that may not spontaneously react before deposition and may have minimal reactions before deposition. These embodiments and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the accompanying descriptions and figures.

[0012]

[0012] A further understanding of the nature and advantages of the disclosed technology can be obtained by referring to the following parts of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1]

[0013] This is a top view of one embodiment of an exemplary processing system according to several embodiments of the present technology. [Figure 2A]

[0014] This is a schematic cross-sectional view of an exemplary processing chamber according to several embodiments of this technology. [Figure 2B]

[0015] This is a detailed view of a portion of the processing chamber shown in Figure 2A, according to several embodiments of this technology. [Figure 3]

[0016] This is a bottom view of an exemplary shower head according to several embodiments of this technology. [Figure 4]

[0017] This is an exemplary step in a method according to several embodiments of the present technology. [Figure 5A-5B]

[0018] This is a cross-sectional view of a substrate under processing according to an embodiment of this technology. [Modes for carrying out the invention]

[0014]

[0019] Some diagrams are included as schematic representations. These diagrams are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic representations, they are provided to aid understanding and may not include all aspects or information compared to realistic representations, and may contain additional or exaggerated material for illustrative purposes.

[0015]

[0020] In the attached diagrams, similar components and / or features may have the same reference numeral. Furthermore, various components of the same kind may be distinguished according to their reference numerals by letters that distinguish similar components from each other. Where only the first reference numeral is used herein, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letters.

[0016]

[0021] During semiconductor manufacturing, structures can be created on a substrate using a variety of deposition and etching processes. Hard mask materials can be used to at least partially etch the material, allowing features to be created across the substrate. As devices become smaller and the selectivity between materials improves, making structure formation easier, improved hard masks can facilitate manufacturing. For example, future DRAM nodes may require higher capacitor structures, which may involve forming deeper trenches on the substrate. Conventional hard masks may reach their limit in terms of selectivity for the underlying silicon material. Therefore, many semiconductor manufacturing processes are attempting to use thicker hard mask films for larger vertical device structures or to develop hard mask materials characterized by increased hardness. However, while hard masks may feature sufficient transparency at a certain thickness, the transparency of the film may decrease as the thickness increases. If the film transparency is insufficient, additional processes may be required to open up areas near alignment markers to ensure correct orientation. Furthermore, thicker hard mask films can make patterning more difficult, potentially affecting the uniformity of transfer to the underlying structure.

[0017]

[0022] This technology can overcome these limitations by creating hard mask materials that incorporate both silicon and one or more metals. While counterintuitive, these materials may reduce transparency and hardness, but they offer increased selectivity for the underlying material, allowing for a reduction in hard mask thickness and overall improvement in semiconductor substrate etching and structuring. Since the described techniques can be used to improve several film formation processes and are applicable to a variety of processing chambers and processes, it should be understood that this technology is not intended to be limited to the specific films and processes described.

[0018]

[0023] The remaining disclosures, as is customary, identify specific deposition processes utilizing the disclosed technology, but it will be readily apparent that the systems and methods are equally applicable to deposition and cleaning processes that may be carried out in the described chambers. Therefore, the technology should not be considered limited to use with exemplary deposition processes or chambers alone. Furthermore, while exemplary chambers are described to provide the basis for the technology, it should be understood that the technology is applicable to substantially any semiconductor processing chamber capable of enabling the described processes.

[0019]

[0024] FIG. 1 shows a top view of one embodiment of a processing system 100 by a deposition chamber, an etching chamber, a baking chamber, and a curing chamber according to an embodiment. In the figure, a pair of front-opening unified pods (FOUPs) 102 are received by a robot arm 104 and positioned in a tandem section 109a-109c, and are arranged in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-108f to supply substrates of various sizes. A second robot arm 110 can be used to transfer the substrate wafer from the holding area 106 to the substrate processing chambers 108a-108f or back. Each of the substrate processing chambers 108a-108f can be equipped to perform several substrate processing steps including, in addition to cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, degassing, orientation, and other substrate processes, the dry etching processes described herein.

[0020]

[0025] The substrate processing chambers 108a-108f can include one or more system components for depositing, annealing, curing, and / or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers (e.g., 108c-108d and 108e-108f) are used to deposit a dielectric material on the substrate, and a third pair of processing chambers (e.g., 108a-108b) can be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-108f) can be configured to etch the dielectric film on the substrate. Any one or more of the processes described can be performed in a chamber (s) separate from the manufacturing system shown in various embodiments. It will be understood that additional configurations of a deposition chamber, an etching chamber, an annealing chamber, and a curing chamber for a dielectric film are envisioned by the system 100.

[0021]

[0026] FIG. 2A shows a cross-sectional view of an exemplary processing system 200 having a plasma generation region partitioned within a processing chamber. During the etching of a film (e.g., titanium nitride, tantalum nitride, tungsten, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.), a process gas can be flowed into the first plasma region 215 through the gas injection assembly 205. A remote plasma system (RPS) 201 may optionally be included within the system and can process the first gas. The first gas then moves through the gas injection assembly 205. The injection assembly 205 may include two or more separate gas supply channels, and if a second channel (not shown) is included, the second channel may bypass the RPS 201.

[0022]

[0027] A cooling plate 203, a faceplate 217, an ion suppressor 223, a showerhead 225, and a pedestal 265 or substrate support on which a substrate 255 is disposed are shown, each of which may be included according to an embodiment. The pedestal 265 may have a heat exchange channel through which a heat exchange fluid for controlling the temperature of the substrate flows. The heat exchange channel may operate to heat and / or cool the substrate or wafer during a processing step. The wafer support platter of the pedestal 265, which may include aluminum, ceramic, or a combination thereof, may also be resistively heated and may reach a relatively high temperature (e.g., from about 100 °C or less to about 1100 °C or more) using an embedded resistive heating element.

[0023]

[0028] The faceplate 217 may be pyramidal, conical, or of another similar structure that is narrow at the top and widens towards the bottom. Further, the faceplate 217 may be flat as shown and may include a plurality of through-channels used to disperse the process gas. Plasma generation gas and / or plasma excitation species may pass through the plurality of holes in the faceplate 217 shown in FIG. 2B so as to be more uniformly sent into the first plasma region 215 depending on the use of the RPS 201.

[0024]

[0029] An exemplary configuration may include having the gas injection assembly 205 leading to a gas supply region 258 separated from the first plasma region 215 by a faceplate 217, thereby allowing the gas / type to flow into the first plasma region 215 through holes in the faceplate 217. Structural and operational features may be selected to prevent a large backflow of plasma from the first plasma region 215 back to the supply region 258, the gas injection assembly 205, and the fluid supply system 210. The faceplate 217 (or the upper conductive portion of the chamber) and the showerhead 225 are illustrated with an insulating ring 220 positioned between these features. This allows an AC potential to be applied to the faceplate 217 relative to the showerhead 225 and / or the ion suppressor 223. The insulating ring 220 may be positioned between the faceplate 217 and the showerhead 225 and / or the ion suppressor 223, enabling the formation of a capacitively coupled plasma (CCP) within the first plasma region. Furthermore, a baffle (not shown) may be located within the first plasma region 215, or it may be connected to the gas injection assembly 205 so as to affect the flow of fluid entering this region through the gas injection assembly 205.

[0025]

[0030] The ion suppressor 223 may include a plate or other geometric dimensions defining multiple openings throughout its structure, which is configured to suppress the movement of ion-charged species from the first plasma region 215, while allowing uncharged neutral species or radical species to pass through the ion suppressor 223 and enter the active gas delivery region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may include a perforated plate with a variety of opening configurations. These uncharged species may include highly reactive species that are transported through the openings along with a low-reactivity carrier gas. As described above, the movement of ion species through the openings can be reduced, and in some cases, completely suppressed. By controlling the amount of ion species passing through the ion suppressor 223, it is advantageous to improve control over the mixed gas that will come into contact with the underlying wafer substrate, and consequently, to improve control over the deposition and / or etching properties of the mixed gas. For example, adjusting the ion concentration of the mixed gas can significantly alter its etching selectivity (e.g., SiNx:SiOx etching ratio, Si:SiOx etching ratio, etc.). In alternative embodiments where deposition is performed, the balance of deposition from conformal to flowable modes of the dielectric material can also be shifted.

[0026]

[0031] Multiple openings in the ion suppressor 223 may be configured to control the passage of the active gas (i.e., ionic species, radical species, and / or neutral species) through the ion suppressor 223. For example, the aspect ratio of the holes (i.e., the ratio of the diameter to the length of the holes) and / or the shape dimensions of the holes may be controlled to reduce the flow of ionic charged species in the active gas passing through the ion suppressor 223. The holes in the ion suppressor 223 may include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The cylindrical portion may be shaped and dimensional to control the flow of ionic species through the showerhead 225. As an additional means of controlling the flow of ionic species through the suppressor, an adjustable electrical bias may be applied to the ion suppressor 223.

[0027]

[0032] The ion suppressor 223 may function to reduce or eliminate the amount of ionic species that travel from the plasma generation region to the substrate. Uncharged neutral species and radical species can still pass through the openings of the ion suppressor and react with the substrate. It should be noted that in embodiments, complete elimination of ionic species in the reaction region surrounding the substrate may not be achieved. In certain cases, ionic species are intended to reach the substrate to carry out etching and / or deposition processes. In such cases, the ion suppressor may help control the concentration of ionic species in the reaction region at a level that supports the process.

[0028]

[0033] The showerhead 225, in combination with the ion suppressor 223, can allow excited species to move from the chamber plasma region 215 into the substrate processing region 233, while preventing the plasma present in the first plasma region 215 from directly exciting the gas in the substrate processing region 233. In this way, the chamber can be configured to prevent the plasma from coming into contact with the substrate 255 being processed. This advantageously protects various complex structures and films patterned on the substrate, which could be damaged, displaced, or otherwise distorted if the generated plasma came into direct contact with them. Furthermore, if the plasma can come into contact with the substrate or approach the substrate level, the rate of etching, for example, by oxide species may increase. Therefore, if the exposed area of ​​the material is an oxide, the material can be further protected by keeping the plasma away from the substrate.

[0029]

[0034] The processing system may further include a power source 240 electrically connected to the processing chamber to power the faceplate 217, ion suppressor 223, showerhead 225, and / or pedestal 265 to generate plasma within the first plasma region 215 or processing region 233. This power source may be configured to supply a tunable amount of power to the chamber depending on the process being performed. Such a configuration may allow the use of a tunable plasma in the process being performed. Unlike remote plasma units, which are often given an on / off function, a tunable plasma may be configured to supply a specific amount of power to the plasma region 215. This may, in turn, allow for the enhancement of deposition or the etching profile created by these precursors by developing specific plasma properties so that precursors can dissociate in a particular way.

[0030]

[0035] Plasma can be ignited in either the chamber plasma region 215 above the showerhead 225 or the substrate processing region 233 below the showerhead 225. Plasma may be present in the chamber plasma region 215 to create radical precursors from the influx of, for example, fluorine-containing precursors or other precursors. To ignite the plasma in the chamber plasma region 215 during deposition, an AC voltage typically in the radio frequency (RF) range may be applied between the upper conductive portion of the processing chamber (such as the faceplate 217) and the showerhead 225 and / or ion suppressor 223. The RF power source may generate a high RF frequency of 13.56 MHz, but may also generate other frequencies, either alone or in combination with the 13.56 MHz frequency.

[0031]

[0036] Figure 2B shows a detailed diagram 253 of features that affect the dispersion of the process gas through the faceplate 217. As shown in Figures 2A and 2B, the faceplate 217, cooling plate 203, and gas injection assembly 205 are combined to define a gas supply region 258. Process gas can be supplied to the gas supply region 258 from the gas injection assembly 205. The gas fills the gas supply region 258 and can flow through openings 259 in the faceplate 217 to the first plasma region 215. The openings 259 may be configured to direct the flow substantially in one direction. This allows the process gas to flow into the processing region 233, but partially or completely prevents backflow into the gas supply region 258 after crossing the faceplate 217.

[0032]

[0037] A gas distribution assembly, such as a showerhead 225, for use within the processing system 200 may be referred to as a dual-channel showerhead (DCSH), which will be further detailed in the embodiment described in Figure 3. The dual-channel showerhead can provide a process that allows for the separation of precursors outside the processing area 233, resulting in limited interaction between the precursors and chamber components, as well as interaction between the precursors themselves, before they are introduced into the processing area.

[0033]

[0038] The showerhead 225 may comprise an upper plate 214 and a lower plate 216. The plates may be connected to each other so as to define a space 218 between the plates. The plates may be connected such as to provide a first fluid channel 219 through the upper and lower plates and a second fluid channel 221 through the lower plate 216. The formed channels may be configured to provide fluid access from the space 218 only through the second fluid channel 221 through the lower plate 216, and the first fluid channel 219 may be fluidically isolated from the space 218 between the plates and the second fluid channel 221. The space 218 may be fluidically accessible through the side of the showerhead 225.

[0034]

[0039] Figure 3 is a bottom view of a showerhead 325 used in a processing chamber according to an embodiment. The showerhead 325 may correspond to the showerhead 225 shown in Figure 2A. The through-holes 365, showing a view of the first fluid channel 219, may have multiple shapes and configurations to control and influence the flow of precursors passing through the showerhead 225. The small holes 375, showing a view of the second fluid channel 221, can be dispersed almost evenly on the surface of the showerhead even between the through-holes 365, which may help to make the mixing of precursors more uniform than other configurations when the precursors exit the showerhead.

[0035]

[0040] Figure 4 shows exemplary steps of Method 400 according to several embodiments of the present technology. This method may be performed in one of the processing chambers 108a to 108f described above, or in a variety of processing chambers including the processing system 200. Method 400 may include several optional steps, which may or may not be specifically associated with certain embodiments of the method according to the present technology. For example, many of the steps described are provided to offer a broader range of structure formation, but may be performed by alternative methods that are not critical to the technology or that are easily understood. Method 400 may describe steps schematically shown in Figures 5A to 5B. These examples will be described in conjunction with the steps of Method 400. The figures show only partial schematics, and it should be understood that the substrate may include any number of additional materials and features having a variety of properties and characteristics as shown in the figures.

[0036]

[0041] Method 400 may include additional steps before commencing the listed steps. For example, additional processing steps may include forming a structure on the semiconductor substrate (which may include both forming and removing materials). The pre-processing steps may be performed in the chamber in which Method 400 may be performed, or the processing may be performed in one or more other processing chambers before the substrate is delivered to the semiconductor processing chamber in which Method 400 may be performed. Notwithstanding the foregoing, Method 400 may optionally include delivering the substrate 505 to the processing area of ​​the semiconductor processing chamber (e.g., one of the processing chambers 108a to 108f, or the processing system 200 described above), or to the processing area of ​​another chamber which may include the components described above. The substrate 505 may be deposited on a substrate support, which may be a pedestal (such as the pedestal 265 described above), and may be placed in the processing area of ​​the chamber (such as the space 218 described above).

[0037]

[0042] The substrate 505 may be or include any number of materials on which material can be deposited. The substrate 505 may be a dielectric material including silicon, germanium, silicon oxide or silicon nitride, a metallic material, or any number of combinations of these materials, or may include these materials, which may be a substrate or a material formed on the substrate. In some embodiments, optional processing steps, such as pretreatment in optional step 405, may be performed to prepare the surface of the substrate 505 for deposition. For example, pretreatment may be performed to provide specific ligand ends on the surface of the substrate 505, which can facilitate the nucleation of the film to be deposited. For example, other molecular ends including hydrogen, oxygen, carbon, nitrogen, or any combination of these atoms or radicals may be adsorbed, reacted, or formed on the surface of the substrate 505. In embodiments, a pretreatment precursor may be provided to a processing area to generate plasma emissions. The substrate 505 may be brought into contact with the plasma emissions of the pretreatment precursor to introduce the ligand ends to the surface of the substrate 505. In one exemplary embodiment, the pretreatment precursor may include diatomic hydrogen (H2), diatomic nitrogen (N2), or both, as well as any other hydrogen-containing or nitrogen-containing precursor useful for semiconductor processing. To introduce sufficient ligand termination, the flow rate of the pretreatment precursor may be greater than or about 100 sccm, greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 750 sccm, greater than or about 1,000 sccm, greater than or about 2,000 sccm, greater than or about 3,000 sccm, greater than or about 4,000 sccm, greater than or about 5,000 sccm, or more. Furthermore, plasma emissions can be generated at plasma outputs exceeding or approximately 250W, exceeding or approximately 500W, exceeding or approximately 550W, exceeding or approximately 600W, exceeding or approximately 650W, exceeding or approximately 700W, or higher.Furthermore, material removal may be performed, such as reduction of native oxides, etching of materials, or any other steps that can prepare one or more exposed surfaces of the substrate 505 for deposition.

[0038]

[0043] As shown in Figure 5A, following any pretreatment, Method 400 may include forming a seed layer 510 on the substrate 505 in an optional step 410. The seed layer 510 may increase film adhesion between adjacent material layers. Forming the seed layer 510 may include providing a seed layer precursor to the processing area, which may generate plasma emissions. The substrate 505 may come into contact with the plasma emissions of the seed layer precursor to form a seed layer 510 on the surface of the substrate 505. In embodiments in which the pretreatment in any step 405 provides nitrogen ligand terminations, the seed layer 510 may contain hydrogen. The hydrogen in the seed layer 510 may bond strongly to both the nitrogen ligand terminations and the subsequently formed silicon and metal-containing material layers. In one exemplary embodiment, the seed layer 510 may contain an amorphous boron-containing material. The seed layer 510 may be formed using a boron-containing precursor as a seed layer precursor. The boron-containing precursor may be any boron-containing material useful for semiconductor processing, such as diborane (B2H6). The seed layer precursor may also provide one or more inert gases or carrier gases. The flow rate of the seed layer precursor may be greater than or about 100 sccm, greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 750 sccm, greater than or about 1,000 sccm, or higher. Furthermore, plasma emissions can be generated at plasma outputs exceeding or approximately 100W, exceeding or approximately 200W, exceeding or approximately 250W, exceeding or approximately 300W, exceeding or approximately 500W, exceeding or approximately 750W, exceeding or approximately 1,000W, exceeding or approximately 1,500W, or exceeding or approximately 1,500W, or higher. As mentioned above, the strong bond between nitrogen present on the pre-treated surface of the substrate 505 and hydrogen present in the seed layer 510 can promote the film adhesion of the silicon and metal-containing material layers that are subsequently formed.

[0039]

[0044] In step 415, one or more deposition precursors may be sent to the processing area of ​​a semiconductor processing chamber. For example, the film to be deposited may be a hard mask film used in semiconductor processing. The deposition precursors may include any number of hard mask precursors, including one or more silicon and halogen-containing precursors, one or more metal-containing precursors, one or more boron-containing precursors, one or more carbon-containing precursors, and / or one or more nitrogen-containing precursors. The precursors may be flowed together. However, it is also conceivable that one or more of the deposition precursors may be flowed so that they remain fluidly separated from other deposition precursors before reaching the processing area. For example, in an exemplary embodiment in which a silicon and metal-containing film may be formed, at least one silicon and halogen-containing precursor and at least one metal-containing precursor may be sent to the processing area of ​​a semiconductor processing chamber. In some embodiments of the art, plasma-enhanced deposition can be performed, thereby accelerating the reaction and deposition of materials. For example, in any step 420, plasma emissions of the deposition precursors may be generated, and a layer of silicon and metal-containing material 515 may be deposited in step 425, as shown in Figure 5B.

[0040]

[0045] Depending on the precursor used, the flow rate of the deposited precursor can be used to control the incorporation of silicon and metal in the layer of silicon and metal-containing material 515. For example, the flow rate of one or more silicon and halogen-containing precursors may be greater than or about 50 sccm, greater than or about 75 sccm, greater than or about 100 sccm, greater than or about 125 sccm, greater than or about 150 sccm, greater than or about 175 sccm, greater than or about 200 sccm, greater than or about 225 sccm, greater than or about 250 sccm, greater than or about 275 sccm, greater than or about 300 sccm, greater than or about 400 sccm, greater than or about 500 sccm, or more. Similarly, the flow rates of one or more silicon and halogen-containing precursors may be less than or about 750 sccm, less than or about 500 sccm, less than or about 400 sccm, less than or about 300 sccm, or less than or equal to these. The flow rates of one or more metal-containing precursors may be greater than or about 2 sccm, greater than or about 4 sccm, greater than or about 6 sccm, greater than or about 8 sccm, greater than or about 10 sccm, greater than or about 15 sccm, greater than or about 20 sccm, greater than or about 50 sccm, or more than or equal to these. Similarly, the flow rates of one or more metal-containing precursors may be less than or about 50 sccm, less than or about 40 sccm, less than or about 30 sccm, less than or about 20 sccm, or less than or equal to these values.

[0041]

[0046] With respect to one or more silicon and halogen-containing precursors, any number of deposition precursors may be used in this technology. Exemplary silicon and halogen-containing precursors may include silicon tetrafluoride (SiF4), trifluorosilane (SiF3H), difluorosilane (SiF2H2), and any other silicon and halogen-containing materials that can be used to produce silicon and metal-containing materials. The silicon content in the resulting film may be based on any proportion. For example, the resulting film may contain a silicon content of more than or about 5 at.%; in some embodiments, the film may contain a silicon content that is substantially or essentially silicon, less than the amount of metal in the material, including more than or about 10 at.%; more than or about 60 at.%; more than or about 65 at.%; more than or about 70 at.%; more than or about 75 at.%; more than or about 80 at.%; more than or about 85 at.%; more than or about 90 at.%; more than or about 95 at.%; or even higher. It should be understood that trace materials may be incorporated into the material by exposure to air or other process environments, but the material may still essentially be silicon and metal-based.

[0042]

[0047] One or more metal-containing precursors may include any metal-containing precursor, such as any metal or transition metal that can be delivered to the processing area in a stable form. Exemplary metal-containing precursors may include one or more of tungsten, molybdenum, cobalt, tantalum, ruthenium, titanium, rhenium, hafnium, zirconium, or any other metal or transition metal that can be incorporated into silicon in hard mask materials. Exemplary metal-containing precursors may also include one or more halogens, such as fluorine, chlorine, bromine, or iodine. The metal-containing precursor may include any number of metal-containing materials that can be dissociated in the plasma to provide metal for incorporation. For example, non-limiting examples of metal-containing precursors that may be used in embodiments of this technology include tungsten hexafluoride (WF6), hexacarbonyltungsten (W(CO)6), molybdenum hexafluoride (MoF6), molybdenum pentachloride (MoCl5), hexacarbonylmolybdenum (Mo(CO)6), titanium tetrachloride (TiCl4), and tetrakis(dimethylamide)titanium (C8H 24 This may include N4Ti), titanium tetrafluoride (TiF4), trimethylaluminum (Al2(CH3)6), aluminum chloride (AlCl3), cobaltocene (Co(C5H5)2), tantalum pentachloride (TaCl5), or any other metal-containing precursors that can be used to provide metallic materials for incorporation into silicon and metal-containing materials.

[0043]

[0048] One or more additional deposition precursors may be provided. For example, in some embodiments, the silicon and metal-containing material 515 layers may further contain boron, carbon, and / or nitrogen. Exemplary boron-containing precursors may include borane (BH3), diborane (B2H6), boron trichloride (BCl3), or any other boron-containing precursors that may be useful in semiconductor processing. Exemplary carbon-containing precursors may include propene (C3H6) or any other carbon-containing precursors that may be useful in semiconductor processing. Exemplary nitrogen-containing precursors may include diatomic nitrogen (N2), ammonia (NH3), or any other carbon-containing precursors that may be useful in semiconductor processing. Furthermore, one or more carrier gases or inert gases may be provided along with one or more deposition precursors that can function as diluent gases. For example, diatomic hydrogen (H2), argon (Ar), xenon (Xe), diatomic nitrogen (N2), or any other carrier gases or inert gases that may be useful in semiconductor processing may be provided.

[0044]

[0049] As mentioned above, one or more deposition precursors may bind and interact before reaching the processing area. This technique can utilize silicon and halogen-containing precursors that may not spontaneously react with metal-containing precursors. In conventional techniques, it has been difficult to form silicon and metal-containing materials due to the spontaneous interaction between silicon-containing precursors and metal-containing precursors. Such reactions produce large amounts of residue, resulting in material layers with either very low or very high metal concentrations. By utilizing more compatible precursors, such as halogen-containing silicon-containing precursors, spontaneous reactions between one or more deposition precursors can be reduced and / or eliminated. By utilizing silicon and halogen-containing precursors, this technique can also enable an adjustable process window that allows for a wider range of metal concentrations in the deposited material compared to conventional techniques.

[0045]

[0050] In embodiments, method 400 may include cyclically controlling the flow rate of one or more deposition precursors during deposition. For example, the flow rate of a metal-containing precursor may be greater than that of a silicon- and hydrogen-containing precursor during a first period. After a certain amount of deposition, the flow rate of the metal-containing precursor may be less than that of a silicon- and hydrogen-containing precursor during a second period. By cyclically controlling the flow rates of one or more deposition precursors, such as a silicon- and halogen-containing precursor and a metal-containing precursor, the degree of gas-phase reactions between the deposition precursors can be reduced. In embodiments, each period may be the same or different, and may range from about 0.05 seconds to about 2 seconds.

[0046]

[0051] As mentioned above, some embodiments may include a plasma-enhanced deposition process, which may generate plasma emissions of one or more deposition precursors. The plasma power may be a source power of 13.56 MHz and affects the amount of metal concentration in the deposited material, with higher plasma power generating more silicon incorporated into the material. Therefore, depending on the desired metal concentration, the plasma power may be greater than or about 200 W, greater than or about 300 W, greater than or about 400 W, greater than or about 500 W, greater than or about 750 W, greater than or about 1,000 W, greater than or about 1,250 W, greater than or about 1,750 W, greater than or about 2,000 W, or even higher. Similarly, for materials with reduced metal content, the plasma output may be maintained at less than 3,000W or about 3,000W, less than 2,750W or about 2,750W, less than 2,500W or about 2,500W, less than 2,250W or about 2,250W, less than 2,000W or about 2,000W, less than 1,750W or about 1,750W, less than 1,500W or about 1,500W, less than 1,250W or about 1,250W, less than 1,000W or about 1,000W, or less.

[0047]

[0052] The temperature of substrate 505 may affect the deposition process. For example, in some embodiments during deposition, the substrate 505, pedestal, and semiconductor processing chamber may be maintained at a temperature above or about 50°C, above or about 100°C, above or about 150°C, above or about 200°C, above or about 250°C, above or about 300°C, above or about 350°C, above or about 375°C, above or about 400°C, above or about 425°C, above or about 450°C, above or about 475°C, above or about 500°C, above or about 525°C, above or about 550°C, above or about 575°C, above or about 600°C, or higher. By performing deposition according to several embodiments of this technology, the metal content in the silicon and metal-containing material 515 layer can be controlled. As the temperature increases, the silicon content in the silicon and metal-containing material 515 layer may increase, and therefore the metal content may decrease. Conversely, as the temperature decreases, the silicon content in the silicon and metal-containing material 515 layer may decrease, and therefore the metal content may increase. Therefore, in some embodiments, the substrate 505, pedestal, and / or semiconductor processing chamber may be maintained at a temperature of less than 600°C or about 600°C, less than 575°C or about 575°C, less than 550°C or about 550°C, less than 525°C or about 525°C, less than 500°C or about 500°C, less than 475°C or about 475°C, less than 450°C or about 450°C, less than 425°C or about 425°C, less than 400°C or about 400°C, less than 375°C or about 375°C, less than 350°C or about 350°C, less than 300°C or about 300°C, less than 250°C or about 250°C, less than 200°C or about 200°C, less than 150°C or about 150°C, less than 100°C or about 100°C, less than 50°C or about 50°C, or below.

[0048]

[0053] As described above, this technology can increase the deposition rate of silicon and metal-containing material layers, thereby improving throughput and reducing latency. For example, deposition may be performed at pressures greater than or about 0.1 Torr, greater than or about 0.5 Torr, greater than or about 1 Torr, greater than or about 5 Torr, greater than or about 6 Torr, greater than or about 7 Torr, greater than or about 8 Torr, greater than or about 9 Torr, greater than or about 10 Torr, greater than or about 15 Torr, greater than or about 30 Torr, greater than or about 50 Torr, or higher. Similarly, deposition may be carried out at pressures of less than or about 100 Torr, less than or about 75 Torr, less than or about 50 Torr, less than or about 40 Torr, less than or about 30 Torr, less than or about 20 Torr, less than or about 15 Torr, less than or about 10 Torr, or less than or about 10 Torr.

[0049]

[0054] This technology allows for the deposition of layers of silicon and metal-containing material 515 at a rate exceeding or approximately 500 Å / m (for example, exceeding or approximately 525 Å / m, exceeding or approximately 550 Å / m, exceeding or approximately 575 Å / m, exceeding or approximately 600 Å / m, exceeding or approximately 625 Å / m, exceeding or approximately 650 Å / m, exceeding or approximately 675 Å / m, exceeding or approximately 700 Å / m, exceeding or approximately 725 Å / m, exceeding or approximately 750 Å / m, or higher).

[0050]

[0055] By performing the process according to embodiments of this technology, metal can be included in the silicon and metal-containing material 515 layer in any amount or concentration. In embodiments, the metal may be included in the silicon and metal-containing material 515 layer in an amount greater than or about 1 at.%; in some embodiments, greater than or about 2 at.%; greater than or about 3 at.%; greater than or about 4 at.%; greater than or about 5 at.%; greater than or about 6 at.%; greater than or about 7 at.%; greater than or about 8 at.%; greater than or about 9 at.%; greater than or about 10 at.%; greater than or about 11 at.%; greater than or about 12 at.%; greater than or about 13 at.%; greater than or about 14 at.% It may include approximately 14 at.%, more than 15 at.%, more than 16 at.%, more than 17 at.%, more than 18 at.%, more than 19 at.%, more than 20 at.%, more than 25 at.%, more than 30 at.%, more than 40 at.%, more than 50 at.%, more than 60 at.%, more than 70 at.%, more than 80 at.%, more than 90 at.%, or more than 90 at.%, or higher. However, since metal content can reduce not only hardness but also transparency, in some embodiments the metal concentration may be maintained at less than or about 50 at.%, less than or about 45 at.%, less than or about 40 at.%, less than or about 35 at.%, less than or about 30 at.%, less than or about 25 at.%, less than or about 20 at.%, or less than or about 20 at.%. In embodiments, the silicon and metal-containing material 515 layers may not contain fluorine, oxygen, or both.

[0051]

[0056] This technology enables high etching selectivity for the underlying material by incorporating an increased metal concentration within the material layer. Furthermore, this technology can provide a material with a smooth morphology. Material adhesion can be enhanced by optional pretreatment and / or seed layer formation. Therefore, this technology provides silicon and metal-containing materials for hard masks that may optionally contain one or more of boron, carbon, or nitrogen.

[0052]

[0057] The above description includes numerous details for explanatory purposes to provide an understanding of the various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0053]

[0058] While several embodiments are disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the essence of the embodiments. Furthermore, to avoid unnecessarily obscuring the Art, some well-known processes and elements are not described. Therefore, the above description should not be construed as limiting the scope of the Art. Moreover, while methods or processes may be described sequentially or stepwise, it should be understood that steps may be performed simultaneously or in an order different from that listed.

[0054]

[0059] Where a range of values ​​is provided, each of the intervening values ​​between the upper and lower limits of that range is understood to be specifically disclosed down to the smallest unit of the lower limit (unless explicitly indicated otherwise in the context). Narrower ranges between any two listed values ​​or between unlisted intervening values ​​within a given range, and other listed or intervening values ​​within such ranges, are included. The upper and lower limits of such narrower ranges may, individually, be included in or excluded from this range. Each range in which one, neither, or both of the limit values ​​are included in this art, provided that there are limit values ​​specifically excluded within the given range. Where one or both of the limits are included in a given range, the range excluding one or both of the included limits is also included.

[0055]

[0060] In this specification and the appended claims, the singular “a, an” and “the” imply a plural meaning (unless explicitly indicated otherwise in the context). Thus, for example, “a precursor” includes multiple such precursors, “the layer” includes one or more layers and their equivalents known to those skilled in the art, and so on.

[0056]

[0061] Furthermore, when used in this specification and subsequent claims, the terms “comprise(s) / comprising,” “contain(s) / containing,” and “include(s) / including” are intended to identify the presence of a described feature, integer, component, or process, but not to exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, To provide a deposition precursor for a processing area of ​​a semiconductor processing chamber, wherein the deposition precursor comprises a silicon and halogen-containing precursor and a metal-containing precursor, and the substrate is housed within the processing area. To generate plasma ejecta from the aforementioned deposition precursor, Forming layers of silicon and metal-containing material on the aforementioned substrate A semiconductor processing method, including the following.

2. The aforementioned silicon and halogen-containing precursor is silicon tetrafluoride (SiF ４ The semiconductor processing method according to claim 1, including ).

3. The semiconductor processing method according to claim 1, wherein the metal-containing precursor comprises one or more of tungsten, molybdenum, cobalt, tantalum, ruthenium, titanium, rhenium, hafnium, or zirconium.

4. The semiconductor processing method according to claim 1, wherein the metal-containing precursor further comprises a halogen.

5. The semiconductor processing method according to claim 1, wherein the deposition precursor further comprises one or more of a boron-containing precursor, a carbon-containing precursor, or a nitrogen-containing precursor.

6. The flow rate of the deposition precursor is made cyclic, wherein during a first period, the flow rate of the metal-containing precursor is greater than the flow rate of the silicon and hydrogen-containing precursor, and during a second period, the flow rate of the metal-containing precursor is less than the flow rate of the silicon and hydrogen-containing precursor. The semiconductor processing method according to claim 1, further comprising:

7. The semiconductor processing method according to claim 1, wherein the silicon and metal-containing material layer is characterized by a metal concentration of more than 20 at.% or about 20 at.%.

8. The substrate is pre-treated before forming the silicon and metal-containing material layers. The semiconductor processing method according to claim 1, further comprising:

9. Pre-processing the aforementioned substrate To provide a nitrogen-containing precursor to the processing region of the semiconductor processing chamber, To generate plasma emissions of the nitrogen-containing precursor, The substrate is brought into contact with the plasma emitted from the nitrogen-containing precursor. The semiconductor processing method according to claim 8, including the method described in claim 8.

10. After pre-treating the substrate, a seed layer is formed on the substrate. The semiconductor processing method according to claim 8, further comprising:

11. The semiconductor processing method according to claim 10, wherein the seed layer comprises an amorphous boron-containing material.

12. A semiconductor processing method, To provide a deposition precursor for a processing area of ​​a semiconductor processing chamber, wherein the deposition precursor comprises a silicon and halogen-containing precursor and a metal-containing precursor, and the substrate is housed within the processing area. The method involves generating the plasma emission of the deposition precursor, wherein the plasma emission of the deposition precursor is generated with a plasma output exceeding 200 W or approximately 200 W. Forming layers of silicon and metal-containing material on the aforementioned substrate A semiconductor processing method, including the following.

13. The semiconductor processing method according to claim 12, wherein the plasma emission of the deposition precursor is generated with a plasma output of less than 2,000 W or about 2,000 W.

14. The semiconductor processing method according to claim 12, wherein the silicon and metal-containing material layer does not contain fluorine, oxygen, or both.

15. Before providing the deposition precursor, the substrate is pre-treated to form a seed layer on the substrate. The semiconductor processing method according to claim 12, further comprising:

16. The semiconductor processing method according to claim 12, wherein the temperature within the processing area is maintained at less than 600°C or approximately 600°C.

17. The semiconductor processing method according to claim 12, wherein the pressure in the processing area is maintained at less than 50 Torr or about 50 Torr.

18. A semiconductor processing method, To provide a silicon-containing precursor and a metal-containing precursor in a processing area of ​​a semiconductor processing chamber, wherein the substrate is housed within the processing area. The method involves forming a layer of silicon and metal-containing material on the substrate, wherein the layer of silicon and metal-containing material is characterized by a metal concentration of more than 20 at.% or approximately 20 at.%. A semiconductor processing method, including the following.

19. The silicon-containing precursor is silicon tetrafluoride (SiF ４ ) contains, and the metal-containing precursor is tungsten hexafluoride (WF ６ The semiconductor processing method according to claim 18, including ).

20. The semiconductor processing method according to claim 18, wherein the silicon and metal-containing material layer is formed at a speed of more than 500 Å / m or about 500 Å / m.

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