Methods for variable angle etching, pattern improvement, cyclic surface adjustment, and etching of sidewalls of feature areas.

Abstract

This invention relates to a method for controlling the sidewall roughness and reducing structural defects of feature areas on a substrate. The method includes adjusting the inclination angle of a particle beam for oblique incidence particle beam etching of at least one sidewall of a feature area. This technique enables improved control of sidewall roughness and reduction of structural defects in various applications such as semiconductor manufacturing. Methods for pattern improvement, cyclic surface preparation, and etching the sidewalls of feature areas are also disclosed.

Description

Technical Field

[0001] This technology relates to the field of semiconductor manufacturing. Specifically, it relates to processes for controlling sidewall roughness, reducing structural defects of features on a substrate, etching the sidewalls of features on a substrate, and areas of methods for improving the smoothness and uniformity of various surfaces such as semiconductor, metal, dielectric, and 2D material surfaces. This is a critical process in the manufacture of integrated circuits, microelectromechanical systems (MEMS), and other microscale and nanoscale devices.

Background Art

[0002] In the field of semiconductor processing, it is often desirable to create precise patterns, structures, and features on a substrate surface. These structures are typically formed using photolithography techniques where a pattern is defined in a photosensitive material called a resist. The resist is then used as a mask to transfer the pattern onto the substrate by etching or deposition.

[0003] One of the main challenges in semiconductor processing is the reduction of line edge roughness (LER). LER is quantified as the root mean square deviation of the line edge profile from an ideal straight line in the horizontal plane. LER is one of the most critical metrics of fabrication process performance, and thus obtaining substantial LER values is a well-known challenge in modern state-of-the-art semiconductor processing. LER is caused by several effects during the fabrication process. As LER becomes comparable to the critical dimension (CD) of semiconductor devices, it becomes increasingly difficult to control the process and achieve well-defined and reproducible structures. Since LER does not increase or decrease with feature size, when the feature size is well below 100 nm, LER ultimately becomes a factor limiting resolution in lithography. Therefore, minimizing LER is essential to achieve the highest possible resolution.

[0004] Reduced sidewall roughness is important for all different structures on the substrate, including dots, holes, fins, and other structures, as well as lines commonly referred to as LERs, and those used in micro-electromechanical systems (e.g., resonators). In this case, it is important to reduce the deviation of the sidewall outline from the sidewall tangent plane. Hereafter, all of this will be referred to as sidewall roughness reduction. In a more general concept, this is called sidewall roughness control, meaning that the sidewall surface is adjusted to a desired roughness level on different specific surfaces. Furthermore, it is important to efficiently reduce structural defects such as striations, bows, and scallops of the sidewall and roughness of the horizontal top surface, minimizing damage to different layers and areas during preceding processing. Hereafter, this will be referred to as structural defect reduction. [Overview of the project] [Problems that the invention aims to solve]

[0005] In view of the foregoing, it is desirable to provide a method for overcoming the shortcomings of the prior art, reducing LER, controlling the sidewall roughness of different feature areas on a substrate, and reducing structural defects. This disclosure addresses these and other objectives. [Means for solving the problem]

[0006] In a first aspect, the present invention provides a method for controlling the sidewall roughness and reducing structural defects of a feature area on a substrate. The method includes adjusting the inclination angle of a particle beam for oblique incidence particle beam etching of at least one sidewall of the feature area.

[0007] In some embodiments, the method further includes a combination of conformal deposition and variable-angle etching to achieve sidewall roughness control and structural defect reduction. The method also includes alternating the deposition step and the etching step to achieve sidewall roughness control and structural defect reduction.

[0008] Optionally, the method may further include self-limiting reactions such as chemiadsorption, deposition, extraction, oxidation, nitriding, or conversion. The particle beam used in the method may include neutral particles, radicals, photons, ions, electrons, or combinations thereof. The inclination angle of the particle beam can be in the range of 0 to 85 degrees from the angle of the perpendicular line of the substrate.

[0009] In some embodiments, sidewall roughness control results in at least a 50% reduction in line-edge roughness (LER). Sidewall roughness control and defect reduction may include adjusting the tilt angle of the particle beam during oblique incidence etching or self-limiting reactions, or a combination thereof. Deposition, etching, or self-limiting reactions, or a combination thereof, may be selectively applied to specific areas.

[0010] In certain embodiments, deposition is performed using atomic layer deposition (ALD). The substrate, having its patterned two- and three-dimensional features, and the particle beam can be rotated relative to each other during oblique incidence etching. Sidewall roughness control can result in reduced sidewall roughness. Oblique incidence etching can be performed using atomic layer etching (ALE).

[0011] In some embodiments, the etching process is selective for silicon or silicon oxide. The tilt of the particle beam can be 0 degrees from the angle of the line perpendicular to the substrate, and thus the process can be carried out without adjusting the tilt angle of the particle beam during particle beam etching. The deposited material may be amorphous or glassy.

[0012] Optionally, at least some of the beam particles have an atomic mass lower than at least one of the components of the exposed surface. The method may further include rapid surface temperature cycling. The material being deposited may be the same as the material being etched.

[0013] A second aspect of this disclosure provides a method for reducing the sidewall roughness of feature portions on a substrate. The feature portions are spaced apart and each has a field region and a sidewall. (<- To be deleted, but left as a comment) The method includes forming a patterned and selectively protective masking layer such that at least a portion of the field region is masked and the sidewall is not masked. The method also includes performing dry etching in a process chamber surrounding the substrate. This involves creating a horizontal component of the etching direction by setting the pressure in the process chamber to exceed a defined pressure threshold for sidewall etching. The horizontal component etches the sidewall that is not masked for the reduction of the sidewall roughness. This method enables precise etching of the sidewall, thus reducing the sidewall roughness, and does not require tilting the substrate or particle beam to target the sidewall using directional etching. Therefore, this process is less complex to implement than conventional solutions.

[0014] Optionally, in some examples, the defined pressure threshold for sidewall etching is 40 mTorr. This specific pressure threshold has been found to be particularly effective in producing the desired horizontal component in the etching direction, leading to more efficient and effective roughness reduction.

[0015] Optionally, in some examples, dry etching is self-limiting, so that dry etching stops when the sidewall roughness is reduced by a threshold amount. The plasma energy is lower than the bulk binding energy of the material in the original feature area. This stops the etching process after the roughness has been removed, allowing the applied plasma to have lower energy than the remaining material and preventing over-etching.

[0016] Optionally, in some examples, sidewall roughness is reduced by at least 50%. This significant reduction in roughness can greatly improve the performance and reliability of feature areas on the substrate.

[0017] Optionally, in some examples, the line-edge roughness of the sidewalls is reduced to a value below 1 nm root mean square (RMS). Here, line-edge roughness (LER) is quantified as the RMS deviation of the line-edge outline from a straight line in the horizontal plane. This extremely low level of roughness can further enhance the performance of feature parts, especially in applications requiring very high precision.

[0018] Optionally, in some examples, the method further includes self-limiting reactions. A self-limiting reaction is a reaction that slows down or stops as a function of time, or equivalently, as a function of the species supply. Self-limiting reactions can include, but are not limited to, chemiadsorption, deposition, transformation (e.g., oxidation, nitriding), and extraction. Chemiadsorption is a chemical adsorption process caused by a reaction on an exposed surface, creating an electronic bond between the surface and the adsorbent with a bond energy greater than 0.5 eV per adsorbed species. During the chemical reaction, distinct chemical species are created on the adsorbent surface, and these species cause the bond to form. In the case of extraction, the original material is a compound, and the modification preferentially removes one element from the surface, while other elements are removed in subsequent removal steps. These reactions provide additional control over the etching process, which can further enhance the precision and effectiveness of roughness reduction.

[0019] In some cases, optionally, self-limiting reactions or dry etching are selectively applied to specific areas of the substrate. This selectivity means that the process is preferentially applied to certain surfaces or materials, while being suppressed on other surfaces or materials; i.e., the suppressed process has a significantly reduced process rate. This selective application allows for greater control over the etching process, enabling roughness reduction to be adapted to the specific needs of various areas of the substrate.

[0020] Optionally, in some examples, dry etching is performed using atomic layer etching (ALE). ALE is a high-precision etching technique that can further enhance the effect of roughness reduction and accuracy.

[0021] Optionally, in some examples, dry etching is a cyclic etching process. This cyclic process can apply additional control to the etching and enables more precise and effective roughness reduction.

[0022] Optionally, in some examples, dry etching is selective to materials including any of silicon, silicon oxide, silicon nitride, hafnium oxide, and aluminum oxide. This selectivity can enable precise and effective roughness reduction without damaging other materials on the substrate, and can be particularly beneficial in applications where features on the substrate are made from these materials.

[0023] Optionally, in some examples, the method further includes rapid surface temperature cycling. Here, rapid surface temperature cycling is defined as rapid heating and cooling of the surface, which may be performed once or repeated multiple times. The heating process requires less than 5 minutes, typically less than 30 seconds, in some examples. This can enhance the effect of the etching process and lead to more efficient and effective roughness reduction.

[0024] Optionally, in some examples, rapid surface temperature cycling is performed by surface exposure to plasma. This provides a very effective means of rapidly cycling the surface temperature and can further enhance the effect of the etching process.

[0025] Optionally, in some examples, rapid surface temperature cycling is assisted using flash light. This provides a convenient and effective means of rapidly cycling the surface temperature and can further enhance the effect of the etching process.

[0026] Optionally, in some examples, rapid surface temperature cycling assisted by flash light is performed using a laser light source. This provides a very precise and effective means of rapidly cycling the surface temperature and can further enhance the effect of the etching process.

[0027] Optionally, in some examples, features on the substrate include any of microscale and nanoscale devices, waveguides, transistors, fins, protrusions, grooves, holes, and / or pillars. This method can be applied to a wide range of different features, is very versatile, and enables it to be applied to a wide range of different applications.

[0028] According to a third aspect of the present disclosure, a method for surface conditioning based on cyclic processing is provided. The method includes activating the surface, removing excess material from the surface and the surrounding environment, subjecting the surface to low-energy particle treatment, and repeating the above steps until the surface has the desired smoothness. Optionally, the low-energy particle treatment may use ions and may be atomic layer etching (ALE) or atomic layer etching with molecular activation. The cyclic processing may also include a deposition step that results in atomic layer deposition (ALD).

[0029] The method may include a combination of etching and deposition and may involve alternating etching and deposition. The repetition of the steps can be performed until the process no longer has an impact on different processed surfaces. The method can further include ion beam shaping techniques and oblique incident particle beam etching.

[0030] The surface processed by the method can be a sidewall surface or an inclined surface and can be selected from the group consisting of semiconductor surfaces, metal surfaces, dielectric surfaces, and 2D material surfaces. The surface can be a patterned surface or an unpatterned surface.

[0031] Surface activation may include exposing the surface to a gas, exposing the surface to a chemical solution, heating the surface to a specific temperature, or irradiating the surface with a particle beam. Low-energy particle treatment may include low-energy particle beams with particle energies between 10 eV and 100 eV, or low-energy plasma treatment with plasma power between 1 W and 50 W.

[0032] Surfaces prepared by the method are also provided.

[0033] A fourth aspect of the present disclosure provides a method for etching the sidewalls of feature portions on a substrate. The feature portions are spaced apart and each has a field region and sidewalls. The method includes providing a composite masking layer on the feature portions. The composite masking layer includes a first masking layer and a second masking layer on top of the first masking layer. At least a portion of the field region is masked by the composite masking layer, while the sidewalls are not masked. The method further includes etching the sidewalls. During this process, the second masking layer prevents etching of the first masking layer so that the height of the feature portions and the first masking layer relative to the substrate is maintained. The method includes removing the first masking layer, thereby removing any remaining portion of the second masking layer. The method ensures that the feature portions are left on the substrate at their original intended heights, thus preventing height reduction of the feature portions during sidewall etching.

[0034] Optionally, in some examples, the first masking layer has the same etching properties as the feature portion on the substrate. This means that etching of the sidewalls of the feature portion removes the material of the sidewalls of the first masking layer at at least the same rate as etching the material of the feature portion. This ensures that when sidewall etching occurs, the first masking layer and the feature portion on the substrate can be removed at the same rate.

[0035] Optionally, in some examples, the second masking layer is formed from a material with a lower etching rate than the material of the first masking layer. This prevents etching of the first masking layer during sidewall etching and maintains the height of the feature area and the first masking layer relative to the substrate.

[0036] Optionally, in some examples, the first masking layer is selectively removed after etching the sidewalls. This ensures that the height of the feature area after sidewall etching is the same as before sidewall etching. Alternatively, any remaining portion of the second masking layer and any residual material can be removed, leaving the feature area on the substrate at its original intended height.

[0037] Optionally, in some examples, the first masking layer separates the feature area from the residual material after etching of the sidewalls. This separation allows the feature area to have essentially uninterrupted vertical sidewalls relative to the substrate after etching, thus facilitating the subsequent easy removal of the residual material.

[0038] Optionally, in some examples, residual material adheres to the first and / or second masking layer, thereby being removed along with the removal of the first masking layer. This ensures that the feature areas are left on the substrate at their original intended heights, and that the residual material instead adheres to the first and / or second masking layer, facilitating their removal without affecting the feature areas.

[0039] Optionally, in some examples, the composite masking layer includes a third masking layer. The third masking layer is positioned between the feature and the first masking layer. The material of the third masking layer is different from the material of the feature. This is advantageous when it is difficult to find a suitable material for the first masking layer. The third masking layer separates the feature from the residual material after sidewall etching, ensuring that after sidewall etching, the feature has essentially uninterrupted vertical sidewalls relative to the substrate. Selective removal of the third masking layer results in the removal of the entire composite masking layer after sidewall etching, leaving the feature on the substrate with its originally intended height.

[0040] Optionally, in some examples, the thickness of the third masking layer is smaller than that of the first masking layer. This ensures that the third masking layer is thin enough to effectively etch the feature area at at least the same rate as the sidewalls of the feature area, while separating the feature area from the first masking layer.

[0041] In some cases, the thickness of the third masking layer is less than 10 nm, optionally.

[0042] Optionally, in some examples, the etching rate of the sidewalls of the third masking layer corresponds at least to the etching rate of the sidewalls of the feature portion during the etching of the sidewalls of the feature portion. This ensures that the third masking layer and the feature portion on the substrate can be removed at the same rate during sidewall etching.

[0043] Optionally, in some examples, the material of the first masking layer is the same as the material of the feature area. The first masking layer can be provided as a soft mask with the same material as the feature area, thereby exhibiting the same etching properties as the feature area, while being easily removed when separated from the feature area by the third masking layer.

[0044] Optionally, in some examples, the method includes removing a third masking layer, thereby removing any remaining portion of the first and second masking layers. This ensures that the entire composite masking layer is removed after etching of the sidewalls, leaving the feature portions on the substrate at their original intended heights.

[0045] Optionally, in some examples, a third masking layer separates the feature from the residual material after etching the sidewalls, so that the feature has essentially uninterrupted vertical sidewalls relative to the substrate. This ensures that the feature is left on the substrate at their original intended height, and instead the residual material adheres to one of the masking layers.

[0046] Optionally, in some examples, a third masking layer separates the first masking layer from the feature portion such that the feature portion and the third masking layer have essentially uninterrupted vertical sidewalls relative to the substrate after sidewall etching. This ensures that the feature portion is left on the substrate at their original intended height, and instead, residual material adheres to the first and / or second masking layer.

[0047] Next, this disclosure will be described in more detail with reference to the attached drawings. Numbers should not be taken restrictively, but rather used for illustrative and understanding purposes. [Brief explanation of the drawing]

[0048] [Figure 1a-1f] This figure shows a cyclic sidewall roughness and defect reduction process using a self-limiting reaction and obliquely incident particle beam etching, resulting in a final structure with desired sidewall roughness. In this case, two cycles are exemplified. [Figure 2a-2d] This figure shows a process for reducing cyclic sidewall roughness and structural defects using a combination of atomic layer deposition (ALD) and variable-angle etching. In this case, one cycle is illustrated. [Figure 3]This block diagram shows the execution process flow of a method combining ALD and variable-angle etching for sidewall roughness control. [Figure 4] This is a schematic representation of the desired size and outline of a patterned feature on a substrate. [Figure 5] This is an explanatory diagram of the actual surface of a feature area before the completion of a method for reducing sidewall roughness, also known as Atomic Level Improvement. [Figure 6] This figure shows a large structure after lithography and before atomic-level pitch splitting (APS). [Figure 7] This figure shows the structure after APS (Advanced Plastic Surgery) and before the completion of methods for reducing sidewall roughness. [Figure 8] This figure shows the structure after APS (Advanced Plastic Surgery) and after the completion of methods for reducing sidewall roughness. [Figure 9] This figure shows an example of a surface preparation method based on cyclic processing. [Figure 10] This figure shows another example of a surface preparation method based on cyclic processing. [Figure 11] This figure shows another example of a surface preparation method based on cyclic processing. [Figure 12] This flowchart shows a method for surface preparation based on cyclic processing according to an example of the present disclosure. [Figure 13] These are atomic force microscope (AFM) images of the initial and final surfaces after a cyclic process, as an example. [Figures 14A-14B] These are cross-sectional views of a substrate in various intermediate processes of oblique incidence particle beam etching without a masking layer, where both the width and height of the feature area are reduced. [Figure 15A-15C] This is a cross-sectional view of the substrate after various intermediate steps of oblique incident particle beam etching using a hard mask layer 4300, as well as after removal of the masking layer and unwanted structures 4131, illustrating the formation of artifact features during the etching process. [Figure 16A-16C] This is a cross-sectional view of a substrate in various intermediate steps of oblique incidence particle beam etching using a composite masking layer including a first masking layer 4400 and a second masking layer 4300, where the original vertical size of the feature area is maintained after removal of the composite masking layer. [Figures 17A-17C] This is a cross-sectional view of a substrate at various intermediate steps of oblique incidence particle beam etching using a composite masking layer including a third masking layer 4500, a first masking layer 4400, and a second masking layer 4300, showing the preservation of the original vertical size of the feature area after removal of the masking layer. [Modes for carrying out the invention]

[0049] Definition of Terms • Oblique incidence particle beam etching - Surface etching that operates in a specific regime where etching occurs only when driven by particle beam collisions. The particle beam can contain neutral particles, radicals, photons, ions, electrons, or a combination thereof. The inclination angle of the particle beam can range from 0 to 85 degrees perpendicular to the surface plane.

[0050] • Perpendicular to the surface plane - Perpendicular to any two intersecting lines on the surface plane.

[0051] • Variable angle etching - Adjusting the angle of the particle beam for oblique incidence particle beam etching.

[0052] • Particle beam - Multiple arriving particles with an angular velocity distribution of less than 10 degrees full width at half maximum (FWHM).

[0053] • Sidewall Roughness Control - Adjustment of the sidewall surface to a desired roughness level. Sidewall surface roughness is quantified as the root mean square of the deviation of the sidewall outline from the sidewall tangent plane.

[0054] • Structural defect reduction - Reduction of structural surface defects such as striations, bows, punctate defects, scallops, and roughness of horizontal surfaces on sidewalls. This defect reduction also includes minimizing different surface layers and areas damaged during preceding processing, for example, during the preceding etching process.

[0055] Atomic layer etching (ALE) is defined as an etching technique that utilizes a series of half-reactions to result in layer-by-layer material reduction. The implementation of ALE consists of at least two sequential steps: surface modification (reaction A) and removal (reaction B). These reactions can be cycled, and at least one step is at least partially self-limiting. The modification step forms a thin reactive surface layer of a clearly defined thickness, which is then removed more easily than the unmodified material. The layer is characterized by a steep gradient of chemical composition. Removal methods include thermal desorption, particle bombardment, and chemical reactions. Here, the ALE process also includes quasi-atomic layer etching processes, which may include quasi-self-limiting and non-self-limiting reactions.

[0056] • Self-limiting reactions – reactions that slow down or stop as a function of time, or equivalently as a function of the seed supply. Self-limiting reactions can include, but are not limited to, chemiadsorption, deposition, transformation (e.g., oxidation, nitriding), and extraction. In the case of extraction, the original material is a compound, and the modification preferentially removes one element from the surface, while other elements are removed in subsequent removal steps.

[0057] Chemisorption - A chemical adsorption process triggered by reactions on exposed surfaces, creating electronic bonds between the surface and the adsorbed material with bond energies exceeding 0.5 eV per adsorbed species. During the chemical reaction, separate chemical species are created on the surface of the adsorbed material, and these species cause the bonds to form.

[0058] • Physical adsorption - Adsorption where intermolecular interactions between adsorbed molecules and the adsorbed material are mainly governed by van der Waals forces, and the binding energy between the surface and the adsorbed material per adsorbed species is 0.5 eV or less.

[0059] Atomic layer deposition (ALD) is defined as a deposition technique that utilizes a series of half-reactions to result in layer-by-layer material addition. These reactions can be cycled, and at least one step is at least partially self-limiting. Here, the ALD process also includes quasi-atomic layer deposition processes, which may include quasi-self-limiting and non-self-limiting reactions.

[0060] • Exposed surface - The substrate surface to be treated.

[0061] • Rapid surface temperature cycling - Rapid heating and cooling of the surface, which may be performed only once or repeated multiple times. The heating process takes less than 5 minutes, typically less than 30 seconds.

[0062] • Line-edge roughness (LER) - Quantified as the root mean square deviation of the line-edge outline shape from a straight line in a horizontal plane.

[0063] • Selective process - A process that is preferentially applied to certain surfaces or materials, while being suppressed on other surfaces or materials.

[0064] • Suppressed process - A process with a significantly reduced process speed.

[0065] • Conformal deposition - A method of deposition where the deposition rate is the same on all surfaces, regardless of the geometric orientation. ALD is an example of conformal deposition.

[0066] Next, the present disclosure will be described in detail with reference to exemplary embodiments. It should be understood that these exemplary embodiments are provided for illustrative purposes only and are not intended to limit the scope of the present disclosure. A. Variable angle etching According to the embodiment shown in Figure 1, a sidewall roughness control method is provided for improving the sidewall roughness of a feature portion on a substrate. The substrate 100 has a feature portion 110 with sidewalls 111 and 112 having initial sidewall roughness. The method includes a step of a self-limiting reaction 300 shown in Figures 1b and 1d, and a step of obliquely incident particle beam 200 etching shown in Figures 1c and 1e, to modify sidewall 111 to sidewalls 113 and 114 to reduce the sidewall roughness of the feature portion 110.

[0067] As shown in Figures 1a to 1f, the following steps may occur during a sidewall roughness reduction process utilizing oblique incident particle beam etching of the sidewalls of feature regions: Figure 1a shows an initial structure with sidewall roughness, where the feature portion 110 is formed on the substrate 100. The sidewalls 111 and 112 of the feature portion 110 have initial surface roughness that needs to be reduced in order to improve the sidewalls.

[0068] In Figures 1b and 1d, the initial structure is processed by a self-limiting reaction 300. This self-limiting reaction slows down or stops as a function of time, or equivalently as a function of the seed supply. Self-limiting reactions may include, but are not limited to, chemiadsorption, deposition, transformation (e.g., oxidation, nitriding), and extraction. In the case of extraction, the original material is a compound, and the modification preferentially removes one element from the surface, while other elements are removed in subsequent removal steps. In the case of chemiadsorption, the reaction on the exposed surface creates an electronic bond between the surface and the adsorbed material.

[0069] In Figures 1c and 1e, a particle beam source (not shown) generates an obliquely incident particle beam 200 adjusted to an appropriate inclination angle, creating obliquely incident particle beam etching of the side walls 111 and 113 of the feature section 110.

[0070] Figure 1f shows the processed structure after the obliquely incident particle beam etching process. The original sidewall 111 is now transformed into sidewall 114, which exhibits a new surface roughness smaller than the initial surface roughness, while sidewall 112, which was not subjected to obliquely incident particle beam etching, remains the same or has only minimal modification. The newly smoothed sidewall surface leads to a reduction in sidewall roughness of the feature portion 110, in this case only on one side.

[0071] In modified examples, as shown in Figures 2a to 2d, the sidewall roughness reduction process may involve a combination of conformal deposition, preferably ALD, and variable-angle etching.

[0072] • Figure 2a shows the initial structure with sidewall roughness, which is the same as that shown in Figure 1a.

[0073] In Figure 2b, the initial structure is fabricated using conformal thin film 400 deposition, preferably ALD, resulting in new sidewalls 115 of the feature portion 110.

[0074] In Figure 2c, variable-angle particle beam assisted etching 501 and 502 performs obliquely incident particle beam etching on the sidewalls 115, resulting in smoothing of the initial surface roughness of these sidewalls.

[0075] Figure 2d shows the final structure with the desired sidewall surface 114 and reduced sidewall roughness of the feature portion 110, while retaining the original critical dimensions of the feature portion 110. A1. Device In one example, an apparatus for controlling sidewall roughness and reducing structural defects in feature areas on a substrate comprises a particle beam source, a wafer, a substrate holder, and a vacuum chamber or several separate vacuum chambers. The apparatus may be designed to provide a controlled environment for etching and deposition processes, ensuring precise control over the tilt angle of the particle beam and enabling reduction of sidewall roughness and defects in feature areas on the substrate. A1.1. Particle beam source In some examples, a particle beam source generates an ion beam for surface irradiation purposes, which may include ion beam-assisted etching and deposition processes. The particle beam source may include a variable tilt angle mechanism for adjusting the ion beam tilt angle for optimized processing, including etching and deposition. The variable tilt angle mechanism may have a tilt angle range of 0 to 85 degrees from the angle of the vertical line of the wafer, and a tilt angle accuracy of within 10 degrees, preferably within 1 degree. The particle beam may contain different species, such as neutral particles, radicals, ions, electrons, photons, or combinations thereof. Examples of ionic species include helium (He), argon (Ar), nitrogen (N), oxygen (O), fluorine (F), chlorine (Cl), bromine (Br), gallium (Ga), hydrogen (H), neon (Ne), krypton (Kr), xenon (Xe), iodine (I), and astatine (At). The ion energy range may be less than 5000 eV, with an example ion energy range of 0 to 2000 eV. The ion beam may be line-focused to a length greater than 10 mm, with examples of ion beam lengths exceeding 200 mm and up to 400 mm. The divergence angle of the ion beam is adjustable and may be less than 10 degrees FWHM, and the uniformity of the ion beam may be less than 2% on the wafer surface. The particle beam may also include a neutral particle beam, a radical beam, a photon beam, an electron beam, or a combination of particle beams. The apparatus may include an obliquely incident particle beam 200 adjusted to an appropriate inclination angle to produce obliquely incident particle beam etching, or variable-inclination particle beams 501 and 502 for variable-inclination etching. A1.2. Wafer In some cases, a wafer is a substrate that is supported and placed during processing by a substrate holder in a vacuum chamber. Wafers can be made from a variety of materials, such as silicon, aluminum oxide, or other semiconductor materials, metallic materials, or dielectric materials, and can have various sizes and shapes depending on the specific application. Typically, wafers have a round shape with several flat sections and notches on their sides. A1.3. PCB holder In one example, a substrate holder supports and positions a substrate during processing. The substrate holder is designed to securely and accurately hold the substrate, ensuring proper alignment and positioning of the substrate during the process. It can also be designed to allow for easy loading and removal of the substrate, facilitating efficient processing and minimizing the risk of damage to the substrate. A1.4. Vacuum Chamber In some cases, a vacuum chamber provides a controlled environment for a process. -6 Base vacuum pressure of Torr or higher, and 10 -9 It has a process pressure control range of ~1 Torr, and the process pressure accuracy can be within 25%. 10 -5 ~10 -1 An example of process pressure control within the Torr range can be used. The vacuum chamber may also have substrate holder temperature control within a temperature range of -196°C to 500°C with an accuracy of 2°C or more, and chamber wall temperature control within a temperature range of 25°C to 350°C with an accuracy of 2°C or more. The vacuum chamber may be designed to maintain a stable and controlled environment during the process, ensuring consistent and accurate results.

[0076] The advantages of the apparatus and its components include precise control of the particle beam inclination angle, enabling control of sidewall roughness and reduction of structural defects in feature areas on the substrate. The apparatus also provides a controlled environment for etching and deposition processes, ensuring consistent and accurate results. The apparatus can further be equipped with optional features such as additional self-limiting reactions or rapid surface temperature cycling, which can enhance the apparatus's sidewall roughness control and structural defect reduction capabilities. A2. Control of sidewall roughness and reduction of structural defects In one example, sidewall roughness control may include line-edge roughness (LER) reduction. The walls of a feature portion where the wall has LER may have a wall aspect ratio of up to 1:10, a wall angle preferably perpendicular to the substrate but varying by ±60 degrees (or ±30 degrees), a wall surface roughness between 0.5 and 5.0 nm RMS, and a concave or convex wall shape. The method can achieve at least a 50% reduction in line-edge roughness (LER), or alternatively, the resulting line-edge roughness can be less than 2 nm, or the method can achieve an LER of sub-1 nm. A3. Obliquely incident particle beam etching In one embodiment, the oblique incidence particle beam etching process involves etching at least one sidewall of a feature area on the substrate. This process can be used to control sidewall roughness and reduce structural defects, resulting in improved device performance and yield. A3.1 Atomic Layer Etching (ALE) and Selectivity In some cases, oblique incidence particle beam etching processes may include atomic layer etching (ALE). ALE is a self-limiting etching process that allows for precise control of etching depth and selectivity. The process may involve alternating steps of self-limiting reactions and oblique incidence particle beam etching, which can be selective for specific materials such as silicon or silicon oxide. This selectivity can be advantageous in achieving precise etching of the desired material while minimizing damage to the underlying unetched material and other materials present within the device structure. A3.2. Variable and fixed angle etching In one example, oblique incidence particle beam etching processes may involve adjusting the inclination angle of the particle beam during the etching process. The inclination angle can be changed within a range of 0 to 85 degrees from the angle of the vertical line of the substrate, with an accuracy of within 10 degrees, preferably within 1 degree. This variable inclination angle etching enables optimized etching of not only the sidewalls of feature areas but also their horizontal upper surfaces, resulting in improved sidewall roughness control and reduction of structural defects.

[0077] In another example, oblique incidence particle beam etching processes may involve fixing the inclination angle of the particle beam during the etching process. A3.3. Rotation of feature regions and particle beams In some cases, the substrate and particle beam, which have patterned two- and three-dimensional features, can be rotated relative to each other during the oblique incidence particle beam etching process. This rotation allows for changes in speed, which helps ensure the desired etching of the sidewalls of the features and can further improve sidewall roughness control and structural defect reduction. A4. Conformal film deposition and atomic layer deposition (ALD) In one embodiment, the sidewall roughness control and structural defect reduction process may include conformal deposition, a deposition technique that enables the uniform deposition of thin films on a substrate with complex topography. Conformal deposition is considered particularly advantageous for depositing thin films on high aspect ratio features because it can provide a uniform coating of film over the entire surface of the feature area, thereby reducing sidewall roughness and, if oblique incident particle beam etching is followed, reducing structural defects.

[0078] In some cases, conformal deposition may be carried out using atomic layer deposition (ALD), a self-limiting deposition technique that allows for precise control of film thickness at the atomic level. ALD can involve a series of alternating self-limiting surface reactions, which can result in the formation of a highly uniform and conformal thin film on a substrate. The use of ALD for conformal deposition can offer several advantages, including improved film quality, precise control of film thickness, and excellent coverage of high aspect ratio features and three-dimensional structures and features. A4.1. Alternate between obliquely incident particle beam etching and conformal deposition. In some examples, the sidewall roughness control and structural defect reduction process may include alternating steps of oblique incidence particle beam etching and conformal deposition. Oblique incidence particle beam etching can be used to selectively remove material from the sidewalls of feature areas, while conformal deposition can be used to deposit a thin film on the etched sidewalls, thereby smoothing the sidewall roughness and reducing structural defects while maintaining the critical dimension (CD). The alternating steps of oblique incidence particle beam etching and conformal deposition may be repeated multiple times to achieve the desired sidewall roughness control and structural defect reduction. Either oblique incidence particle beam etching or conformal deposition can be the initiation step of this process. A4.2. Further Options In some cases, the conformal deposition process may include depositing the same material that is etched by the oblique incidence particle beam etching process. This can be advantageous in reducing sidewall roughness and structural defects while preserving the original critical dimensions of the feature area. In this case, it may be particularly advantageous to perform oblique incidence particle beam etching at a set of angles optimized for the specific material and structure such that the etching rates of the horizontal surface and the sidewalls are equal, or at least partially offset. This method preserves at least some CD for the feature area being processed, while simultaneously allowing for sidewall roughness control and structural defect reduction for the feature area.

[0079] In some cases, conformal deposition processes may involve depositing amorphous or glassy materials onto a structure. This can be advantageous in providing a smooth, stress-free, continuous film on the sidewalls, which can further help control sidewall roughness and reduce structural defects.

[0080] For example, the temperature used in an obliquely incident particle beam etching process may be lower than that of a conformal deposition process. This can be advantageous in minimizing the thermal history of the process and reducing the risk of thermal damage to the substrate and feature areas.

[0081] In some cases, conformal deposition processes may be carried out at pressures different from those used in oblique incidence particle beam etching processes. This can be advantageous in optimizing process conditions at each step to achieve desired sidewall roughness control and structural defect reduction. A5. Self-limiting response In some cases, methods for controlling sidewall roughness and reducing structural defects may include self-limiting reactions. A self-limiting reaction is a reaction that slows down or stops as a function of time, or equivalently as a function of the seed supply. Self-limiting reactions may include, but are not limited to, chemiadsorption, deposition, transformation (e.g., oxidation, nitriding), and extraction. In the case of extraction, the original material is a compound, and the modification preferentially removes one element from the surface, while other elements are removed in subsequent removal steps. In the case of chemiadsorption, a reaction on an exposed surface creates an electronic bond between the surface and the adsorbed material. A5.1. Use with ALE In some cases, self-limiting reactions can be used in combination with atomic layer etching (ALE). Self-limiting reactions can be applied during the ALE process to achieve a more controlled and precise etching process. Self-limiting reactions may be selective for specific materials or areas, enabling a more targeted etching process. This can result in improved sidewall roughness control and structural defect reduction, as well as better preservation of the original critical dimensions of feature areas. A5.2. Use with ALD In some cases, self-limiting reactions can be used in combination with atomic layer deposition (ALD). Self-limiting reactions can be applied during the ALD process to achieve a more controlled and precise deposition process. Self-limiting reactions may be selective for specific materials or areas, enabling a more targeted deposition process. This can result in improved sidewall roughness control and structural defect reduction, as well as better preservation of the original critical dimensions of feature areas. A5.3. Independent Steps In some cases, the self-limiting reaction may be an independent step in the sidewall roughness control and structural defect reduction process. The self-limiting reaction can be applied independently of the oblique incidence particle beam etching or conformal deposition steps. This can provide greater flexibility to the process, allowing for further optimization of sidewall roughness control and structural defect reduction. A6. Rapid surface temperature cycling in sidewall roughness control and structural defect reduction. In some examples, methods for controlling sidewall roughness and reducing structural defects may include one or more additional steps of rapid surface temperature cycling. Rapid surface temperature cycling can be applied independently of all other steps and at any point in the process. This section describes the rapid surface temperature cycling process, its advantages, and its potential integration with other process steps. A6.1. Rapid surface temperature cycling process In some cases, rapid surface temperature cycling involves rapidly changing the temperature of the substrate and its features during the process. This can be achieved in various ways, such as using a substrate holder with built-in temperature control, applying an external or cooling heat source such as a flash lamp, or a combination of both. Temperature cycling can be performed over a wide temperature range depending on the material and process requirements. For example, the temperature range may be -196°C to 500°C with an accuracy of 2°C.

[0082] A rapid surface temperature cycling process may include a series of temperature ramps, plateaus, and cooling steps. Temperature ramps can be performed at different rates depending on the desired process endpoint. Temperature ramps typically range from a few degrees Celsius / second to over 100 degrees Celsius / second. Plateaus may be maintained for a specific period to allow a particular reaction or process to occur. Cooling steps can also be performed at different rates depending on the desired process endpoint. Cooling step rates typically range from a few degrees Celsius / second to over 100 degrees Celsius / second. A6.2 Integration with other process steps The rapid surface temperature cycling process can be integrated with other process steps in various ways. For example, it can be combined with oblique incidence particle beam etching, conformal deposition, self-limiting reactions, or any combination thereof. The rapid surface temperature cycling process can be performed before, during, or after any of these process steps, depending on the desired process endpoint.

[0083] In some examples, a rapid surface temperature cycling process can be implemented during an obliquely incident particle beam etching step to enhance the etching process and improve sidewall roughness control and structural defect reduction. In other examples, a rapid surface temperature cycling process can be implemented during a conformal deposition step to enhance the deposition process and improve sidewall roughness control and structural defect reduction. In yet another example, a rapid surface temperature cycling process can be implemented during a self-limiting reaction step to enhance the reaction process and improve sidewall roughness control and structural defect reduction.

[0084] In some examples, rapid surface temperature cycling processes can be implemented by alternating them with other process steps such as oblique incidence particle beam etching, conformal deposition, or self-limiting reactions. This allows for further process control and optimization, leading to improved sidewall roughness control and structural defect reduction. B. Pattern Improvement B1. Method for reducing sidewall roughness of feature areas on a substrate Figure 4 shows a schematic representation of the desired size and shape of the patterned feature on the substrate 2100. The feature, also called a structure, may be anything, including microscale and nanoscale devices, waveguides, or transistors. The feature can be of various types, such as bumps, grooves, holes, or columns, and can be made from various materials, including semiconductors, metals, dielectrics, and polymers.

[0085] The feature portion has a field region 2110 and sidewalls 2200. The desirable or ideal shape of the feature portion is smooth and uniform with minimal roughness of the sidewalls. The field region 2110 is defined here as a region having a horizontal plane, i.e., a surface parallel or nearly parallel (deviation less than 20°) to the main surface of the substrate 2100, or a surface that coincides with the main surface of the substrate 2100. The field region is shown as feature portion 2110 in Figures 4 and 5, for example.

[0086] However, due to line edge roughness (LER), the actual shape is as shown in Figure 5. Instead of the sidewall surface 2200 in Figure 4, the sidewall has a surface 2210 with a feature that makes the shape slightly larger compared to the desired shape. Thus, Figure 5 is a diagram of the actual surface of the feature before completing the method for reducing sidewall roughness, also known as Atomic Level Improvement, as described later. The sidewall 2210 of the feature exhibits roughness, which can adversely affect the performance of the feature in its intended application. Sidewall roughness is defined here as the deviation of the shape from the sidewall tangent plane. Sidewall surface roughness is quantified as the root mean square (RMS) of the sidewall shape deviation from the sidewall tangent plane.

[0087] A method for reducing sidewall roughness involves forming a patterned and selectively protective masking layer such that at least a portion of the field region 2110 is masked, while the sidewall 2210 is not masked. This masking layer is designed to protect specific areas of the substrate during the etching process, while other areas, particularly the sidewalls of feature areas, remain exposed and are subjected to processing. The method also includes performing dry etching in a process chamber surrounding the substrate 2100. Dry etching involves creating a horizontal component in the etching direction by setting the pressure in the process chamber to exceed a defined pressure threshold for sidewall etching. This horizontal component then etches the sidewall 2210 that is not masked for the aforementioned roughness reduction. Figure 5 shows the direction of plasma ions with a horizontal component created by high-pressure dry etching. When the roughness of the sidewall 2210 is reduced using this method, the line-edge roughness approaches the ideal pattern shown in Figure 4.

[0088] The method can be implemented with currently available equipment and does not require significant changes to the fabrication line, making it cost-effective and sustainable. This is in contrast to more complex conventional roughness reduction solutions, such as relying on the tilt of the substrate or particle beam to target sidewalls with directional etching. Therefore, this process is versatile and applicable to a wide range of materials, including polymers, semiconductors, quatrines, and metals. Compared to several available methods, this method has the advantage of not requiring hardware modification to provide tilted etching for attacking sidewalls. In addition, this method is applicable to all process steps in semiconductor manufacturing, making it a versatile technique compared to other similar methods.

[0089] Figures 6 and 7 illustrate embodiments of the method in so-called atomic-level pitch splitting (APS). Any structure including fins can be fabricated by first forming a large structure as illustrated in Figure 6, and then using APS to split this structure into two or more fins or any other smaller structures. Figure 6 shows a substrate (surface 2300) which can be any material including, but not limited to, metals, semiconductors, dielectrics, and polymers. The large structure is fabricated using some means of lithography and has a field region 2310 and sidewalls 2320.

[0090] Using APS, as shown in Figure 7, the field region 2310 can be divided into two or more parts to form a new structure. An example of such a structure is a finFET. The new structure forms multiple surfaces, such as 2411 as the top surface and 2410 and 2420 as sidewalls. The sidewalls 2410 and 2420 may have roughness that causes the outline to deviate from the desired size. To reduce this roughness, the top surface 2411 is covered with a mask, and the sidewalls 2410 and 2420 are exposed to low-power plasma under high pressure in either a continuous or cyclic scheme to create a horizontal etching component and reduce the roughness. Figure 8 shows an example of the results after this method, where all sidewalls (including 2410 and 2420) have significantly reduced roughness and have reached the ideal size and outline, which consequently improves the performance of the device. Accordingly, Figure 8 shows the structure after APS and after completing the method for reducing sidewall roughness. B1.1. Protective Masking Layer Selective masking allows the etching process to specifically target the sidewalls of feature areas where roughness reduction is required. In some cases, protective masks are formed using selective deposition methods. These methods allow for precise deposition of masking material on the substrate, ensuring that only the desired areas are masked. The masking layer can be formed using any selective deposition method, such as chemical vapor deposition (CVD). Both methods allow for the deposition of a thin, uniform layer of material on the substrate, but they differ in their mechanisms and the types of materials that can be deposited.

[0091] The protective masking layer can be made from various materials depending on the specific requirements of the material of the feature area and the etching process. The composition of the protective masking layer may vary depending on the specific requirements of the material of the feature area and the etching process. The material used for the masking layer can be different from the material being etched, allowing for better control over the etching process. B1.2. Substrate with distinctive features In some configurations, the substrate with the feature is a material on which methods for reducing sidewall roughness are implemented. The substrate can be made from a variety of materials, including semiconductors, metals, dielectrics, and polymers. The feature formed on the substrate can have various shapes, such as bumps, grooves, holes, and columns. The feature also has various aspect ratios up to 1:10, and its sidewall roughness can range from 0.5 to 5.0 nm RMS before the sidewall roughness reduction process. B1.3. High-Pressure Dry Etching Process In some implementations, a high-pressure dry etching process is used to reduce sidewall roughness. This process is carried out in a process chamber surrounding the substrate. The pressure inside the chamber is set to exceed a defined pressure threshold for sidewall etching. This high pressure creates a horizontal component in the etching direction, which plays a role in etching the unmasked sidewalls of feature areas, thereby reducing their roughness. B1.3.1. Setting the pressure threshold for sidewall etching In some configurations, the pressure threshold for sidewall etching is a parameter in the high-pressure dry etching process. This threshold is set to a value that allows for the creation of a horizontal component in the etching direction. In some examples, pressures above 40 mTorr are particularly advantageous for this purpose. The pressure in the process chamber is carefully controlled and monitored to ensure that it remains above this pressure threshold during the etching process. B1.3.2. Effects of high pressure on ion pathways and etching directions In some cases, high pressure within the process chamber significantly affects ion paths and etching direction. High pressure reduces the mean free path of ions, resulting in a higher probability of collisions between ions and the substrate. This creates a horizontal component in the etching direction, which plays a role in etching the unmasked sidewalls of feature areas. B1.3.3. Setting and Monitoring Pressure Thresholds In some configurations, setting and monitoring the pressure threshold is part of the high-pressure dry etching process. The pressure within the process chamber is carefully controlled and monitored to ensure it remains above a defined pressure threshold for sidewall etching. This ensures that the horizontal component in the etching direction is maintained, which is necessary for reducing sidewall roughness. B2.1. Reduction of line edge roughness and preservation of critical feature dimensions. In some implementations, the sidewall etching process offers several benefits. First, the process reduces the line-edge roughness of the feature area, which can improve the performance of the feature area in its intended application. This roughness is defined as the deviation of the outline from the sidewall tangent plane. By reducing this roughness, the method improves the uniformity and smoothness of the feature area. In some examples, line-edge roughness can be reduced by at least 50%. In some examples, line-edge roughness can be reduced to a value below 1 nm RMS. In some examples, line-edge roughness can be reduced to a value in the range of 5 to 10 angstroms (Å) RMS. Second, the sidewall etching process preserves the dimensions of the feature area, ensuring that the feature area retains its desired shape and size.

[0092] In some cases, another benefit of the sidewall etching process is the preservation of the feature dimensions. Despite the etching of the sidewalls, the process does not significantly alter the overall size and shape of the feature. This ensures that the feature retains the desired dimensions for its functionality. B2.2. Low-energy dry etching process In some implementations, methods for reducing sidewall roughness involve a low-energy dry etching process. This process is designed to etch the unmasked sidewalls of feature areas without significantly affecting the bulk material. The plasma energy used in the etching process can be set lower than the binding energy of the bulk material, which helps preserve the dimensions of the feature areas.

[0093] Therefore, low-energy dry etching processes can be self-limiting in some cases. This means that the etching process stops when the roughness of the sidewall falls below a certain threshold. This self-limiting nature of the etching process helps prevent over-etching of the sidewall, which could damage the feature or alter its dimensions. B3. Post-etching process In some cases, a further post-etching process may be performed after a high-pressure dry etching process. These processes include rapid surface temperature cycling and self-limiting reaction processes. These processes are configured to further enhance the results of the etching process and ensure the preservation of feature dimensions. B3.1. Rapid Surface Temperature Cycling In some cases, rapid surface temperature cycling is performed after a high-pressure dry etching process. This process involves rapidly changing the temperature of the substrate surface, which can help further reduce the roughness of the sidewalls. Rapid surface temperature cycling can be achieved through various methods, such as surface exposure to plasma or the use of flash light or laser light sources. B3.2. Self-limiting response processes In some cases, methods for reducing sidewall roughness may involve self-limiting reactions. These processes involve self-limiting reactions that stop when certain conditions are met. These reactions may include chemisorption, deposition, extraction, oxidation, nitriding, or conversion. Self-limiting reaction processes can be carried out during or after a high-pressure dry etching process. These self-limiting reactions can further enhance the etching process by providing additional control over the etching process.

[0094] In some cases, etching or self-limiting reactions can be selectively applied to specific areas of the substrate. This selective application allows for targeted reduction of sidewall roughness in those areas while preserving the dimensions of feature areas in other areas. B4. Explanation of further examples of disclosure For example, methods for reducing sidewall roughness may include atomic layer etching, as well as the use of particle beam etching selective for silicon oxide and silicon. The methods may also include cyclic etching processes. B4.1. Use of atomic layer etching In some implementations, atomic layer etching (ALE) is used as a method for reducing sidewall roughness. ALE is defined as an etching technique that utilizes a series of half-reactions to result in layer-by-layer material reduction. The implementation of ALE consists of at least two sequential steps: surface modification (reaction A) and removal (reaction B). These reactions can be cycled, and at least one step is at least partially self-limiting. The modification step forms a thin reactive surface layer of a clearly defined thickness, which is then removed more easily than the unmodified material. The layer is characterized by a steep gradient of chemical composition. Removal methods include thermal desorption, particle bombardment, and chemical reactions. The ALE process may also include a quasi-atomic layer etching process, which may include quasi-self-limiting and non-self-limiting reactions. This can help achieve a high level of control over the etching process and a high level of roughness reduction.

[0095] ALE is defined as an etching technique that utilizes a series of half-reactions to result in layer-by-layer material reduction. An ALE implementation consists of at least two sequential steps: surface modification (reaction A) and removal (reaction B). These reactions can be cycled, and at least one step is at least partially self-limiting. The modification step forms a thin reactive surface layer of a clearly defined thickness, which is subsequently removed more easily than the unmodified material. The layer is characterized by a steep gradient of chemical composition. Removal methods include thermal desorption, particle bombardment, and chemical reactions. The ALE methods described above may include quasi-atomic layer etching processes that may include quasi-self-limiting and non-self-limiting reactions. B4.1.1. Selective particle beam etching for silicon oxide and silicon In some configurations, particle beam etching selective for silicon oxide and silicon is used in methods for reducing sidewall roughness. This type of etching process involves the use of a particle beam selective for silicon oxide and silicon, meaning that these materials are preferentially etched. This selectivity can help maintain the dimensions of feature areas while reducing sidewall roughness. In further examples, etching is selective for materials containing silicon nitride, hafnium oxide, and / or aluminum oxide. B4.2. Cyclic Etching Process In some examples, methods for reducing sidewall roughness include a cyclic etching process in which material is removed at the atomic level in each cycle. Each cycle thus removes a small amount of material from the sidewall. This cyclic process can help achieve a high level of control over the etching process and can result in a high level of roughness reduction. The method may also include rapidly changing the temperature of the substrate surface between each etching cycle. This can help further improve the results of the etching process by providing additional control over the etching process.

[0096] Furthermore, each etching cycle may have a step that helps to lower the binding energy of the surface atoms. The added gas phase material reacts with the sidewall 2200, lowering the energy of the material, thereby allowing a low-energy plasma (another step in the cycle) to remove it. An example of such a process may be: The surface of a semiconductor, metal, dielectric, or polymer is patterned by any type of lithography and then moved to an ALD chamber, where the top surface is covered with a mask, and then moved to another chamber, an ICP-RIE, where it is subjected to cyclic etching. Etching includes a step in which the surface is exposed to a reactive gas such as Cl gas. Excess Cl can be removed and a low-power plasma of 10-20 eV can be applied to sputter the roughness. The sputtering plasma can be a neutral gas such as Ar, or any other gas such as SF6 or C4F8. The chamber pressure may be 60 mTorr. As a result, roughness can be significantly improved, such as reducing the line-edge roughness from the range of 5–10 angstroms (Å) to less than 1–10 Å. B5. Potential Uses For example, a method for reducing sidewall roughness can be applied to atomic-level pitch splitting. This is a process in which a large structure on a substrate is divided into two or more smaller structures. The method can also be used with various material types, including semiconductors, metals, dielectrics, and polymers. B5.1. Applications in atomic-level pitch splitting In some implementation configurations, methods for reducing sidewall roughness can be used in atomic-level pitch splitting (APS). This process involves dividing a large structure on a substrate into two or more smaller structures. In some configurations, the use of methods for reducing sidewall roughness in atomic-level pitch splitting can significantly impact the size and shape of the smaller structures. The methods help reduce the sidewall roughness of the smaller structures, resulting in smoother and more uniform structures. This can improve the performance of the structures in their intended applications. B5.2. Applications in semiconductors, metals, dielectrics, and polymers In several configurations, the method for reducing sidewall roughness can be applied to feature parts made from a variety of materials, including semiconductors, metals, dielectrics, and polymers. The method helps reduce the sidewall roughness of feature parts made from these materials, improving their performance in their intended applications. The method can be adapted to the specific properties of each material type, ensuring that sidewall roughness is effectively reduced without damaging the material or altering its properties. This versatility makes the method suitable for use in a wide range of applications, from semiconductor manufacturing to the production of polymer-based devices. B5.3. Influence on different feature shapes In some cases, methods for reducing sidewall roughness can be used on feature parts of various shapes. These may include ridges, grooves, holes, columns, etc. The method can be adapted to the specific shape of each feature part, ensuring that the sidewall roughness is effectively reduced without altering the shape of the feature part. This flexibility makes the method suitable for a wide range of applications, from the production of complex semiconductor devices to the fabrication of intricate polymer-based structures. Because the method enables sidewall roughness reduction without compromising the shape of the feature part, it may be particularly beneficial in applications where the shape of the feature part is its performance characteristic. C. Cyclic surface preparation method Figure 9 shows an example of a surface preparation method based on cyclic processing. Figure 9a illustrates a substrate 3100 with an initial surface roughness 3110. The substrate 3100 can be made from various materials, such as semiconductor materials, metallic materials, dielectric materials, or 2D materials. The surface of the substrate 3100 can be patterned or unpatterned.

[0097] Figure 9b shows the final surface, where the substrate 3100 has the desired surface 3111 with reduced surface roughness while retaining the original thickness of the substrate 3100. This reduction in surface roughness is achieved through a cyclic processing method, which includes activating the surface, removing excess material, treating with low-energy particles, and repeating these steps until the desired smoothness is achieved. This surface preparation is achieved through a cyclic processing method as described above and may include any cyclic process, including atomic layer etching (ALE) or atomic layer deposition (ALD).

[0098] Figure 10 shows another example of a surface preparation method based on cyclic processing. Figure 10a illustrates an initial structure 3110 with rough surfaces 3111, 3112, and 3122. In addition, the substrate 3100 has another feature section 3210 of a different height than 3110. The feature section 3210 has different rough surfaces 3211, 3212, and 3222, as shown.

[0099] Figure 10b shows the final structure with feature section 3110 having the desired surfaces 3311, 3312, and 3322, and reduced sidewall roughness of feature section 3110 while retaining the original dimensions of feature section 3110. Furthermore, Figure 10b shows feature section 3210 with the desired surfaces 3411, 3412, and 3422, and reduced surface roughness of feature section 3210 while retaining the original critical dimensions of feature section 3210. This surface preparation is achieved through cyclic processing methods as described above and may include any cyclic process, including atomic layer etching (ALE) or atomic layer deposition (ALD).

[0100] Figure 11 shows another example of a surface preparation method based on cyclic processing. In Figure 11a, an initial structure 3110 is illustrated with rough surfaces 3111, 3112, and 3122.

[0101] Figure 11b shows the final structure with the desired surfaces 3222, 3212, and 3211, and reduced sidewall roughness of feature portion 3110 while retaining the original critical dimensions of feature portion 3110. This surface preparation is achieved through cyclic processing methods as described above and may include any cyclic process, including atomic layer etching (ALE) or atomic layer deposition (ALD).

[0102] Figure 12 is a flowchart illustrating a method for surface preparation based on cyclic processing according to an example of the present disclosure. The method includes activating the surface (step 3401), removing excess material from the chamber (step 3402), treating the surface with low-energy particles (step 3403), and repeating the above steps until the surface has the desired smoothness (step 3404). The low-energy particle treatment can be etching, deposition, or a combination of both. The method may also include ion beam shaping techniques and oblique incidence particle beam etching.

[0103] Figure 13 shows atomic force microscope (AFM) images of the initial and final surfaces after a cyclic process in one example. Figure 13a shows a micrograph with a scan area of ​​3500, which is approximately 1 μm². 2 In the graph below, roughness values ​​3501, 3502, and 3503 are measured at different locations in the scan area: the top, middle, and bottom, respectively. The roughness was measured to be approximately 0.11 nm.

[0104] Figure 13b shows the results from the AFM measurement of the final surface. The upper section 3504 shows a micrograph of the scan area, which is approximately 1 μm². 2 The graph below shows roughness values ​​of 3505, 5306, and 3507 measured at different locations in the scan area: the top, middle, and bottom, respectively. The roughness was measured at approximately 0.021 nm. This reduction in surface roughness was achieved through cyclic processing methods as described above and can include any cyclic process, including atomic layer etching (ALE) or atomic layer deposition (ALD). C1. Surface activation process The surface activation process is a step in surface preparation methods based on cyclic processing. In this process, the substrate surface is activated to facilitate subsequent low-energy particle processing, which can involve etching, deposition, or a combination of both. The activation process can be carried out using various techniques, including gas exposure, chemical solution exposure, temperature-based activation, and particle beam activation. Each of these techniques has its own advantages and can be adapted to meet the specific requirements of the substrate material and the desired surface smoothness. C1.1. Gas exposure activation In some cases, the surface activation process may involve exposing the surface to a gas or a mixture of gases. Gas exposure can modify the surface chemistry, making it more susceptible to the effects of low-energy particle treatment. The selection of an appropriate gas is necessary to achieve the desired surface activation and ensure compatibility with the substrate material. C1.2. Chemical solution activation In some cases, the surface activation process may involve exposing the surface to a chemical solution. The chemical solution interacts with the surface material, altering its properties and making it more responsive to low-energy particle treatment. The selection of an appropriate chemical solution is crucial for achieving the desired surface activation and ensuring compatibility with the substrate material. C1.3. Temperature-based activation In some cases, the surface activation process may involve heating the surface to a specific temperature or a specific temperature range. Temperature-based activation can cause thermal expansion or contraction of the surface material, leading to changes in surface properties that can facilitate the processing of low-energy particles. Determining the optimal temperature range is essential to achieving the desired surface activation and ensuring compatibility with the substrate material. C1.3.1. Determine the optimal temperature range. The optimal temperature range for a temperature-based activation process depends on the substrate material and the desired surface properties. In some cases, the temperature range may be selected to induce thermal expansion or contraction of the surface material, leading to changes in surface roughness or other properties that can facilitate low-energy particle processing. In other cases, the temperature range may be selected to induce a phase transition or other structural change in the surface material, which can alter its properties and make it more responsive to low-energy particle processing. The determination of the optimal temperature range can be based on factors such as the thermal properties of the substrate material, the desired surface properties, and the compatibility of the temperature range with the low-energy particle processing process. C1.4. Particle Beam Activation In some examples, a surface activation process may involve irradiating a surface with a particle beam. The selection of a particle beam for a particle beam activation process depends on the substrate material and the desired surface properties. In some examples, the particle beam may include ions, electrons, or neutral particles that can physically sputter the surface material or chemically react with it to modify its properties. In other examples, the particle beam may include photons or other electromagnetic radiation that can induce electronic or vibrational excitations in the surface material, leading to changes in surface properties that can facilitate low-energy particle processing. The selection of an appropriate particle beam may be based on factors such as the reactivity of the particles with the substrate material, the desired surface properties, and the compatibility of the particle beam with the low-energy particle processing process. C2. Excess Material Removal Process For example, the excess material removal process is a step in a surface conditioning method based on cyclic processing. This process aims to remove any excess material from the surface and surrounding environment after the surface activation process. Removal of excess material ensures that subsequent low-energy particle treatment can be effectively applied to the surface without interference from unwanted material. The excess material removal process can include various techniques, such as purging gas, pumping gas, or a combination of pumping and purging. C2.1. Gas purging In some cases, the excess material removal process may include gas purging. Gas purging involves introducing an inert gas, such as nitrogen or argon, into the processing chamber to replace and remove any excess material, including reactive gases or by-products from surface activation processes. Gas purging can be introduced at controlled flow rates and pressures to ensure efficient removal of excess material without damaging the surface or altering its surface properties. In excess material removal processes, the use of gas purging offers the advantage of being a simple and cost-effective technique for removing unwanted material from the processing environment. C2.2. Gas pump exhaust In other examples, the excess material removal process may include pumping gases. Pumping gases involves using a vacuum pump to evacuate the processing chamber, thereby removing any excess material, including reactive gases or by-products from the surface activation process. The vacuum pump can be operated at controlled pressure and flow rate to ensure efficient removal of excess material without damaging the surface or altering its surface properties. In the excess material removal process, the use of pumping gases offers the advantage of more thorough removal of unwanted material from the processing environment compared to purging gases alone. C2.3. Combination of pump exhaust and purging In some cases, the excess material removal process may include a combination of pumping and purging. This technique involves using both a vacuum pump to evacuate the processing chamber and an inert gas to replace and remove any excess material, including reactive gases or by-products from the surface activation process. The combination of pumping and purging can be carried out sequentially or simultaneously, depending on the specific requirements of the surface conditioning process. In the excess material removal process, the use of a combination of pumping and purging offers the advantage of more comprehensive removal of unwanted material from the processing environment, ensuring that subsequent low-energy particle treatment can be effectively applied to the surface without interference from excess material.

[0105] The excess material removal process can be adapted to meet the specific requirements of the surface conditioning process, taking into account factors such as the type of surface being treated, the materials involved in the surface activation process, and the desired surface smoothness. By effectively removing excess material from the surface and surrounding environment, the excess material removal process plays a certain role in achieving the desired surface smoothness and ensuring the overall success of the surface conditioning method based on cyclic processing. C3. Low-energy particle processing For example, a surface preparation method based on cyclic processing includes a low-energy particle treatment step. This low-energy particle treatment can be applied to various types of surfaces, such as patterned and unpatterned surfaces, and can be used on a variety of materials, including semiconductor surfaces, metallic surfaces, dielectric surfaces, and 2D material surfaces. Low-energy particle treatment can be carried out using a low-energy particle beam with particle energy between 10 eV and 100 eV, or low-energy plasma treatment with plasma power between 1 W and 50 W. C3.1. Low-energy particle etching In some cases, low-energy particle processing may include low-energy particle etching processes. This etching process is used to selectively remove material from a surface, thereby reducing surface roughness and improving overall surface quality. Low-energy particle etching processes can be carried out using various techniques such as ion beam etching, reactive ion etching, or plasma etching. C3.1.1. Atomic layer etching with molecular activation (ALE) For example, low-energy particle etching processes can include atomic layer etching (ALE) with molecular activation. ALE with molecular activation is a highly controlled etching process that allows for the removal of material at the atomic level, resulting in a very smooth surface. This process involves surface activation using an appropriate activation method such as gas exposure, chemical solution exposure, heating, or particle beam exposure, followed by the application of a low-energy particle beam or plasma treatment to selectively remove material from the surface. The use of ALE with molecular activation can offer several advantages, including improved control over the etching process, reduced surface roughness, and minimal damage to the underlying material. C3.2. Low-energy particle deposition In some cases, low-energy particle processing may include low-energy particle deposition processes. These deposition processes are used to selectively deposit material onto a surface, thereby filling any surface irregularities and improving overall surface quality. Low-energy particle deposition processes can be carried out using various techniques, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). C3.2.1. Atomic layer deposition (ALD) For example, low-energy particle deposition processes can include atomic layer deposition (ALD). ALD is a highly controlled deposition process that allows for the deposition of material at the atomic level, resulting in a very smooth surface. This process involves sequential exposure of the surface to various precursor gases that react with the surface to form a thin layer of the desired material. The use of ALD can offer several advantages, including improved control over the deposition process, reduced surface roughness, and the ability to deposit material with high conformality and uniformity. C3.3. Combination of Etching and Deposition In some cases, low-energy particle processing may involve a combination of etching and deposition processes. This may involve alternating etching and deposition steps, or performing both etching and deposition simultaneously. The combination of etching and deposition can be used to selectively remove material from specific areas of a surface while depositing material in other areas, thereby reducing surface roughness and improving overall surface quality. C3.3.1. Alternate between etching and deposition. In one example, low-energy particle processing may involve alternating etching and deposition steps. This may involve performing an etching step to selectively remove material from the surface, followed by a deposition step to selectively deposit material onto the surface. By alternating the etching and deposition steps, surface roughness can be reduced while maintaining the overall thickness of the material. This technique can offer several advantages, including improved control over the surface preparation process, reduced surface roughness, and the ability to selectively modify the surface without affecting the underlying material. C4. Cyclic processing and surface smoothness In one example, the cyclic processing and surface smoothing section focuses on determining the desired surface smoothness, implementing a self-stopping cyclic process, and monitoring the reduction of surface roughness during the surface conditioning process. The cyclic processing method may include a variety of optional features to achieve the desired surface smoothness and effectively reduce surface roughness. C4.1. Determining the desired surface smoothness. In some cases, the desired surface smoothness is determined based on the specific application or requirements of the processed substrate. Surface smoothness can be quantified using various surface roughness parameters, such as root mean square (RMS) roughness, mean roughness, or peak-to-valley roughness. The desired surface smoothness can be achieved by repeating the cyclic processing steps until the surface roughness parameter reaches a predetermined value or the specific requirements of the processed substrate are met. C4.2. Self-Stopping Cyclic Processes For example, a cyclic processing method may include a self-stopping feature, in which case the process automatically stops when it has no further effect on the surface or when the surface roughness parameter reaches a plateau. This self-stopping feature can be advantageous in preventing over-processing of the surface and preserving the original dimensions of the substrate or patterned feature. A self-stopping cyclic process can be achieved by optimizing process parameters such as activation conditions, excess material removal methods, and low-energy particle treatment conditions, ensuring that once the desired surface smoothness is achieved, the process has minimal or no effect on the surface. C4.3. Monitoring of Surface Roughness Reduction In some cases, surface roughness reduction during cyclic processing can be monitored using various in-situ or ex-situ measurement techniques. In-situ measurement techniques may include optical monitoring, ellipsometry, or reflectometry, which can provide real-time feedback on surface roughness parameters during cyclic processing. Ex-situ measurement techniques may include atomic force microscopy (AFM), scanning electron microscopy (SEM), or transmission electron microscopy (TEM), which can provide high-resolution images and quantitative measurements of surface roughness parameters after cyclic processing.

[0106] Monitoring surface roughness reduction can be advantageous in determining the progress of the surface preparation process and ensuring that the desired surface smoothness is achieved. In addition, monitoring can provide valuable information for optimizing process parameters and improving the efficiency of cyclic processing methods. C5. Integration with ion beam shaping technology For example, surface preparation methods based on cyclic processing can be integrated with ion beam shaping technology to further enhance the surface smoothing process. Ion beam shaping technology can be used to modify surface topography by controlling ion beam parameters such as ion energy, ion species, ion incidence angle, and ion flux. This integration can provide additional control over the surface preparation process, enabling more precise and efficient surface smoothing. C5.1. Obliquely incident particle beam etching In some cases, the integration of ion beam shaping techniques with surface preparation methods can include oblique incidence particle beam etching. Oblique incidence particle beam etching can be used to selectively remove material from specific areas of a surface, such as peaks in surface roughness features, while preserving valleys. This can result in more uniform surface topography and reduced surface roughness.

[0107] For example, oblique incidence particle beam etching can be performed by directing an ion beam at a certain angle to the surface perpendicular line. The angle can be adjusted to optimize the etching process for specific surface features and material properties. By controlling ion beam parameters such as ion energy, ion species, ion incidence angle, and ion flux, the etching process can be adapted to achieve a desired surface smoothing effect. C5.2. Optimization of Ion Beam Parameters In some cases, ion beam parameters can be optimized to achieve the desired surface conditioning effect. Ion beam parameters can include ion energy, ion species, ion incidence angle, and ion flux. By adjusting these parameters, ion beam shaping techniques can be adapted to specific surface features and material properties, resulting in more efficient and precise surface smoothing.

[0108] For example, ion energy can be adjusted to control the penetration depth of ions into the surface material. Higher ion energy results in deeper penetration and more corrosive etching, while lower ion energy results in shallower penetration and milder etching. The optimal ion energy may depend on the specific surface features and material properties, as well as the desired surface smoothing effect.

[0109] In another example, ionic species can be selected based on their chemical reactivity with the surface material. Some ionic species may be effective in etching certain materials, while others may be less effective or even cause undesirable side effects such as surface damage or contamination. The optimal ionic species may depend on the specific surface features and material properties, as well as the desired surface smoothing effect.

[0110] In yet another example, the ion incidence angle can be adjusted to control the directionality of the etching process. By directing the ion beam at a certain angle to the surface perpendicularity, the etching process can be made more selective, allowing for preferential removal of material from specific areas of the surface, such as peaks in surface roughness features. The optimal ion incidence angle may depend on the specific surface features and material properties, as well as the desired surface smoothing effect.

[0111] In yet another example, ion flux can be adjusted to control etching rate and uniformity. Higher ion flux results in faster etching and more corrosive surface smoothing, while lower ion flux results in slower etching and milder surface smoothing. The optimal ion flux may depend on the specific surface features and material properties, as well as the desired surface smoothing effect.

[0112] By optimizing ion beam parameters, integrating ion beam shaping technology with cyclic processing-based surface preparation methods can achieve more precise and efficient surface smoothing, resulting in improved surface quality and reduced surface roughness. This integration can be particularly advantageous for applications requiring high-quality surfaces, such as semiconductor devices, optical components, and other advanced technologies. C6. Surface preparation for various surface types Surface preparation methods based on cyclic processing can be applied to a variety of surface types, including not only surfaces made from different materials such as semiconductor materials, metallic materials, dielectric materials, and 2D materials, but also patterned and unpatterned surfaces. The methods are adapted to address the specific requirements of each surface type and material, providing a versatile and efficient approach to surface preparation. C6.1. Patterned Surfaces In some cases, surface conditioning methods can be applied to patterned surfaces that may contain features such as lines, dots, columns, vias, grids, and other patterns. The methods can be adapted to address specific challenges associated with conditioning patterned surfaces, such as reducing surface roughness while preserving the original dimensions of the feature areas. C6.1.1. Side wall surface For example, a surface conditioning method can be applied to the sidewall surface of a patterned feature. The method can be adapted to address specific challenges associated with conditioning the sidewall surface, such as maintaining the original dimensions of the feature while reducing surface roughness. Cyclic processing methods, including activation, excess material removal, and low-energy particle treatment, can be optimized to achieve the desired surface smoothness of the sidewall surface without affecting the overall dimensions of the patterned feature. C6.1.2. Inclined surfaces In some cases, surface conditioning methods can be applied to the inclined surfaces of patterned features. The methods can be adapted to address specific challenges associated with conditioning inclined surfaces, such as maintaining the original dimensions of the features while reducing surface roughness. Cyclic processing methods, including activation, excess material removal, and low-energy particle treatment, can be optimized to achieve desired surface smoothness on inclined surfaces without affecting the overall dimensions of the patterned features. C6.2. Unpatterned surfaces For example, a surface conditioning method can be applied to an unpatterned surface, such as the surface of a substrate 3100. The method can be adapted to address specific challenges associated with conditioning an unpatterned surface, such as reducing surface roughness without affecting the overall thickness of the substrate. Cyclic processing methods, including activation, excess material removal, and low-energy particle treatment, can be optimized to achieve desired surface smoothness on an unpatterned surface while preserving the original thickness of the substrate. C6.3. Material-Specific Surface Preparation Surface preparation methods based on cyclic processing can be adapted to address the specific requirements of various materials, including semiconductor materials, metallic materials, dielectric materials, and 2D materials. In some cases, activation processes, excess material removal, and low-energy particle treatments can be adapted to specific material properties and requirements to ensure optimal surface preparation results.

[0113] For example, the selection of appropriate gases, chemical solutions, temperature ranges, and particle beams for activation processes can be based on specific material properties and requirements. Similarly, the selection of appropriate low-energy particle treatments, such as etching and deposition processes, can be adapted to specific material properties and requirements.

[0114] By adapting surface conditioning methods to specific material properties and requirements, the methods can provide efficient and effective surface conditioning results for various surface types and materials, ensuring optimal performance and reliability of the conditioned surface. D. Method for etching the side walls of feature areas Figures 14A and 14B show cross-sectional views of a substrate at various intermediate steps in oblique incidence particle beam etching without a masking layer. Figure 14A shows a substrate 4100 having a feature area 4110 with a field region 4111 and sidewalls 4112. The feature area 4110 is also referred to in this disclosure as a structural area 4110. Figure 14A shows the initial feature area 4110 at the very beginning of processing, and Figure 14B shows the same feature area at the end of processing, where the original feature area 4110 has been transformed into a feature area 4120 with reduced lateral dimensions and height. Thus, Figure 14B shows the substrate 4100 after oblique incidence particle beam etching, where both the width and height of the feature area 4110 have been reduced. The goal of the processing performed on the feature area 4110 is to change its lateral dimensions, and no change in height is required.

[0115] Figures 15A to 15C show cross-sectional views of the substrate during various intermediate steps of oblique-incident particle beam etching using a hard mask layer 4300, and the subsequent removal of the masking layer and the residual material, which is the unwanted structure 4131. Figures 15A to 15C illustrate one known in-situ solution for avoiding unwanted height reduction using a mask layer. Figure 15A shows the substrate 4100 with the feature portion 4110 and the hard mask layer 4300 at the start of the process. Figure 15B shows that after oblique-incident particle beam etching, the original feature portion 4110 is transformed into feature portion 4130, and the original mask 4300 is transformed into the masking layer 4310.

[0116] Typically, the masking layer is etched less than, or at least differently from, the material of the feature portion 4110, and for this reason, when a standard masking layer is used, artifact structures 4131 of the residual material are formed. These artifact structures 4131 are shown in Figure 15B immediately after the remaining masking layer 4310 and are caused by the masking effect of the protruding masking layer 4310. Typically, the masking layer is selectively removed after processing. However, artifact structures 4131 may remain even after the masking layer has been removed and may need to be removed separately. For example, artifact structures 4131 can be removed using an additional etching process, which then converts the critical structure 4130 into a structure 4140 with reduced height, which is then unnecessary, as shown in Figure 15C. Alternatively, artifact structures 4131 may remain even after the removal of the masking layer 4310, in which case they may distort or even fail the final device manufactured with the assistance of processing. Therefore, Figure 15C shows the substrate 4100 after the removal of the hard mask layer 4300 and the unwanted structure 4131, leaving the feature portion 4130 with a reduced height compared to the original height of the feature portion 4110.

[0117] Figures 16A to 16C are schematic diagrams of the method according to the present disclosure for etching the sidewall 4112 of a feature portion 4110 on a substrate 4100. Cross-sectional views of the substrate 4100 at various intermediate steps of oblique incident particle beam etching are shown with a composite masking layer including a first masking layer 4400 and a second masking layer 4300 on the first masking layer 4400. The method includes providing a composite masking layer on the feature portion 4110 so that at least a portion of the field region 4111 is masked by the composite masking layer, while the sidewall 4112 is not masked. Figure 16A shows the substrate 4100 with the feature portion 4110, the first masking layer 4400, and the second masking layer 4300.

[0118] The method involves etching the sidewall 4112, thereby preventing the second masking layer 4300 from etching the first masking layer 4400. Figure 16B shows the substrate 4100 after oblique incident particle beam etching 4200, where the second masking layer (shown as 4310 after etching) prevents etching of the first masking layer, thereby maintaining the height (h1) of the feature portion of the substrate 4100 and the first masking layer (shown as 4130 and 4410 after etching, respectively).

[0119] The method involves removing the first masking layer 4410, thereby removing any remaining portion of the second masking layer 4310. Figure 16C shows the substrate 4100 after removal of the composite masking layer, leaving their original intended height (h2) feature portions (shown as 4130 after removal of the composite masking layer), which corresponds to the height of feature portion 4110 in Figure 16A. Thus, the composite masking layer prevents height reduction of feature portions 4110 during sidewall etching, such as during ion beam etching at an inclined angle.

[0120] Any residual material 4411 after sidewall etching is separated from the feature portion 4130 by the first masking layer 4410. The residual material 4411 is instead adhered to the first masking layer 4410 and / or the second masking layer 4310, see Figure 16B. As further seen in Figure 16B, the first masking layer 4410 separates the feature portion 4130 from the residual material 4411 so that the feature portion 4130 has essentially uninterrupted vertical sidewalls relative to the substrate 4100. The removal of the first masking layer 4410 also removes any remaining portion of the second masking layer 4310, as well as the residual material 4411. Thus, the feature portion 4130 is left on the substrate 4100 at their original intended height (h2), but its lateral dimensions have been reduced by sidewall etching, see Figure 16C.

[0121] In some cases, the second masking layer 4300 prevents etching of the first masking layer 4400, although the first masking layer 4400 may still be etched to a relatively small extent relative to its original thickness. In such cases, the height (h1) of the feature portions 4110, 4130 and the first masking layers 4400, 4410 relative to the substrate 4100 is essentially maintained, and in some cases, is affected by only a few percent after sidewall etching. In such cases, the first masking layer 4410 separates any residual material 4411 from the feature portion 4130, and also allows for the subsequent removal of the composite masking layer and residual material 4411, so that the original height (h2) of the feature portions 4110, 4130 is maintained after sidewall etching. Therefore, the second masking layer 4300, which prevents etching of the first masking layer 4400, should be interpreted as providing the favorable benefit described, such as either essentially preventing etching of the first masking layer 4400, or reducing or substantially reducing etching of the first masking layer 4400, while the feature portions 4110, 4130 maintain their original height (h2) after sidewall etching. In some examples, etching of the first masking layer 4400 is reduced by at least half by the second masking layer 4300.

[0122] In one example, the second masking layer 4300 is made of chromium, or SiO2, or Al2O3; the first masking layer 4400 is made of amorphous Si; and the feature portion 4110 is made of crystalline Si. The masking layers 4300, 4400, the substrate 4100, and the feature portion 4110 may be made of semiconductors, dielectrics, metals, and two-dimensional (2D) materials such as graphene or transition metal dichalcogenide monolayers.

[0123] Figures 17A–17C are schematic diagrams of further examples of the method according to this disclosure for etching the sidewalls 4112 of a feature portion 4110 on a substrate 4100. The composite masking layer may include a third masking layer 4500. Cross-sectional views of the substrate 4100 at various intermediate steps of oblique incident particle beam etching 4200 are shown with a composite masking layer including a third masking layer 4500, a first masking layer 4400, and a second masking layer 4300. The third masking layer 4500 is positioned between the feature portion 4110 and the first masking layer 4400, see Figure 17A. The material of the first masking layer 4400 is typically the same as the material of the feature portion 4110, but it is advantageous to have a third masking layer 4500 if it is difficult to find a suitable material for the first masking layer 4400.

[0124] The material of the third masking layer 4500 is different from the material of the feature portion 4110 in this example. The thickness of the third masking layer may be thinner than that of the first masking layer, and in some examples, it is less than 10 nm. Figure 17B shows the substrate 4100 after oblique incident particle beam etching, where the third masking layer 4500 separates the feature portion 4130 from the residual material 4411 after sidewall etching. Accordingly, the feature portion 4130 can have essentially uninterrupted vertical sidewalls with respect to the substrate 4100. The etching rate of the sidewall 4501 of the third masking layer 4500 corresponds to at least the etching rate of the sidewall 4112 of the feature portion 4110. Selective removal of the third masking layer, shown at 4510 in Figure 17B, results in the removal of the entire composite masking layer after sidewall etching, leaving the feature portion 4130 with its originally intended height, see Figure 17C.

[0125] Because the third masking layer 4500 is very thin, its etching properties differ significantly when processing the exposed material on the sides. This makes the layer substantially as soft as, or even softer than, the material of the sidewalls of the critical structure 4130 due to the small thickness of the material, and this material is selected in such a way that the entire masking layer can be easily removed after processing without attacking the critical structure remaining in its current state.

[0126] In one example, the second masking layer 4300 is made from chromium, SiO2, or Al2O3; the first masking layer 4400 is made from amorphous Si, crystalline Si, or polycrystalline Si; the third masking layer 4500 is made from SiO2; and the feature portion 4110 is made from the same material as the first masking layer 4400.

[0127] In another example, the second masking layer 4300 is made from chromium, or SiO2, or Al2O3; the first masking layer 4400 is made from amorphous Si, or crystalline Si, or polycrystalline Si; the third masking layer 4500 is made from graphene; and the feature portion 4110 is made from the same material as the first masking layer 4400.

[0128] The masking layers 4300, 4400, 4500, the substrate 4100, and the feature portion 4110 may be made of semiconductors, dielectrics, metals, and two-dimensional (2D) materials such as graphene or transition metal dichalcogenide monolayers. It may be particularly advantageous to make the third masking layer 4500 from a 2D material.

[0129] Further examples of methods for etching the side walls of feature areas are described below.

[0130] A method for etching the sidewalls of a feature area on a substrate involves a series of steps designed to reduce the lateral dimension of the feature area while maintaining its height. This is achieved through the use of a composite masking layer applied to the feature area on the substrate. The composite masking layer protects the feature area during the etching process and prevents unwanted height reduction. The operation involves applying a composite masking layer to the feature area, etching the sidewalls of the feature area, and then removing the first masking layer. D1. Etching of the composite masking layer, sidewall etching, and removal of the composite masking layer. In one example of this disclosure, the etching method involves the use of two masking layers as a composite masking layer, as described above in relation to Figures 16A to 16C. The composite masking layer is provided on the feature area on the substrate. This composite masking layer includes a first masking layer and a second masking layer. The composite masking layer is designed to mask at least a portion of the field area of ​​the feature area, leaving the sidewalls unmasked.

[0131] In one configuration, a first masking layer is provided on the substrate, over the feature area. This layer is configured to have the same etching properties as the feature area on the substrate. This means that during the sidewall etching process, the first masking layer and the feature area on the substrate can be removed at the same rate. In one example, the material of the first masking layer is the same as the material of the feature area. The first masking layer can also be selectively removed after the sidewall etching process.

[0132] In some examples, the first masking layer separates the feature area on the substrate from any residual material that might remain after the sidewall etching process. This residual material is instead adhered to the first and / or second masking layer. This separation allows the feature area to have essentially uninterrupted, vertical sidewalls relative to the substrate after the sidewall etching process.

[0133] A second masking layer is provided on top of the first masking layer. This second masking layer is designed to prevent etching of the first masking layer during the sidewall etching process. The etching rate of the second masking layer may be lower than that of the first masking layer, which helps to protect the first masking layer during the etching process. The second masking layer can also be selectively removed after the sidewall etching process.

[0134] In some configurations, the etching method involves the use of three masking layers, as described above in relation to Figures 17A to 17C. The third masking layer may be provided between the feature area and the first masking layer. Therefore, the third masking layer can be applied directly to the feature area on the substrate. The first masking layer is applied on top of the third masking layer, and the second masking layer is applied on top of the first masking layer.

[0135] This third masking layer is typically thinner than the first masking layer and made from a different material than the feature area. The etching rate of the third masking layer corresponds at least to the etching rate of the sidewalls of the feature area. The third masking layer separates the feature area from any residual material that may remain after the sidewall etching process. This allows the feature area to have essentially uninterrupted, perpendicular sidewalls to the substrate after the sidewall etching process. The third masking layer can also be selectively removed after the sidewall etching process, resulting in the removal of any residual material as well as the entire composite masking layer.

[0136] In some configurations, the method for etching the sidewalls of a feature area on a substrate involves a series of steps designed to reduce the lateral dimension of the feature area while maintaining its height. This is achieved through the use of a composite masking layer applied to the feature area on the substrate. The composite masking layer is designed to protect the feature area during the etching process and prevent unwanted height reduction. The method involves applying a composite masking layer to the feature area, etching the sidewalls of the feature area, and then removing the first masking layer.

[0137] In one configuration, the sidewall etching process involves directing an etching agent towards the sidewalls of the feature area. A composite masking layer protects the feature area during this process and prevents unwanted height reduction. After the sidewall etching process, the first masking layer is removed. This also removes any remaining portion of the second masking layer and any residual material that may remain after the sidewall etching process. Thus, the feature area is left on the substrate at its original intended height. D2. Potential uses Methods for etching the sidewalls of feature areas on a substrate have potential applications in various fields, including semiconductor manufacturing and microfabrication. D2.1. Applications in semiconductor manufacturing In some cases, the method can be used in semiconductor manufacturing. The method allows etching the sidewalls of a feature on a substrate without affecting the feature's height. This is particularly useful in semiconductor manufacturing, where it is often necessary to reduce the lateral dimension of a feature without reducing its height. In one use case, the method can be used in the manufacture of semiconductor devices such as transistors. The method allows etching the sidewalls of a transistor gate without affecting its gate height. This can help improve transistor performance by shortening the gate length without reducing the gate height. D2.2. Applications in micro-machining In some cases, the method can be used in microfabrication processes. The method allows etching of the sidewalls of a feature on a substrate without affecting the height of the feature. This can be particularly useful in microfabrication processes where feature parts often need to be manufactured to precise dimensions. In one use case, the method can be used in the fabrication of micro-electromechanical systems (MEMS). The method allows etching of the sidewalls of a feature on a substrate without affecting the height of the feature. This can be particularly useful in the fabrication of MEMS devices where feature parts often need to be manufactured to precise dimensions. For example, the method can be used in the fabrication of a MEMS accelerometer where the sidewalls of the accelerometer's sensing element need to be etched without affecting its height.

[0138] In another use case, the method can be used in the fabrication of microfluidic devices. The method allows for etching the sidewalls of channels within a microfluidic device without affecting the channel height. This can be particularly useful in the fabrication of microfluidic devices where channels often need to be fabricated to precise dimensions. For example, the method can be used in the fabrication of microfluidic devices for lab-on-a-chip applications where the sidewalls of microfluidic channels need to be etched without affecting their height.

[0139] In yet another use case, the method can be used in the fabrication of optical devices. The method allows for etching of the sidewalls of an optical waveguide without affecting the waveguide's height. This can be particularly useful in the fabrication of optical devices where waveguides often need to be manufactured to precise dimensions. For example, the method can be used in the fabrication of a one-piece optical device where the sidewalls of the optical waveguide need to be etched without affecting their height.

[0140] In summary, a method for etching the sidewalls of feature areas on a substrate has potential applications in various fields, including semiconductor manufacturing and microfabrication. The method allows etching the sidewalls of feature areas on a substrate without affecting the height of the feature area. This can be particularly useful in applications where feature areas need to be manufactured to precise dimensions. The method involves applying a composite masking layer over the feature area, etching the sidewalls of the feature area, and then removing the first masking layer. The composite masking layer includes a first masking layer, a second masking layer, and optionally a third masking layer. The first masking layer is applied directly to the feature area, and the second masking layer is applied on top of the first masking layer. The third masking layer, if used, is provided between the feature area and the first masking layer. After the sidewall etching process, the first masking layer is removed. This also removes any remaining portion of the second masking layer and any residual material that may remain after the sidewall etching process. In this way, the feature elements are left on the substrate at their original intended height.

[0141] The terms used herein are for the sole purpose of describing specific aspects and are not intended to limit the disclosure. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. Where used herein, the term “and / or” includes all combinations of one or more of the enumerated items relating to it. Where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” indicate the presence of the described features, integers, actions, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, actions, steps, operations, elements, components, and / or groups thereof.

[0142] In this specification, terms such as "first," "second," etc., may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, the first element may be called the second element, and similarly, the second element may be called the first element without departing from the scope of this disclosure.

[0143] In this specification, relative terms such as “down,” “up,” “up,” “down,” “horizontal,” or “vertical” may be used to describe the relationship between one element and another, as shown in the diagrams. It will be understood that these terms, and the terms mentioned above, are intended to encompass different orientations of the device, in addition to the orientation depicted in the diagrams. When an element is said to be “connected” or “joined” to another element, it will be understood that the element may be directly connected or joined to the other element, or there may be an intervening element. In contrast, when an element is said to be “directly connected” or “directly joined” to another element, there is no intervening element.

[0144] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art in which this disclosure pertains. Furthermore, terms used herein should be interpreted as having meanings consistent with their meanings in the context of this specification and related art, and should not be interpreted as idealized or overly formal unless expressly defined herein.

[0145] This disclosure is not limited to the embodiments described above and illustrated in the drawings, and rather, those skilled in the art will understand that many changes and modifications can be made within the scope of this disclosure and the attached claims. The drawings and specification disclose embodiments for illustrative purposes only and not limiting purposes, and the scope of the disclosure is set forth in the following claims.

Claims

1. A method for controlling the sidewall roughness of a feature portion on a substrate and reducing structural defects, To perform oblique incidence particle beam etching of at least one side wall of the aforementioned feature portion, the inclination angle of the particle beam is adjusted. Methods that include...

2. The method according to claim 1, further comprising a combination of conformal deposition and variable-angle etching to achieve the sidewall roughness control and the reduction of structural defects.

3. The method according to claim 2, further comprising alternating the deposition step and the etching step in order to achieve the control of the sidewall roughness and the reduction of structural defects.

4. The method according to any one of claims 1 to 3, further comprising a self-limiting reaction such as chemiadsorption, deposition, extraction, oxidation, nitriding, or conversion.

5. The method according to any one of claims 1 to 4, wherein the particle beam comprises neutral particles, radicals, photons, ions, electrons, or a combination thereof.

6. The method according to any one of claims 1 to 5, wherein the inclination angle of the particle beam is in the range of 0 to 85 degrees from the angle of the vertical line of the substrate.

7. The method according to any one of claims 1 to 6, wherein the sidewall roughness control results in at least a 50% reduction in line edge roughness (LER).

8. The method according to any one of claims 1 to 7, wherein the sidewall roughness control and structural defect reduction include adjusting the inclination angle of the particle beam during oblique incidence etching or a self-limiting reaction, or a combination thereof.

9. The method according to claim 8, wherein the deposition, etching, self-limiting reaction, or a combination thereof is selectively applied to a specific area.

10. The method according to any one of claims 1 to 9, wherein the deposition is performed using atomic layer deposition (ALD).

11. The method according to any one of claims 1 to 10, wherein the feature portion and the particle beam are rotated relative to each other during the oblique incidence etching.

12. The method according to any one of claims 1 to 11, wherein the sidewall roughness control results in a reduction of sidewall roughness.

13. The method according to any one of claims 1 to 12, wherein the oblique incidence etching is performed using atomic layer etching (ALE).

14. The method according to any one of claims 1 to 13, wherein the etching process is selective for silicon.

15. The method according to claim 14, wherein the etching process is selective for silicon oxide.

16. The method according to any one of claims 1 to 15, wherein the inclination of the particle beam can be set to 0 degrees from the angle of the perpendicular line to the substrate, and therefore the process can be carried out without adjusting the inclination angle of the particle beam during particle beam etching.

17. The method according to any one of claims 1 to 16, wherein the deposited material is amorphous or glassy.

18. The method according to any one of claims 1 to 17, wherein the beam particles have an atomic mass lower than at least one of the components of the exposed surface.

19. The method according to any one of claims 1 to 18, wherein the process further comprises rapid surface temperature cycling.

20. The method according to any one of claims 1 to 19, wherein the material to be deposited is the same as the material to be etched.

21. A method for reducing the sidewall roughness of feature portions on a substrate, wherein the feature portions are spaced apart and each has a field region and a sidewall, and the method is A patterned and selectively protective masking layer is formed such that at least a portion of the field region is masked, while the sidewalls are not masked. The process involves performing dry etching in a process chamber surrounding the substrate, and includes creating a horizontal component in the etching direction by setting the pressure in the process chamber to exceed a defined pressure threshold for sidewall etching, thereby performing dry etching in which the horizontal component etches the unmasked sidewalls to reduce the roughness of the sidewalls. Methods that include...

22. The method according to claim 21, wherein the defined pressure threshold for sidewall etching is 40 mTorr.

23. The method according to claim 21 or 22, wherein the dry etching is self-limiting, thereby stopping when the sidewall roughness decreases by a threshold amount.

24. The method according to any one of claims 21 to 23, wherein the sidewall roughness is reduced by at least 50%.

25. The method according to any one of claims 21 to 24, wherein the line edge roughness of the side wall is reduced to a value less than 1 nm RMS.

26. The method according to any one of claims 21 to 25, further comprising a self-limiting reaction such as chemiadsorption, deposition, extraction, oxidation, nitriding, or conversion.

27. The method according to claim 26, wherein the self-limiting reaction or the dry etching is selectively applied to a specific area of ​​the substrate.

28. The method according to any one of claims 21 to 27, wherein the dry etching is a cyclic etching process.

29. The method according to any one of claims 21 to 28, wherein the dry etching is performed using atomic layer etching (ALE).

30. The method according to any one of claims 21 to 29, wherein the dry etching is selective for materials comprising silicon, silicon oxide, silicon nitride, hafnium oxide, or aluminum oxide.

31. The method according to any one of claims 21 to 30, further comprising rapid surface temperature cycling.

32. The method according to claim 31, wherein the rapid surface temperature cycling is performed by surface exposure to plasma.

33. The method according to claim 31, wherein the rapid surface temperature cycling is assisted by the use of flash light.

34. The method according to claim 33, wherein the rapid surface temperature cycling assisted by flash light is performed using a laser light source.

35. The method according to any one of claims 21 to 34, wherein the feature portion on the substrate includes any of microscale and nanoscale devices, waveguides, transistors, bumps, grooves, holes, and / or columns.

36. A method for surface preparation based on cyclic processing, Activating the surface, Removing excess material from the aforementioned surface and surrounding environment, The surface is treated with low-energy particles, Repeat the above steps until the surface has the desired smoothness. Methods that include...

37. The method according to claim 36, wherein the low-energy particle treatment uses ions.

38. The method according to claim 37, wherein the low-energy particle treatment is atomic layer etching (ALE).

39. The method according to claim 38, wherein the low-energy particle treatment is atomic layer etching (ALE) with molecular activation.

40. The method according to claim 36, wherein the cyclic processing includes a deposition step.

41. The method according to claim 40, wherein the deposition step results in atomic layer deposition (ALD).

42. The method according to any one of claims 37 to 41, comprising a combination of etching and deposition.

43. The method according to any one of claims 37 to 42, comprising alternating etching and deposition.

44. The method according to any one of claims 36 to 43, wherein the repetition of the step is carried out until the process no longer affects different processed surfaces.

45. The method according to any one of claims 36 to 44, further comprising ion beam shaping technology.

46. The method according to claim 45, further comprising oblique incidence particle beam etching.

47. The method according to any one of claims 36 to 46, wherein the surface is a side wall surface.

48. The method according to any one of claims 36 to 47, wherein the aforementioned surface is an inclined surface.

49. The method according to any one of claims 36 to 48, wherein the surface is selected from the group consisting of a semiconductor surface, a metal surface, a dielectric surface, and a 2D material surface.

50. The method according to any one of claims 36 to 49, wherein the surface is a patterned surface.

51. The method according to any one of claims 36 to 50, wherein the surface is an unpatterned surface.

52. The method according to any one of claims 36 to 51, wherein the activation of the surface includes exposing the surface to a gas.

53. The method according to any one of claims 36 to 52, wherein the activation of the surface includes exposing the surface to a chemical solution.

54. The method according to any one of claims 36 to 53, wherein the activation of the surface includes heating the surface to a specific temperature.

55. The method according to any one of claims 36 to 54, wherein the activation of the surface includes irradiating the surface with a particle beam.

56. The method according to any one of claims 36 to 55, wherein the low-energy particle treatment includes a low-energy particle beam having a particle energy between 10 eV and 100 eV.

57. The method according to any one of claims 36 to 55, wherein the low-energy particle treatment includes low-energy plasma treatment with a plasma power between 1 W and 50 W.

58. A surface prepared by the method described in any one of claims 36 to 57.

59. A method for etching the sidewalls of feature portions (4110) on a substrate (44100), wherein the feature portions are spaced apart and each has a field region (4111) and a sidewall (4112), and the method is A composite masking layer is provided on the feature portion, comprising a first masking layer (4400) and a second masking layer (4300) on the first masking layer, thereby providing a composite masking layer in which at least a portion of the field region is masked by the composite masking layer, while the side walls are not masked. The method includes, Etching the side wall thereby reduces the height (h) between the feature portion and the first masking layer on the substrate. １ To maintain the above, etching of the side wall prevents etching of the first masking layer, Removing the first masking layer, thereby removing any remaining portion of the second masking layer Methods that further include this.

60. The method according to claim 59, wherein the first masking layer has the same etching properties as the feature portion on the substrate, and thereby the etching of the side wall (4112) of the feature portion removes the material of the side wall (4401) of the first masking layer at at least the same rate as the etching of the material of the feature portion.

61. The method according to claim 59 or 60, wherein the second masking layer is formed of a material having a lower etching rate than the material of the first masking layer.

62. The first masking layer is selectively removed after etching of the side wall, thereby reducing the height (h) of the feature portion after etching of the side wall. ２ The method according to any one of claims 59 to 61, wherein the surface is the same as before etching the side wall.

63. The method according to any one of claims 59 to 62, wherein the first masking layer separates the feature portion from the residual material (4411) after etching of the side wall.

64. The method according to claim 63, wherein the residual material adheres to the first masking layer and / or the second masking layer, and is thereby removed along with the removal of the first masking layer.

65. The method according to claim 63 or 64, wherein the first masking layer separates the feature portion from the residual material such that the feature portion has essentially uninterrupted vertical sidewalls with respect to the substrate.

66. The method according to any one of claims 59 to 65, wherein the composite masking layer includes a third masking layer (4500), thereby positioning the third masking layer between the feature portion and the first masking layer, and the material of the third masking layer is different from the material of the feature portion.

67. The method according to claim 66, wherein the thickness of the third masking layer is less than the thickness of the first masking layer.

68. The method according to claim 66 or 67, wherein the thickness of the third masking layer is less than 10 nm.

69. The method according to any one of claims 66 to 68, wherein the etching rate of the side wall (4501) of the third masking layer corresponds at least to the etching rate of the side wall (4112) of the feature portion (4110) when etching the side wall of the feature portion (4110).

70. The method according to any one of claims 66 to 69, wherein the material of the first masking layer is the same as the material of the feature portion.

71. The method according to any one of claims 66 to 70, wherein the method comprises removing the third masking layer, thereby removing any remaining portion of the first masking layer and the second masking layer.

72. The method according to any one of claims 66 to 71, wherein the third masking layer separates the feature portion from the residual material after etching of the sidewalls such that the feature portion has essentially uninterrupted vertical sidewalls with respect to the substrate.

73. The method according to claim 72, wherein the third masking layer separates the first masking layer from the feature portion such that the feature portion and the third masking layer have essentially continuous vertical sidewalls with respect to the substrate after the sidewall etching.

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