Method for manufacturing a semiconductor structure and semiconductor structure

By employing a carrier substrate with an adhesive layer and rewiring layer to facilitate the reuse of silicon substrates, the method addresses the high cost issue in semiconductor packaging by reducing material waste and enhancing process efficiency.

JP2026521811APending Publication Date: 2026-07-01CR RUNAN TECHNOLOGIES (CHONGQING) CO LTD +1

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
CR RUNAN TECHNOLOGIES (CHONGQING) CO LTD
Filing Date
2024-08-27
Publication Date
2026-07-01

AI Technical Summary

Technical Problem

The high cost of semiconductor packaging processes is attributed to the consumption and non-reusability of silicon substrates in existing technologies.

Method used

A method involving the use of a carrier substrate with an adhesive layer to mount electrical elements, forming a mold layer, removing the carrier substrate, and creating a rewiring layer connected to protruding bumps, allowing for the reuse of the carrier substrate and reducing material waste.

Benefits of technology

This approach reduces manufacturing costs by enabling the reuse of carrier substrates and improving the efficiency of semiconductor packaging processes.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 2026521811000001_ABST
    Figure 2026521811000001_ABST
Patent Text Reader

Abstract

The present invention provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes the steps of: providing an adhesive layer on one side of a carrier substrate; arranging one or more electrical elements on the side of the adhesive layer opposite to the carrier substrate, wherein at least one electrical element includes a body and a bump protruding from the body, the bump facing the carrier substrate and positioned such that at least a portion of the bump is inside the adhesive layer; forming a mold layer on the adhesive layer to seal at least the side of the electrical element; removing the carrier substrate and the adhesive layer, thereby exposing the portion of the bump that is inside the adhesive layer; and forming a redistribution layer on the side of the electrical element where the bump is provided, wherein the redistribution layer is electrically connected to the bump.
Need to check novelty before this filing date? Find Prior Art