Method for manufacturing a semiconductor structure and semiconductor structure
By employing a carrier substrate with an adhesive layer and rewiring layer to facilitate the reuse of silicon substrates, the method addresses the high cost issue in semiconductor packaging by reducing material waste and enhancing process efficiency.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- CR RUNAN TECHNOLOGIES (CHONGQING) CO LTD
- Filing Date
- 2024-08-27
- Publication Date
- 2026-07-01
AI Technical Summary
The high cost of semiconductor packaging processes is attributed to the consumption and non-reusability of silicon substrates in existing technologies.
A method involving the use of a carrier substrate with an adhesive layer to mount electrical elements, forming a mold layer, removing the carrier substrate, and creating a rewiring layer connected to protruding bumps, allowing for the reuse of the carrier substrate and reducing material waste.
This approach reduces manufacturing costs by enabling the reuse of carrier substrates and improving the efficiency of semiconductor packaging processes.
Smart Images

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