A set of configurable mesh network nodes and related methods for mitigating voltage droop in integrated circuit (IC) chips.

Abstract

A cluster circuit provided at each node of the IC chip is used to reduce power consumption at the nodes of the cluster zone and mitigate voltage droop based on a power consumption index in the cluster zone of the IC chip. Each cluster zone includes a first node that receives a power consumption index associated with the first node and power consumption indexes associated with other nodes in the cluster zone. The first node generates a control signal based on the received index, and each of the multiple nodes in the cluster zone reduces power consumption based on the control signal. In some examples, the cluster circuit of any node may be configured to operate in a first mode as the first node or in a second mode as one of the second nodes, providing flexibility in the configuration of the cluster zone.

Description

[Technical Field]

[0001] Areas of disclosure

[0001] The technologies of the present disclosure relate in general to reducing voltage droop in integrated circuits, and more particularly to minimizing current spikes by controlling circuit switching. [Background technology]

[0002] background

[0002] In order to reduce the package size of the technologies used for high-performance processing capabilities, the number of processing circuits provided on an integrated circuit (IC) chip continues to increase. Congestion can occur on the IC chip due to data communication between many processing circuits. One method of handling data processed by many processing circuits is to use a mesh network in which each processing circuit is connected to a node in the network, and data is passed between nodes across segments of the network. At each node, the number of circuits that are switched by data transmission in a given system clock cycle varies from node to node, depending on each processing circuit. Therefore, the power demand between nodes can change frequently, and the power level of the IC chip area can rise sharply. In such situations, the demand for current in the power rails that provide the power supply voltage to these areas increases sharply. The capacitance of the power distribution network within the IC chip can discharge in response to the sharp increase in current, causing a temporary drop in the voltage level of the power rails. To prevent the power supply voltage of the power rails from dropping below the minimum voltage, which would prevent the processing circuits from continuing to operate normally, a voltage margin can be provided by always maintaining a higher nominal voltage level maintained on the power rails. However, maintaining a higher nominal voltage level on the power rail increases the power consumption of the IC chip, which can lead to thermal issues and shorten the battery life of mobile devices. Power will be saved and excessive heat will be avoided by circuits and methods to avoid voltage droop at nodes in the mesh network without simply increasing the power supply voltage to the entire IC chip. [Overview of the Initiative]

[0003] overview

[0003] Embodiments disclosed in the detailed description include a set of configurable mesh network nodes for mitigating voltage droop in an integrated circuit (IC) chip. Related methods for configurably assembling mesh network nodes to mitigate voltage droop are also disclosed. A sudden increase in current demand at a node in a mesh network on an IC chip, known as a di / dt event, can cause droop in the power supply voltage of the power rails coupled to the node. This problem can occur in individual nodes or regions of the IC chip due to data transmission between multiple adjacent nodes on the mesh network. An IC chip may have multiple such regions that can be identified through inspection. Using exemplary aggregation circuits provided at each node of the IC chip, voltage droop can be mitigated by reducing power consumption at nodes in aggregation zones based on an index of power consumption in the aggregation zone of the IC chip. In particular, each aggregation zone includes a first node (also referred to herein as a “leader” node), which receives an index of power consumption associated with the first node and an index of power consumption associated with each of the other nodes in the aggregation zone. The first node generates a control signal based on the received indicator, and each of the multiple nodes in the aggregate zone reduces power consumption based on the control signal. In some examples, the aggregate circuit of any node may be configured to operate in either a first leader mode or a second follower mode, providing flexibility in the configuration of the aggregate zone. In some examples, the aggregate circuit of several nodes in the aggregate zone is configured in a third intermediate mode, which receives a power consumption indicator from a node in second follower mode and provides that indicator to the first node. In addition, in such examples, the node in third intermediate mode may receive a control signal from the first node and provide a first control signal to the node in second follower mode.

[0004]

[0004] In this regard, an IC chip is disclosed. The IC chip includes a plurality of nodes in a mesh network. The IC chip further includes a first aggregation zone including a first node and at least a second node of the plurality of nodes, each node of the plurality of nodes includes aggregation circuitry configured to receive a first indicator of power consumption associated with the node, the aggregation circuitry of the first node is configured to, in response to operating in a first mode, receive at least a second indicator of power consumption associated with each of at least the second nodes, and provide a first control signal to each of the at least second nodes based on the first indicator and at least the second indicator, and the aggregation circuitry of the first node and at least the second node is configured to reduce power consumption at the node in response to the first control signal.

[0005]

[0005] In another embodiment, a method in an IC chip is disclosed. The method includes receiving a first indicator of power consumption associated with a node in the aggregation circuit of each node among a plurality of nodes in a mesh network, in a first aggregation zone including a first node and at least a second node among a plurality of nodes. The method further includes, in response to the aggregation circuit of the first node being configured to operate in a first mode, receiving at least a second indicator of power consumption associated with each of at least a second node, providing a first control signal to each of the at least second nodes based on the first indicator and at least a second indicator, and reducing power consumption at the node in the aggregation circuit of the first node and at least a second node in response to the first control signal. [Brief explanation of the drawing]

[0006] A brief explanation of the diagram. [Figure 1]

[0006] This is a block diagram of an integrated circuit (IC) chip including nodes interconnected within a mesh network. [Figure 2]

[0007] This graph illustrates the voltage changes over time in response to current load steps that generate primary, secondary, and tertiary voltage droops. [Figure 3]

[0008] This is an exemplary block diagram of a node including a cluster circuit that can be coupled to a segment of a mesh network and used to configure cluster zones for mitigating voltage droop in regions containing nodes within an IC chip. [Figure 4]

[0009] This is a block diagram of an exemplary aggregate circuit that can be configured to operate in one of several modes within aggregate zones, which are located at each node of a mesh network within an IC chip and are used to mitigate voltage droop in the region of the IC containing the node. [Figure 5]

[0010] This is a block diagram of an IC chip, consisting of multiple nodes in a first example of a cluster zone, which receives an indicator of power consumption and reduces power consumption in each of the multiple nodes within the cluster zone to mitigate voltage droop. [Figure 6]

[0011] This is a flowchart of a method in a set circuit within an IC chip, configured to mitigate voltage droop by forming at least one set zone containing multiple nodes. [Figure 7]

[0012] This is a block diagram of a node that includes multiple router circuits connected to a mesh network segment and configured to reduce power consumption at the node in response to control signals. [Figure 8]

[0013] This is a block diagram of an IC chip, consisting of multiple nodes in a second example of a cluster zone, which receives power consumption indicators and reduces power consumption in each of the multiple nodes within the cluster zone to mitigate voltage droop. [Figure 9]

[0014] This is a block diagram of an IC chip consisting of multiple nodes in a third example of a cluster zone, which receives power consumption indicators and reduces power consumption in each of the multiple nodes within the cluster zone to mitigate voltage droop. [Figure 10]

[0015] This is a block diagram of an exemplary processor-based system which may include IC chips with nodes in a mesh network, and each node includes exemplary aggregation circuits for configuring the nodes in aggregation zones to reduce power consumption and mitigate voltage droop in the area of ​​the IC chip, as shown in Figures 3-5 and 7-9. [Modes for carrying out the invention]

[0007] Detailed explanation

[0016] Herein, several exemplary embodiments of the present disclosure are described with reference to the drawings. The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” No embodiment described herein as “exemplary” is necessarily construed to be preferable or advantageous to any other embodiment.

[0008]

[0017] The aspects disclosed in the detailed description include a set of configurable mesh network nodes for mitigating voltage droop in an integrated circuit (IC) chip. Related methods for configurable assembly of mesh network nodes for mitigating voltage droop are also disclosed. A rapid increase in current demand at nodes within a mesh network on an IC chip, known as a di / dt event, can cause a droop in the supply voltage of the supply rail coupled to the node. This problem can occur in individual nodes or regions of the IC chip due to data transmission between multiple adjacent nodes on the mesh network. The IC chip can have multiple such regions that can be identified through inspection. Using exemplary set circuits provided at each of the nodes of the IC chip, based on an indicator of power consumption in a set zone of the IC chip, power consumption at the nodes within the set zone can be reduced to mitigate voltage droop. In particular, each set zone includes a first node (also referred to herein as a "leader" node), which receives an indicator of power consumption associated with the first node and an indicator of power consumption associated with each of the other nodes within the set zone. The first node generates a control signal based on the received indicators, and each of the plurality of nodes within the set zone reduces power consumption based on the control signal. In some examples, the set circuit of any node can be configured to operate in a first leader mode or a second follower mode, providing flexibility in the configuration of the set zone. In some examples, the set circuits of some of the nodes within the set zone are configured in a third intermediate mode that receives an indicator of power consumption from a node in the second follower mode and provides that indicator to the first node. Additionally, in such examples, a node in the third intermediate mode can receive a control signal from the first node and provide the first control signal to a node in the second follower mode.

[0009]

[0018] Before describing exemplary aspects of the aggregation circuits 310 and 400 of FIGS. 3 and 4 used at each node of the mesh network of the IC chip to configure an aggregation zone to mitigate voltage droop, referring to FIG. 1, an IC chip 100 including a plurality of nodes 102(1) to 102(X) will first be described, and referring to FIG. 2, a diagram of voltage droop in the IC chip 100 will be described.

[0010]

[0019] The IC chip 100 can be a system-on-chip (SOC) and can include many processing circuits (not shown here) each coupled to one of a plurality of nodes 102(1) to 102(X) (collectively referred to as nodes 102) within the mesh network 104. The nodes 102 are coupled to each other by segments 106 of the mesh network 104. That is, each of the segments 106 is coupled, for example, between a first node 102(1) and a second node 102(2) adjacent to each other. Each of the nodes 102(1) to 102(X) is coupled to at least two segments of the mesh network 104. Due to its length, the segment 106 has a significant capacitance. Thus, when switching the data transmitted in the segment 106 in each cycle of the system clock CLK, a significant amount of power is consumed by a driver circuit (not shown) driving the data. The system clock CLK is used to trigger the flow of data through sequential circuits and to provide synchronization in the IC chip 100.

[0011]

[0020] A significant amount of power is consumed in a short period of time by any of the nodes 102 (e.g., a high power consumption rate), requiring a high level of current to be supplied to those nodes 102. As described above, data transmission on segment 106 is a significant source of such power consumption. In situations where power consumption increases rapidly from a low power consumption state where data transmission may not occur frequently to a high power consumption state where data transmission occurs in all or nearly all cycles, the current demand from the power rails supplying power to the data-transmitting nodes 102 can increase rapidly. A rapid increase in current (i) over a short period of time (t), known as a di / dt event, in a node 102 or group of nodes 102 within the area of ​​IC chip 100 can discharge the capacitance of the power distribution network within the area of ​​IC chip 100 or the entire IC chip 100 before an external power management circuit (not shown) can respond and supply power more quickly.

[0012]

[0021] As a result of the discharge of capacitance in the power distribution network, the available charge is consumed, which can cause a sharp drop in the power rail voltage. If the voltage to the processing circuit drops below a minimum threshold, the processing circuit and data driver may not operate as intended, which can cause malfunction of IC chip 100. Such a drop in power supply voltage is known as voltage droop and is explained in more detail with reference to Figure 2.

[0013]

[0022] Figure 2 shows the power supply voltage V on the power rail of the IC chip without the exemplary circuit set 400 in Figure 4. ps Graph 200 illustrates an example of this. Figure 2 shows the power supply voltage V changing over time (in nanoseconds (ns)) in response to voltage droop. ps This is shown. Graph 200 shows that the voltage droop response to a di / dt event can have up to three stages, which are called primary, secondary, and tertiary voltage droops, and these are based on the supply voltage V psThese can be identified by low points 202, 204, and 206, respectively. These low points 202, 204, and 206 correspond to the depletion of capacitance supplied to the IC chip 100 in the power grid at different distances from node 102, respectively. For example, the primary droop indicated as low point 202 corresponds to the discharge of the power grid capacitance of the IC chip 100 itself. The capacitance of the IC chip 100 can be supplied by coupled capacitors. Outside the IC chip 100, the first level power capacitor is typically coupled to the same substrate as the IC chip 100 in an IC package (not shown) or otherwise located in physical proximity to the IC chip 100. Power supply voltage V ps The low point 202 occurs before the charge from the first level power capacitor can reach the power network inside the IC chip 100. When the charge from the first level power capacitor reaches the power network, the power supply voltage V ps The system recovers and begins to stabilize. However, if the condition persists and / or is sufficiently severe, the first level power capacitor may also completely discharge, leading to a second low point 204. In some cases, the capacitance of the first level power capacitor is greater than the capacitance of the internal power network (e.g., coupling capacitor), resulting in a longer discharge time for the first level power capacitor and a delayed arrival at the second low point 204.

[0014]

[0023] To supply power to the IC chip 100, a power management chip or a voltage regulator (not shown) may be coupled to the IC package substrate. The power management chip is typically located further away from the IC chip 100 than the first-level power capacitor. Adjacent to the power management chip, the power distribution network supplying power to the IC chip 100 includes one or more second-level power capacitors having even larger capacitances than the first-level power capacitor. The second-level power capacitors may also discharge before the second-level power capacitor coupled to the power management chip can provide charge to meet the current level required by the IC chip 100. From the discharge of the second-level power capacitors, the power supply voltage V ps Stabilized voltage VST The transition to is shown as the third low point 206 in FIG. 2. The power supply voltage V ps is such that each of the coupling capacitor, the power capacitor at the first level, and the power capacitor at the second level is recharged, and the stabilized voltage V ST gradually recovers from the nominal supply voltage V NOM to the nominal supply voltage V

[0015]

[0024] As shown in the example of FIG. 2, the first low point 202 reduces the power supply voltage V ps the most. In other examples, depending on the relative capacitance of the on-chip coupling capacitor and the power capacitor at the first level, the low point 204 of the secondary voltage droop may be lower than the low point 202. As described above, when the power supply voltage V PS drops below the minimum threshold voltage V MIN , the operation of the circuit may start to become abnormal or unexpected. To avoid malfunction of the circuit of the IC chip 100 when such a voltage droop occurs, the nominal supply voltage V NOM provided to the IC chip 100 is set high enough so that none of the first low point 202, the second low point 204, and the third low point 206 of the power supply voltage V ps falls below the minimum threshold voltage V MIN . However, in this example, the nominal supply voltage V NOM determined based on the first low point 202 is significantly higher than the minimum threshold voltage V MIN required to keep the circuit of the IC chip 100 operating normally. Since the power consumption of the IC chip 100 is based on the power supply voltage V MIN that has risen above the minimum threshold voltage V ps due to the voltage droop, it would be preferable to reduce the voltage droop and lower the nominal supply voltage V NOM to reduce the power consumption. Reducing the power consumption reduces power-related heat generation and extends the battery life of the mobile device including the IC chip 100. Therefore, it would be beneficial to mitigate the voltage droop by using the integrated circuit 400 and method to avoid a sudden change in the current level (e.g., a di / dt event).

[0016]

[0025] Figure 3 is a block diagram illustrating an exemplary node 300 coupled to multiple segments 302 of a mesh network 304. Processing circuitry 306 is coupled to node 300 by interface 308. Node 300 may be any of the nodes 102 in Figure 1, and segment 302 may be segment 106 in Figure 1. Figure 3 is provided to show the environment of node 300 and mesh network 304 in more detail and to show that aggregation circuitry 310 is included in each of the nodes 300. Aggregation circuitry 310 may include node 300 and be configured to implement aggregation zones to mitigate voltage droop in the area of ​​IC chip 100 containing node 300.

[0017]

[0026] The processing circuit 306 may include any type of processor, processor core, and / or data storage circuit (e.g., cache memory or register file). The processing device can rapidly process large amounts of data based on a sequence of instructions. Instructions and raw data for processing are transferred from another node to node 300 before being provided to the processing circuit 306, and the data processed by the processing circuit 306 is transferred from node 300 to another node through the mesh network 304 for further processing or storage. Thus, processing activities and events in the processing circuit 306 cause traffic (data transfer) in segment 302 coupled to node 300. In addition to all the traffic from the processing circuit 306, data may also be transferred from the processing circuit 306 of the first node 102(1) in Figure 1 to the second node 102(3) through node 300 (e.g., node 102(2) in Figure 1), further increasing the traffic level entering and leaving the intermediate node 102(2) beyond the traffic from the processing circuit 306 coupled to node 300.

[0018]

[0027] In this regard, the power consumption inside and around node 300 may be mainly attributable to the processing circuit 306 and the traffic passing through node 300. In particular, the majority of the power consumption associated with node 300 may be attributable to data transmission (e.g., data egress) in segment 302 from node 300, as power is required to charge the long wires of segment 302 from node 300 to adjacent nodes (see Figure 1). The configuration of the aggregation circuit 310 will be further described with reference to Figures 4 and 5.

[0019]

[0028] Figure 4 is a block diagram of an exemplary aggregate circuit 400 that may be located at node 300 of the mesh network 304 in Figure 3 and can be configured to operate in one of several modes at node 300 which is included in an aggregate zone for mitigating voltage droop in the region of the IC chip 100 in Figure 1.

[0020]

[0029] The aggregation circuit 400 includes a plurality of inputs 402 and outputs 404, each described for each mode in which the aggregation circuit 400 may be configured to operate. The aggregation circuit 400 includes a configuration register 406, which may be configured to selectively control the aggregation circuit 400 to operate in one of a first mode, a second mode, and a third mode. The configuration register 406 may be configured to include information about the aggregation zone in which the aggregation circuit 400 is contained. The configuration register 406 may be programmed to include threshold information, which is compared against an index of power consumption at node 300 and, in some examples, also against an index of power consumption at other nodes in the aggregation zone. The aggregation circuit 400 includes a zone circuit 408 that receives a signal at input 402 and generates a signal (described later) at output 404. The aggregation circuit 400 also includes memory circuits 410P and 410C and selectors 412P and 412C. Signals 414P and 414C received at input 402 may be used to generate signals 416P and 416C at output 404. In some first examples, signals 416P and / or 416C generated at output 404 may be generated by zone circuit 408 in the same cycle in which signals 414P and / or 414C are received at input 402. In some second examples, signals 416P and 416C are generated at output 404 in the next cycle after signals 414P and 414C are received at input 402. In these second examples, memory circuits 410P and 410C are provided to store signals 416P and 416C for one or more cycles as needed. Selectors 412P and 412C are controlled by signals 418P and 418C and provide signals 416P and 416C directly from zone circuit 408 or memory circuits 410P and 410C. Memory circuits 410P and 410C may be used due to timing constraints.

[0021]

[0030] Figure 5 is a block diagram of an IC chip 500 containing multiple nodes 502(1) to 502(N), each node containing the aggregation circuit 400 of Figure 4 to constitute multiple nodes 502(1) to 502(N) in its respective aggregation zone 504(1) to 504(Z). In this example, there are 12 aggregation zones 504(1) to 504(Z) (where Z=12). The IC chip 500 may be the IC chip 100 of Figure 1. The multiple nodes 502(1) to 502(N) are interconnected by segments 506 of a mesh network 508. Aggregation zone 504(1) is described here as an example of aggregation zones 504(1) to 504(Z) and will not be described separately unless necessary. Aggregation zone 504(1) contains a first leader node 510, in which the aggregation circuit 400 is configured in a first leader operating mode. The aggregate zone 504(1) also includes the second follower nodes 512(1) to 512(F), where F=4 in this example. Each aggregate zone 504(1) to 504(Z) includes at least one second follower node 512(1) to 512(F). In aggregate zones 504(1) to 504(Z), the number of follower nodes 512(1) to 512(F) may be less than or equal to the number of segments 506 joined to the leader node 510. Each of the leader node 510 and the follower nodes 512(1) to 512(F) is one of a group of nodes 502(1) to 502(N). Each of the follower nodes 512(1) to 512(F) is adjacent to the leader node 510, meaning that each of the follower nodes 512(1) to 512(F) is connected to the leader node 510 by one of the segments 506. In this example, the aggregate zones 504(1) to 504(Z) may contain up to four follower nodes 512(1) to 512(F) adjacent to the leader node 510. The configuration register 406 of the aggregate circuit 400 may be configured to identify which of the nodes adjacent to the leader node 510 is included in the aggregate zone 504(1).

[0022]

[0031] Each of the multiple node 502(1) to 502(N) cluster circuits 400 may be configured to receive a power consumption index 514 associated with each of the nodes 502(1) to 502(N). For example, the cluster circuit 400 of node 502(1) receives a power consumption index 514 associated with node 502(1). The power consumption index 514 associated with node 502(1) may include an index of the power supply voltage (e.g., in a power rail not shown here) that provides the power supply voltage to node 502(1). In this regard, the IC chip 500 receives the power supply voltage V of the power rail (not shown) of the IC chip 500. PS The system may include a voltage comparator 516 configured to compare the power supply voltage to one or more threshold voltages and generate an output indicating whether the power supply voltage is higher or lower than a threshold or within a range between thresholds, in order to indicate the voltage level. The index 514 may include the output from the voltage comparator 516.

[0023]

[0032] Instead, indicator 514 may include or be based on indicators of one or more activities or events related to data transmission from node 502(1). For example, indicator 514 may be an indicator of an activity or event that is occurring or is scheduled to occur in processing circuit 306 (and coupled to node 502(1)) shown in Figure 3, which may lead to data transmission from one node 502(1) of segment 506. Indicator 514 is one of the signals 414P that may be received at input 402 of the aggregation circuit 400.

[0024]

[0033] In some examples, the aggregate circuit 400 of node 502(1) may also receive an indicator 518 of activity or event at a node adjacent to node 502(1) (for example, a node connected to node 502(1) by one of the segments 506), because activity and / or events at an adjacent node may indicate data transmission that will also occur at node 502(1). Indicator 518 is one of the signals 414P that may also be received at input 402 of the aggregate circuit 400 in Figure 4.

[0025]

[0034] Multiple nodes 502(1) to 502(N) can use indices 514 and 518, without the aggregation circuit 400, to identify situations where a di / dt event may or may occur and where power consumption or the rate of change in power consumption needs to be reduced. In such situations, multiple nodes 502(1) to 502(N) can reduce power consumption by blocking data transmission in segment 506, as will be further described below. Power consumption reduction can also be achieved by reducing other activities in multiple nodes 502(1) to 502(N), and the aggregation circuit 400 is not limited in this respect.

[0026]

[0035] However, multiple nodes 502(1) to 502(N), including the aggregation circuit 400, can cooperate and communicate to mitigate voltage droop in one or more areas of the IC chip 500 by configuring the aggregation circuit 400 in aggregation zones 504(1) to 504(Z) as follows: In aggregation zone 504(1), the aggregation circuit 400 of the leader node 510 is configured to operate in leader mode, and the aggregation circuits 400 of the follower nodes 512(1) to 512(F) are configured to operate in a second mode. It should be understood that any aggregation circuit 400 of nodes 502(1) to 502(N) may be configured to operate in either the first or second mode, thus enabling many different aggregation zone configurations. It should also be understood that the operation of the aggregation circuit 400 in the leader node 510 and follower nodes 512(1) to 512(F) may refer to the operation of the leader node 510 and follower nodes 512(1) to 512(F).

[0027]

[0036] In the second operating mode, instead of directly responding to indices 514 and 518 by reducing its own data transmission, each of the follower nodes 512(1) to 512(F) generates a power consumption index 520 in the zone circuit 408 of the aggregate circuit 400 and provides the index 520 at the output 404 of the aggregate circuit 400. In this example, the index 520 is provided to the leader node 510 in the aggregate zone 504(1). The index 520 may be one of the signals 416P in Figure 4.

[0028]

[0037] In the first operating mode, in addition to receiving its own indices 514 and 518, the leader node 510 receives indices 520 from all follower nodes 512(1) to 512(F). Based on the indices 514, 518, and 520 received by the leader node 510, the aggregate circuit 400 of the leader node 510 generates a control signal 522 to reduce power consumption in the leader node 510 and all follower nodes 512(1) to 512(F). In other words, the control signal 522 can be used to reduce power consumption in each of the multiple nodes 502(1) to 502(N) within the aggregate zone 504(1). The control signal 522 may be generated by the zone circuit 408 in Figure 4 and provided by output 404. In the leader node 510, the control signal 522 may be one of the signals 416C in Figure 4. The control signal 522 can be generated based on the sum, combination, or algorithm of indices 514, 518, and 520 in a single or multiple cycles of the system clock CLK. In this regard, indices 514, 518, and 520 can be used to generate values ​​that are compared to configurable thresholds in the configuration register 406 of the assembly circuit 400. The control signal 522 is provided to each of the follower nodes 512(1) to 512(F) and can be used by each of the follower nodes 512(1) to 512(F), in addition to the leader node 510, to reduce power consumption, which may include blocking data transmission. In the follower nodes 512(1) to 512(F), the control signal 522 may be one of the signals 414C in Figure 4.

[0029]

[0038] Similar to aggregation zone 504(1), each of aggregation zones 504(2) to 504(Z) includes a follower node operating in a second mode, which in response to a control signal provided by the leader node, operates in a first mode to reduce power consumption.

[0030]

[0039] Figure 6 is a flowchart of Method 600 for IC chip 500. Method 600 includes receiving a first index 514 of power consumption associated with a node in a first aggregate zone 504(1) (block 602) which includes a first node 510 and at least one second node 512(1) to 512(F) among a plurality of nodes 502(1) to 502(N) in a mesh network 508 (block 604). Method 600 further includes, in response to the leader node 510's aggregation circuit 400 being configured to operate in a first mode (block 606), receiving at least a second indicator 520 of power consumption associated with each of the at least one follower nodes 512(1) to 512(F) (block 608), and providing a first control signal 522 based on the first indicator 514 and at least the second indicator 520 to each of the at least one follower node 512(1) to 512(F) (block 610). Method 600 further includes reducing power consumption in the leader node 510 and each of the aggregation circuits 400 of the at least one follower node 512(1) to 512(F) in response to the first control signal 522 (block 612).

[0031]

[0040] Figure 7 is a block diagram of node 700, which includes multiple router circuits 702(1) to 702(D), which are coupled to segments 704(1) to 704(4) of the mesh network 706 and configured to reduce power consumption at node 700 in response to control signals, such as control signal 522 (not shown here) in Figure 5. Node 700 may be node 300 in Figure 3, or any of the multiple nodes 502(1) to 502(N) in Figure 5. Segments 704(1) to 704(4) each contain multiple channels 708(1) to 708(D), and router circuits 702(1) to 702(D) each couple to one of the corresponding channels 708(1) to 708(D) in segments 704(1) to 704(4). Router circuits 702(1) to 702(D) provide routing or switching capabilities and can selectively receive and transmit data on any one of segments 704(1) to 704(4). Figure 7 is provided to illustrate an example of a method that can reduce power consumption at node 700. In particular, power consumption at node 700 can be reduced by reducing the number of data transmissions from router circuits 702(1) to 702(D). For example, router control circuits 710(1) to 710(D) can receive control signal 522 shown in Figure 5, which is interpreted as an instruction to control router circuits 702(1) to 702(D) to block data transmission for a certain number of cycles or pattern over a period of time. In some examples, reducing power consumption at node 700 includes blocking data transmission from a subset or all of router circuits 702(1) to 702(D).

[0032]

[0041] Figure 8 is a block diagram of IC chip 800 in which multiple nodes 802(1) to 802(N) are composed of a second example of aggregation zones 804(1) to 804(Z). For example, aggregation zone 804(1) can receive power consumption indicators from multiple nodes 806, 808(1) to 808(5), 810(1), and 810(2), and reduce power consumption to mitigate voltage droop. In this example, aggregation zones 804(1) to 804(Z) are configured differently from those in Figure 5. Aggregation zone 804(1) is described as an example that can be applied to any of aggregation zones 804(1) to 804(Z). In this example, there are six aggregation zones 804(1) to 804(6) (where Z=6).

[0033]

[0042] The aggregate zone 804(1) includes a first leader node 806, in which the aggregate circuit 400 (Figure 4) is configured in a first leader operating mode. The aggregate zone 804(1) also includes second follower nodes 808(1) to 808(5). In addition, the aggregate zone 804(1) includes third intermediate nodes 810(1) and 810(2). In contrast to the aggregate zone 504(1) in Figure 5, where all follower nodes 512(1) to 512(4) are adjacent to the leader node 510 and can be said to be one "hop" away from the leader node 510 through one of the segments 506, follower nodes 808(1), 808(3), 808(4), and 808(5) are not adjacent to the leader node 806 (e.g., not one hop away from the leader node 806). Instead, intermediate nodes 810(1) and 810(2) are adjacent to leader node 806, follower nodes 808(1), 808(4), and 808(5) are adjacent to intermediate node 810(1), and follower node 808(3) is adjacent to intermediate node 810(2). In other words, follower nodes 808(1), 808(3), 808(4), and 808(6) are two hops away from leader node 806. Figure 5 shows that follower node 808(2) and intermediate node 810(2) can be reversed.

[0034]

[0043] In the intermediate node 810's aggregate circuit 400, the configuration register 406 is configured to selectively control the aggregate circuit 400 to operate in a third mode. It should be noted that any of the aggregate circuits 400 in nodes 802(1) to 802(N) can be configured in one of the first, second, or third modes, depending on the aggregate zone 804(1) to 804(Z). In the third mode, the intermediate node 810's aggregate circuit 400 also receives indices 514 and 518 (not shown here) as signals 414P indicating power consumption associated with the intermediate node 810, as shown in Figure 5. Intermediate nodes 810(1) and 810(2) also receive index 816 from adjacent follower nodes 808(1), 808(3), 808(4), and 808(5), which corresponds to index 520 from follower nodes 512(1) to 512(4) received by leader node 510 in Figure 5. However, unlike leader node 510 in Figure 5 and leader node 806 in Figure 8, intermediate nodes 810(1) and 810(2) each generate index 818 (similar to index 520) based on indices 514, 518, and 816, and provide this index 818 to leader node 806. Follower nodes 808(2) and 808(5) also generate index 816 based on index 812 they themselves received. Leader node 806 receives index 816 from follower node 808(2). Intermediate node 810(1) aggregates indicators 816 from follower nodes 808(1), 808(4), and 808(5) and provides indicator 818 to leader node 806. Based on indicators 816 and 818 from follower nodes 808(2) and 808(5) and intermediate node 810, leader node 806 generates a control signal 522 (not shown here to avoid congestion) as shown in Figure 5 and provides this control signal 522 to follower node 808(2) and intermediate nodes 810(1) and 810(2). Intermediate nodes 810(1) and 810(2) receive the control signal 522 and provide this control signal 522 to follower nodes 808(1), 808(3), 808(4), and 808(5).In this way, the leader node 806 receives power consumption indicators from all nodes in aggregation zone 804(1) and provides control signals 522 based on these indicators to reduce power consumption in all nodes within aggregation zone 804(1). In this regard, compared to aggregation zones 504(1) to 504(Z) in Figure 5, larger or differently shaped regions of the IC chip 800 can be centrally monitored by the leader node 806 with respect to power consumption and uniformly controlled to avoid voltage droop in the regions of the IC chip 800. In the intermediate nodes 810(1) and 810(2), the control signal 522 received from the leader node 806 is one of the signals 414C received at input 402 of the aggregation circuit 400.

[0035]

[0044] Figure 9 is a block diagram of an IC chip 900 consisting of multiple nodes 902(1) to 902(N) in a third example, which has only an aggregation zone 904 that receives an indicator of power consumption and reduces power consumption in each of the multiple nodes within the aggregation zone 904 to mitigate voltage droop in the IC chip 900. Each aggregation circuit 400 of the multiple nodes 902(1) to 902(N) is configured to operate in one of a first leader mode, a second follower mode, and a third intermediate mode. Aggregation zone 904 includes a leader node 906 and multiple second follower nodes 908(1) to 908(F), but aggregate zone 904 differs from aggregation zone 804(1) in Figure 8 mainly by having multiple levels of intermediate nodes 910(1) to 910(M). Each intermediate node 910(1) to 910(M) essentially operates similarly to intermediate node 810 in Figure 8, receiving power consumption indicators from up to four adjacent nodes, which can be any combination of intermediate nodes 910(1) to 910(M) and follower nodes 908(1) to 908(F). Instead of receiving control signals directly from leader node 906, intermediate nodes 910(1) to 910(M) can receive control signals from another intermediate node 910(1) to 910(M). In this configuration, all voltage consumption indicators of multiple nodes 902(1) to 902(N) can be considered, and control signals based on such indicators can be used across all multiple nodes 902(1) to 902(N) to reduce power consumption in order to mitigate voltage droop across IC chip 900. In the example shown in Figure 9, the mesh network 912 spans area A of the IC chip 900, and the leader node 906 is located in the central part of area A. Placing the leader node 906 in the central part allows for optimization of the number of hops from the follower nodes 908(1) to 908(F) to the leader node 906.

[0036]

[0045] Figure 10 is a block diagram of an exemplary processor-based system 1000, which includes a processor 1002 (e.g., a microprocessor) that includes an instruction processing circuit 1004 coupled to a mesh network of nodes, each containing a cluster circuit configured to receive an indicator of power consumption using cluster zones and reduce power consumption at each of the nodes, as illustrated in Figures 5, 7, and 8. Any of the processor-based system 1000, processor 1002, and instruction processing circuit 1004 may, for example, be the IC chip 100 in Figure 1. The processor-based system 1000 may be one or more circuits contained in an electronic board card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer.

[0037]

[0046] In this example, processor 1002 represents one or more general-purpose processing circuits, such as a microprocessor or a central processing unit. Processor 1002 is configured to execute processing logic with instructions for performing the operations and steps described herein. In this example, processor 1002 includes an instruction cache 1006 for temporary high-speed access storage of instructions accessible by instruction processing circuit 1004. Instructions fetched or prefetched from memory, for example, from cache memory 1012 via system bus 1010, are stored in instruction cache 1006. Instruction processing circuit 1004 is configured to process the instructions fetched into instruction cache 1006 and process the instructions for execution.

[0038]

[0047] The processor 1002 and cache memory 1012 are coupled to a system bus 1010, enabling interconnection of peripheral devices included in the processor-based system 1000. As is well known, the processor 1002 communicates with these other devices by exchanging address, control, and data information through the system bus 1010. For example, the processor 1002 may communicate bus transaction requests to the memory controller 1014 of the main memory 1008, as an example of a slave device. Although not shown in Figure 10, multiple system buses 1010 may be provided, each system bus having a different structure. In this example, the memory controller 1014 is configured to provide memory access requests to the memory array 1016 of the main memory 1008. The memory array 1016 consists of an array of storage bit cells for storing data. The main memory 1008 may, in non-limiting examples, be read-only memory (ROM), flash memory, synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM)).

[0039]

[0048] Other devices can be connected to the system bus 1010. As shown in Figure 10, these devices may include, for example, main memory 1008, one or more input devices 1018, one or more output devices 1020, a modem 1022, and one or more display controllers 1024. Input devices 1018 may include, but are not limited to, any type of input device, including, input keys, switches, voice processors, etc. Output devices 1020 may include, but are not limited to, any type of output device, including, audio, video, other visual indicators, etc. Modem 1022 may be any device configured to enable data exchange with network 1026. Network 1026 may include, but are not limited to, any type of network, including, wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth® networks, and the Internet. Modem 1022 may be configured to support any type of communication protocol required. The processor 1002 may also be configured to access the display controller 1024 via the system bus 1010 to control the information sent to one or more displays 1028. The displays 1028 may include, but are not limited to, any type of display, such as a cathode ray tube (CRT), liquid crystal display (LCD), or plasma display.

[0040]

[0049] The processor-based system 1000 in Figure 10 may include a set of instructions 1030 that are executed by the processor 1002 for any necessary use according to the instructions. The instructions 1030 may be stored in main memory 1008, the processor 1002 and / or the instruction cache 1006 as an example of a non-temporary computer-readable medium 1032. The instructions 1030 may also reside entirely or at least partially in main memory 1008 and / or the processor 1002 during their execution. The instructions 1030 may be further transmitted or received through the network 1026 via the modem 1022, thereby including the computer-readable medium 1032, while the computer-readable medium 1032 is shown as a single medium in one exemplary embodiment, but the term “computer-readable medium” shall be interpreted to include a single medium or multiple mediums (e.g., centralized or distributed databases and / or associated caches and servers) that store one or more sets of instructions. The term “computer-readable medium” is also to be interpreted as including any medium capable of storing, encoding, or transporting a set of instructions for execution by a processing device, causing the processing device to perform one or more of the methodologies of the embodiments disclosed herein. Accordingly, the term “computer-readable medium” is to be interpreted as including, but not limited to, solid memory, optical media, and magnetic media.

[0041]

[0050] The embodiments disclosed herein include a variety of steps. The steps of the embodiments disclosed herein may be formed by hardware components or embodied in machine-executable instructions, which can be used to cause a general-purpose or special-purpose processor programmed with those instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0042]

[0051] Embodiments disclosed herein may be provided as computer program products or software that may include a machine-readable medium (or computer-readable medium) on which instructions are stored, and may be used to program a computer system (or other electronic device) to perform a process in accordance with the embodiments disclosed herein. The machine-readable medium includes any mechanism for storing or transmitting information in a format readable by a machine (e.g., a computer). For example, the machine-readable medium includes machine-readable storage media (e.g., ROM, random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory, etc.).

[0043]

[0052] Unless otherwise specified, as is clear from the foregoing explanation, throughout this specification, any use of terms such as “processing,” “calculation,” “determination,” and “display” refers to the operation and processes of a computer system or similar electronic computing device that manipulate and convert data and memory, represented as physical (electronic) quantities in the registers of a computer system, into other data, similarly represented as physical quantities in the memory or registers of the computer system or other such information storage, transmission, or display devices.

[0044]

[0053] Those skilled in the art will further recognize that various exemplary logic blocks, modules, circuits, and algorithms described in relation to the embodiments disclosed herein may be implemented as instructions stored in electronic hardware, memory, or another computer-readable medium, and that any such instructions may be executed by a processor, other processing device, or a combination thereof. The devices and components described herein may be used, for example, in any circuit, hardware component, integrated circuit (IC), or IC chip. The memories disclosed herein may be of any type and size and may be configured to store any type of necessary information. To illustrate this compatibility clearly, various exemplary components, blocks, modules, circuits, and steps have been generally described above in relation to their functionality. How such functionality is implemented will depend on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the functionality described herein in various ways for each specific application, but such determination of implementation form shall not be construed as causing a departure from the scope of this disclosure.

[0045]

[0054] Various exemplary logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or run using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in other options, the processor may be any conventional processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working with a DSP core, or any other such configuration).

[0046]

[0055] The embodiments disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside, for example, in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. In another option, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0047]

[0056] It should also be noted that the operational steps described in any of the exemplary embodiments of this specification are provided for the purpose of providing examples and explanations. The operations described may be performed in many different orders other than the order shown. Furthermore, the operations described in a single operational step may, in practice, be performed in many different steps. In addition, one or more operational steps described in the exemplary embodiments may be combined. It should be understood that the operational steps illustrated in the flowcharts may be subject to many different modifications, as will be readily apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of the various different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols and chips which may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0048]

[0057] The foregoing descriptions in this disclosure are provided to enable those skilled in the art to create or use this disclosure. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other modifications without departing from the spirit or scope of this disclosure. Accordingly, this disclosure is not intended to be limited to the examples and designs described herein, but rather to be given the broadest scope that is not inconsistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit (IC) chip (100), Multiple nodes (502(1) to 502(N)) within a mesh network, A first aggregate zone (504(1)) including a first node (510) and at least a second node (512(1) to 512(F)) among the plurality of nodes (502(1) to 502(N)) Includes, Each of the plurality of nodes (502(1) to 502(N)) includes a collection circuit (400) configured to receive a first indicator (414P) of power consumption associated with the node. The assembly circuit (400) of the first node (510) operates in the first mode, Receiving at least a second indicator (414P) of power consumption associated with each of the at least second nodes (512(1) to 512(F)), The first indicator (414P) and a first control signal (416C) based on at least the second indicator (414P) are provided to each of the at least second nodes (512(1) to 512(F)). It is configured to do, The combined circuit (400) of each of the first node (510) and at least the second nodes (512(1) to 512(F)) is configured to reduce power consumption at the node in response to the first control signal (416C), comprising an integrated circuit (IC) chip (100).

2. The IC chip according to claim 1, wherein the aggregate circuit of each node among the plurality of nodes includes a configuration register configured to selectively control the aggregate circuit to operate in one of the first mode and the second mode.

3. The IC chip according to claim 1 or 2, wherein each of the assembly circuits of at least the second node is configured to operate in the second mode.

4. It further includes at least a second aggregate zone which includes a third node and at least a fourth node, The assembly circuit of the third node is configured to operate in the first mode, and The IC chip according to any one of claims 1 to 3, wherein the aggregate circuit of each of the third node and at least the fourth node is configured to reduce power consumption at the node in response to a second control signal provided by the third node.

5. The mesh network further includes segments connected between two adjacent nodes among the plurality of nodes, and The IC chip according to any one of claims 1 to 4, wherein each node among the plurality of nodes is coupled to at least two segments of the mesh network.

6. The IC chip according to any one of claims 1 to 5, wherein the first node of the first aggregation zone is adjacent to each of the at least second nodes.

7. The IC chip according to any one of claims 1 to 6, wherein the at least second node includes up to four nodes from the plurality of nodes that are adjacent to the first node.

8. The IC chip according to claim 7, wherein the aggregation circuit of the first node is further configured to identify each of the nodes among the plurality of nodes, at least the second nodes adjacent to the first node.

9. The first aggregate zone further includes at least a fifth node, Each of the at least fifth nodes is adjacent to one of the at least second nodes, Each of the aggregate circuits of at least two nodes adjacent to at least one of the five nodes is, Receiving at least a third indicator of power consumption associated with each of the at least fifth nodes, To provide the first node with at least the third indicator, Providing the first control signal to each of the at least five nodes It is configured to do, The IC chip according to any one of claims 1, 2, or 4 to 8, wherein the first node is further configured to provide the first control signal based on at least the third index.

10. The aggregation circuit of each of the plurality of nodes is further configured to selectively control the aggregation circuit to operate in a third mode, Each of the at least second nodes includes the assembly circuit configured to operate in the third mode, and The IC chip according to claim 9, wherein each of the assembly circuits of at least the fifth node is configured to operate in the second mode.

11. The first aggregate zone includes the plurality of nodes on the IC chip, The mesh network extends over the first area of ​​the IC chip, and The IC chip according to any one of claims 1 to 10, wherein the first node is located in the central part of the first area.

12. The IC chip according to any one of claims 1 to 11, further comprising a voltage comparator configured to compare a power supply voltage with a threshold, wherein in each of the plurality of nodes, the first indicator of power consumption associated with the node includes an output from the voltage comparator.

13. At least one of the plurality of nodes is coupled to a corresponding processing circuit, and The IC chip according to any one of claims 1 to 12, wherein in at least one node coupled to a corresponding processing circuit, the first indicator of power consumption associated with the node includes an indicator of events related to data transmission from the corresponding processing circuit.

14. Each of the plurality of nodes further includes a plurality of router circuits configured to transmit data in the segment of the mesh network, and The IC chip according to any one of claims 1 to 13, wherein reducing power consumption in each of the plurality of nodes includes blocking data transmission from at least a subset of the plurality of router circuits in the node.

15. A method in an integrated circuit (IC) chip (100), In a first aggregate zone (504(1)) that includes a first node (510) and at least a second node (512(1) to 512(F)) among multiple nodes (502(1) to 502(N)) in a mesh network (304), In the aggregate circuit (400) of each of the plurality of nodes (502(1) to 502(N)), a first indicator (414P) of power consumption associated with the node is received, In response to the fact that the assembly circuit (400) of the first node (510) is configured to operate in the first mode, The first node (510) receives at least a second indicator (414P) of power consumption associated with each of the at least second nodes (512(1) to 512(F)), The first indicator (414P) and a first control signal (416C) based on at least the second indicator (414P) are provided to each of the at least second nodes (512(1) to 512(F)), In the respective aggregation circuits (400) of the first node (510) and at least the second nodes (512(1) to 512(F)), the power consumption at the node is reduced in response to the first control signal (416C). A method that includes this.

16. The method according to claim 15, further comprising configuring a register in each of the plurality of nodes to selectively control the set circuit to operate in one of the first mode and the second mode.

17. The method according to claim 15 or 16, further comprising configuring each of the set circuits of at least the second nodes to operate in the second mode.

18. In a second aggregate zone including a third node and at least a fourth node, The assembly circuit of the third node is configured to operate in the first mode, In the aggregate circuit of each of the third node and at least the fourth node, the power consumption of the node is reduced in response to the second control signal provided by the third node. The method according to any one of claims 15 to 17, further comprising:

19. The assembly circuit of each node among the at least second nodes is Receiving at least a third indicator of power consumption associated with at least one fifth node connected to the node, To provide the first node with at least the third indicator, Providing the first control signal to each of the at least five nodes To configure it to do so, The first node provides the first control signal based on at least the third indicator. The method according to any one of claims 15 to 18, further comprising:

20. The method according to any one of claims 15 to 19, wherein reducing power consumption in each of the plurality of nodes includes blocking data transmission from at least a subset of a plurality of router circuits configured to transmit data from the node.

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