Systems and methods for semiconductor structures

Abstract

The method includes forming a first masking layer on a substrate, wherein the first masking layer includes a first mask line and a second mask line; heating the upper surfaces of the first mask line and the second mask line, respectively, using polarized light; and forming a second masking layer on the first masking layer using a region-selective deposition process. The second masking layer is thinner on the sidewalls of the first mask line than on the upper surface of the first mask line.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the benefits of U.S. Nonprovisional Patent Application No. 18 / 314,885, filed on 10 May 2023, which is incorporated herein by reference in its entirety.

[0002] The present invention generally relates to systems and methods for semiconductor processing, and in specific embodiments, to systems and methods for region-selective deposition. [Background technology]

[0003] Dimensional reduction is one of the driving forces behind the development of integrated circuit processing. Reducing size dimensions can lead to improved cost-effectiveness and device performance. This scalability inevitably leads to complexity in process flow, particularly in patterning techniques. For example, as circuits such as transistors being manufactured become smaller, generating the critical dimension (CD) or resolution of the patterned features becomes increasingly difficult, especially in mass production. Self-aligned patterning can replace overlay-driven patterning to ensure cost-effective scaling continues even after the introduction of extreme ultraviolet (EUV) lithography. In mass manufacturing environments, patterning options that enable reduced variability, expanded scaling, and improved CD and process control are useful. However, manufacturing scaled devices at a reasonable low cost and high yield is becoming extremely difficult. Selective deposition, along with selective etching, can significantly reduce the costs associated with advanced patterning. Selective deposition of thin films, such as gap filling, selective deposition of dielectrics and metals on specific substrates, and selective hard masking are important processes in patterning at highly scaled technology nodes.

[0004] Area-selective deposition (ASD) techniques can be advantageous for photoresist mask smoothing, but ASD techniques can present new challenges. Selectivity to different regions can often be material-dependent, which can limit the applicability of ASD techniques. Various material modification techniques exist to improve selectivity, such as precursor adhesion and wettability modifications in atomic layer deposition (ALD) and atomic layer etching (ALE). However, improving deposition on top of features, either simultaneously or independently of any of these effects, can lead to an overall improvement in ASD techniques. [Overview of the project] [Means for solving the problem]

[0005] According to one embodiment, a method for a region-selective deposition process includes forming a first masking layer on a substrate, wherein the first masking layer includes a first mask line and a second mask line, and the trench between the first mask line and the second mask line has a first width; heating the upper surfaces of the first mask line and the second mask line, respectively, in a plasma processing chamber using polarized light, wherein the first width is less than half the wavelength of the polarized light; and forming a second masking layer on the first masking layer in a plasma processing chamber using a region-selective deposition process, wherein the second masking layer is thinner on the sidewalls of the first mask line than on the upper surface of the first mask line.

[0006] According to another embodiment, a method for manufacturing a semiconductor structure includes: placing a substrate in a plasma processing chamber such that a patterned first masking layer is placed on a target layer of the substrate; irradiating the patterned first masking layer with linearly polarized light such that the polarization direction of the linearly polarized light is aligned with a trench pattern through the patterned first masking layer; performing a first region-selective deposition of a second masking layer on the patterned first masking layer; patterning a target layer using the second masking layer and the patterned first masking layer as etching masks; and forming a pattern between the rest of the target layer.

[0007] In yet another embodiment, the plasma processing system includes a plasma processing chamber, a chuck configured to hold a substrate, and an ellipsometer configured to provide polarization to the substrate in the plasma processing chamber, wherein the ellipsometer includes a laser generator, a polarizing filter between the laser generator and the plasma processing chamber, a detector, and an analyzer between the detector and the plasma processing chamber.

[0008] Please understand that both the above summary and the following detailed description are illustrative and explanatory only and do not limit the claimed disclosure.

[0009] To fully understand the present invention and its advantages, refer hereto to the following description, which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1A] Diagrams of plasma processing systems according to several embodiments are shown. [Figure 1B] The diagrams show different plasma processing systems according to several embodiments. [Figure 2A]The diagrams show different plasma processing systems according to several embodiments. [Figure 2B] The diagrams show different plasma processing systems according to several embodiments. [Figure 3] This shows various cross-sectional views of intermediate steps in a semiconductor manufacturing process according to several embodiments. [Figure 4A] This shows various cross-sectional views of intermediate steps in a semiconductor manufacturing process according to several embodiments. [Figure 4B] Various top views of intermediate steps in a semiconductor manufacturing process are shown according to several embodiments. [Figure 5] This shows various cross-sectional views of intermediate steps in a semiconductor manufacturing process according to several embodiments. [Figure 6A] This shows various cross-sectional views of intermediate steps in a semiconductor manufacturing process according to several embodiments. [Figure 6B] Various top views of intermediate steps in a semiconductor manufacturing process are shown according to several embodiments. [Figure 7A] This shows various cross-sectional views of intermediate steps in a semiconductor manufacturing process according to several embodiments. [Figure 7B] Various top views of intermediate steps in a semiconductor manufacturing process are shown according to several embodiments. [Figure 7C] This shows various cross-sectional views of intermediate steps in a semiconductor manufacturing process according to several embodiments. [Figure 8A] This shows various cross-sectional views of intermediate steps in a semiconductor manufacturing process according to several embodiments. [Figure 8B] Various top views of intermediate steps in a semiconductor manufacturing process are shown according to several embodiments. [Figure 9A] This shows various cross-sectional views of intermediate steps in a semiconductor manufacturing process according to several embodiments. [Figure 9B] Various top views of intermediate steps in a semiconductor manufacturing process are shown according to several embodiments. [Figure 10A]Shows cross-sectional views of various intermediate steps of a semiconductor manufacturing process according to some embodiments. [Figure 10B] Shows top views of various intermediate steps of a semiconductor manufacturing process according to some embodiments. [Figure 11] Shows a process flow chart diagram of a method for performing area selective deposition according to some embodiments. [Figure 12] Shows a process flow chart diagram of a method for manufacturing a semiconductor structure according to some embodiments.

Mode for Carrying Out the Invention

[0011] Corresponding numbers and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly show relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of the features depicted in the figures do not necessarily indicate the end of the scope of those features.

[0012] Creation and use of various embodiments are detailed below. However, it should be recognized that the various embodiments described herein are applicable in a wide variety of specific situations. The specific embodiments discussed are merely illustrative of specific ways for creating and using the various embodiments and should not be construed in a limited sense.

[0013] According to one or more embodiments of the present disclosure, the present application relates to a method of area selective deposition (ASD) using polarization to differentially heat features. Differential heating of the upper surface of a feature by light can improve the reaction rate of an ASD precursor deposition process. Patterns having regularly spaced features (e.g., trenches or vias) can be differentially heated by linearly polarized light using an orientation and wavelength that reduces or prevents light from reaching the lower part of each feature. Patterns having irregular or isolated features (e.g., curved waveguides) can preferentially deliver light to the upper part of the feature using grazing incidence or circular polarization.

[0014] Embodiments of this disclosure will be described with reference to the accompanying drawings. An embodiment of a plasma processing system will be described using Figures 1A, 1B, 2A, and 2B. An embodiment of a semiconductor manufacturing process will be described using Figures 3, 4A, 4B, 5, 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, and 10B. An embodiment of a method for a region-selective deposition process will be described using Figure 11. An embodiment of a method for manufacturing a semiconductor structure will be described using Figure 12.

[0015] Figure 1A shows a diagram of one embodiment of a plasma processing system 100 operating using inductively coupled plasma (ICP), according to several embodiments. The plasma processing system 100 may (or may not) be arranged as shown in Figure 1A, and includes an RF source 101, a matching circuit 102, an antenna 104, a plasma processing chamber 106, a polarized laser system including a laser generator 120, a polarizing filter 122, and a beam expander 124, and optionally a dielectric plate 114. Furthermore, the plasma processing system 100 may include additional components not shown in Figure 1A.

[0016] In various embodiments, the antenna 104 is coupled to the RF source 101 through a matching circuit 102. The RF source 101 includes an RF power supply, which may include a generator circuit. The RF source 101 provides the antenna 104 with forward RF waves that are radiated toward the plasma processing chamber 106. Throughout this description, the RF source 101 may be referred to alternatively as a power supply or RF source.

[0017] The RF source 101 is coupled to a matching circuit 102, which is coupled to an antenna 104 via a transmission line, such as a coaxial cable or similar. The RF source 101 may be used to supply RF power to the antenna 104 as a continuous wave (CW). In various embodiments, the RF source 101 may be used to supply pulse-modulated RF power to the antenna 104.

[0018] Typically, a matching circuit (automatic or manual) coupled to the radiating antenna is used to minimize losses (i.e., reflected power) in response to changes in load conditions. The matching circuit 102 (also called a matching network or impedance matching network) is coupled between the RF source 101 and the antenna 104. As forward power propagates from the RF source 101 to the antenna 104, some reflected power may be reflected back due to impedance mismatch between the plasma processing chamber 106 and the RF source 101. The matching circuit 102 is used to reduce reflected power by converting the impedance seen within the matching circuit 102 (in other words, the impedance of the transmission line, the plasma processing chamber 106, and the antenna 104) to the same impedance as the RF source 101 and any intermediate transmission line. This improves the efficiency of powering the plasma processing chamber 106.

[0019] The plasma processing chamber 106 may be, for example, an intermediate frequency (MF) or high frequency (HF) plasma chamber. The plasma processing chamber 106 may be a vacuum chamber. In some embodiments, the plasma processing chamber 106 is configured to operate the plasma 115 at a first resonant frequency, which is in the range of approximately 1 MHz to approximately 27 MHz. For example, the plasma processing chamber 106 is configured to operate the plasma 115 at 1 MHz or higher, 13.56 MHz or higher, 27 MHz or higher, or similar frequencies. However, any suitable plasma processing chamber 106 may be used, and the plasma may be generated using any suitable method, such as DC plasma.

[0020] In various embodiments, the plasma processing chamber 106 includes a substrate holder 108 (e.g., a chuck). As shown, a substrate 110 (e.g., a semiconductor wafer) is placed on the substrate holder 108 for processing. Optionally, the plasma processing chamber 106 may include a bias power supply 118 coupled to the substrate holder 108. The plasma processing chamber 106 may also include one or more pump outlets 116 for removing by-products from the plasma processing chamber 106 by selective control of the internal gas flow rate. In various embodiments, the pump outlets 116 are located near the substrate holder 108 and the substrate 110 (e.g., below / around their periphery). In various embodiments, the plasma processing chamber 106 may include additional substrate holders (not shown). In various embodiments, the arrangement of the substrate holders 108 may differ from that shown in Figure 1A. Thus, the number and location of the substrate holders 108 are not limiting.

[0021] In various embodiments, the antenna 104 radiates an electromagnetic field toward the plasma processing chamber 106. In one embodiment, the antenna 104 includes an arm connected to a capacitive structure that generates azimuthal symmetry. In various embodiments, the excitation frequency of the antenna 104 is in the radio frequency range (10 to 400 MHz), but this is not limiting, and other frequency ranges may be similarly intended. For example, aspects of the present invention disclosed herein are equally applicable to applications in the microwave frequency range. Various examples of designs for the antenna 104 can be found in U.S. Patent Application No. 17,649,823, which is incorporated herein by reference in its entirety. However, any suitable antenna 104 may be used.

[0022] In various embodiments, the antenna 104 is located outside the plasma processing chamber 106 and is isolated from the plasma processing chamber 106 by a dielectric plate 114, typically made of a dielectric material. The dielectric plate 114 isolates the low-pressure environment inside the plasma processing chamber 106 from the external atmosphere. It should be understood that the antenna 104 may be positioned directly adjacent to the dielectric plate 114. In various embodiments, the antenna 104 is isolated from the plasma processing chamber 106 by air. In various embodiments, the properties of the dielectric plate 114 are selected to minimize the reflection of RF waves from the plasma processing chamber 106. In other embodiments, the antenna 104 is embedded inside the dielectric plate 114. In various embodiments, the dielectric plate 114 is in the shape of a disk. The dielectric plate 114 may be transparent or translucent to light, such as laser light generated by a laser generator 120.

[0023] The dielectric plate 114 includes a first outer surface and a second outer surface. The first outer surface faces the plasma processing chamber 106. The second outer surface faces the antenna 104. The second outer surface is located vertically above the first outer surface.

[0024] In one embodiment, the antenna 104 couples RF power from the RF source 101 to the plasma processing chamber 106 in order to process the substrate 110. Specifically, the antenna 104 emits electromagnetic waves in response to being supplied with forward RF waves from the RF source 101. The emitted electromagnetic waves enter the plasma processing chamber 106 from the atmosphere side (i.e., the antenna 104 side) of the dielectric plate 114. The emitted electromagnetic waves generate an electromagnetic field within the plasma processing chamber 106. The generated electromagnetic field ignites and maintains the plasma in the plasma generation region 112 by transferring energy to the free electrons within the plasma processing chamber 106. The generated plasma can be used for a plasma process, for example, to selectively etch or deposit material on the substrate 110. Plasma processes may include etching processes such as reactive ion etching (RIE), atomic layer etching (ALE), or similar processes, and deposition processes such as plasma-accelerated physical deposition (PVD), plasma-accelerated chemical deposition (CVD), atomic layer deposition (ALD), region-selective deposition (ASD), or similar processes.

[0025] In various embodiments, the plasma generation region 112 is located directly below the portion of the dielectric plate 114 closest to the plasma processing chamber 106. In various embodiments, the uppermost surface of the plasma generation region 112 corresponds to the plane on which the outer surface of the dielectric plate 114 faces the plasma processing chamber 106.

[0026] In Figure 1A, the antenna 104 is located outside the plasma processing chamber 106. However, in various embodiments, the antenna 104 may be located inside the plasma processing chamber 106. In such embodiments, the plasma generation region 112 is located directly below the portion of the antenna 104 closest to the plasma processing chamber 106.

[0027] The plasma processing system 100 includes a polarizing laser system for processing the substrate 110 to improve selectivity for the area-selective deposition (ASD) process performed on the substrate 110. The polarizing laser system includes a laser generator 120, a polarizing filter 122, and a beam expander 124. In various embodiments, the laser generator 120 has a polarity of, for example, 3 mJ / cm². 2 / Pulse ~1000 3mJ / cm 2 The pulsed laser has a pulse energy delivered to the wafer within the pulse range and a wavelength in the range of 170 nm to 3000 nm. The laser generator 120 may be configured to generate laser pulses having a duration of 20 femtoseconds to 100 milliseconds. The wavelength of the laser generator may be smaller than the width of the trench on the substrate 110.

[0028] The laser beam from the laser generator 120 passes through the polarizing filter 122 and the beam expander 124 to target the substrate 110 and enter the plasma processing chamber 106. The laser beam may be guided through the polarizing filter 122 and the beam expander 124 by, for example, an optical fiber or similar. In various embodiments, the polarizing filter 122 is a linear filter for generating linearly polarized laser light. In other embodiments, the polarizing filter 122 is a circular filter for generating circularly polarized light. The beam expander 124 broadens the polarized laser beam to target a large portion of the substrate 110, or a plurality of substrates 110. In some embodiments, the beam expander 124 includes one or more lenses. However, any suitable beam expander or focusing lens may be used.

[0029] In some embodiments, as shown in Figure 1B, the beam expander is or includes a decoy digital light projection system 180 (also referred to as the digital projection system) as described in U.S. Patent No. 10,147,655, which is included herein by reference in its entirety. In addition, the digital light projection system 180 may include a mirror with a built-in polarizing grating, so that the function of the polarizing filter 122 can also be performed by the digital light projection system 180, and the polarizing filter 122 outside the digital light projection system 180 can be omitted. Thus, the digital light projection system 180 projects the polarized light 130 into the plasma processing chamber 106. In some embodiments, the digital light projection system 180 illuminates specific spots on the substrate 110 as controlled by the program of the digital light projection system. For example, if more material is etched in the central portion of the substrate 110, the digital light projection system 180 may illuminate only the central portion of the substrate 110, or it may illuminate the central portion of the substrate 110 for a longer period than the edge portions of the substrate 110. However, the digital light projection system 180 can illuminate any suitable portion of the substrate 110 for any suitable length of time.

[0030] Referring again to Figure 1A, the polarization 130 from the beam expander 124 passes through the antenna 104 and the dielectric plate 114 (if present). The beam expander 124 may be directed towards the target through a gap in the antenna 104 (e.g., the space between the spiral arms of the antenna 104). The dielectric plate 114, if present, may be transparent to the polarization 130. The plasma processing chamber 106 may have one or more openings or transparent windows (also referred to as viewports) adjacent to the beam expander 124 to allow the polarization 130 to enter the plasma processing chamber 106. If multiple light sources are within the range of a window, or if multiple light sources are moved to and from a predetermined position (e.g., on a turret or linear stage), one or more additional windows in the body of the plasma processing chamber 106 may be used to enable the ASD process.

[0031] In some embodiments, the polarization 130 penetrates the plasma within the plasma generation region 112 and reaches the substrate 110. In other embodiments, the pulses of the polarization 130 are synchronized to be out of phase with the pulse power of the plasma to enable better transmission to the substrate 110 through the plasma processing chamber 106.

[0032] Polarized light 130 can differentially deposit thermal energy on the upper surface of features on the substrate 110 (e.g., mask lines with trenches between them) rather than on the sidewalls or undersides of the features on the substrate 110. In other words, polarized light 130 allows for preferential heating, for example, on the top of trenches. This heating of the upper surface of features by polarized light 130 can improve the reaction rate of the ASD precursor deposition process (see Figures 5, 6A, and 6B below). The energy of the laser generator depends on the type of material of the features, other plasma conditions, or similar factors, and is 1 mJ / cm². 2 / less than pulse to 400-600 mJ / cm 2 The pulse can be adjusted over a range up to the ablation threshold, thus enabling a wide process range. In addition, the adhesion on the top surface can be modified by the polarization 130 as a function of temperature to promote the reaction rate or molecular decomposition on the top surface. Since pulsed heating from pulsed polarization 130 can dissipate rapidly, preferential heating by polarization irradiation can be useful for thin resists (e.g., EUV resists) and short features. Preferential heating by polarization irradiation is independent of chemical or substrate material selectivity and can be used with any suitable ASD precursor or substrate material.

[0033] Prioritizing the delivery of thermal energy to the top of the features can enable the adjustment of reaction kinetics without causing desirable deposition of precursors and / or desorption of undesirable contaminants and reaction byproducts, as well as undesirable ablation of the material on the substrate 110. The improved deposition selectivity enabled by polarized irradiation can improve the existing chemoselectivity of the ASD process, for example, for high aspect ratio features. This can preferably increase the reaction rate and result in higher process throughput. In addition, improved ASD by polarized irradiation can enable smoothing of mask features (e.g., reduction of line edge roughness (LER)) or expansion of masks (e.g., adjustment of double patterning or correction of lithography) with better selectivity between the mask and the underlying layer, as well as selectivity between the mask and the underlying layer that was previously not achievable using the ASD process. In some embodiments, the improved mask formed by a larger amount of material deposited on the top surface of the mask features by polarized irradiation allows for the generation of a new hard mask. This can be done by etching the underlying hard mask layer using the improved mask as an etching mask. Improved ASD by polarized irradiation can be used to improve the pattern in the photoresist after the patterning step, to recover the mask pattern through a partial etching process (or a series of etching processes) as the mask degrades, to regenerate the mask on a partially etched structure by preferentially depositing it on the top surface of the lines, and for similar purposes, or a combination thereof. For example, a single process could include three steps of improved ASD by polarized irradiation: a first step to improve the mask pattern before etching, a second step to recover the mask pattern through partial etching, and a third step to regenerate the mask after the original mask has been used up.

[0034] In embodiments where the polarization 130 is linearly polarized, the linear polarization may have an orientation and wavelength that reduces or prevents light from reaching the bottom of regularly spaced features (e.g., trenches or vias). For example, the laser wavelength may be selected to be smaller than the trench width. This allows the linear polarization of the polarization 130 to allow thermal energy to be deposited on the upper surface of the features (e.g., on the top of mask lines adjacent to the trenches) while avoiding the bottom of the trenches which are oriented 90 degrees out of phase with the direction of the linear polarization. However, trenches oriented in phase with the direction of the linear polarization may be heated on the bottom surface of each trench. Targeting of the top of the features is independent of the depth of the features (e.g., trenches) and depends on the pitch between the features. Therefore, the polarization irradiation 130 can be used with features having a high aspect ratio (e.g., deep trenches), a low aspect ratio (e.g., shallow trenches), or a combination thereof (e.g., stepped structures or etchings).

[0035] Figure 2A shows a diagram of one embodiment of a plasma processing system 150 operating using a capacitively coupled plasma (CCP), according to several embodiments. The plasma processing system 100 may (or may not) be arranged as shown in Figure 2A, and includes an RF source 101, a matching circuit 102, a first electrode 132, a second electrode 134, a plasma processing chamber 106, and a polarized laser system including a laser generator 120, a polarizing filter 122, and a beam focuser 126. Furthermore, the plasma processing system 100 may include additional components not shown in Figure 2A.

[0036] The first electrode 132 is located in the plasma processing chamber 106 above the substrate holder 108 and is coupled to the RF source 101, for example, through a matching circuit 102. The second electrode 134 is located in the plasma processing chamber 106 below the substrate holder 108. In some embodiments, the second electrode 134 is coupled to ground. In other embodiments, the second electrode 134 is coupled to another RF source, for example, through another matching circuit. An electric field is generated between the first electrode 132 and the second electrode 134, which act as the opposite plates of a capacitor. The electric field ignites the plasma in the plasma generation region 112 and couples power to the plasma. The generated plasma can be used for a plasma process, for example, an area-selective deposition (ASD) process, or another plasma process as described above with reference to Figure 1A.

[0037] Since the first electrode 132 may be positioned on the substrate holder 108 (and on the mounted substrate 110), in some embodiments, the polarizing laser system is positioned to project polarization 140 through the side walls of the plasma processing chamber 106 rather than through the top surface of the plasma processing chamber 106. The polarizing system includes a beam focuser 126 coupled to the laser generator 120 through a polarizing filter 122, for example, by an optical fiber or similar. The beam focuser 126 may be positioned in an opening or transparent window into the plasma processing chamber 106 above the top surface of the substrate holder 108. Therefore, the polarizing system may be included in any existing plasma chamber design that fits into an opening or transparent window in a preferred location. The beam focuser 126 focuses the polarizing laser beam to target a large portion of the substrate 110, or a plurality of substrates 110. In some embodiments, the beam focuser 126 includes one or more lenses. However, any suitable beam focuser 126 may be used.

[0038] Figure 2B shows a diagram of one embodiment of a plasma processing system 152 including an ellipsometer, according to several embodiments. The plasma processing system 152 is shown similarly to the plasma processing system 150 (see Figure 2A above), which operates using capacitively coupled plasma (CCP) with polarization 140 projected through the sidewall of the plasma processing chamber 106, but the plasma processing system 152 may also operate using inductively coupled plasma (ICP) and project polarization 140 through the top surface of the plasma processing chamber 106 (see Figures 1A-1B above).

[0039] The polarized laser system includes an ellipsometer coupled with a polarizing filter 122. The ellipsometer may be used to focus on a single spot on the substrate 110. The ellipsometer includes a light source (e.g., a laser generator 120, see Figure 1A above), a polarizing filter 122, and a detector 160 having associated optical elements such as an analyzer 162 (e.g., a second polarizing filter) and an optional compensator (e.g., a quarter-wave plate) between the detector 160 and the plasma processing chamber 106. Polarized light 140 strikes a single spot on the substrate 110, from which reflected polarized light 142 is received by the detector 160 through the analyzer 162. The detector 160 measures the change in polarization of the reflected polarized light 142 from the polarization of polarized light 140, which may be used, for example, to provide feedback on the physical properties of the substrate 110. The vertical positions of the laser generator 120 and the detector 160 relative to the substrate 110 may differ from those exemplified in Figure 2A. For example, in some embodiments, the laser generator 120 and detector 160 are located above the substrate 110, so that the incident angle of polarization 140 and the reflection angle of reflected polarization 142 are within the range of 40° to 70°. However, any suitable vertical position of the laser generator 120 and detector 160 can be used.

[0040] Figures 1A, 1B, 2A, and 2B show embodiments of ICP plasma processing system 100 having a polarization system that provides polarization through the upper surface of the plasma processing chamber 106, and CCP plasma processing systems 150 and 152 having a polarization system that provides polarization through the sidewalls of the plasma processing chamber 106. In other embodiments, ICP plasma processing system 100 has a polarization system that provides polarization through the sidewalls of the plasma processing chamber 106, and CCP plasma processing systems 150 and 152 have a polarization system that provides polarization through the upper surface of the plasma processing chamber 106. For example, one embodiment of CCP plasma processing system 150 may have a beam expander 124 positioned on the upper surface of the plasma processing chamber 106 such that the first electrode 132 does not obstruct the path of polarization 140 to the substrate holder 108.

[0041] In embodiments where the polarization 140 is linearly polarized, selectivity for the upper parts of features on the substrate 110 (e.g., the tops of trenches) may be possible. The substrate holder 108 may be rotated during irradiation with the polarization 140 to increase the uniformity of heating across the substrate 110. In embodiments where the polarization 130 is circularly polarized, the light may be preferentially delivered to the upper parts of shallow, irregular, or isolated features (e.g., curved waveguides). Depending on the embodiment, unpolarized light may be used as a grazing incidence to target the upper parts of features on the substrate 110. Rotating the substrate holder 108 during polarized irradiation and using circularly polarized or unpolarized light as a grazing incidence may also be used in embodiments of the ICP plasma processing system 100 (see Figure 1A above).

[0042] Figures 3, 4A, 4B, 5, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, and 10B show various cross-sectional and top views of intermediate steps in an exemplary semiconductor manufacturing process according to several embodiments. The exemplary semiconductor manufacturing process illustrates an example of a region-selective deposition (ASD) process on an EUV-patterned metal-based resist (MBR). Prior to the ASD process, polarized irradiation is performed to increase the selectivity of the top surface of the features. However, embodiments of polarized irradiation may be used in conjunction with any suitable ASD process (including processes using non-MBR photoresists that are not patterned using EUV), and all such combinations are within the scope of embodiments of this disclosure.

[0043] Figure 3 shows a cross-sectional view of a semiconductor structure 200 according to several embodiments. The semiconductor structure 200 includes a substrate 202 and a target layer 204 on the substrate 202. Depending on the embodiment, the substrate 202 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In certain embodiments, the substrate 202 may include a silicon-germanium wafer, silicon carbide wafer, gallium arsenide wafer, gallium nitride wafer, and other compound semiconductors. In other embodiments, the substrate 202 includes heterogeneous layers such as silicon-germanium-on-silicon, gallium nitride-on-silicon, and silicon-carbon-on-silicon, and a silicon layer on a silicon or SOI substrate. In various embodiments, the substrate 202 is patterned or embedded in other components of a semiconductor device. In various embodiments, the substrate 202 may be part of a semiconductor device and may undergo several processing steps following a conventional process, for example. Thus, the substrate 202 may include layers of semiconductors useful in various microelectronics. For example, the semiconductor structure 200 may include a substrate 202 on which various device regions are formed.

[0044] In some embodiments, the target layer 204 includes a dielectric layer 206 and a hard mask layer 208. The dielectric layer 206 is formed on the substrate 202, and the hard mask layer 208 is formed on top of the dielectric layer 206. The dielectric layer 206 is a layer to be patterned using the hard mask layer 208 as an etch mask after the hard mask layer 208 has been patterned (see Figures 8A to 8B below). After patterning, a metallization pattern is formed in the trench through the dielectric layer 206 (see Figures 9A to 10B below). In some embodiments, the dielectric layer 206 may include a silicon-based dielectric material having a low dielectric constant (i.e., a low k value), such as organosilicate glass (SiCOH), high-density SiCOH, porous SiCOH, and other porous dielectric materials. Depending on the embodiment, the hard mask layer 208 may include titanium nitride, titanium, titanium oxide, tantalum, tungsten carbide, other tungsten-based compounds, ruthenium-based compounds, aluminum-based compounds, amorphous silicon, silicon nitride, silicon carbide, or similar materials. However, any suitable material may be used for the dielectric layer 206 and the hard mask layer 208.

[0045] In some embodiments, the lower layer 220 is formed on top of the target layer 204. The lower layer 220 may be a bottom antireflective coating (BARC) that can also serve as a hard mask layer for etching the portion of the layer below the lower layer 220. Examples of materials used to form the lower layer 220 include spin-on glass (SOG), silicon-containing antireflective coating (SiARC), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), organic BARC, or combinations thereof.

[0046] A first mask material containing a metal resist (MBR) is deposited on a lower layer 220, and the deposition forms an MBR layer 230. In some embodiments, the MBR contains metal oxide nanoparticles or nanoclusters, and the metal includes hafnium, zirconium, titanium, tin, zinc, indium, or aluminum. The MBR may also contain organometallic complexes, and the metal may be antimony, tin, bismuth, tellurium, platinum, palladium, cobalt, iron, or chromium.

[0047] Generally, the resist layer (e.g., MBR layer 230) and the anti-reflective film / hard mask (e.g., lower layer 220) are layers of the sacrificial lithography stack that can be patterned and used as etch masks for patterning the layers below the lithography stack contained within the device structure. Sometimes, the layer adjacent to the lower layer of the lithography stack may be referred to as the base layer. For example, the target layer 204 located adjacent to the lower layer 220 in Figure 3 may be referred to as the base layer.

[0048] Figures 4A and 4B show cross-sectional and top views of the semiconductor structure 200, continuing from Figure 3, according to several embodiments. In Figures 4A and 4B, the MBR layer 230 is patterned using an extreme ultraviolet (EUV) lithography process to form a patterned MBR layer, for example, referred to as a first masking layer 232. The first masking layer 232 exposes portions of the lower layer 220 on the underside of a pattern of trenches 236 between portions of the first masking layer 232 (also referred to as mask lines), as shown in the cross-sectional view in Figure 4A and the top view in Figure 4B. In some embodiments, the trenches 236 have a first width W1 which is half the wavelength of the developing radiation (e.g., EUV light with a wavelength of 13.5 nm), for example, in the range of 7 nm to 10 nm. To deposit thermal energy during the ASD process, the width W1 is preferably less than half the light source used for the ASD process. For example, if a 193 nm ArF laser is used to provide developing radiation, the width W1 will preferably be 96.5 nm or less.

[0049] Figure 5 shows a cross-sectional view of the semiconductor structure 200 during polarized light irradiation. After forming the first masking layer 232, the semiconductor structure 200 is transferred to a plasma chamber (e.g., plasma processing chamber 106 of the ICP plasma processing system 100 or CCP plasma processing system 150, see Figures 1A, 1B, and 2 above). Polarized light 130 is used to irradiate the semiconductor structure 200, thereby preferentially heating the upper surface of the first masking layer 232 without heating the lower surface of the trench 236. Therefore, after heating each upper surface of the first masking layer 232 with polarized light, the temperature of each upper surface of the first masking layer 232 is higher than the temperature of the lower surface of the trench 236.

[0050] In some embodiments, the polarization 130 is linearly polarized and has a wavelength greater than the first width W1 of the trench 236. However, as described above with reference to Figures 1A, 1B, and 2, any suitable linear or circular polarization 130 or 140 may be used. Differential deposition of thermal energy into the upper surface of the first masking layer 232 can improve subsequent region-selective deposition processes (see Figures 6A and 6B below) by increasing deposition on the upper surface of the first masking layer 232 relative to the sidewalls of the first masking layer 232. In embodiments where the polarization 130 is linearly polarized, the polarization direction of the polarization 130 is aligned with the pattern of the trench 236.

[0051] Figures 6A and 6B show cross-sectional and top views of the semiconductor structure 200, continuing from Figure 5, according to several embodiments. A first plasma is used to deposit a second masking layer 240 in a plasma processing chamber 106. The first plasma contains a source gas that selectively chemically reacts with the first masking layer 232 against the underlying layer 220. The semiconductor structure 200 is exposed to the first plasma to selectively deposit the second mask material on the first masking layer 232. By appropriately selecting the process parameters of the plasma deposition process, the chemoselectivity of the reaction can be utilized to carry out a region-selective deposition (ASD) process for forming the second masking layer 240. As shown in the cross-sectional view in Figure 6A, the second mask material is deposited on the first masking layer 232 (patterned MBR layer), while the thickness of the second mask material (not shown) formed on the portion of the underlying layer 220 not covered by the first masking layer 232 is negligible.

[0052] In some embodiments, forming the second masking layer 240 may involve performing an optional in-situ trim etch process to remove portions of the deposited second mask material. In embodiments where the second mask material includes a silicon-based material, the trim etch process may be plasma etch using carbon fluoride, fluorine, chlorine, or hydrogen bromide as the etchant. In embodiments where the second mask material includes an organic material, the etchant may include CO, CH4, CO2, O2, or similar. One objective for performing the trim etch process is to open up larger portions of space between resist lines that can be covered by the second mask material along the sidewalls of the lines.

[0053] In the exemplary embodiment shown in FIG. 6A, the completed second masking layer 240 has a thinner layer of the second mask material along the sidewalls of the first masking layer 232 as compared to the thickness of the second mask material on the substantially flat upper surface of the first masking layer 232. The preferential deposition of a greater proportion of the second mask material on the upper surface of the first masking layer 232 as compared to the deposition of the second mask material along the sidewalls of the first masking layer 232 can be increased by pre-heating the upper surface of the first masking layer 232 by polarization, as explained above with respect to FIG. 5. The second mask material and process used to form the second masking layer 240 can be selected such that some of the roughness along the sidewalls of the first masking layer 232 is smoothed. The combined first masking layer 232 and second masking layer form an etch mask 250 that can be used in a subsequent etch process to pattern the underlying layer 220.

[0054] In some embodiments, the ASD process is used to deposit an amorphous material containing silicon as the second mask material. The first plasma used to deposit silicon includes silane (SiF4) as the source gas, and an inert gas (e.g., argon, nitrogen, or helium) as the dilution gas. In embodiments using silane as the source gas, the first plasma may include additive gases such as H2, SiCl4, CH4, CH x F 4-x , or mixtures thereof.

[0055] In addition, the gas mixture used for the first plasma can be selected to deposit an organic polymer as the second mask material. The first plasma used to deposit the organic polymer includes carbon monoxide (CO) as the source gas, and an inert dilution gas (e.g., argon, nitrogen, or helium). In embodiments using CO as the source gas, the first plasma may include additive gases such as H2, CH4, CH x F 4-x , CO 2、 O2, or mixtures thereof.

[0056] Next, in Figures 7A and 7B, after an etch mask 250 including a first masking layer 232 and a second masking layer 240 is formed, the pattern of the etch mask 250 is transferred to the underlying layer 220, thereby performing an etch process to form a patterned underlying layer 320. In some embodiments, the underlying layer 220 may be etched in situ by a plasma etch process by generating a second plasma in the same plasma chamber where the first plasma was generated. In other embodiments, the pattern transfer etch using the etch mask 250 may be performed after the substrate has been transferred to some other processing equipment. The second plasma contains an etching agent to remove the material of the underlying layer 220. For example, if the underlying layer 220 includes spin-on glass (SOG), silicon-containing anti-reflective coating (SiARC), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), or silicon oxycarbonitride (SiOCN), the second plasma may use a fluorine-based or chlorine-based etching chemistry. If the lower layer 220 contains organic BARC, then the second plasma may contain carbon fluoride, HBr, O2, CO2, CO, or similar. Plasma etching involves exposing the substrate to the second plasma for a fixed etching duration, or terminating the etching process based on an endpoint signal. In some embodiments, plasma etching may be a substantially anisotropic etching process. As shown in Figure 7A, portions of the etching mask 250 may be removed by the second plasma by the time the etching process is completed. In this example, portions of the second masking layer 240 were lost during etching. In other examples, etching may remove the entire second masking layer 240, and possibly portions of the first masking layer 232.

[0057] The method described with reference to Figures 5 and 6A to 7B illustrates exemplary embodiments in which the polarization irradiation, ASD process, and pattern transfer etch used to form the patterned underlayer are a single-step process. In other embodiments, a method may be used in which repeated deposition and etch processes are carried out in a plasma process chamber 106 to pattern an underlayer disposed adjacent to the patterned MBR layer.

[0058] Figure 7C shows an embodiment in which the first masking layer 232 has been exhausted by the etching process and the dimensions of the patterned underlayer 320 have been reduced by the etching process. Additional polarization irradiation and ASD processes may be performed to preferentially form additional portions of the second masking layer 240 on top of the patterned underlayer 320. This can be done by preferentially depositing the mask on the upper surface and / or upper sidewall portions of lines (such as lines of the patterned underlayer 320), for example, thereby regenerating the mask on the partially etched structure (e.g., semiconductor structure 200). In other words, the semiconductor structure 200 is again irradiated with linearly polarized light through an etching process to partially pattern the target layer 204, and another ASD process is performed on the second masking layer 240.

[0059] Next, in Figures 8A and 8B, the target layer 204 is patterned to later form a pattern (e.g., a metallization pattern; see Figures 10A to 10B below). The etch mask 250 (if still present) and the patterned underlayer 320 are used as etching masks in an etching process (e.g., a wet or dry process) to penetrate the target layer 204 and enlarge the trench 236. After the etching process, the patterned target layer 304 remains beneath the etch mask 250 (if present) and the patterned underlayer 320. In some embodiments, the patterned target layer 304 includes a patterned dielectric layer 306 and a patterned hard mask layer 308 on the patterned dielectric layer 306.

[0060] In Figures 9A and 9B, material 312 is formed on the semiconductor structure 200 to fill trenches 236 between portions of the patterned target layer 304. In some embodiments, material 312 is a conductive material used to form a metallization pattern. However, material 312 may include any suitable material, such as a dielectric material, a conductive material, or a combination thereof, and may be used to form any suitable feature, such as another mask for a subsequent patterning process. In some embodiments, before forming material 312, the etch mask 250 (if present) and the patterned underlayer 320 may be removed using a suitable process, such as CMP. In embodiments where material 312 is conductive, material 312 may be copper formed using electroplating. However, any suitable conductive material (e.g., tungsten, cobalt, ruthenium, etc., or a combination thereof) and deposition method (e.g., ALD, PVD, etc.) may be used.

[0061] In Figures 10A and 10B, excess material 312 formed on the upper surface of the patterned target layer 304 is removed using a suitable process, such as CMP, to form a pattern 314. In embodiments where material 312 is a conductive material, the pattern 314 may be, for example, a metallization pattern. However, the pattern 314 may also be a mask for a subsequent patterning process. In some embodiments, the patterned hard mask layer 308 is also removed, leaving the pattern 314 between the rest of the patterned dielectric layer 306. The shape of the pattern 314 may be improved by controlling the ASD process with polarized irradiation to preferentially deposit more second masking layers 240 on the upper surface of the first masking layer 232 in a previous patterning step (see Figures 5 and 6A-6B above).

[0062] Figure 11 shows a process flowchart of Method 400 for a region-selective deposition process according to several embodiments. In step 402, a first masking layer 232 including a first mask line and a second mask line is formed on the substrate 202, as described above with reference to Figures 3, 4A, and 4B. The trench 236 between the first mask line and the second mask line has a first width W1.

[0063] In step 404, the upper surfaces of the first and second mask lines are heated in the plasma processing chamber 106 using polarized light 130, as described above with respect to Figures 1A and 5. The first width W1 is less than half the wavelength of the polarized light 130.

[0064] In step 406, a second masking layer 240 is formed on the first masking layer 232 using a region-selective deposition process, as described above with respect to Figures 6A and 6B. The second masking layer is thinner on the sidewalls of the first masking line than on the upper surface of the first masking line.

[0065] Figure 12 shows a process flowchart of method 500 for manufacturing a semiconductor structure according to several embodiments. In step 502, the substrate 110 is placed in the plasma processing chamber 106 as described above with reference to Figures 1A and 5. A patterned first masking layer 232 is placed on the target layer 204 of the substrate 110 as described above with reference to Figures 3, 4A, and 4B.

[0066] In step 504, the patterned first masking layer 232 is illuminated with linearly polarized light (e.g., polarized light 130) as described above with respect to Figures 1A and 5. The polarization direction of the linearly polarized light is aligned with the pattern of the trench 236 through the patterned first masking layer 232.

[0067] In step 506, the second masking layer 240 is selectively deposited onto the patterned first masking layer 232, as described above with respect to Figures 6A to 6B. In step 508, the target layer 204 is patterned using the second masking layer 240 and the patterned first masking layer 232 as etching masks, as described above with respect to Figures 7A to 8B. In step 510, the pattern 314 is formed between the remaining portions of the target layer 204 (e.g., the patterned dielectric layer 306), as described above with respect to Figures 9A to 10B.

[0068] Exemplary embodiments of the present invention are described below. Other embodiments can also be understood from the entirety of this specification and the claims submitted herein.

[0069] Example 1. A method for a region-selective deposition process, the method comprising: forming a first masking layer on a substrate, wherein the first masking layer includes a first mask line and a second mask line, and the trench between the first mask line and the second mask line has a first width; heating the upper surfaces of the first mask line and the second mask line, respectively, using polarized light in a plasma processing chamber, wherein the first width is less than half the wavelength of the polarized light; and forming a second masking layer on the first masking layer in a plasma processing chamber using a region-selective deposition process, wherein the second masking layer is thinner on the sidewalls of the first mask line than on the upper surface of the first mask line. Example 2. The method according to Example 1, wherein the polarization is linearly polarized. Example 3. The method according to Example 1, wherein the polarization is circularly polarized. Example 4. The method according to any one of Examples 1 to 3, wherein polarized light enters the plasma processing chamber through the upper surface of the plasma processing chamber. Example 5. The method according to any one of Examples 1 to 3, wherein polarized light enters the plasma processing chamber through the side wall of the plasma processing chamber. Example 6. The method according to any one of Examples 1 to 5, wherein polarization is projected into the plasma processing chamber by a digital light projection system. Example 7. The method according to any one of Examples 1 to 6, wherein the upper surfaces of the first and second mask lines are heated using polarized light, and then the temperature of the upper surfaces of the first and second mask lines is higher than the temperature of the lower surface of the trench. Example 8. A method for manufacturing a semiconductor structure, the method comprising: placing a substrate in a plasma processing chamber such that a patterned first masking layer is placed on a target layer of the substrate; irradiating the patterned first masking layer with linearly polarized light such that the polarization direction of the linearly polarized light is aligned with a trench pattern through the patterned first masking layer; performing a first region-selective deposition of a second masking layer on the patterned first masking layer; patterning a target layer using the second masking layer and the patterned first masking layer as etching masks; and forming a pattern between the remaining parts of the target layer. Example 9. The method of Example 8, further comprising irradiating the substrate with linearly polarized light through an etching process to partially pattern the target layer and performing a second region-selective deposition of a second masking layer. Example 10. The method according to Example 8 or 9, wherein the first region-selective deposition forms a larger proportion of material on the upper surface of the patterned first masking layer than on the sidewalls of the patterned first masking layer. Example 11. The method according to any one of Examples 8 to 10, wherein the plasma processing chamber is part of an inductively coupled plasma processing system. Example 12. The method according to any one of Examples 8 to 10, wherein the plasma processing chamber is part of a capacitively coupled plasma processing system. Example 13. The method according to any one of Examples 8 to 12, wherein linear polarization is generated by a pulsed laser generator. Example 14. A plasma processing system comprising a plasma processing chamber, a chuck configured to hold a substrate, and an ellipsometer configured to provide polarization to a substrate in the plasma processing chamber, wherein the ellipsometer includes a laser generator, a polarizing filter between the laser generator and the plasma processing chamber, a detector, and an analyzer between the detector and the plasma processing chamber. Example 15. The plasma processing system according to Example 14, wherein the ellipsometer is configured to provide polarization through the upper surface of the plasma processing chamber. Example 16. The plasma processing system according to Example 14, wherein the ellipsometer is configured to provide polarization through the side wall of the plasma processing chamber. Example 17. A plasma processing system according to any one of Examples 14 to 16, wherein the plasma processing chamber includes an antenna on a chuck, and the antenna is configured to inductively couple power to the plasma. Example 18. A plasma processing system according to any one of Examples 14 to 17, wherein the plasma processing chamber includes a first electrode above a chuck and a second electrode below a chuck, and the first electrode and the second electrode are configured to capacitively couple power to the plasma. Example 19. A plasma processing system according to any one of Examples 14 to 18, wherein the laser generator is configured to generate laser pulses. Example 20. A plasma processing system according to any one of Examples 14 to 19, wherein the polarizing filter is a linear filter.

[0070] Although the present invention has been described with reference to exemplary embodiments, this specification is not intended to be constrained. By reference to this specification, various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present invention, will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications or embodiments.

Claims

1. A method for a region-selective deposition process, wherein the method is A first masking layer is formed on a substrate, wherein the first masking layer includes a first mask line and a second mask line, and the trench between the first mask line and the second mask line has a first width. Heating the upper surfaces of the first and second mask lines in a plasma processing chamber using polarized light, wherein the width of the first mask line is less than half the wavelength of the polarized light. In the plasma processing chamber, a second masking layer is formed on the first masking layer using a region-selective deposition process, wherein the second masking layer is formed thinner on the sidewalls of the first masking line than on the upper surface of the first masking line. Methods that include...

2. The method according to claim 1, wherein the polarization is linearly polarized.

3. The method according to claim 1, wherein the polarization is circularly polarized.

4. The method according to claim 1, wherein the polarized light enters the plasma processing chamber through the upper surface of the plasma processing chamber.

5. The method according to claim 1, wherein the polarized light enters the plasma processing chamber through the side wall of the plasma processing chamber.

6. The method according to claim 1, wherein the polarization is projected into the plasma processing chamber by a digital light projection system.

7. The method according to claim 1, wherein, after heating the respective upper surfaces of the first mask line and the second mask line using polarized light, the temperature of the respective upper surfaces of the first mask line and the second mask line is higher than the temperature of the lower surface of the trench.

8. A method for manufacturing a semiconductor structure, wherein the method is The substrate is placed in a plasma processing chamber, wherein the patterned first masking layer is placed on the target layer of the substrate. The method involves irradiating the patterned first masking layer with linearly polarized light such that the polarization direction of the linearly polarized light is aligned with the trench pattern through the patterned first masking layer. Performing a first region-selective deposition of a second masking layer onto the patterned first masking layer, Patterning the target layer using the second masking layer and the patterned first masking layer as etching masks, To form a pattern between the remaining parts of the target layer, Methods that include...

9. The method according to claim 8, further comprising, in part, irradiating the substrate with linearly polarized light through an etching process for patterning the target layer, thereby carrying out a second region-selective deposition of the second masking layer.

10. The method according to claim 8, wherein the first region-selective deposition forms a larger proportion of material on the upper surface of the patterned first masking layer than on the sidewalls of the patterned first masking layer.

11. The method according to claim 8, wherein the plasma processing chamber is part of an inductively coupled plasma processing system.

12. The method according to claim 8, wherein the plasma processing chamber is part of a capacitively coupled plasma processing system.

13. The method according to claim 8, wherein the linear polarization is generated by a pulsed laser generator.

14. A plasma processing system, Plasma processing chamber and A chuck configured to hold a circuit board, An ellipsometer, wherein the ellipsometer is configured to provide polarization to the substrate in the plasma processing chamber, and the ellipsometer includes a laser generator, a polarizing filter between the laser generator and the plasma processing chamber, a detector, and an analyzer between the detector and the plasma processing chamber. A plasma processing system equipped with the following features.

15. The plasma processing system according to claim 14, wherein the ellipsometer is configured to provide polarization through the upper surface of the plasma processing chamber.

16. The plasma processing system according to claim 14, wherein the ellipsometer is configured to provide polarization through the side wall of the plasma processing chamber.

17. The plasma processing system according to claim 14, wherein the plasma processing chamber includes an antenna on the chuck, and the antenna is configured to inductively couple power to the plasma.

18. The plasma processing system according to claim 14, wherein the plasma processing chamber includes a first electrode above the chuck and a second electrode below the chuck, and the first electrode and the second electrode are configured to capacitively couple power to the plasma.

19. The plasma processing system according to claim 14, wherein the laser generator is configured to generate laser pulses.

20. The plasma processing system according to claim 14, wherein the polarizing filter is a linear filter.

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