Methods for controlling the selectivity of spin-on self-assembled monolayers (SAMs)

Abstract

Various embodiments of the method are provided to control the formation of self-assembled monolayers (SAMs) used in region-selective deposition (ASD) processes and thus prevent defects in the ASD process. In the disclosed embodiments, the SAM structure is formed by a spin-on process comprising: (a) a spin-coating step of coating the surface of a semiconductor substrate with a liquid solution containing SAM-forming molecules, wherein the semiconductor substrate has an exposed target material and a non-target material on the substrate surface; and (b) an annealing step of heat-treating the semiconductor substrate to chemically bond the SAM-forming molecules to the exposed non-target material on the substrate surface. By controlling and / or changing process parameters utilized during the annealing step, the embodiments disclosed herein improve the selectivity of the SAM structure to the non-target material and subsequently prevent defects from occurring when the film is deposited on the target material.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims priority and the benefit of the filing date of U.S. Non - Provisional Patent Application No. 18 / 223,881, filed on July 19, 2023, which is hereby incorporated by reference in its entirety.

Background Art

[0002] This disclosure relates to processes for substrates. Specifically, this disclosure provides improved processes and methods for controlling the selectivity of self - assembled monolayers (SAMs) formed on substrates.

[0003] As geometries in substrate processes continue to shrink, the technical challenges of forming structures on substrates are increasing. Lithography technology is particularly problematic for the shrinking of geometries. One of the conventional substrate lithography methods utilizes a photolithography process that includes a photoresist coating step, an exposure step, and a photoresist development step. The materials and processes utilized in these steps can all affect critical dimension targeting, line roughness, and uniformity on the substrate.

[0004] As the feature sizes of integrated circuit (IC) devices continue to shrink down to the angstrom level, conventional lithography either reaches its resolution limit or becomes too costly for large - scale use. One strategy is to use chemically - induced self - aligned selective bottom - up patterning to mitigate the reliance on lithography. Central to this strategy is area - selective processing (ASP), which focuses on the idea of using the surface chemistry of an exposed material layer to drive the selective processing of such a layer. Area - selective processing techniques can be used to selectively deposit materials onto, and / or remove materials from, desired regions of a patterned substrate, thereby avoiding the use of photolithography for patterning.

[0005] Area-selective deposition (ASD) is an example of a bottom-up area-selective process that provides uniform deposition of material only in desired areas of a patterned substrate. Unlike conventional deposition techniques designed to achieve uniform deposition over a wide area, ASD allows for the selective deposition of material on target areas (or "growth surfaces") while avoiding deposition on non-target areas (or "non-growth surfaces"). A variety of materials can be selectively deposited on target materials using ASD. For example, ASD techniques can be used to selectively deposit dielectric-on-dielectric (DoD), dielectric-on-metal (DoM), metal-on-dielectric (MoD), and metal-on-metal (MoM).

[0006] Region-selective deposition can often be achieved using a variety of deposition techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and molecular layer deposition (MLD), which utilize surface modification and vapor phase deposition to deposit materials onto a target region. Surface modification typically aims to promote the adsorption of precursor molecules on the growth surface and / or suppress the adsorption of precursor molecules on the non-growth surface. For example, currently available DoD techniques can use molecular inhibitors, such as self-assembled monolayers (SAMs), to suppress the deposition of dielectric materials on non-growth surfaces, such as metal or metal oxide surfaces.

[0007] Self-assembled monolayers (SAMs) are organic molecules that form regular surface monolayer coatings on a material, altering its chemical and physical properties. Some SAM-forming molecules (e.g., those with thiol, amine, or carboxylic acid head groups) selectively assemble on metals compared to dielectric materials. For this reason, SAMs are used in various DoD applications to suppress dielectric growth on metal surfaces. For example, SAMs are used to passivate metal (e.g., copper) lines when fabricating fully self-aligned vias (FSAVs) at the back-end of line (BEOL). The passivation provided by SAMs enables selective dielectric growth on interlayer dielectric (ILD) patterns by suppressing dielectric growth on the passivated metal lines. [Overview of the project] [Means for solving the problem]

[0008] This disclosure provides various embodiments of processes and methods for improving the selectivity of self-assembled monolayers (SAMs) to underlying layers. More specifically, this disclosure provides improved ASD processes and related methods for reducing or eliminating defects in ASD processes by improving the selectivity of SAMs used in ASD processes. In one exemplary embodiment, edge exclusion defects in dielectric-on-dielectric (DoD) processes can be prevented by using the processes and methods disclosed herein to control the formation of SAMs selectively deposited on conductive surfaces of semiconductor substrates.

[0009] The Disclosure describes a SAM structure formed using a spin-on process, which generally comprises: (a) a spin-coating step for coating the surface of a semiconductor substrate with a liquid solution containing SAM-forming molecules, wherein the semiconductor substrate has exposed target material and non-target material on the surface of the semiconductor substrate; (b) an annealing step for heat-treating the semiconductor substrate to chemically bond the SAM-forming molecules to the exposed non-target material on the substrate surface; and (c) a rinsing step for washing and removing excess solution from the substrate surface after bonding has occurred. In at least one embodiment of the Disclosure, the selectivity of the SAM structure is improved by controlling and / or changing one or more process parameters used during the annealing step. For example, the selectivity of the SAM structure is improved by controlling and / or changing the gas, gas flow rate, chamber pressure, annealing temperature and / or annealing time used during the annealing step.

[0010] By controlling and / or changing process parameters used during the annealing step, the processes and methods disclosed herein provide a SAM structure that completely covers the exposed surface of the non-target material, while preventing the SAM structure from extending beyond the boundary of the non-target material and covering a portion of the target material. In some embodiments, the processes and methods disclosed herein may be used to control the formation of SAM structures used in DoD processes. By controlling SAM formation and preventing the SAM from extending beyond the boundary of the exposed metal surface, the methods disclosed herein can reduce or eliminate defects (such as edge exclusion defects) that occur in the DoD process when the dielectric film is subsequently deposited on the exposed dielectric surface of the metal / dielectric pattern. However, it will be recognized that the techniques disclosed herein are not strictly limited to DoD applications and may be used in other ASD processes that utilize SAM to suppress growth on non-target materials.

[0011] According to one embodiment, a method for controlling the formation of a self-assembled monolayer (SAM) structure used in a region-selective deposition (ASD) process is provided herein. In some embodiments, the method may be initiated by providing a substrate in a process chamber, the substrate having an exposed target material and a non-target material on the surface of the substrate. The method may then include (a) dispensing a liquid solution onto the surface of the substrate while rotating the substrate, thereby coating the surface of the substrate with the liquid solution, the liquid solution containing SAM-forming molecules, and (b) heat-treating the substrate to chemically bond the SAM-forming molecules to the exposed surface of the non-target material, thereby forming a SAM structure on the exposed surface of the non-target material.

[0012] The method may further include controlling one or more process parameters used during the heat treatment to ensure that the SAM structure completely covers the exposed surface of the non-target material and that the SAM structure does not extend beyond the boundary of the non-target material to cover a portion of the target material. In some embodiments, the method may further include forming the SAM structure on the exposed surface of the non-target material and then selectively depositing the film on the exposed surface of the target material. By controlling one or more process parameters during the heat treatment, the method reduces defects in the ASD process by ensuring that the film completely covers the exposed surface of the target material.

[0013] According to another embodiment, a method for reducing edge exclusion defects in a dielectric-on-dielectric (DoD) process is provided herein. In some embodiments, the method may be initiated by providing a substrate in a process chamber, the substrate having a metal layer and a dielectric layer exposed on the surface of the substrate. The method may then include (a) dispensing a liquid solution onto the surface of the substrate while rotating the substrate, thereby coating the surface of the substrate with the liquid solution, the liquid solution containing SAM-forming molecules, and (b) heat-treating the substrate to chemically bond the SAM-forming molecules to the exposed surface of the metal layer, thereby selectively depositing a self-assembled monolayer (SAM) structure on the exposed surface of the metal layer.

[0014] The method may further include controlling one or more process parameters used during the heat treatment to ensure that the SAM structure completely covers the exposed surface of the metal layer and prevents the SAM structure from covering a portion of the dielectric layer beyond the boundary of the metal layer, and selectively depositing a dielectric film on the exposed surface of the dielectric layer after forming the SAM structure on the exposed surface of the metal layer. By controlling one or more process parameters during the heat treatment, the method reduces edge exclusion defects in the DoD process by ensuring that the dielectric film completely covers the exposed surface of the dielectric layer.

[0015] The methods disclosed herein allow for the control of a wide variety of process parameters during the heat treatment (or annealing step) used to form the SAM structure. For example, one or more process parameters may include one or more of the following: gas, gas flow rate, pressure in the process chamber, temperature and time used during the heat treatment (or annealing step).

[0016] In some embodiments, one or more process parameters may be controlled by selecting the gas used during the heat treatment, the gas flow rate, the pressure in the process chamber, the temperature, and / or the time, based on experimental results. For example, one or more process parameters may be controlled by selecting (a) a gas from the group of gases including nitrogen (N2), ammonia (NH3), helium (He), and argon (Ar), (b) a gas flow rate from a range including about 4 liters / min (L / min) to about 7 L / min, (c) a temperature from a range including about 130°C to about 180°C, and / or (d) a time from a range of constant time including about 60 seconds to about 180 seconds.

[0017] In other embodiments, one or more process parameters may be controlled by changing one or more of the gas, gas flow rate, pressure in the process chamber, temperature, and time during the heat treatment, based on a predetermined recipe or based on feedback control. Such changes may occur during the annealing step.

[0018] Various embodiments of methods for controlling the formation of SAM structures used in the ASD process and, therefore, reducing defects in the ASD process, are provided herein. Naturally, the order in which the various steps described herein are considered is presented for clarity. In general, these steps can be performed in any preferred order. Furthermore, while each of the various features, techniques, configurations, etc., described herein may be considered in different parts of this disclosure, each concept is intended to be performed independently or in combination with others. Therefore, the present invention can be embodied and considered in many different ways.

[0019] It should be noted that this summary section does not specify all embodiments and / or stepwise novel aspects of the invention as described in this disclosure or claims. Instead, this summary provides only preliminary considerations of various embodiments and aspects corresponding to novelty over the prior art. For further details and / or anticipated aspects of the invention and embodiments, readers should refer to the detailed description sections of this disclosure and the corresponding drawings, as further discussed below.

[0020] The present invention and its advantages can be better understood by referring to the following description, which is to be interpreted in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features. However, it should be noted that the accompanying drawings only illustrate exemplary embodiments of the disclosed concept and should not be considered limiting in scope, as the disclosed concept may also encompass other equally valid embodiments. [Brief explanation of the drawing]

[0021] [Figure 1A-1C] This paper demonstrates an exemplary dielectric-on-dielectric (DoD) process that uses self-assembled monolayers (SAMs) to suppress the growth of dielectrics on a metal surface. [Figure 2A-2C] This document describes an improved dielectric-on-dielectric (DoD) process that utilizes the techniques described herein to selectively deposit a SAM structure on a metal surface with improved selectivity for the metal surface. [Figure 3] Figure 2B shows one embodiment of a spin process that may be used to form the SAM structure. [Figure 4A-4D] Figures 2 and 3 show scanning electron microscope (SEM) images of semiconductor substrates after the DoD process, illustrating the different results obtained by varying the gas flow rate during the annealing step shown in Figure 3. [Figure 5A-5H]SEM images of semiconductor substrates after the DoD process shown in FIGS. 2 to 3, showing different results obtained by changing the temperature used during the annealing step shown in FIG. 3. [Figure 6A-6C] SEM images of the semiconductor substrate 200 after performing the DoD process shown in FIGS. 2 to 3, showing different results obtained by changing the annealing time used during the annealing step shown in FIG. 3. [Figure 7] Block diagram of an exemplary processing system that can be used to perform the spin-on process shown in FIG. 3. [Figure 8] Flowchart showing one embodiment of a method for controlling the formation of a SAM structure used in an area-selective deposition (ASD) process according to the present disclosure. [Figure 9] Flowchart showing another embodiment of a method for reducing edge exclusion defects in a dielectric-on-dielectric (DoD) process according to the present disclosure.

Mode for Carrying Out the Invention

[0022] Selective dielectric-on-dielectric growth is one technique that can be used to ensure the reliability when manufacturing fully self-aligned vias (FSAV) in the back end of line (BEOL). Currently available dielectric-on-dielectric (DoD) processes use self-assembled monolayers (SAMs) to passivate the metal surfaces (e.g., copper lines) within metal / dielectric patterns and enable selective dielectric growth on the interlayer dielectric (ILD). In conventional DoD processes, a SAM structure is formed on the metal surface of the metal / dielectric pattern, and by suppressing dielectric growth on the metal surface, area-selective DoD is enabled. DoD is typically performed using deposition methods such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). In such methods, the SAM structure prevents the dielectric precursor used during the deposition process from reaching the metal surface, thereby suppressing dielectric growth on the metal surface.

[0023] Figures 1A and 1C illustrate an exemplary DoD process that utilizes SAM to suppress dielectric growth on a metal surface. As shown in Figure 1A, the substrate 100 includes metal features 105 (e.g., metal lines) formed within a dielectric pattern 110. The SAM 115 is formed on the metal features 105 in Figure 1A, and when a deposition process is subsequently performed to selectively deposit dielectric material 120 onto the dielectric pattern 110 in Figure 1B, dielectric growth on the exposed surface of the metal features 105 is suppressed.

[0024] A variety of deposition techniques can be used to selectively deposit SAM 115 onto the metal feature 105 shown in Figure 1A. For example, SAM 115 can be selectively deposited onto the metal feature 105 using a variety of wet and dry deposition processes, including, but not limited to, immersion, dip coating, spin coating, and chemical vapor deposition (CVD). Unfortunately, current processes used to form self-assembled monolayers (such as SAM 115 shown in Figure 1A) often do not provide sufficient selectivity between the SAM and the underlying layer. For example, as shown in Figure 1A, SAM 115 deposited on the metal feature 105 extends beyond the edges of the metal feature 105 and covers at least a portion of the surface of the dielectric pattern 110. If dielectric material 120 is subsequently deposited on the dielectric pattern 110 in Figure 1B, the SAM 115 inhibits the growth of dielectric material 120 on the edges of the dielectric pattern 110, resulting in edge exclusion defects 125, as shown in Figure 1C.

[0025] This disclosure provides various embodiments of processes and methods for improving the selectivity of self-assembled monolayers (SAMs) to underlying layers in order to overcome the problems shown in Figures 1A to 1C. More specifically, this disclosure provides improved ASD processes and related methods for reducing or eliminating defects in ASD processes by improving the selectivity of SAMs used in ASD processes. In one exemplary embodiment, edge exclusion defects in dielectric-on-dielectric (DoD) processes can be prevented by controlling the formation of SAMs selectively deposited on conductive surfaces of semiconductor substrates using the processes and methods disclosed herein.

[0026] The Disclosure describes a SAM structure formed using a spin-on process, which generally comprises: (a) a spin-coating step for coating the surface of a semiconductor substrate with a liquid solution containing SAM-forming molecules, wherein the semiconductor substrate has exposed target material and non-target material on the surface of the semiconductor substrate; (b) an annealing step for heat-treating the semiconductor substrate to chemically bond the SAM-forming molecules to the exposed non-target material on the substrate surface; and (c) a rinsing step for washing and removing excess solution from the substrate surface after bonding has occurred. In at least one embodiment of the Disclosure, the selectivity of the SAM structure is improved by controlling and / or changing one or more process parameters used during the annealing step. For example, the selectivity of the SAM structure is improved by controlling and / or changing the gas, gas flow rate, chamber pressure, annealing temperature and / or annealing time used during the annealing step.

[0027] By controlling and / or changing process parameters used during the annealing step, the processes and methods disclosed herein provide a SAM structure that completely covers the exposed surface of the non-target material, while preventing the SAM structure from extending beyond the boundary of the non-target material and covering a portion of the target material. In some embodiments, the processes and methods disclosed herein may be used to control the formation of SAM structures used in DoD processes. By controlling SAM formation and preventing the SAM from extending beyond the boundary of the exposed metal surface, the methods disclosed herein can reduce or eliminate defects (such as edge exclusion defects) that may otherwise occur in the DoD process when the dielectric film is subsequently deposited on the exposed dielectric surface of the metal / dielectric pattern. However, it should be recognized that the techniques disclosed herein are not strictly limited to DoD applications and may be used in other ASD processes that utilize SAM to suppress growth on non-target materials.

[0028] Returning to the drawings, Figures 2A–2C illustrate one embodiment of a region-selective deposition (ASD) process that utilizes the techniques disclosed herein to selectively deposit a self-assembled monolayer (SAM) on a non-target material with improved selectivity to the non-target material. More specifically, Figures 2A–2C illustrate an improved dielectric-on-dielectric (DoD) process that utilizes the techniques disclosed herein to selectively deposit a SAM structure on the surface of a non-target material (e.g., a metal or metal oxide material) while avoiding the deposition of the SAM on a target material, such as a dielectric material provided on the same substrate. In some embodiments, the DoD processes shown in Figures 2A–2C can improve the selectivity of the deposited SAM by controlling or changing one or more process parameters used during the annealing step used to form the SAM structure, as shown and described with reference to Figure 3. It should be recognized that the processes shown in Figures 2A–2C are just one application of the techniques described herein, although this is described in relation to DoD applications.

[0029] Figures 2A to 2C illustrate an improved ASD process that may be used to selectively deposit a dielectric film on a dielectric material according to this disclosure. In the embodiment shown in Figure 2A, a semiconductor substrate 200 is provided with a metal / dielectric pattern having a metal layer 205, a metal liner layer 207, and a dielectric layer 210 exposed on the surface of the semiconductor substrate 200. The metal liner layer 207 is provided between the metal layer 205 and the dielectric layer 210 as a protective barrier layer to prevent the metal from diffusing into the dielectric layer 210.

[0030] The metal layer 205 may include, but is not limited to, a variety of metal-containing materials such as copper (Cu), ruthenium (Ru), cobalt (Co), tungsten (W), molybdenum (Mo), and their oxides. The metal liner layer 207 may include, but is not limited to, a wide variety of metal-containing materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), cobalt (Co), ruthenium (Ru), and ruthenium-tantalum (RuTa). The metal layer 205 and the metal liner layer 207 may also include other conductive materials commonly used in integrated circuit (IC) manufacturing, as is known in the art. Depending on the conductive material used, the exposed surfaces of the metal layer 205 and the metal liner layer 207 may be terminated with various metal, metal oxide, or metal nitride surface groups.

[0031] The dielectric layer 210 may include a variety of dielectric materials, but is not limited to oxides, silicon oxides, and other low-k and high-k dielectric materials commonly used in IC manufacturing. In one exemplary embodiment, the dielectric layer 210 may be a low-k dielectric, for example, a low-k dielectric silicon oxycarbide (SiCOH) dielectric layer. Depending on the dielectric material used, the surface of the dielectric layer 210 may be terminated with -O, -H, or -OH surface groups.

[0032] In the embodiment shown in Figure 2B, a SAM structure 215 is formed on the exposed surfaces of the metal layer 205 and the metal liner layer 207 to modify the chemical and / or physical surface properties of the metal layers and form a SAM passivated metal, metal oxide, or metal nitride. As is known in the art, SAM-forming molecules consist of a head group, a tail group (or polymer chain), and functional end groups. Self-assembled monolayers (or SAMs) are created by chemiadsorption of head groups onto a non-target surface (e.g., a metal surface in a DoD application) by either gas-phase or liquid-phase deposition, followed by the slow organization of tail groups. Head groups have a high chemical affinity for the non-target surface, so they assemble together on the non-target surface, while tail groups assemble away from the non-target surface. Regions of densely packed SAM-forming molecules nucleate and grow until the non-target surface is covered with a single self-assembled monolayer, such as the SAM structure 215. Common head groups include thiols, amines, carboxylic acids, silanes, and phosphates. As described above, SAM-forming molecules having thiol, amine, and carboxylic acid head groups are known to have high chemical affinity to metals and can therefore be used to selectively assemble on the exposed surfaces of the metal layer 205 and the metal liner layer 207 to form the SAM structure 215 shown in Figure 2B. In one exemplary embodiment, a SAM structure 215 having a thiol, silane, phosphate, amine, or carboxylic acid head group and a hydrocarbon tail group can be formed on the exposed surfaces of the metal layer 205 and the metal liner layer 207 by spin-on deposition. However, the SAM structure 215 may also include other head groups and / or tail groups, as is known in the art.

[0033] Figure 3 shows an exemplary spin-on process 300 that may be used to form the SAM structure 215 shown in Figure 2B. In some embodiments, the spin-on process 300 may be initiated by pre-cleaning the surface of the semiconductor substrate 200 to remove surface contaminants (in step 310). The surface of the semiconductor substrate 200 may be pre-cleaned in step 310 by applying a cleaning solution to the surface of the semiconductor substrate 200 while the substrate is rotating or stationary. In one example, the cleaning solution may include citric acid and deionized water. Other cleaning solutions may also be used in step 310 to clean the substrate surface.

[0034] After pre-cleaning, a liquid solution containing SAM-forming molecules (i.e., SAM-forming solution) is applied to the surface of the semiconductor substrate 200 in the spin-coating step (in step 320). During the spin-coating step, the substrate may be rotated at a rotational speed (e.g., 500-3000 revolutions per minute, RPM) to ensure that the SAM-forming solution uniformly coats the substrate surface. In step 320, the SAM-forming molecules in the SAM-forming solution applied to the substrate surface chemically bond to surface groups on the non-target surface of the semiconductor substrate 200. The SAM-forming molecules nucleate and grow to cover the non-target surface and form a self-assembled monolayer. The SAM-forming molecules are selected to bond to the non-target surface. In the exemplary embodiment shown in Figure 2B, the SAM-forming solution applied in step 320 contains SAM-forming molecules having thiol, silane, phosphate, amine, or carboxylic acid head groups, which selectively assemble on the exposed surfaces of the metal layer 205 and the metal liner layer 207 to selectively deposit the SAM structure 215 thereon.

[0035] A variety of SAM-forming solutions can be used during the spin-coating step. For example, a SAM-forming solution containing a SAM precursor dissolved in an organic solvent can be used to form the SAM structure 215 shown in Figure 2B. The SAM precursor may include various thiols, silanes, phosphates, carboxylic acids, amines, etc. Examples of suitable organic solvents, but not limited to, include propylene glycol methyl ether acetate (PGMEA), propylene glycol methyl ether (PGME), methyl isobutyl ketone (MIBK), methyl isobutyl carbinol (MIBC), propanol, ethanol, ethyl lactate, and other alcohols. In some embodiments, as shown in Figure 2C and described in more detail below, a SAM precursor dissolved in PGMEA may be used during the spin-coating step to form a SAM structure 215 having thiol, silane, phosphate, carboxylic acid, or amine head groups that selectively adhere to the exposed surfaces of the metal layer 205 and the metal liner layer 207, and hydrocarbon polymer tail groups that provide a hydrophobic barrier to the dielectric precursor or co-reactants used to selectively deposit the dielectric film 220 on the exposed surfaces of the dielectric layer 210. However, the SAM structure 215 shown in Figure 2B is not strictly limited to hydrocarbon polymer tail groups and may include other polymers that can be deposited by spin-on and provide a barrier to the dielectric film 220.

[0036] After applying the SAM-forming solution to the surface of the semiconductor substrate 200 (in step 320), an annealing step is performed (in step 330) to supply the activation energy necessary to chemically bond the functional head groups of the SAM-forming molecules to the surface groups on the non-target surface, thereby forming the SAM structure 215 on the non-target surface. After the annealing step, a rinsing step is performed (in step 340) to wash off any excess SAM-forming solution from the substrate surface. In one embodiment, during the rinsing step (in step 340), propylene glycol methyl ether acetate (PGMEA) may be applied to the surface of the semiconductor substrate 200. The rinsing solution (such as PGMEA) removes SAM-forming molecules that are not bonded to the non-target surface without disturbing the SAM structure 215 formed on the non-target surface. Other rinsing solutions may also be used in step 340.

[0037] The annealing step may be performed in the same processing chamber used to perform the pre-cleaning, spin-coating, and rinsing steps (in step 330), or in a different processing chamber. During the annealing step, one or more process parameters may be controlled and / or varied to ensure that the SAM structure 215 extends beyond the boundaries of the non-target material (e.g., the metal layer 205 and the metal liner layer 207) and completely covers the exposed surface of the non-target material without covering any portion of the target material (e.g., the dielectric layer 210). For example, the gas used during the annealing step, gas flow rate, chamber pressure, annealing temperature, and / or annealing time may be individually controlled and / or varied during the annealing step to improve the selectivity of the SAM structure for the non-target material.

[0038] During the annealing step (in step 330), a variety of gases, gas flow rates, chamber pressures, annealing temperatures, and / or annealing times may be used. In some embodiments, nitrogen (N2), ammonia (NH3), or other gases (e.g., helium (He) or argon (Ar), etc.) may be supplied to the processing chamber at a gas flow rate of about 4 to 7 liters / minute (L / min) during the annealing step. During the annealing step, annealing temperatures between about 130°C and about 180°C and annealing times between about 60 seconds and about 180 seconds may also be used.

[0039] After forming the SAM structure 215 as shown and described in Figures 2B and 3, in the embodiment shown in Figure 2C, a dielectric film 220 is selectively deposited on the exposed surface of the dielectric layer 210. The dielectric film 220 may include a variety of dielectric materials, but are not limited to oxides, silicon oxides, and other low-k and high-k dielectric materials commonly used in IC manufacturing. In one exemplary embodiment, the dielectric film 220 may be a high-k dielectric such as aluminum oxide (Al2O3), but is not limited to these. While a variety of deposition processes can be used to selectively deposit the dielectric film 220 on the dielectric layer 210, the dielectric film 220 is preferably deposited by CVD or ALD using a dielectric precursor. The SAM structure 215 formed on the metal layer 205 and the metal liner layer 207 suppresses dielectric growth on the metal surface by preventing the dielectric precursor from reaching the metal surface. In some embodiments, the hydrophobicity of the SAM tail may also repel water, a co-reactant commonly used in oxide ALD recipes.

[0040] The ASD process shown in Figures 2-3 and described above offers various advantages. Unlike the DoD process shown in Figures 1A-1C, for example, the DoD process shown in Figures 2-3 provides a SAM structure 215 with improved selectivity for exposed metal surfaces on the semiconductor substrate. As described above, the SAM structure 215 formed in Figures 2B and 3 extends beyond the boundary of the metal surface and completely covers the exposed metal surface (e.g., the exposed surface of the metal layer 205 and the metal liner layer 207) without eroding and covering a portion of the exposed dielectric surface (e.g., the exposed surface of the dielectric layer 210). By improving the selectivity of the SAM structure 215 for exposed metal surfaces in the ASD process shown in Figures 2-3, the edge exclusion defect shown in Figure 1C is eliminated by providing a dielectric film 220 that completely covers the underlying dielectric layer 210, as shown in Figure 2C.

[0041] As described above, the SAM selectivity is improved in this disclosure by controlling and / or changing one or more process parameters used during the annealing step shown in Figure 3. Experiments were conducted to determine the optimal process parameters that can be used during the annealing step shown in Figure 3 and to improve SAM selectivity for the exposed metal surface on the substrate. Figures 4A to 4D, 5A to 5H, and 6A to 6C show the experimental results obtained by varying the gas flow rate, annealing temperature, and annealing time, respectively.

[0042] Figures 4A to 4D are scanning electron microscope (SEM) images of the semiconductor substrate 200 after the DoD process shown in Figures 2 to 3, and show different results obtained by changing the gas flow rate during the annealing step shown in Figure 3. In the embodiments shown in Figures 4A to 4D, nitrogen (N2) gas is supplied to the processing chamber at a variable gas flow rate during the annealing step. Specifically, N2 gas is supplied at a gas flow rate of 1 L / min in Figure 4A, 4 L / min in Figure 4B, 7 L / min in Figure 4C, and 9.5 L / min in Figure 4D. The experimental results shown in Figures 4A to 4C show that increasing the gas flow rate (for example, up to about 7 L / min) reduces edge exclusion defects in the dielectric film 220 without reducing selectivity. On the other hand, the experimental results shown in Figure 4D show that increasing the N2 gas flow rate to 9.5 L / min reduces selectivity, making it possible to deposit the dielectric film 220 on a portion of the exposed metal surface. Therefore, in some embodiments, edge exclusion defects in the DoD process can be reduced or eliminated by using an N2 gas flow rate of about 4–7 L / min during the annealing step shown in Figure 3. Similar results can be obtained by increasing the pressure in the processing chamber, although this is not explicitly shown or described herein.

[0043] Figures 5A to 5H are SEM images of the semiconductor substrate 200 after the DoD process shown in Figures 2 to 3, illustrating different results obtained by varying the temperature used during the annealing step. In the embodiments shown in Figures 5A to 5H, nitrogen (N2) gas is supplied to the processing chamber at a predetermined gas flow rate (e.g., 1 L / min) for 180 seconds, and the temperature used during the annealing step is varied. As shown, the temperatures used during the annealing step are 180°C in Figure 5A, 150°C in Figure 5B, 145°C in Figure 5C, 140°C in Figure 5D, 135°C in Figure 5E, 130°C in Figure 5F, 125°C in Figure 5G, and 120°C in Figure 5H. The experimental results shown in Figures 5A to 5F demonstrate that lowering the annealing temperature (e.g., to approximately 130°C) reduces edge exclusion defects in the dielectric film 220 without reducing selectivity. On the other hand, the experimental results shown in Figures 5G to 5H indicate that lowering the annealing temperature to below 130°C reduces selectivity, making it possible to deposit the dielectric film 220 on a portion of the exposed metal surface. Therefore, in some embodiments, edge exclusion defects in the DoD process can be reduced or eliminated by utilizing an annealing temperature of approximately 130°C to 145°C and an annealing time of 180 seconds during the annealing step.

[0044] Figures 6A to 6H are SEM images of the semiconductor substrate 200 after the DoD process shown in Figures 2 to 3, illustrating different results obtained by varying the annealing time used during the annealing step. In the embodiments shown in Figures 6A to 6C, nitrogen (N2) gas is supplied to the processing chamber at a predetermined gas flow rate (e.g., 7 L / min) during the annealing step. The annealing temperature is kept constant (e.g., 140°C), while the annealing time is varied. As shown, the semiconductor substrate 200 is annealed (or baked) for 180 seconds in Figure 6A, 120 seconds in Figure 6B, and 60 seconds in Figure 6C. As shown in Figures 6A to 6C, reducing the annealing time from 180 seconds to 60 seconds reduces edge exclusion defects in the dielectric film 220 without reducing selectivity. Therefore, in some embodiments, edge exclusion defects in the DoD process can be reduced or eliminated by using an annealing temperature of approximately 140°C and an annealing time of approximately 60 seconds during the annealing step.

[0045] Since annealing temperature and annealing time are inversely proportional, acceptable results can be obtained by lowering the annealing temperature and increasing the annealing time, or conversely, by raising the annealing temperature and decreasing the annealing time. In some embodiments, edge exclusion defects in the DoD process can be reduced or eliminated by using an annealing temperature of about 130°C to 180°C and an annealing time of about 60 seconds to 180 seconds during the annealing step.

[0046] In some embodiments of this disclosure, process parameters for the annealing step (e.g., gas used during the annealing step, gas flow rate, chamber pressure, annealing temperature, and / or annealing time) are selected based on experimental results and used during the annealing step to improve SAM selectivity and reduce / eliminate defects in the DoD process. Process parameters selected based on experimental results result in processing conditions that are effective for forming a SAM structure that completely covers a non-target surface without covering any part of the target surface. The process parameters and processing conditions described herein can be optimized to obtain desired results using the methods described herein.

[0047] In other embodiments of the present disclosure, one or more process parameters (e.g., gas used during the annealing step, gas flow rate, chamber pressure, annealing temperature, and / or annealing time) may be varied during the annealing step based on a predetermined recipe or based on feedback control. For example, a higher annealing temperature may be initially used at the start of the annealing step to achieve the activation energy required to ensure chemical bonding between SAM-forming molecules and the exposed metal surface, thereby improving SAM selectivity to the exposed metal surface. As annealing continues, the annealing temperature may be lowered to reduce / eliminate defects in the DoD process. In another example, the annealing temperature may start at a low temperature, gradually increase, and end at a high temperature to improve SAM selectivity and reduce / eliminate defects in the DoD process. In yet another example, the annealing temperature may vary in a low-high-low pattern during the annealing process.

[0048] The ASD processes described herein can be used in a variety of applications. For example, the ASD processes shown in Figures 2-3 can be used to provide selective dielectric-on-dielectric (DoD) deposition with reduced or eliminated edge exclusion defects in interlayer dielectric (ILD) and metal line patterns. The ASD processes shown and described herein improve SAM selectivity for underlying metal layers, such as copper (Cu) lines, by controlling and / or changing one or more process parameters used in the annealing process shown in Figure 3. Similar selectivity is expected for other metal-containing surfaces, including, but not limited to, ruthenium (Ru), cobalt (Co), tungsten (W), molybdenum (Mo), and their oxides and nitrides.

[0049] By controlling and / or changing the process parameters used during annealing, the DoD processes disclosed herein provide a SAM structure that completely covers the exposed metal surface, while preventing the SAM structure from extending beyond the boundary of the metal surface and covering a portion of the dielectric surface. In some embodiments, the DoD processes disclosed herein can be used to reduce or eliminate defects (such as edge exclusion defects) that may otherwise occur in the DoD process when the dielectric film is selectively deposited on the exposed dielectric surface of the metal / dielectric pattern. However, it will be recognized that the techniques disclosed herein are not strictly limited to DoD processes and may be used in other ASD processes that utilize SAM to suppress growth on various surfaces. Other advantages and alternative uses of the techniques described herein may be apparent to those skilled in the art.

[0050] The ASD processes described herein can be performed in a variety of semiconductor processing chambers, modules, and / or systems. In some embodiments, a spin processing system may be used to selectively deposit the SAM structure 215 onto the exposed metal surface of the metal / dielectric pattern. Subsequently, the dielectric film 220 may be deposited onto the exposed dielectric surface of the metal / dielectric pattern using a variety of wet and dry techniques. In some embodiments, the dielectric film 220 may be formed in the same processing chamber used to form the SAM structure 215. In other embodiments, the dielectric film 220 may be formed using a variety of deposition techniques (such as CVD or ALD) and thus transferred to a different processing chamber after the SAM structure 215 has been formed.

[0051] Figure 7 shows one embodiment of a spin processing system 700 capable of selectively depositing self-assembled monolayers, such as the SAM structure 215 shown and described in Figures 2B and 3, onto a substrate surface using the techniques described herein. As shown in Figure 7, the spin processing system 700 comprises a process chamber 710, which in some embodiments may be a pressure-controlled chamber. In the embodiment shown in Figure 7, the process chamber 710 is a spin chamber having a spinner 720 (or spin chuck), which is configured to spin or rotate at a predetermined rotational speed. The substrate 730 is held on the spinner 720, for example, by electrostatic force or vacuum pressure. As described above, the substrate 730 may be a semiconductor wafer having target and non-target materials exposed on the surface of the substrate 730. In one exemplary embodiment, the substrate 730 may have a metal / dielectric pattern formed on or within the substrate 730, and therefore may have metallic and dielectric materials exposed on the surface of the substrate 730.

[0052] The spin processing system 700 shown in Figure 7 further includes a liquid nozzle 740, which is positioned above the substrate 730 to dispense various liquid solutions 742 onto the surface of the substrate 730. The liquid solutions 742 dispensed onto the surface of the substrate 730 may generally include cleaning solutions, SAM-forming solutions, and rinsing solutions. Examples of cleaning solutions, SAM-forming solutions, and rinsing solutions are discussed above.

[0053] As shown in Figure 7, the liquid solution 742 may be stored in a chemical supply system 746 which may include a chemical injection manifold that is fluidly coupled to the spin processing system 700 via one or more reservoirs and liquid supply lines 744 for holding various liquid solutions 742. In operation, the chemical supply system 746 may selectively apply the desired chemical to the process chamber 710 via liquid supply lines 744 and liquid nozzles 740 located within the process chamber 710. Thus, the chemical supply system 746 can be used to dispense the liquid solution 742 onto the surface of the substrate 730. The process chamber 710 may further include a drain 750 for removing the liquid solution 742 from the process chamber 710.

[0054] The spin processing system 700 shown in Figure 7 is positioned on the substrate 730 and further includes a gas nozzle 760 that supplies various gases into the process chamber 710. Various gases can be dispensed into the process chamber 710 when forming the SAM structure 215. For example, nitrogen (N2), ammonia (NH3), or other gases (e.g., helium (He) and argon (Ar)) can be dispensed into the process chamber 710 at a gas flow rate in the range of about 4 to 7 liters / minute (L / min) during the annealing step, as discussed above. In some embodiments, as further discussed above, the gas and / or gas flow rate of the gas dispensed into the process chamber 710 can be controlled and / or varied to control the selectivity of the SAM structure 215.

[0055] As shown in Figure 7, the gas may be stored in a gas supply system 766, which may include a gas injection manifold that is fluidly coupled to the spin processing system 700 via one or more reservoirs for holding the gas and a gas supply line 764. During operation, the gas supply system 766 may selectively supply the desired gas to the process chamber 710 via the gas supply line 764 and gas nozzles 760 located within the process chamber 710. Thus, the gas supply system 766 can be used to dispense gas into the process chamber 710. The process chamber 710 may further include a gas exhaust line (not shown) for removing or exhausting gas from the process chamber 710.

[0056] The components of the spin processing system 700 are coupled to and controlled by a controller 770, which may be coupled to a corresponding memory storage unit and a user interface (not shown). Various processing operations can be performed via the user interface, and various processing recipes and operations can be stored in the memory storage unit. Thus, a given substrate 730 can be processed in the process chamber 710 according to a specific recipe. In some embodiments, a given substrate 730 can be processed in the process chamber 710 according to a recipe that utilizes the techniques disclosed herein to control the formation of SAM structures used in the ASD process and to prevent defects in the ASD process.

[0057] The controller 770, shown in block diagram form in Figure 7, can be implemented in a variety of ways. In one example, the controller 770 may be a computer. In another example, the controller 770 may include one or more programmable integrated circuits programmed to provide the functions described herein. For example, one or more processors (e.g., microprocessors, microcontrollers, central processing units, etc.), programmable logic devices (e.g., complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), etc.) and / or other programmable integrated circuits can be programmed with software or other programming instructions to realize the functions of a given plasma process recipe. It should be further noted that the software or other programming instructions may be stored in one or more non-temporary computer-readable media (e.g., memory storage devices, flash memory, dynamic random access memory (DRAM), reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, etc.), and that when the software or other programming instructions are executed by the programmable integrated circuit, they cause the programmable integrated circuit to perform the processes, functions and / or capabilities described herein. Other modifications are also possible.

[0058] As shown in Figure 7, the controller 770 may be coupled to various components of the spin processing system 700 to receive inputs from the components and supply outputs to them. For example, the controller 770 may be coupled to the process chamber 710 to control the temperature and / or pressure inside the process chamber 710, to the spinner 720 to control the rotational speed of the spinner 720, to the chemical supply system 746 to control various liquid solutions 742 supplied onto the substrate 730, and to the gas supply system 766 to control the gas and / or gas flow rate of the gas dispensed into the process chamber 710. The controller 770 may also control other processing system components not shown in Figure 7, as is known in the art.

[0059] In some embodiments, the controller 770 may control various components of the spin processing system 700 according to a recipe utilizing the techniques described herein to control the formation of SAM structures used in the ASD process and to prevent defects in the ASD process. For example, the controller 770 may supply various control signals to the chemical supply system 746, which may dispense (a) a cleaning solution onto the surface of the substrate 730 to remove surface contaminants, (b) a SAM formation solution onto the surface of the substrate 730 to selectively deposit SAM structures onto the exposed surface of the non-target material, and (c) a rinse solution to wash away excess SAM formation solution from the surface of the substrate 730 after the SAM formation molecules have bonded to the exposed surface of the non-target material.

[0060] In some embodiments, the controller 770 may control and / or vary one or more process parameters used during the annealing step shown in Figure 3 to control the selectivity of the SAM structure formed on the exposed surface of the non-target material. For example, the controller 770 may supply various control signals to the gas supply system 766 to control the gas, gas flow rate, and / or pressure in the process chamber 710 during the annealing step. In some embodiments, the controller 770 may supply various control signals to the process chamber 710 and / or spinner 720 to control the temperature in the process chamber 710 or the temperature of the substrate 730 mounted on the spinner 720 during the annealing step. In addition to controlling the annealing temperature, the controller 770 may supply control signals to the process chamber 710 and / or spinner 720 to control the annealing time. The gas, gas flow rate / pressure, annealing temperature, and / or annealing time may be controlled and / or varied as discussed above.

[0061] Figures 8 and 9 illustrate exemplary methods of utilizing the techniques disclosed herein to control the formation of SAM structures used in the ASD process and to prevent defects in the ASD process. The embodiments in Figures 8 and 9 are illustrative, and it will be understood that additional methods may utilize the techniques described herein. Furthermore, since the processing steps described are not intended to be exclusive, additional processing steps may be added to the methods shown in Figures 8 and 9. Moreover, the order of the steps is not limited to that shown in the drawings, as they may occur in different orders and / or various steps may be performed in combination or simultaneously.

[0062] Figure 8 shows one embodiment of Method 800, which may be used to control the formation of a self-assembled monolayer (SAM) structure used in a region-selective deposition (ASD) process according to the present disclosure. Method 800 may generally begin (in step 810) with providing a substrate in a process chamber, the substrate having an exposed target material and a non-target material on the surface of the substrate. Next, Method 800 may (in step 820) include (a) dispensing a liquid solution onto the surface of the substrate while rotating the substrate, thereby coating the surface of the substrate with the liquid solution, the liquid solution containing SAM-forming molecules, and (b) heat-treating the substrate to chemically bond the SAM-forming molecules to the exposed surface of the non-target material, thereby forming a SAM structure on the exposed surface of the non-target material.

[0063] Method 800 may further include controlling one or more process parameters used during the heat treatment (in step 830) to ensure that the SAM structure completely covers the exposed surface of the non-target material and that the SAM structure does not extend beyond the boundary of the non-target material to cover a portion of the target material. In some embodiments, Method 800 may further include selectively depositing a film on the exposed surface of the target material after forming the SAM structure on the exposed surface of the non-target material. By controlling one or more process parameters during the heat treatment (in step 830), Method 800 reduces defects in the ASD process by ensuring that the film completely covers the exposed surface of the target material.

[0064] Figure 9 shows one embodiment of Method 900, which may be used to reduce edge exclusion defects in a dielectric-on-dielectric (DoD) process according to the present disclosure. Method 900 may generally begin (in step 910) with providing a substrate in a process chamber, the substrate having a metal layer and a dielectric layer exposed on the surface of the substrate. Next, Method 900 may (in step 920) include (a) dispensing a liquid solution onto the surface of the substrate while rotating the substrate, thereby coating the surface of the substrate with the liquid solution, the liquid solution containing SAM-forming molecules, and (b) heat-treating the substrate to chemically bond the SAM-forming molecules to the exposed surface of the non-target material, thereby selectively depositing a self-assembled monolayer (SAM) structure on the exposed surface of the metal layer.

[0065] Method 900 further includes controlling one or more process parameters used during the heat treatment to ensure that the SAM structure completely covers the exposed surface of the metal layer and prevents the SAM structure from covering a portion of the dielectric layer beyond the boundary of the metal layer (in step 930), and selectively depositing a dielectric film on the exposed surface of the dielectric layer after forming the SAM structure on the exposed surface of the metal layer (in step 940). By controlling one or more process parameters during the heat treatment (in step 930), Method 900 reduces edge exclusion defects in the DoD process by ensuring that the dielectric film completely covers the exposed surface of the dielectric layer.

[0066] Methods 800 and 900, shown in Figures 8 and 9, allow for the control of various process parameters during the heat treatment (or annealing step) used to form the SAM structure in steps 820 and 920. For example, one or more process parameters controlled in steps 830 and 930 may include one or more of the following: gas, gas flow rate, pressure in the process chamber, temperature, and time used during the heat treatment (or annealing step).

[0067] In some embodiments, in steps 830 and 930, one or more process parameters may be controlled by selecting the gas used during the heat treatment, the gas flow rate, the pressure in the process chamber, the temperature, and / or the time, based on experimental results. For example, one or more process parameters may be controlled in steps 830 and 930 by selecting (a) a gas from the group of gases including nitrogen (N2), ammonia (NH3), helium (He), and argon (Ar), (b) a gas flow rate from a range of gas flow rates including about 4 liters / min (L / min) to about 7 L / min, (c) a temperature from a range of temperatures including about 130°C to about 180°C, and / or (d) a time from a range of constant time including about 60 seconds to about 180 seconds.

[0068] In other embodiments, one or more process parameters may be controlled in steps 830 and 930 by changing one or more of the gas, gas flow rate, pressure in the process chamber, temperature, and time during the heat treatment, based on a predetermined recipe or based on feedback control. In one example, one or more process parameters may be controlled in steps 830 and 930 by changing the temperature. In another example, one or more process parameters may be controlled in steps 830 and 930 by changing the pressure.

[0069] Throughout this specification, any reference to “one embodiment” or “an embodiment” means that certain features, structures, materials, or properties described in relation to that embodiment are included in at least one embodiment of the present invention, but not that they are present in all embodiments. Therefore, the appearance of the phrase “in one embodiment” or “in an embodiment” in various places throughout this specification does not necessarily refer to the same embodiment of the present invention. Furthermore, certain features, structures, materials, or properties may be combined in any suitable manner in one or more embodiments. Other embodiments may include various additional layers and / or structures, and / or omit the described features.

[0070] As used herein, the term “substrate” means, and includes, a substrate or structure on which a material is formed. It will be understood that a substrate may include a single material, multiple layers of different materials, or one or more layers having regions of different materials or different structures within them. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, a substrate may be a semiconductor substrate, a basic semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. A substrate may be a conventional silicon substrate or other bulk substrates including layers of semiconducting material. As used herein, the term “bulk substrate” means, and includes, not only silicon wafers, but also silicon-on-insulator ("SOI") substrates such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates, epitaxial layers of silicon on a basic semiconductor substrate, and other semiconductor or optoelectronic materials such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The circuit board may or may not be doped.

[0071] Systems and methods for processing substrates are described in various embodiments. The substrate may include any material portion or structure of an element, in particular a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor substrate or layer on or covering a base substrate structure such as a thin film. Therefore, the substrate is not intended to be limited to any particular base structure, underlayer or upper layer, whether patterned or unpatterned, but rather is intended to include any such layer or base structure and any combination of layers and / or base structures.

[0072] Those skilled in the art will recognize that various embodiments may be carried out without one or more specific details, or with other alternative and / or additional methods, materials, or components. In other examples, details of known structures, materials, or operations are not illustrated or described so as not to obscure the various embodiments of the present invention. Similarly, specific numbers, materials, and configurations are described for illustrative purposes to provide a complete understanding of the present invention. Nevertheless, the present invention may be carried out without specific details. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0073] Further variations and alternative embodiments of the systems and methods described herein will become apparent to those skilled in the art from the description herein. Therefore, it will be recognized that the systems and methods described herein are not limited to these exemplary configurations. It should be understood that the forms of systems and methods illustrated and described herein should be considered exemplary embodiments. Various modifications may be made to the implementation. Therefore, although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the invention. Accordingly, this specification and the drawings should be considered exemplary rather than restrictive, and such modifications are intended to fall within the scope of the invention. Furthermore, no benefit, advantage, or solution to a problem described herein with respect to a specific embodiment is intended to be construed as an important, necessary, or essential feature or element of any or all of the claims.

Claims

1. A method for reducing edge exclusion defects in a dielectric-on-dielectric (DoD) process, the method being: A step of providing a substrate in a process chamber, wherein the substrate has a dielectric layer and a metal layer exposed on the surface of the substrate, The step of selectively depositing a self-assembled monolayer (SAM) structure onto the exposed surface of the metal layer, The steps include distributing a liquid solution onto the surface of the substrate while rotating the substrate, and coating the surface of the substrate with the liquid solution, wherein the liquid solution contains SAM-forming molecules, and The step of heat-treating the substrate to chemically bond the SAM-forming molecules to the exposed surface of the metal layer, thereby forming the SAM structure on the exposed surface of the metal layer. The steps to be implemented are as follows: The steps include controlling one or more process parameters used during the heat treatment to ensure that the SAM structure completely covers the exposed surface of the metal layer and that the SAM structure extends beyond the boundary of the metal layer and covers a portion of the dielectric layer, A step of forming the SAM structure on the exposed surface of the metal layer, followed by a step of selectively depositing a dielectric film on the exposed surface of the dielectric layer, wherein edge exclusion defects in the DoD process are reduced by ensuring that the dielectric film completely covers the exposed surface of the dielectric layer, by controlling one or more process parameters during the heat treatment. A method having.

2. The method according to claim 1, wherein the one or more process parameters include one or more of the gas used during the heat treatment, the gas flow rate, the pressure in the process chamber, the temperature, and the time.

3. The method of claim 2, wherein the step of controlling one or more process parameters comprises the step of selecting one or more of the gas, the gas flow rate, the pressure in the process chamber, the temperature used during the heat treatment, and the time, wherein the step of selecting is based on experimental results.

4. The step of controlling one or more process parameters includes nitrogen (N) ２ ), ammonia (NH ３ The method according to claim 2, further comprising the step of selecting the gas from the group of gases including ), helium (He), and argon (Ar).

5. The method according to claim 2, wherein the step of controlling one or more process parameters includes the step of selecting the gas flow rate from a range of gas flow rates including about 4 liters / minute (L / min) to about 7 L / min.

6. The method according to claim 2, wherein the step of controlling one or more process parameters includes the step of selecting the temperature from a temperature range including about 130°C to about 180°C.

7. The method according to claim 2, wherein the step of controlling one or more process parameters comprises the step of selecting the time from a time range including about 60 seconds to about 180 seconds.

8. The method according to claim 2, wherein the step of controlling one or more process parameters includes changing one or more of the gas, the gas flow rate, the pressure in the process chamber, the temperature, and the time during the heat treatment, based on a predetermined recipe or based on feedback control.

9. A method for controlling the formation of self-assembled monolayer (SAM) structures used in region-selective deposition (ASD) processes, wherein the method is: A step of providing a substrate in a process chamber, wherein the substrate has a target material and a non-target material exposed on its surface, A step of forming the SAM structure on the exposed surface of the non-target material, The steps include distributing a liquid solution onto the surface of the substrate while rotating the substrate, and coating the surface of the substrate with the liquid solution, wherein the liquid solution contains SAM-forming molecules, and The step of heat-treating the substrate to chemically bond the SAM-forming molecules to the exposed surface of the non-target material, thereby forming the SAM structure on the exposed surface of the non-target material. The steps to be implemented are as follows: The steps include controlling one or more process parameters used during the heat treatment to ensure that the SAM structure completely covers the exposed surface of the non-target material and that the SAM structure extends beyond the boundary of the non-target material and covers a portion of the target material, A method having.

10. Furthermore, the process includes the step of forming the SAM structure on the exposed surface of the non-target material, followed by the step of selectively depositing a film on the exposed surface of the target material. The method according to claim 9, wherein during the heat treatment, the step of controlling one or more process parameters ensures that the film completely covers the exposed surface of the target material.

11. The method according to claim 10, wherein the non-target material is a conductive material, the target material is a dielectric material, and the film is a dielectric film.

12. The method according to claim 11, wherein the SAM-forming molecule has a head group that bonds to the exposed surface of the conductive material and a tail group that provides a barrier to the dielectric film.

13. The method according to claim 12, wherein the SAM-forming molecule has a head group of thiol, silane, phosphate, amine, or carboxylic acid.

14. The method according to claim 9, wherein the one or more process parameters include one or more of the gas used during the heat treatment, the gas flow rate, the pressure in the process chamber, the temperature, and the time.

15. The step of controlling one or more process parameters comprises selecting one or more of the gas used during the heat treatment, the gas flow rate, the pressure in the process chamber, the temperature, and the time, wherein the selection step is based on experimental results, according to claim 14.

16. The step of controlling one or more process parameters includes nitrogen (N) ２ ), ammonia (NH ３ The method according to claim 14, further comprising the step of selecting the gas from the group of gases including ), helium (He), and argon (Ar).

17. The method according to claim 14, wherein the step of controlling one or more process parameters includes the step of selecting the gas flow rate from a range of gas flow rates including about 4 liters / minute (L / min) to about 7 L / min.

18. The method according to claim 14, wherein the step of controlling one or more process parameters includes the step of selecting the temperature from a temperature range including about 130°C to about 180°C.

19. The method according to claim 14, wherein the step of controlling one or more process parameters comprises the step of selecting the time from a time range including about 60 seconds to about 180 seconds.

20. The method according to claim 14, wherein the step of controlling one or more process parameters includes changing one or more of the gas, the gas flow rate, the pressure in the process chamber, the temperature, and the time during the heat treatment, based on a predetermined recipe or based on feedback control.

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