Methods for manufacturing semiconductor devices

Abstract

According to one embodiment, a method for manufacturing a semiconductor device (100) includes the step of providing a semiconductor body (1) having a surface formed at least partially of SiC. In a further step, a nitride-based dielectric layer (2) is applied to this surface. Next, the dielectric layer is annealed in a hydrogen-containing atmosphere.

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing a semiconductor device and to a semiconductor device. [Background technology]

[0002] Reference US2019 / 0296146A1 relates to a semiconductor device comprising: a silicon carbide layer; a gate electrode; a gate insulating layer disposed between the silicon carbide layer and the gate electrode; a first region disposed in the silicon carbide layer and containing nitrogen; and a second region disposed between the first region and the gate insulating layer and containing at least one element selected from the group consisting of nitrogen, phosphorus, arsenic, antimony, scandium, yttrium, lanthanum, lanthanide, hydrogen, deuterium, and fluorine.

[0003] Reference US2020 / 0220001A1 relates to a semiconductor device comprising: a silicon carbide layer having a first surface and a second surface; a first electrode located on the side of the first surface; a second electrode located on the side of the second surface; a gate electrode; an aluminum nitride layer containing aluminum nitride crystals between the second silicon carbide region and the gate electrode; and an insulating layer between the aluminum nitride layer and the gate electrode having a wider band gap than the aluminum nitride layer.

[0004] Reference US2012 / 0223338A1 relates to a method for manufacturing a semiconductor device, the method comprising the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in a hydrogen-containing gas, and forming an aluminum oxynitride film on the silicon oxide film after annealing the silicon carbide substrate and the silicon oxide film.

[0005] Reference US2020 / 0091297A1 relates to a semiconductor device comprising a silicon carbide layer, a gate electrode, a gate insulating layer provided between the silicon carbide layer and the gate electrode, and a region located between the silicon carbide layer and the gate insulating layer and having a first bonding structure, wherein the first bonding structure includes a three-coordinate first nitrogen atom bonded to three first silicon atoms, a three-coordinate second nitrogen atom bonded to three second silicon atoms, and a three-coordinate third nitrogen atom bonded to three third silicon atoms, and the first nitrogen atom, second nitrogen atom, and third nitrogen atom are adjacent to each other in the first bonding structure.

[0006] Reference US2023 / 0187525A1 discloses an insulated gate structure. [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] One objective is to achieve flat band voltage (V FB The objective is to provide a method for manufacturing semiconductor devices that will help enable the design of (V). FB is V th This affects the device performance. A further objective to be achieved is to provide a semiconductor device with an improved flatband voltage, thereby having an appropriate threshold voltage for improving the blocking and on-state performance of the device. [Means for solving the problem]

[0008] First, we will describe the methods for manufacturing semiconductor devices.

[0009] According to one embodiment, a method for manufacturing a semiconductor device includes the step of providing a semiconductor body having a surface formed at least partially of SiC. In a further step, a nitride-based dielectric layer is applied to this surface. The dielectric layer is then annealed in a hydrogen-containing atmosphere. The surface may also be referred to as the upper surface.

[0010] According to one embodiment, a method for manufacturing a semiconductor device includes, for example, the following steps in the described order. The following steps are - providing a semiconductor body made of SiC having an upper side; - directly forming a silicon-containing interface layer having a thickness of up to 5 nm on the upper side; - directly applying a nitride-based dielectric layer on the interface layer; - annealing the dielectric layer in an atmosphere containing hydrogen at a temperature of at least 1050 °C; - applying a conductive layer, particularly a gate electrode, on the annealed dielectric layer.

[0011] For example, the step of forming the silicon-containing interface layer includes - directly forming a silicon layer having a thickness of up to 5 nm on the upper side; - annealing the silicon layer in an atmosphere containing nitrogen at a temperature of at least 1200 °C, for example, to form a silicon-containing interface layer.

[0012] For example, the silicon layer is a layer of amorphous Si. The thickness of the silicon layer is, for example, one single layer, or at least two single layers, or at least 1 nm. Alternatively or additionally, the above thickness is up to 5 nm, or up to 3 nm, or up to 2 nm.

[0013] The silicon layer may be formed from the SiC of the semiconductor body, or the silicon layer may be formed by applying silicon to the upper side. The silicon for the silicon layer can be applied, for example, by CVD or PVD.

[0014] For example, the silicon layer is annealed at a temperature of at least 1000 °C or at least 1200 °C. The above temperature can be up to 1600 °C or up to 1400 °C.

[0015] For example, the silicon layer is annealed in an atmosphere containing nitrogen. The atmosphere may consist of nitrogen. In this context, the phrase "consisting of" here and below may mean that the mass ratio of all other substances other than those mentioned is at most 1%, or at most 0.1%, or at most 0.01%. To anneal the silicon layer, the atmosphere may be, for example, atmospheric pressure + / - 20%.

[0016] For example, the average concentration of carbon atoms and / or nitrogen atoms in the interface layer is at most 1×10 18 cm -3 or at most 5×10 16 cm -3 or at most 2×10 15 cm -3 These values may be considered to contain no carbon.

[0017] For example, the interface layer consists of silicon nitride. In particular, the interface layer consists of Si x N y where 2.5≦x≦3.5 and 3.3≦y≦4.7, such as stoichiometric Si3N4. In this case, the average concentration of carbon atoms in the interface layer is at most 1×10 18 cm -3 or at most 5×10 16 cm -3 or at most 2×10 15 cm -3 [[ID=三十二]]is.

[0018] Therefore, by annealing in a nitrogen atmosphere, an interface layer consisting of silicon nitride, for example, can be formed.

[0019] The conductive layer can be a gate electrode. In this case, the conductive layer consists of, for example, polysilicon (poly-Si) or metal. When the conductive layer is made of polysilicon, it can be annealed at a temperature of at least 500°C. The latter annealing may be at a lower temperature than during the formation of the silicon layer and / or during the annealing of the dielectric layer.

[0020] Furthermore, the dielectric layer can be formed by a method different from that used to form the silicon-containing interface layer. In particular, the dielectric layer may be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Conversely, for example, the silicon layer may be formed by thermal decomposition of the semiconductor body SiC, as well as by CVD and PVD.

[0021] For example, the thickness of the dielectric layer to be applied is at least 5 nm, or at least 10 nm, or at least 20 nm. Alternatively or additionally, the thickness may be up to 300 nm, or up to 200 nm, or up to 100 nm. The dielectric layer can be applied in its final material composition, which means, for example, that nitrides are actually grown on a silicon-containing interface layer as well as the raw material layer later used to manufacture the dielectric layer.

[0022] Conventional SiC semiconductor devices, such as SiC-MOSFETs or SiC-IGBTs, typically contain SiO2 as a dielectric layer. Due to defects at the interface between the dielectric layer and SiC, such devices have limited mobility values, and R ON The value becomes high. To minimize the defect density at the interface, SiO2 can be annealed in an NO or N2O atmosphere to improve the interface with SiC. However, this treatment provides only limited improvement in terms of mobility.

[0023] R ON To reduce this, for example, a high-k insulator can be implemented as the gate dielectric. Such materials result in higher dielectric capacitance values, and process optimization can reduce R compared to their SiO2 comparison examples. ON The value becomes lower. However, when these materials are incorporated into SiC semiconductor devices and annealed in an inert atmosphere, V FB This would shift it undesirably high (towards a negative or positive value).

[0024] In practice, annealing nitride-based dielectric materials at high temperatures (>1000°C) in an inert atmosphere (mainly N2) creates nitrogen vacancies within the dielectric layer. These defects cause deep trap levels to form in the material, resulting in V FB This would shift the voltage to an undesirably high (positive or negative) level. In this invention, this problem is solved by annealing the nitride dielectric layer with hydrogen after deposition. Introducing hydrogen back into the dielectric layer replaces the nitrogen vacancies. This converts deep traps into shallow traps, resulting in a voltage of several volts, for example, up to 3V, V FB Furthermore, in MOSFETs or IGBTs, the negative / positive V decreases. TH It is converted into a characteristic.

[0025] The semiconductor body of the semiconductor device includes SiC, for example, 4H-SiC or 3C-SiC. For example, SiC is epitaxially grown on a substrate containing the semiconductor body. The substrate may consist of Si, SiO2, or SiC. At least a portion of the semiconductor body, for example, its SiC, may be doped, for example, n-doped.

[0026] A portion or the entire surface of the semiconductor body is formed of SiC, meaning that SiC is exposed on the surface of the semiconductor body. For example, the SiC portion of the surface is located on the upper side of the semiconductor body or in a trench formed in the semiconductor body. The exposed SiC may be epitaxially grown SiC.

[0027] The nitride dielectric layer is applied to a surface that is at least partially formed of SiC. In particular, the nitride dielectric layer is applied on top of the SiC portion of this surface. For example, the nitride dielectric layer is applied directly to exposed SiC adjacent to the SiC in the semiconductor body. Then, an interface is formed between the nitride dielectric layer and the semiconductor body, at which the SiC and the nitride dielectric material are in direct contact with each other. Alternatively, an intermediate layer may be formed between the nitride dielectric layer and the SiC. The intermediate layer may be, for example, SiO2. The intermediate layer may have a thickness of, for example, up to 200 nm, up to 100 nm, or up to 50 nm. The nitride dielectric layer, hereafter also referred to as the "dielectric layer," is applied by vacuum deposition such as PECVD, PEALD, or LPCVD.

[0028] In particular, the dielectric layer is at least a part of the gate dielectric or forms at least a part of it; that is, the dielectric layer electrically insulates the gate electrode from the semiconductor body.

[0029] Nitride-based dielectric layers are particularly high-k dielectric layers. For example, nitride-based dielectric layers are applied with a thickness of 10 nm to 1 μm, preferably 20 nm to 200 nm.

[0030] After the dielectric layer is formed, it is annealed in a hydrogen-containing atmosphere. In this step, hydrogen molecules come into contact with the dielectric layer, and hydrogen atoms can diffuse into the dielectric layer. For example, the annealing of the dielectric layer is carried out only in a hydrogen-containing atmosphere. In particular, annealing in a hydrogen-free atmosphere is not performed before annealing in a hydrogen-containing atmosphere.

[0031] According to further embodiments, the atmosphere in which the dielectric layer is annealed mainly consists of nitrogen and hydrogen, or consists of nitrogen and hydrogen. For example, at least 80 atomic percent, or at least 90 atomic percent, or at least 99 atomic percent, or at least 99.9 atomic percent of the atmosphere is formed by nitrogen (N2) and hydrogen (H2). In this specification, atomic percent is used as an abbreviation for atomic percentage.

[0032] According to further embodiments, the concentration of hydrogen in the atmosphere in which the dielectric layer is annealed is at least 1 atomic percent or at least 2 atomic percent. Additionally or alternatively, the concentration is up to 10 atomic percent or up to 6 atomic percent. For example, the concentration is 4 atomic percent.

[0033] According to further embodiments, the dielectric layer is annealed at a temperature of at least 800°C or at least 1000°C.

[0034] According to further embodiments, the dielectric layer is annealed at atmospheric pressure ±20% or atmospheric pressure ±10%. That is, the pressure at which the dielectric layer is annealed is in the range of 811 mbar to 1216 mbar, particularly in the range of 912 mbar to 1115 mbar. Boundaries are included.

[0035] According to a further embodiment, the dielectric layer is annealed in a hydrogen-containing atmosphere for at least 10 minutes, or at least half an hour, or at least 1 hour.

[0036] In further embodiments, the dielectric layer comprises or consists of a nitride or oxynitride of a metal, or a nitride or oxynitride of a semiconductor material. For example, the dielectric layer is aluminum oxynitride. Furthermore, boron nitride or boron oxynitride is also possible, as is phosphorus nitride or phosphorus oxynitride. In particular, the dielectric layer does not have to be made of AlN.

[0037] According to further embodiments, the dielectric layer comprises or consists of at least one of silicon nitride (Si3N4) and silicon oxynitride (e.g., Si2N2O). For example, the dielectric layer consists of silicon nitride or silicon oxynitride. The silicon nitride or silicon oxynitride may be stoichiometric or non-stoichiometric.

[0038] For example, the dielectric layer is made of Si with a molecular weight of 2.5 ≤ m ≤ 3.5 and 3.3 ≤ n ≤ 4.7. m N n It consists of, or the dielectric layer is made of Si with values ​​of 1.5 ≤ i ≤ 1.5, 1.5 ≤ j ≤ 1.5, and 0.5 ≤ k ≤ 1.5. i N j O k It consists of.

[0039] According to further embodiments, the method includes a further step of cleaning a surface formed at least partially from SiC. This step is performed before applying a dielectric layer. The surface is cleaned, for example, by a wet cleaning process.

[0040] According to further embodiments, the method further includes the step of annealing the dielectric layer and then applying a conductive layer on the dielectric layer. For example, the conductive layer may be formed of a metal or of highly doped polysilicon. The conductive layer may be, for example, a gate electrode in a semiconductor device. The conductive layer may be applied directly on the dielectric layer such that its conductive material is adjacent to the nitride-based dielectric material of the dielectric layer.

[0041] Next, semiconductor devices will be described. Semiconductor devices can be manufactured, for example, by a method according to any embodiment described herein. Therefore, all features disclosed for such methods are also disclosed for semiconductor devices, and vice versa.

[0042] According to one embodiment, the semiconductor device comprises a semiconductor body and a nitride-based dielectric layer on the semiconductor body. At least one side of the semiconductor body facing the nitride-based dielectric layer is formed of SiC at least partially. The nitride-based dielectric layer contains hydrogen atoms in its nitrogen vacancies.

[0043] The dielectric layer is applied directly on top of the material derived from the semiconductor body. For example, the semiconductor material of the semiconductor body adjacent to the dielectric layer is formed at least partially, and especially entirely, from SiC modified to form a silicon-containing interface layer. This means that there may be an interface where the silicon-containing interface layer is adjacent to the nitride-based dielectric layer and the remaining semiconductor body that forms the material of the silicon-containing interface layer.

[0044] According to further embodiments, the concentration of hydrogen in the dielectric layer is at least 0.1 atomic%, or at least 0.5 atomic%, or at least 1 atomic%. Alternatively or additionally, the above concentration is at most 10 atomic%, or at most 5 atomic%, or at most 2 atomic%.

[0045] According to further embodiments, the semiconductor device is a power semiconductor device.

[0046] According to further embodiments, the semiconductor device is an insulated gate device, and more particularly, a transistor having an insulated gate electrode. Specifically, the dielectric layer acts as an insulator between the gate electrode and the semiconductor body. In other words, the dielectric layer forms at least a portion of the gate dielectric.

[0047] In further embodiments, the semiconductor device is a MISFET, MOSFET, IGBT, or JFET. The IGBT may be a conventional IGBT or an RC IGBT.

[0048] The following describes in more detail a method for manufacturing a semiconductor device and the semiconductor device itself, based on exemplary embodiments with reference to the attached drawings. The attached drawings are included for further understanding. In these drawings, elements having the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are illustrative and not necessarily drawn to scale. To the extent that elements or components correspond to each other in terms of their function in separate drawings, their descriptions are not repeated in each of the attached drawings. For clarity, elements may not be shown with corresponding reference numerals in all drawings. [Brief explanation of the drawing]

[0049] [Figure 1] This figure shows a location in an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 2] This figure shows another location in an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 3] This figure shows another location in an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 4] This figure shows another location in an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 5] This figure shows another location in an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 6] This figure shows another location in an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 7] This figure shows an exemplary embodiment of a semiconductor device. [Figure 8] This figure shows another exemplary embodiment of a semiconductor device. [Figure 9] This figure shows specific measured values. [Figure 10] This figure shows another measurement. [Figure 11]This figure shows a further exemplary embodiment of a semiconductor device. [Modes for carrying out the invention]

[0050] Figure 1 shows a first position in an exemplary embodiment of a method for manufacturing a semiconductor device. The semiconductor body 1 comprises an upper part 10 and a bottom part 19 opposite the upper part 10. At least the upper part 10 is made of SiC. The semiconductor body 1 may be made entirely of SiC. In particular, the semiconductor body 1 in Figure 1 is made of n-doped semiconductor material.

[0051] In the upper part 10, a silicon-containing interface layer 22 is formed. The interface layer 22 can be formed, in particular, by having a nitrogen atmosphere above the semiconductor body 1 and by applying a temperature of at least 1200°C. The thickness of the resulting interface layer 22 is, for example, at least one single layer and up to 2 nm.

[0052] To simplify the drawings, the interface layer 22 is not shown in the following diagrams.

[0053] For example, the step of generating the silicon-containing interface layer 22 is: - The process includes the step of directly generating a silicon layer on the upper part 10, wherein the thickness of the silicon layer is at least one monolayer or at least two monolayers, and is at most 5 nm, and the silicon layer may be generated by CVD or PVD, and further, -The process includes the step of annealing a silicon layer in a nitrogen-containing atmosphere at a temperature of at least 1200°C to produce a silicon-containing interface layer, which is a silicon nitride layer such as a Si3N4 layer.

[0054] With regard to the manufacturing of the interface layer, reference is also made to US2023 / 0187525A1, and its disclosures, particularly those in paragraphs 57-60, which state that the first nitride layer may correspond to the interface layer of the present application and the second nitride layer may correspond to the nitride-based dielectric layer of the present application, are incorporated by reference.

[0055] Figure 2 shows an arbitrary position where the interface layer 22 is cleaned. Furthermore, optionally, the upper side 10 of the semiconductor body 1 can be cleaned before the interface layer 22 is generated.

[0056] At the location shown in Figure 3, the semiconductor body 1 is further processed. In particular, a p-doped base region 12 is formed inside the semiconductor body 1, for example, using ion implantation. Furthermore, an n-doped contact region 11 is formed, for example, using ion implantation. Furthermore, the n-doped contact region 11 is separated and spaced apart from the drift region 14 of the semiconductor body 1 by the base region 12. The drift region 14 is also n-doped. Furthermore, an n-doped contact layer 13 is formed on the bottom side 19 of the semiconductor body 1.

[0057] Figure 4 shows the position where the dielectric layer 2 is directly deposited on the upper side 10 of the semiconductor body 1. The dielectric layer 2 is a high-k nitride-based dielectric layer. The dielectric layer 2 is made of, for example, Si3N4. The dielectric layer 2 may be deposited by vacuum deposition. This forms an interface between the semiconductor body 1 and the dielectric layer 2 where the Si-containing interface layer 12 and the nitride-based dielectric material are adjacent to each other.

[0058] Figure 5 shows the location where the dielectric layer 2 is annealed in a hydrogen-containing atmosphere. The dielectric layer 2 is annealed, for example, at a temperature of at least 1000°C and at atmospheric pressure. For example, the atmosphere contains only hydrogen and nitrogen, and the concentration of hydrogen in the atmosphere is about 4 atomic percent. The annealing of the dielectric layer 2 may be carried out for, for example, at least half an hour. Nitrogen vacancies are formed during the annealing. These nitrogen vacancies are at least partially filled with hydrogen atoms.

[0059] Figure 6 shows the position of the conductive layer 3 after the dielectric layer 2 has been annealed and the conductive layer 3 has been applied to the dielectric layer 2 in the shape of a gate electrode 3. The gate electrode 3 is formed, for example, of highly doped polysilicon. The dielectric layer 2 forms the gate dielectric.

[0060] Figure 7 shows the finished position of the semiconductor device 100. In this case, the semiconductor device 100 is a MOSFET or MISFET. To finish the semiconductor device 100, the gate electrode 3 is further covered with dielectric material, and the main electrodes 4 and 5 are mounted on the upper side 10 and the bottom side 19. The first main electrode 4 is in electrical contact with the contact region 11, and the second main electrode 5 is in electrical contact with the contact layer 13. The IGBT in Figure 7 is a planar design or planar gate design.

[0061] Figure 8 shows a further exemplary embodiment of a semiconductor device 100 that can also be manufactured using the method described herein. In this case, the semiconductor device 100 is a MOSFET or MISFET with a trench design or trench gate design, respectively. Here, the gate electrode 3 is located in a trench 6 that extends from the upper side 10 into the semiconductor body 1. The gate electrode 3 in the trench 6 is electrically insulated from the semiconductor body 1 by a nitride-based dielectric layer 2. The semiconductor body 1 may be made of SiC. The dielectric layer 2 has been re-annealed in a hydrogen-containing atmosphere, so that its nitrogen vacancies contain hydrogen atoms.

[0062] Figures 9 and 10 show measured capacitance-voltage characteristics of various dielectric layers applied to a SiC epitaxial wafer. Here, the y-axis represents the relative capacitance C / Cmax, and the x-axis represents the applied voltage Vg.

[0063] In Figure 9, the dielectric layer is made of a nitride, for example, Si3N4. Curve A1 shows the results when the dielectric layer 2 is annealed in a pure nitrogen atmosphere, and curve A2 shows the results when the dielectric layer is annealed in an atmosphere containing nitrogen and hydrogen, i.e., about 4 atomic percent of hydrogen.

[0064] In Figure 10, a laminate of an oxide layer and a nitride-based dielectric layer is applied to a wafer. Curve B1 shows the results when this laminate is annealed in a pure nitrogen atmosphere, and curve B2 shows the results when the dielectric layer is annealed in an atmosphere containing nitrogen and hydrogen.

[0065] In both Figure 9 and Figure 10, when the nitride-based dielectric layer 2 is annealed in a hydrogen-containing atmosphere, V FB It can be seen that the voltage clearly shifts to 0V.

[0066] Figure 11 shows a further exemplary embodiment of the semiconductor device 100, which is similar to the embodiment in Figure 7, except that in this case the contact layer 13 is p-doped so that the semiconductor device 100 constitutes an IGBT.

[0067] The embodiments shown in Figures 1 to 8 and 11 above represent exemplary embodiments of a method for manufacturing a semiconductor device and the semiconductor device itself. Therefore, they do not constitute a complete list of all embodiments according to the method and the semiconductor device. Actual methods and semiconductor devices may differ from the illustrated embodiments, for example, in terms of arrangement and device configuration. [Explanation of Symbols]

[0068] Reference sign 1. Semiconductor body 22 Silicon-containing interface layer 2 Nitride-based dielectric layer 3. Conductive layer / Gate circuit 4. First main electrode 5. Second main electrode 6 Trench 10 Upper side 11 Contact Area 12 Base area 13 Contact Layer 14. Drift Region 19 Bottom 100 Semiconductor Devices A1, A2 curve B1, B2 curve

Claims

1. A method for manufacturing a semiconductor device (100), - The step of providing a semiconductor body (1) made of SiC, which includes an upper part (10), - A step of directly generating a silicon-containing interface layer (22) having a maximum thickness of 5 nm on the upper side (10), - A step of directly applying a nitride-based dielectric layer (2) to the silicon-containing interface layer (22) with a thickness of at least 5 nm, - The step of annealing the dielectric layer (2) in a hydrogen-containing annealing atmosphere at a temperature of at least 1050°C, A method comprising the step of applying a conductive layer (3) on the annealed dielectric layer (2).

2. - The dielectric layer (2) is Si ３ N ４ or Si ２ N ２ The method according to claim 1, comprising O.

3. The method according to claim 1 or 2, wherein the annealing atmosphere consists of nitrogen and hydrogen, and the concentration of hydrogen in the annealing atmosphere is at least 1 atomic percent and 10 atomic percent or less.

4. - The silicon-containing interface layer (22) is made of nitrogen or produced in an intermediate atmosphere containing nitrogen, and the finished interface layer is made of silicon nitride. The step of generating the silicon-containing interface layer (22) is: - A step of directly generating a silicon layer having a maximum thickness of 5 nm on the upper side (10), The method according to any one of the preceding claims, comprising the step of annealing the silicon layer in a nitrogen-containing atmosphere at a temperature of at least 1200°C to produce the silicon-containing interface layer (22).

5. - The method according to any one of the preceding claims, wherein the dielectric layer (2) is annealed at atmospheric pressure ±20%.

6. - The method according to any one of the preceding claims, wherein the dielectric layer (2) is applied by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

7. - The method according to any one of the preceding claims, wherein the dielectric layer (2) is applied to a maximum thickness of 200 nm.

8. - A method according to at least one embodiment, further comprising the step of applying a further dielectric layer on the conductive layer (3).

9. - The dielectric layer (2) is a gate dielectric, - The conductive layer (3) is a gate electrode, and the method further, - The method according to claim 8, further comprising the step of providing a first main electrode (4) on the further dielectric layer.

10. A semiconductor device (100), - A semiconductor body (1) made of SiC having an upper part (10), - A silicon-containing interface layer (22) located directly above the upper side (10) and having a maximum thickness of 5 nm, - A nitride-based dielectric layer (2) located directly on the silicon-containing interface layer (22) having a thickness of at least 5 nm, - Includes a conductive layer (3) located directly on the dielectric layer (2), - The nitride-based dielectric layer (2) is a semiconductor device (100) in which hydrogen atoms are contained in the nitrogen vacancies.

11. - The semiconductor device (100) according to claim 10, wherein the concentration of hydrogen in the nitride-based dielectric layer (2) is at least 0.1 atomic percent.

12. - The semiconductor device (100) according to claim 10 or 11, wherein the semiconductor device (100) is a power semiconductor device.

13. - The semiconductor device (100) is an insulated gate device, - The semiconductor device (100) according to any one of claims 10 to 12, wherein the nitride-based dielectric layer (2) forms at least a portion of the gate dielectric.

14. - The semiconductor device (100) according to claim 13, wherein the semiconductor device (100) is a MOSFET, MISFET, or IGBT.

15. A semiconductor device (100) according to any one of claims 10 to 14, manufactured by the method described in any one of claims 1 to 9.

Images