Read operation with pattern analysis enabled in NAND components

Abstract

A method for enabling data to be read from memory comprises the steps of: applying a first reference drive voltage to the word line of a memory cell to generate a first resulting voltage level from each cell in the word line; and storing in memory a first logical value indicated by the first resulting voltage level for each memory cell. The method further comprises applying a second reference drive voltage to the word line of a memory cell to generate a second resulting voltage level from each cell in the word line, and simultaneously detecting in parallel a pattern of logical values ​​stored in memory. The memory is modified based on the second logical values ​​indicated by the second resulting voltage levels, and at least one of the first and second reference drive voltages is modified based on the data of the detected pattern.

Description

[Technical Field]

[0001] This disclosure relates to detecting patterns in data output by applying a read reference voltage to the word line of a memory cell, and more particularly to detecting patterns in intermediate data output by the word line after each reference voltage has been applied, when multiple reference voltages are used in a single-bit read operation. [Overview of the project]

[0002] In some memory devices, memory cells can store more than one bit per cell. For example, triple-level cell (TLC) memory can store a total of three bits, and there may be a total of eight different voltage levels representing each bit combination. One or more reference drive voltages may be used to determine the stored bit value. For example, in TLC memory, reading the most significant bit (MSB) may require only one reference drive voltage, while reading the central significant bit (CSB) may require three different reference drive voltages.

[0003] However, as the memory cell undergoes more read / write operations, the memory voltage corresponding to a particular bit combination may shift, and if one or more reference drive voltages are used to determine the stored bit value, erroneous reads may occur. Some techniques can use multiple read retry voltages instead as the reference drive voltage in response to the detection of erroneous reads (e.g., by cyclic redundancy check (CRC) of the output bit value), or can use an automatic reference counting (ARC) process to correct the reference voltage. However, both processes require processing time and can delay read / write operations (e.g., from the memory device to the host device).

[0004] According to some embodiments of the present disclosure, methods and systems are provided herein for dynamically selecting a reference drive voltage based on a detection pattern at the output of a memory cell's word line before a single bit is read (for example, while applying the first and second reference voltages among three voltages required to read the CSB of a 3-bit cell). In some embodiments, a detection pattern may be detected based on the first reference drive voltage while a second reference drive voltage is input during the read process. In some embodiments, a second detection pattern may be detected based on the first and second reference drive voltages while a third reference drive voltage is input during the read process. In some embodiments, the reference drive voltages can be any number between 2 and 7, and each detection pattern corresponds to its respective applied drive voltage.

[0005] It should be noted that the “first” and “second” reference drive voltages described herein are intended to describe the order in which such voltages are applied, and are not limited to specifically referring only to the first and second actual reference voltages applied to the word line of the memory cell to read one of the bit positions. For example, in a memory cell that stores 3 bits, the “first” reference drive voltage may refer to the first or second actual reference voltage, and the “second” reference drive voltage may refer to the second or third actual reference voltage.

[0006] In another example where reading a bit in a memory cell (e.g., one that stores at least 2 bits) requires, for example, seven reference drive voltages, the first reference drive voltage could refer to any of the first through sixth actual reference voltages, and the second reference drive voltage could refer to any of the second through seventh actual reference voltages. More generally, for any cell that stores at least 2 bits, in a read operation (e.g., on one of the stored bits) that requires n+1 reference drive voltages, the "first" reference drive voltage could refer to any of the first through n actual reference drive voltages, and the "second" reference drive voltage could refer to an actual reference drive voltage applied after the "first" reference drive voltage, as shown in the table below. [Table 1]

[0007] In some embodiments, a method for enabling data to be read from memory comprises the step of applying a first reference drive voltage to the word line of memory cells to generate a first resulting voltage level from each cell in the word line. For each first resulting voltage level output by each cell in the word line, a first logical value indicated by each first resulting voltage level is stored in memory (e.g., each latch coupled to each each memory cell). The method further comprises applying a second reference drive voltage to the word line of memory cells to generate a second resulting voltage level from each cell in the word line and simultaneously detecting a pattern of logical values ​​stored in memory. For each second resulting voltage level output by each cell in the word line, the memory is modified based on the second logical value indicated by each second resulting voltage level. At least one of the first and second reference drive voltages is modified based on the detected pattern data. In some embodiments utilizing more than two reference drive voltages, the method further comprises the step of applying each additional reference voltage to the word line of a memory cell to generate each additional resulting voltage level from each cell in the word line to be stored in memory. The method further comprises detecting a pattern of logical values ​​in memory while each additional reference voltage is applied, the pattern of logical values ​​in memory being detected before the newly additional resulting voltage level is stored in memory.

[0008] According to some embodiments of the present disclosure, the system comprises a memory, a word line of memory cells configured to store data, and a control circuit. The control circuit is configured to apply a first reference drive voltage to the word line of memory cells to generate a first resulting voltage level from each cell in the word line. For each first resulting voltage level output by each cell in the word line, the control circuit stores in the memory a first logical value indicated by the first resulting voltage level. The control circuit then applies a second reference voltage to the word line of memory cells to generate a second resulting voltage level from each cell in the word line, while simultaneously detecting a pattern of logical values ​​stored in the memory. For each second resulting voltage level output by each cell in the word line, the control circuit modifies the memory based on a second logical value indicated by the second resulting voltage level. The control circuit is further configured to modify the first reference drive voltage and at least one of the second reference drive voltages based on the detected pattern data. A correction of at least one reference drive voltage may occur, for example, when an incorrect read operation occurs (e.g., if the incorrect read can be detected by cyclic redundancy check (CRC) or other suitable process). In some applications where there is no intermediate reference drive voltage pattern detection, when an incorrect read occurs, a read retry process is performed and the reference drive voltage is readjusted. However, in the case of only a final read operation output, all reference drive voltages are retried until the combination of reference voltages successfully returns the correct bits (e.g., the read retry process may be repeated multiple times), with each retry being an additional read operation. Further retries increase the delay time of the initially requested read operation.Therefore, by obtaining intermediate data outputs from each reference drive voltage, as well as the final read operation output, the process of readjusting the reference drive voltage (for example, in the event of an incorrect read) is simplified, resulting in fewer retries and reduced overhead delay time for the read operation. [Brief explanation of the drawing]

[0009] This disclosure in one or more different embodiments is described in detail with reference to the following figures. These figures are provided for illustrative purposes only and merely illustrate representative or exemplary embodiments. They are provided to facilitate understanding of the concepts disclosed herein and should not be considered to limit the breadth, scope, or applicability of those concepts. Note that for clarity and ease of representation, the figures are not necessarily drawn to scale.

[0010] [Figure 1] The following are block diagrams of systems including a host communicatively coupled to a memory device, according to some embodiments of the present disclosure.

[0011] [Figure 2] The following are block diagrams of word lines of memory cells coupled to a set of latches according to some embodiments of the present disclosure.

[0012] [Figure 3A] The present disclosure shows exemplary timelines of the process for reading intermediate bits of the word line of a memory cell and the corresponding pattern detection process according to some embodiments of this disclosure.

[0013] [Figure 3B] The following is an exemplary timeline of the second reference voltage detection process described in Figure 3A, according to some embodiments of the present disclosure.

[0014] [Figure 4A]Shows an intermediate bit (CSB) read process of a triple-level cell (TLC) flash memory cell without a pattern detection process according to some embodiments of the present disclosure. [Figure 4B] Shows an intermediate bit (CSB) read process of a triple-level cell (TLC) flash memory cell without a pattern detection process according to some embodiments of the present disclosure.

[0015] [Figure 5] Shows a CSB read process of a TLC flash memory cell including a pattern detection process according to some embodiments of the present disclosure.

[0016] [Figure 6A] Shows an exemplary flowchart of a read process including a pattern detection process performed during program interruption according to some embodiments of the present disclosure. [Figure 6B] Shows an exemplary flowchart of a read process including a pattern detection process performed during program interruption according to some embodiments of the present disclosure.

[0017] [Figure 7] Shows an exemplary flowchart of steps for dynamically modifying one or more read reference drive voltages based on data of a detected pattern according to some embodiments of the present disclosure.

[0018] [Figure 8] Shows a flowchart of steps for modifying at least one of a first drive voltage or a second drive voltage according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

[0019] In memory devices that include a word line of memory cells, multiple reference drive voltages may be used to determine the bit values ​​stored in the memory cells. However, as the memory cells undergo more read / write operations, the storage voltage corresponding to a particular bit combination may shift, and using one or more reference drive voltages to determine the stored bit values ​​may result in unstable or erroneous reads.

[0020] According to some embodiments of the present disclosure, a method and system for dynamically selecting a reference drive voltage based on a pattern detected for each reference drive voltage applied to the word line of a memory cell are provided herein. The method and system provided herein may be used to dynamically select or detect patterns for two further reference drive voltages. In some embodiments, a pattern may be detected based on the first reference drive voltage while a second reference drive voltage is input in the read process. In some embodiments utilizing at least a third reference drive voltage, a second detection pattern may be detected based on the first and second reference drive voltages while a third reference drive voltage is input in the read process. In some embodiments utilizing more than three reference drive voltages, this process may be repeated until each respective reference drive voltage is input to the read process. The present disclosure aims to reduce overhead delay time during a read operation in the event of an incorrect read.

[0021] Figure 1 shows a block diagram of a system 100, including a host device 102 communicatively coupled to a memory device 108, according to some embodiments of the present disclosure. The host device 102 may be, for example, a computer (e.g., equipped with an onboard memory device 108) or any other suitable computing device that utilizes read and / or write operations from memory. As shown, the host device 102 is coupled to the memory device 108. In some embodiments, the memory device 108 may be located inside the host 102, or it may be located outside the host 102. In some embodiments, the devices may be coupled via one or more buses using a non-volatile memory express (NVMe) on a peripheral component interconnect express (PCIe). However, it should be understood that any other suitable protocol or combination of protocols may also be used. For example, such protocols may include Serial Attached Small Computer System Interface (SAS), Serial Advanced Technology Attachment (SATA), any other suitable protocol, or any combination thereof.

[0022] The host device 102 includes a control circuit 104, memory 105, and input / output (I / O) circuit 106, but it will be understood that in other preferred embodiments, the host device 102 may include other components. For example, the control circuit 104 may include a controller, which may include one or more central processing units (CPUs), or one or more programmable logic arrays (PLAs), one or more field programmable gate arrays (FPGAs), one or more complex programmable logic devices (CPLDs), any other preferred controller circuit, or any combination thereof. The memory 105 may include random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, any other preferred memory, or any combination thereof. In some embodiments, the I / O circuit 106 may include a PCIe adapter for connecting the host device 102 and the memory device 108 in a communicative manner (e.g., via one or more buses) (e.g., using the PCIe protocol over NVMe). In some embodiments, the host device 102 may store information in the memory device 108 via the I / O circuit 106 (e.g., from users utilizing the host device 102, external servers, operating systems, other suitable applications, or a combination thereof).

[0023] The memory device 108 includes a controller 110 and a word line of memory cells 115, each containing cells 1161-116 n Each of the series of latches 1181-118 nIt is coupled to. Although only one word line is shown for ease of reference, in some embodiments the memory device 108 may contain multiple word lines. In some embodiments the word line of memory cell 115 has 18,000 cells (for example, n is equal to 18,000, and the word line of memory cell 115 has cells 1161-116) 18000 It may include 20,000 cells (including), or any other suitable number of cells. The controller 110 includes a control circuit 111, which is configured to read data from or write data to the word line of the memory cell 115 by, for example, providing one or more reference drive voltages to the word line of the memory cell 115. In some embodiments, read and write operations in the memory device 108 occur when corresponding commands are received from the host device 102 (for example, via the I / O circuit 106). In some embodiments, cells 1161-116 n This could be a triple-level cell (TLC) flash memory. In some embodiments, a TLC flash memory may store voltages corresponding to combinations of three bits (e.g., the most significant bit, the middle bit, and the least significant bit). In some embodiments, the flash memory may contain any number of bits from 2 to 7, and may store a number of different voltages corresponding to the total number of combinations of bits to be stored. In an ideal TLC flash memory, eight different combinations of three bits may be represented by eight discrete voltage levels stored in the TLC flash memory. However, it will be understood by those skilled in the art that when read / write operations are performed on the TLC flash memory, the discrete voltages corresponding to each of the stored combinations of three bits may change or shift over time.

[0024] Cells 1161-116 n These are the latches 1181-118 n In some embodiments, each latch 1181-118 nmay include a sense-amp data latch (SDL), a transfer data latch (TDL), a counting-capable data latch (CDL), or a combination thereof. Latches 1181 to 118 n may store the information (e.g., bit data) included in each cell 1161 to 116 n In some embodiments, reading data from the word line of memory cell 115 may include reading the data in latches 1181 to 118 n For example, the latch read may be performed by control circuit 111 attached to memory device 105.

[0025] In some embodiments, reading data from the word line of memory cell 115 includes configuring control circuit 111 to apply one or more reference drive voltages to each memory cell 1161 to 116 n In some applications where multiple bits are stored in each memory cell 1161 to 116 n it is possible to utilize multiple drive voltages and bitwise logical operations to determine the value of a particular bit. For example, this specification provides an example directed to reading an intermediate bit (CSB) in a TLC flash memory cell (as described, for example, in FIGS. 3 to 5 below). However, those skilled in the art should understand that similar operations may be performed in suitable embodiments that store more or less than three bits per memory cell, determine different bit values (e.g., the most significant bit, or the least significant bit, other bits stored in each memory cell, or combinations thereof), or include combinations thereof.

[0026] As stated herein, the first and second reference drive voltages described herein are relative and are not limited to specifically referring only to the first and second actual reference voltages applied to the word line of the memory cell. For example, in a memory cell storing 7 bits, the first and second reference drive voltages described herein may refer to the second and third actual reference voltages, the third and fourth actual reference voltages, the sixth and seventh actual reference voltages, or any nth and (n+1)th actual reference voltages, respectively. In some embodiments including multiple iterations or pairs of reference drive voltages, the relative first and second reference drive voltages described herein may refer to different actual reference voltages in each iteration or pair. For example, in a memory cell storing 7 bits, the method described herein, utilizing a first reference drive voltage and a second reference drive voltage, is first applied to the first actual reference drive voltage and the second actual reference drive voltage, respectively, and then can be applied to the second actual reference drive voltage and the third actual reference drive voltage, any preferred nth actual reference drive voltage and (n+1) actual reference drive voltage, or any combination thereof. Similarly, the third reference drive voltage described herein is also relative, and if the first reference drive voltage represents the actual nth reference drive voltage, the third reference drive voltage may represent the (n+2)th actual reference drive voltage. For example, if the first reference drive voltage represents the fifth actual reference voltage, the third reference drive voltage represents the seventh actual reference voltage. Therefore, the following may be described in the context of CSB reading of the word line of a TLC flash memory cell, but in particular, when this disclosure applies to memory cells that store more than 3 bits, it will be understood that the first reference drive voltage, the second reference drive voltage, and the third reference drive voltage may refer to any nth actual reference drive voltage, the (n+1)th actual reference drive voltage, and the (n+2)th actual reference drive voltage, respectively.

[0027] Figure 2 shows a series of latches 1181-118 according to several embodiments of the present disclosure. nThe block diagram shows the word line of the memory cell 115 coupled to the series of latches 1181-118. n Each latch is a sense amplifier data latch (SDL) 1201-120 n , each of the transfer data latches (TDL) 1221~122 n , and their respective count-corresponding data latches (CDL) 1241~124 n This may include. In other embodiments, other combinations of latches may be preferred, with each latch 1181-118 n It will be understood that this may include additional latches.

[0028] The sense amplifier data latch 1201 may be configured to receive bit data as a voltage from cell 1161 and amplify the received voltage. In some embodiments, cell 1161 may contain any number of bits from 2 to 7. For example, cell 1161 may be a TLC flash memory and contain three different data bits accordingly. When data is read from cell 1161, each bit may be read by utilizing one or more reference drive voltages. Using the above example where cell 1161 is a TLC flash memory, three reference drive voltages (for example, the three reference drive voltages may be referred to herein as a first reference drive voltage R2, a second reference drive voltage R4, and a third reference drive voltage R6) may be utilized to read the intermediate bit (CSB), and each applied reference drive voltage outputs a bit (e.g., either 0 or 1) to SDL1201, where 0 corresponds to a first output voltage and 1 corresponds to a second output voltage having a discrete value distinct from the first output voltage. However, since the difference between the first and second output voltages may be small, the SDL1201 may amplify the output to increase the difference between the first and second output voltages (for example, to prevent reading errors).

[0029] The output bit value (represented, for example, by an amplified voltage level) is then transmitted to a transfer data latch (TDL) 1221, which may function as a temporary memory holding the output bit value. In some embodiments, the TDL 1221 may hold the output bit value until a latch read is performed. As shown in Figure 1, a latch read may be performed, for example, by a control circuit 111, and the latch read may involve reading data in the TDL 1221. In some embodiments, a bit value previously stored in the TDL 1221 may be compared with a new bit value received from the SDL 1201. For example, a comparison may be performed if multiple reference drive voltages are used for a bit read (e.g., a CSB read). An exemplary example of the comparison process is shown in Figure 4B.

[0030] According to some embodiments of the present disclosure, the latch 1181 may further include a count-responsive data latch (CDL) 1241. The CDL 1241 may receive a bit value stored in the TDL 1221. In some embodiments, a latch read (performed, for example, by the control circuit 111 shown in Figure 1) may read a bit value stored in the CDL 1241 instead of data stored in the TDL 1221. In some embodiments, a latch read may read data stored in the TDL 1221, and data stored in the CDL 1241 may instead be read as part of a different pattern detection process performed by the control circuit 111.

[0031] Only latch 1181, including SDL1201, TDL1221, and CDL1241, will be described, but other cells 1162-116 nIt will be understood that each corresponding latch is similar to the latch described above. Thus, the pattern detection process can count the total number of logical 1 bits, the total number of logical 0 bits, or combinations thereof across all CDLs in the word line of memory cell 115. Furthermore, according to some embodiments of this disclosure, the pattern detection process can be performed simultaneously with a reading process (e.g., utilizing multiple reference drive voltages), a comparison process (in TDL), or a combination thereof.

[0032] In applications that do not include a pattern detection process, a read operation performed by the memory device 105 (e.g., requested by the host device 102) may return the requested bit from each cell in the word line of the memory cell, but not intermediate data (e.g., the output resulting from each applied reference drive voltage, the output resulting from bitwise logical operations, or a combination thereof). However, as illustrated in Figure 1, when a read / write operation is performed on the TLC flash memory, the discrete voltages corresponding to each combination of three stored bits may change or shift over time. If the reference drive voltages are not changed accordingly, an incorrect read may occur. When an incorrect read is detected (e.g., by cyclic redundancy check (CRC) of the output bit values) and a subsequent retry process is applied to select a different reference drive voltage, the memory device 105 may have little or no information about which reference drive voltage is incorrect or which intermediate stage is returning an incorrect result. Therefore, a controller attached to the memory device (e.g., controller 110) retries at a predetermined set of reference drive voltage levels, based on previous trends and patterns observed in the shift of the stored voltage level over time, which may result in lower accuracy and a higher number of retries (e.g., corresponding to a large overhead delay time in the requested read operation). By performing pattern analysis and / or bit counting on the output for each reference drive voltage, it becomes easier to infer which reference drive voltage and / or stage caused the incorrect read in the read operation, resulting in higher accuracy in the read retry process (e.g., fewer retries required, resulting in a shorter delay time). Furthermore, as described below, the pattern analysis process is performed in parallel with the read operation, resulting in little to no additional overhead delay time from the pattern analysis process itself (however, more processing power and / or additional latches (e.g., CDLs) are required per memory cell).

[0033] Figure 3A shows an exemplary timeline of a process 300 for reading intermediate bits of a word line of a memory cell and a corresponding pattern detection process according to several embodiments of the present disclosure. Figure 3A shows an example of the method and system described in Figures 1 and 2 in an application targeting the reading of each CSB of the word line of a TLC flash memory cell (e.g., each memory cell stores 3 bits). Although Figure 3A is described in the context of the specific structures, components, and processes of the present disclosure, it will be understood that in some embodiments, one or more processes described in Figure 3A may be modified, moved, deleted, or added for reading different bits (e.g., MSB, LSB, other preferred bits, or combinations thereof) and / or different types of memory cells (e.g., storing different numbers of bit counts per cell).

[0034] At time t0, a read command 302 is received and processed, which may be provided by an external host (e.g., host device 102) of the memory device. In some embodiments, the read command 302 may be processed and then executed by a control circuit 111, an external controller, or a combination thereof. At time t1, in the R2 detection process 304, a first reference drive voltage R2 is applied to the word line of the memory cell, and the output bits from each memory cell may be sent to their respective SDLs, for example, as shown in Figure 2. As described above, eight discrete voltage levels may be stored in the TLC flash memory cell, each voltage level corresponding to a different combination of three binary bits, and three reference drive voltages are required to read the CSB value. When a reference drive voltage is applied, if the voltage level stored in the TLC flash memory is higher than the applied reference drive voltage, the voltage corresponding to logic 0 is returned (e.g., output to the SDL), and if the voltage level stored in the TLC flash memory is lower than the applied reference drive voltage, the voltage corresponding to logic 1 is returned. In some embodiments, if any output voltage is detected, the logic value may be determined to be 0, and if no output voltage is detected, the logic value may be determined to be 1. In some embodiments, if any output voltage is detected, the logic value may be determined to be 1, and if no output voltage is detected, the logic value may be determined to be 0. The return voltage is amplified by the SDL (for example, to more clearly distinguish between logic 0 and logic 1) and transmitted to the TDL and CDL.

[0035] At time t2, the output bits from each cell from the R2 detection process 304 are completed, and the second reference drive voltage R4 is applied to the word line of the memory cell in the R4 detection process 306. Similar to the R2 detection process 304, in response to the applied second reference drive voltage R4, the output bits from each memory cell are sent to their respective SDLs and may be amplified. Once the data is amplified in the SDLs, additional operations may be required to correctly read and return the bit value (e.g., CSB) stored in memory. In some embodiments, the additional operations may be bitwise logical operations in each TDL, each bitwise logical operation including negating an input bit value (e.g., output in response to the applied second reference drive voltage R4), and then performing an OR operation on the negated input bit value and the bit value currently stored in the TDL (e.g., output from the applied first reference drive voltage R2). The logical operation processes are described in more detail in Figure 4B. The output of the bitwise logical operation is stored in the respective TDL.

[0036] While the R4 detection process 306 is taking place at time t2, the R2 bit counting process 308, which is a pattern detection process, is also taking place. As previously stated, the pattern detection process is shown as a bit counting process, but it could be any preferred process for detecting patterns in the values ​​stored in the CDL of the word line of the memory cell. In some embodiments, the R2 bit counting process 308 may include calculating the number of logical 1s in the data stored in the TDL (for example, by sending the data stored in the TDL to the CDL for counting, as the TDL may be receiving other storage operations from the R4 detection process 306). However, it will be understood that the R2 bit counting process 308 may include additional processes, or that different processes may be used instead to determine patterns in the data stored in the TDL. For example, the R2 bit counting process 308 may include the number of logical 0s in the data stored in the TDL, the ratio of the total number of logical 1s to the total number of logical 0s in the TDL, or a combination thereof. In some embodiments, the time required to execute the R2 bit counting process 308 is shorter than the time required to execute the R4 detection process 306 (for example, shorter than the time value obtained by subtracting t2 from t3), and as a result, the R2 bit counting process 308 is performed without adding any overhead processing time to the execution of the reading process 300.

[0037] At time t3, the per-cell output bits from the R4 detection process 306 are completed, and the third reference drive voltage R6 is applied to the word line of the memory cell in the R6 detection process 310. The R6 detection process 310 is the same as the R4 detection process 306, except that the third reference drive voltage is applied, and in some embodiments, different bitwise logical operations are performed on each TDL compared to the bitwise logical operations performed in the R4 detection process 308. In some embodiments, each bitwise logical operation in the R6 detection process 310 includes an AND operation between the input bit value (e.g., output in response to the applied third reference drive voltage) and the bit value currently stored in the TDL. The logical operation process is described in more detail in Figure 4B. The value stored in each TDL is then replaced with the bit value obtained as a result of the bitwise logical operation for each TDL.

[0038] While the R6 detection process 310 is running, the R2+R4 bit counting process 312 is also running. The process of the R2+R4 bit counting process 312 is the same as the process described in the R2 bit counting process 308, but it counts the bits stored in the CDL as a result of the R4 detection process 306. In some embodiments, the time required to run the R2+R4 bit counting process 312 is shorter than the time required to run the R6 detection process 310 (for example, shorter than a time value equal to t4 minus t3), and as a result, the R2+R4 bit reading process 312 is run without adding any overhead processing time to the execution of the reading process 300.

[0039] At t4, the data-out process 314 completes the execution of the read command 302. During the data-out process 314, the control circuit 111 reads the data held in memory (e.g., TDL) containing the output bit value of the R6 detection process 310. It will be understood that the bit value read in the data-out process 314 represents the actual value of the CSB stored in the memory cell.

[0040] While the data-out process 314 is running, the R2+R4+R6 bit counting process 316 is also running. The process of the R2+R4+R6 bit counting process 316 is the same as the process described in the R2+R4 bit counting process 312, but it counts the bits stored in the CDL as a result of the R6 detection process 310. In some embodiments, the time required to run the R2+R4+R6 bit counting process 316 is shorter than the time required to run the data-out process 314, and as a result, the R2+R4+R6 bit reading process 316 is performed without adding any overhead processing time to the execution of the reading process 300.

[0041] Figure 3B shows an exemplary timeline 350 of the second reference drive voltage detection process described in Figure 3A, according to some embodiments of the present disclosure. As shown, the second reference drive voltage detection process is the R4 detection process 306, which is initiated at time t2 (e.g., time t2 in Figure 3A). The R4 detection process 306 is initiated at step 352, in which the second reference drive voltage is applied. In some embodiments, the application of the reference drive voltage to the word line occurs within 2 microseconds. Immediately thereafter, at time t2a, the bit line precharge process is performed at step 354, in which the applied voltage applied to the word line of the memory cell has time to pass through each of the memory cells. In some embodiments, the bit line precharge process is performed within 6 microseconds. Immediately thereafter, at time t2b, detection is performed at step 356. If voltage is detected (for example, if the applied reference drive voltage is higher than the memory cell voltage), logic 1 is output. If no voltage is detected in step 356 (for example, if the applied reference drive voltage is lower than the memory cell voltage), logic 0 is output.

[0042] At time t2c, detection in step 356 is completed, and a 0.5 microsecond break interval occurs in step 358. The bit value obtained as a result of the detection may be transferred to the SDL, where it is amplified and then sent to the TDL to be read or stored in memory and / or sent to the CDL to be counted. In some embodiments, the combination of steps 356 and 358 may occur within 1.5 microseconds.

[0043] While stages 352, 354, 356, and 358 of the R4 detection process 306 are taking place, the R2 bit counting process 308 is also taking place, as shown in Figure 3A. As illustrated, the R2 bit counting process 308 may start a little after time t2, as long as the R2 bit counting process 308 is completed before time t3.

[0044] Figures 4A–4B illustrate a CSB reading process 400 of a TLC flash memory cell that does not include a pattern detection process, according to several embodiments of the present disclosure. Similar to Figure 3, Figures 4A–4B illustrate examples of the methods and systems described in Figures 1 and 2 in applications targeting the reading of each CSB of the word line of a TLC flash memory cell (e.g., each memory cell stores 3 bits). While Figures 4A–4B are described in the context of the specific structures, components, and processes of the present disclosure, it will be understood that in some embodiments, one or more processes described in Figures 4A–4B may be modified, moved, deleted, or added for reading different bits (e.g., MSB, LSB, other preferred bits, or combinations thereof) and / or different types of memory cells (e.g., storing different numbers of bit counts per cell).

[0045] Figure 4A shows the drive voltages applied to a TLC flash memory cell that stores voltages corresponding to combinations of three bits. The TLC flash memory cell has eight discrete voltage levels 402a to 402h, each discrete voltage level corresponding to a different combination of three bits stored in the TLC memory cell. For example, voltage 402a may correspond to the binary value 111, voltage 402b may correspond to the binary value 110, and voltage 402h may correspond to the binary value 000. Three reference drive voltages (e.g., including a first reference drive voltage 404a, a second reference drive voltage 404b, and a third reference drive voltage 404c) may be required to determine the CSB in the CSB reading process 400. The first reference drive voltage 404a may be a voltage level between the voltage levels representing 110 and 101 (e.g., 402b and 402c, respectively). The second reference drive voltage 404b may be a voltage level between the voltage levels representing 100 and 011 (e.g., 402d, 402e), and the third reference drive voltage 404c may be a voltage level between the voltage levels representing 010 and 001 (e.g., 402f, 402g).

[0046] It will be understood that a non-ideal TLC flash memory cell will not store the exact voltage level for a given bit combination (for example, if the binary value 110 is stored in TLC flash memory, deleted, and then stored again, the two stored voltages will not necessarily be exactly equal). Because TLC flash memory cells have low overall voltages, maintaining accuracy in the stored voltage levels can be difficult. Therefore, voltage levels 402a to 402h are shown as probability distributions in Figure 4, where the value of the distribution function at a particular voltage level represents the probability that the corresponding bit combination is stored in the memory cell at that particular voltage level. As shown in the figure, the distribution for each combination of three binary bits is centered around the ideal discrete voltage level corresponding to that combination (e.g., where the probability is highest).

[0047] However, as mentioned above, in a non-ideal TLC flash memory cell, one or more combinations of stored voltage levels may shift as read / write operations are performed over time. For example, if the stored voltage level 402b increases over time and the first reference drive voltage 404a does not change, an increase in the number of erroneous reads may occur (for example, the CSB read process 400 may more often misread 1 bit as 0 bit, especially in the case of the binary value 110 in this example).

[0048] Figure 4B shows an exemplary chart 450 of the bit values ​​output at each stage of the CSB reading process 400 according to several embodiments of the present disclosure. In some embodiments, the output bit values ​​described in Figure 4B correspond to the output bit values ​​of the bitwise logical operations described in Figure 3A (e.g., at least in the R4 detection process and the R6 detection process). Column 452 shows eight possible combinations of three specific binary bits. As previously stated, each combination is represented as a discrete voltage level in the TLC flash memory cell. For each combination listed in column 452, the respective values ​​in column 454 indicate the bit value obtained after applying a first reference drive voltage R2 (e.g., 404a) to the TLC flash memory cell. A logic 1 is returned if the TLC flash memory cell is storing a voltage level lower than the first reference drive voltage, and a logic 0 is returned if the TLC flash memory cell is storing a voltage level higher than the first reference drive voltage. It will be understood that the output of column 454 is the output value of the R2 detection process (e.g., sent to SDL) which is stored in memory (e.g., TDL) and counted in CDL (e.g., in the R2 bit counting process).

[0049] For each combination listed in column 452, each value in column 456 represents the resulting bit value after applying a second reference drive voltage R4 (e.g., 404b) to the TLC flash memory cell. A logic value of 1 is returned if the TLC flash memory cell is storing a voltage level lower than the second reference drive voltage, and a logic value of 0 is returned if the TLC flash memory cell is storing a voltage level higher than the second reference drive voltage.

[0050] Next, the result in column 456 is negated, and a logical OR operation is performed between the negated value in column 456 and the corresponding bit value in column 454 (e.g., the value stored in TDL) to obtain the resulting bit value shown in column 458. It will be understood that the output of column 458 is the output value of the R4 detection process (e.g., sent to SDL) that is stored in memory (e.g., TDL) and counted in CDL (e.g., in the R2+R4 bit counting process).

[0051] For each combination listed in column 452, each value in column 460 represents the resulting bit value after applying a third reference drive voltage R6 (e.g., 404c) to the TLC flash memory cell. A logic value of 1 is returned if the TLC flash memory cell is storing a voltage level lower than the third reference drive voltage, and a logic value of 0 is returned if the TLC flash memory cell is storing a voltage level higher than the third reference drive voltage.

[0052] A logical AND operation is performed between the resulting value in column 460 and the corresponding bit value in column 458 (e.g., stored in TDL) to obtain the resulting bit value shown in column 462. It will be understood that the output of column 462 is the output value of the R6 detection process (e.g., sent to SDL) that is stored in memory (e.g., TDL) and counted in CDL (e.g., in the R2+R4+R6 bit counting process). As shown in the figure, the resulting bit value shown in column 462 corresponds precisely to the CSB value of each combination of bits in column 452.

[0053] Figure 5 shows a CSB reading process 500 of a TLC flash memory cell, including a pattern detection process, according to some embodiments of the present disclosure. Similar to Figure 3, Figure 5 shows examples of the methods and systems described in Figures 1 and 2 in applications targeting the reading of each CSB of a word line of a TLC flash memory cell (e.g., each memory cell stores 3 bits), and in some embodiments of different bit readings (e.g., MSB, LSB, other preferred bits, or combinations thereof) and / or different types of memory cells (e.g., storing a different number of bit counts per cell), one or more processes described in Figure 5 may be modified, moved, deleted, or added.

[0054] Similar to Figure 4A, Figure 5 includes eight discrete voltage levels 402a–402h corresponding to the probability distribution of voltages stored in the TLC flash memory cell for specific combinations of three binary bits. Figure 5 also includes three reference drive voltages 404a–404c (e.g., R2, R4, and R6, respectively).

[0055] The R2 detection process, the R4 detection process, and the R6 detection process are executed, and the first result 554, the second result 556, and the third result 562 are returned, respectively. The first result 554 corresponds to the result value of column 454 in Figure 4B, the second result 558 corresponds to the result value of column 458, and the third result 562 corresponds to the result value of column 462. In CSB reading processes without pattern detection, such as the CSB reading process 400, only the third result 562 is output by latch reading (e.g., the data-out process 314 in Figure 3A), where the third result 562 is the CSB value. However, in the CSB reading process 500 that utilizes a pattern detection process, the pattern detection process is executed on intermediate results 554 and 558. As shown in the figure, the pattern detection process is the bit count of logical 1s in the word line of the memory cell. In some embodiments, the pattern detection process may be the bit count of logical 1s, the bit count of logical 0s, the ratio of logical 1s to logical 0s, other preferred pattern detection processes, or a combination thereof. In some embodiments, as shown in Figure 2, bit counting can be performed using a series of CDLs for each cell in the word line of the memory cell, and the bit values ​​in the corresponding TDL (e.g., memory) are transferred to the CDL for bit counting while the bit values ​​in the TDL are being overwritten or read (e.g., when the next stage of the CSB read process is being performed).

[0056] When an incorrect read operation occurs (for example, detected by a CRC process), the memory device may determine, based on the detected pattern, which reference drive voltage may need to be adjusted. For example, if the R2 sensing process is expected to return approximately 50% logical 1s and 50% logical 0s (e.g., a random distribution), and pattern analysis determines that only 25% of the output bits from the R2 sensing process are logical 1s (e.g., the voltage stored in the memory cell is lower than the R2 voltage), then the R2 voltage is determined to be incorrect and may be shifted upward by a predetermined amount. In some embodiments, the predetermined amount may be a fixed value. In some embodiments, the predetermined amount may be variable based on the results returned by the sensing process. Subsequent reads will use this new R2 voltage in place of the previous R2 voltage until another incorrect read occurs and it becomes necessary to shift the reference drive voltage again.

[0057] Figures 6A and 6B show exemplary flowcharts 600 and 650, respectively, of a read process that includes a pattern detection process performed during program interruption, according to several embodiments of the present disclosure. The process described in Figures 6A and 6B pertains to the CSB read process of the word line of a TLC flash memory cell. For example, the word line of the memory cell corresponds to the word line of memory cell 115 in Figure 1, and memory cells 1161 to 116 n , and latches 1181-118 coupled accordingly n It may have latches 1181-118 nEach latch may include an SDL (e.g., SDL120), a TDL (e.g., TDL122), and a CDL (e.g., CDL124). Program interruption may occur, for example, when internal garbage collection or other preferred operation utilizing the memory (e.g., TDL or CDL) of a memory device (e.g., memory device 105 in Figure 1) is stopped, or when a read operation is requested (e.g., from host device 102). In some embodiments, when a program interruption occurs, the data corresponding to the interrupted program in the latch must be unreadable and held in the latch memory (e.g., to prevent loss). Therefore, interrupted data may be moved between latches, for example, while a detection and pattern detection process is being performed to perform a CSB read of the word line of a memory cell (e.g., the memory cell includes at least TLC flash memory cells).

[0058] As shown in Figure 2, latches (for example, latches 1181, 1182, ..., 118) n These may include SDL, TDL, and CDL. In illustrative flowcharts 600 and 650, SDL602 is all the SDLs in the word line of the memory cell (e.g., SDL1201, 1202, ..., 120 n ) may represent, TDL604 may represent all TDLs in the word line of the memory cell, and CDL606 may represent all CDLs in the word line of the memory cell. CDL606 may currently hold suspended program data, and the read process shown in flowcharts 600 and 650 may be started at step 612, where the suspended program data is transferred to the TDL (e.g., temporary memory).

[0059] In step 614, the R2 detection process (e.g., the R2 detection process 304 described in Figure 3) is executed, and the output bit value is sent to each SDL in the SDL602. As shown in Figure 2, the received voltage (e.g., corresponding to the output bit value) is amplified in the SDL602 so that the voltage difference between logic 1 and logic 0 is large (e.g., it becomes easier to distinguish between logic 1 and logic 0). The amplified R2 detection data is then sent to the CDL in step 616. In a normal reading process (e.g., without program interruption), it will be understood that in some embodiments the amplified detection data may be sent to the TDL604. However, since the current TDL604 holds interrupted program data, it may not have space in memory to hold the R2 detection data.

[0060] In step 618, the R4 detection process is initiated (as described, for example, in step 306 of Figure 3A). While R4 is detected and the output voltage is sent to the SDL602, which is currently empty, the CDL606 performs a pattern detection process in step 620 using the data currently stored in the CDL606. In some embodiments, the pattern detection process may be a logic 1 bit count. Once the R4 detection process is complete and each voltage has been amplified in the SDL602, the R4 detection data is sent to the CDL in step 622. If the additional bit count process in step 620 does not incur overhead time, it will be understood that the execution of step 620 may be completed before the R4 detection data is sent to the CDL in step 622.

[0061] When the R4 detection data is transmitted to the CDL606 in step 622, the R4 detection data can be compared with the respective R2 detection data using a bitwise logical operation. In some embodiments, the bitwise logical operation may involve negating the R4 detection data (i.e., ~SDL) and then performing an OR operation (i.e., (~SDL)|CDL) with the respective R2 detection data currently present in the CDL606.

[0062] In step 626, the R6 detection process is initiated (for example, as described in step 310 in Figure 3A). While R6 is detected and the output voltage is sent to the SDL602, which is currently empty, the CDL606 performs a pattern detection process in step 628 using the data currently stored in the CDL606. In some embodiments, the pattern detection process in step 628 may be a logic 1 bit count. Once the R6 detection process is complete and each voltage has been amplified in the SDL602, the R6 detection data is sent to the CDL in step 630. If the additional bit count process in step 628 does not incur overhead time, it will be understood that the execution of step 628 may be completed before the R6 detection data is sent to the CDL in step 630.

[0063] When the R6 detection data is transmitted to the CDL606 in step 632, the R6 detection data may be compared with each detection data currently present in the CDL606 (e.g., (~R4)|R2) using a bitwise logical operation. In some embodiments, the bitwise logical operation may be an AND operation between the R6 detection data (e.g., from SDL602) and the data currently present in the CDL606 (e.g., the bitwise logical operation may be written as R6||((~R4)|R2), or SDL&CDL).

[0064] In step 634, a pattern detection process may be performed on the result data from step 632 in CDL606. In some embodiments, the pattern detection process may be a bit count of logic 1. While step 634 is being executed, the suspended program data may be transferred to SDL602. It will be understood that the output data of the read process (e.g., the requested data) is represented by the result of step 632, and in order to read the data out process (e.g., the data out process 314 in Figure 3A), the data from step 632 must be in TDL604. Therefore, the suspended program data is moved to SDL602 to free up memory space in TDL604 (e.g., if the suspended program data cannot be immediately moved to CDL606 because CDL606 is storing the data from step 632). The data from step 632 in CDL606 is then transferred to TDL604, and the data is output in response to the requested read process. The suspended program data is then finally returned to CDL606 in step 640.

[0065] Figure 7 shows an exemplary flowchart 700 of steps for dynamically modifying one or more read reference drive voltages based on detected pattern data, according to some embodiments of the present disclosure. Although the steps in flowchart 700 are described as being performed by the control circuit 111 in Figure 1, the steps in flowchart 700 may also be performed by, for example, an external controller (e.g., one coupled to the memory device 105), an additional controller attached to the memory device, other suitable controllers and / or processors, or a combination thereof. Figure 7 is described in the context of the particular structures, components, and processes of the present disclosure, and while Figure 7 shows a particular order and flow of steps, it will be understood that in some embodiments, one or more steps may be modified, moved, deleted, or added, and the order of steps shown in Figure 7 may be modified.

[0066] As stated herein, the first and second reference drive voltages described herein are relative and are not limited to specifically referring only to the first and second actual reference voltages applied to the word line of the memory cell. For example, in a memory cell storing 7 bits, the first and second reference drive voltages described herein may refer to the second and third actual reference voltages, the third and fourth actual reference voltages, the sixth and seventh actual reference voltages, or any nth and (n+1)th actual reference voltages, respectively. In some embodiments including multiple iterations or pairs of reference drive voltages, the relative first and second reference drive voltages described herein may refer to different actual reference voltages in each iteration or pair. For example, in a memory cell storing 7 bits, the method described herein, utilizing a first reference drive voltage and a second reference drive voltage, is first applied to the first actual reference drive voltage and the second actual reference drive voltage, respectively, and then can be applied to the second actual reference drive voltage and the third actual reference drive voltage, any preferred nth actual reference drive voltage and (n+1) actual reference drive voltage, or any combination thereof. Similarly, the third reference drive voltage described herein is also relative, and if the first reference drive voltage represents the actual nth reference drive voltage, the third reference drive voltage may represent the (n+2)th actual reference drive voltage. For example, if the first reference drive voltage represents the fifth actual reference voltage, the third reference drive voltage represents the seventh actual reference voltage. Therefore, the following may be described in the context of CSB reading of the word line of a TLC flash memory cell, but in particular, when this disclosure applies to memory cells that store more than 3 bits, it will be understood that the first reference drive voltage, the second reference drive voltage, and the third reference drive voltage may refer to any nth actual reference drive voltage, the (n+1)th actual reference drive voltage, and the (n+2)th actual reference drive voltage, respectively.

[0067] The process begins in step 702, when a control circuit (e.g., control circuit 111 in Figure 1) applies a first reference drive voltage to each memory cell in the word line of the memory cells. In some embodiments, the first reference drive voltage may be R2 (e.g., as described in step 304 in Figure 3), and the word line of the memory cells may be word line 115 in Figure 1. Each memory cell (e.g., cells 1161, 1162, ..., 116) n ) generates the respective first resulting voltage levels in response to the applied first reference drive voltage. The process can then proceed to step 704.

[0068] In step 704, the control circuit (e.g., control circuit 111 in Figure 1) stores in memory each first logical value, which is represented by the voltage level obtained as each of the first results. In some embodiments, each first resulting voltage level may be one of two discrete voltage levels (e.g., the first resulting voltage levels correspond to binary bits). For example, if the first resulting voltage level is equal to a first possible voltage level, the respective logical value may be logical 1. If the first resulting voltage level is equal to a second possible voltage level, the respective logical value may be logical 0. In some embodiments, the possible voltage levels may be equal to 0. In some embodiments, each cell has one or more latches (e.g., latches 1181-118) n ) may be connected, and each latch may include a memory (e.g., TDL) for storing the output binary bit value from the applied first reference drive voltage. The process may then proceed to step 706.

[0069] In step 706, the control circuit (e.g., control circuit 111 in Figure 1) applies a second reference drive voltage to each memory cell in the word line of the memory cells. In some embodiments, the second reference drive voltage may be R4 (e.g., as described in step 306 in Figure 3). Each memory cell (e.g., cells 1161-116) n) generates the respective second resulting voltage levels in response to the applied second reference drive voltage. The process can then proceed to step 708.

[0070] In step 708, a control circuit (e.g., control circuit 111 in Figure 1) detects a pattern of logical values ​​stored in memory. As shown in the figure, step 708 may be performed in parallel with the elements of step 706. However, in some embodiments, it will be understood that step 708 may be performed after (e.g., sequentially) step 706. In some embodiments, the detected pattern is provided to an external controller coupled by the control circuit, which may perform further steps related to the detected pattern. In some embodiments, the pattern may be a bit count of the total number of logical 1s stored in memory (e.g., TDL in the word line of the memory cell). In some embodiments, the pattern may be a bit count of logical 0s, the ratio of the total number of logical 1s to the total number of logical 0s, other preferred patterns, or a combination thereof. In some embodiments, pattern detection may be performed while a second reference drive voltage is applied to the word line of the memory cell, generating the respective second resulting voltage levels. The process may then proceed to step 710.

[0071] In step 710, the control circuit (e.g., control circuit 111 in Figure 1) may modify the memory based on each second logical value indicated by each resulting voltage level. Similar to step 704, in some embodiments, each second voltage level may correspond to a binary bit (e.g., either logical 0 or logical 1, depending on the voltage level). In some embodiments, each second logical value may be compared with each first logical value (e.g., a value stored in memory) by a bitwise logical operation. For example, each second logical value may be negated, and each resulting negated second logical value may be compared with each first logical value by an OR operation. Thus, the resulting bit value may be stored in memory in place of each first logical value. The process may then proceed to step 712.

[0072] In step 712, a control circuit (e.g., control circuit 111 in Figure 1, or the aforementioned external controller) modifies at least one of the first reference drive voltage and the second reference drive voltage based on the detected pattern data. In some embodiments, the first reference drive voltage may be modified directly based on the detected pattern data. In some embodiments, the detected pattern data may be a total bit count of logic 1, and based on the expected distribution, the resulting number of logic 1 may indicate whether and how the first reference drive voltage should be modified. For example, if the expected distribution is 50% logic 1 and 50% logic 0 (e.g., the binary bit values ​​are random), then if the detected pattern is, for example, 80% logic 1 (e.g., the stored voltage level of the memory cell is lower than the first reference drive voltage) and 20% logic 0 (e.g., the stored voltage level of the memory cell is higher than the first reference drive voltage), then the first reference drive voltage may be modified to decrease by a predetermined amount. In some embodiments, the predetermined amount may be a fixed value. In some embodiments, a predetermined amount may be variable based on the returned result of the sensing process. In some embodiments, the modification of the second drive voltage may be based on a current modification value stored in memory (for example, based on the voltage levels obtained as a result of the first and second processes).

[0073] In some embodiments utilizing more than two reference voltages, it will be understood that the steps in Figure 7 may be repeated. Since the first and second reference drive voltages are relative, the steps in Figure 7 may be repeated for any nth actual reference voltage and (n+1)th actual reference voltage, respectively. For example, in a second iteration of the steps in Figure 7, the first reference drive voltage may refer to the second actual reference voltage, and the second reference drive voltage may refer to the third actual reference voltage. In some embodiments, the steps in Figure 7 may be repeated until all actual reference voltages have been corrected.

[0074] Figure 8 shows a flowchart 800 of steps for modifying at least one of the first or second drive voltages according to an embodiment of the present disclosure. Although the steps of flowchart 800 are described as being performed by the control circuit 111 of Figure 1, the steps of flowchart 800 may also be performed by, for example, an external controller (e.g., one coupled to the memory device 105), an additional controller attached to the memory device, other suitable controllers and / or processors, or a combination thereof. Figure 8 is described in the context of a particular structure, component, and process of the present disclosure, and while Figure 8 shows a particular sequence and flow of steps, it will be understood that in some embodiments one or more steps may be modified, moved, deleted, or added, and the sequence of steps shown in Figure 8 may be modified. For example, it will be understood that not all steps of Figure 8 may be performed every time a pattern analysis is performed, and in some embodiments, the steps of Figure 8 may only be performed when a reading error occurs (e.g., when detected by the CRC process, for example).

[0075] As stated herein, the first and second reference drive voltages described herein are relative and are not limited to specifically referring only to the first and second actual reference voltages applied to the word line of the memory cell. For example, in a memory cell storing 7 bits, the first and second reference drive voltages described herein may refer to the second and third actual reference voltages, the third and fourth actual reference voltages, the sixth and seventh actual reference voltages, or any nth and (n+1)th actual reference voltages, respectively. In some embodiments including multiple iterations or pairs of reference drive voltages, the relative first and second reference drive voltages described herein may refer to different actual reference voltages in each iteration or pair. For example, in a memory cell storing 7 bits, the method described herein, utilizing a first reference drive voltage and a second reference drive voltage, is first applied to the first actual reference drive voltage and the second actual reference drive voltage, respectively, and then can be applied to the second actual reference drive voltage and the third actual reference drive voltage, any preferred nth actual reference drive voltage and (n+1) actual reference drive voltage, or any combination thereof. Similarly, the third reference drive voltage described herein is also relative, and if the first reference drive voltage represents the actual nth reference drive voltage, the third reference drive voltage may represent the (n+2)th actual reference drive voltage. For example, if the first reference drive voltage represents the fifth actual reference voltage, the third reference drive voltage represents the seventh actual reference voltage. Therefore, the following may be described in the context of CSB reading of the word line of a TLC flash memory cell, but in particular, when this disclosure applies to memory cells that store more than 3 bits, it will be understood that the first reference drive voltage, the second reference drive voltage, and the third reference drive voltage may refer to any nth actual reference drive voltage, the (n+1)th actual reference drive voltage, and the (n+2)th actual reference drive voltage, respectively.

[0076] In step 802, a control circuit (e.g., control circuit 111 in Figure 1) detects a first pattern of logical values ​​stored in memory. In some embodiments, step 802 may correspond to step 706 in Figure 7, and as a result, steps 702 and 704 have already been performed (e.g., a first reference voltage is applied to the word line of the memory cell, and for each memory cell, each first output bit value is stored in memory). In some embodiments, the detected pattern may be a bit count of logical 1 (e.g., across the word line of the memory cell), a bit count of logical 0, a ratio of logical 1 to logical 0, another preferred pattern, or a combination thereof. For example, in the embodiments described, it will be understood that the detected pattern is a bit count of logical 1. The process may then proceed to step 804.

[0077] In step 804, a control circuit (e.g., control circuit 111, or an external controller in some embodiments) determines whether the number of logic 1s in the detected pattern is greater than a first specific number. In some embodiments, the first specific number may be based on the total number of memory cells in the word line, the expected distribution of logic 1s and logic 0s, or a combination thereof. As an exemplary example, for a word line of 18,000 memory cells and an expected distribution of 50% logic 1s, the first specific number may be set to approximately 10,000 (e.g., slightly above 50% to account for variance without overcompensating the reference drive voltage). If the number of logic 1s is greater than the first specific number (e.g., "yes" to step 804), the process may proceed to step 806. If the number of logic 1s is not greater than the first specific number (e.g., "no" to step 804), the process may proceed to step 808.

[0078] In step 806, the control circuit (e.g., control circuit 111 in Figure 1) reduces the first reference drive voltage. In some embodiments, this reduction may be based on how much larger the bit count of logic 1 is compared to a first specific number. For example, the larger the bit count of logic 1 (i.e., the further the bit count of logic 1 is from the first specific number), the further the first reference drive voltage deviates from the optimal first reference drive voltage. Thus, if the first specific number of word lines for 18,000 memory cells is, for example, 10,000 logic 1s, and the result of the bit count is 15,000 logic 1s, then a greater reduction in the first reference drive voltage may occur compared to, for example, the result of a bit count of 11,000 logic 1s. The process may then proceed to step 812.

[0079] In step 808, a control circuit (e.g., control circuit 111, or an external controller in some embodiments) determines whether the number of logic 1s in the detected pattern is less than a second specific number. In some embodiments, the second specific number may be based on the total number of memory cells in the word line, the expected distribution of logic 1s and logic 0s, or a combination thereof. As an exemplary example, for a word line of 18,000 memory cells and an expected distribution of 50% logic 1s, the second specific number may be set to approximately 8,000 (e.g., slightly below 50% to account for variance without overcompensating the reference drive voltage). If the number of logic 1s is less than the second specific number (e.g., "yes" to step 808), the process may proceed to step 810. If the number of logic 1s is not less than the second specific number (e.g., "no" to step 808), the process may proceed to step 812.

[0080] In step 810, the control circuit (e.g., control circuit 111 in Figure 1) increases the first reference drive voltage. In some embodiments, this increase may be based on how much smaller the bit count of logic 1 is compared to a second specific number. For example, the smaller the bit count of logic 1 (i.e., the further the bit count of logic 1 is from the second specific number), the further the first reference drive voltage deviates from the optimal first reference drive voltage. Thus, if the second specific number of word lines for 18,000 memory cells is, for example, 8,000 logic 1, and the result of the bit count is 3,000 logic 1, then a larger increase in the first reference drive voltage may occur compared to, for example, the result of a bit count of 6,000 logic 1. The process may then proceed to step 812.

[0081] In step 812, a control circuit (e.g., control circuit 111 in Figure 1) determines a second pattern of logical values ​​based on the value stored in memory. In some embodiments, step 812 may occur if the word line of the memory cell is the word line of a TLC flash memory cell (or having more than three levels, such as a quad-level cell (QLC)) and the read process utilizes more than one reference drive voltage (e.g., CSB read). While steps 804 to 810 are being performed, a second reference drive voltage is applied to the word line of the memory cell, and the value stored in memory will be a new value based on the output bit values ​​of the applied second reference drive voltage (e.g., a bitwise logical operation between each bit value output by the second reference drive voltage and each bit value output by the first reference drive voltage). In some embodiments, the second pattern of logical values ​​may be a bit count of logical 1 (e.g., counting the bits of the new value stored in memory), a bit count of logical 0, a logical 1 to logical 0 ratio, another preferred pattern, or a combination thereof. Next, the process may proceed to stage 814.

[0082] In step 814, a control circuit (e.g., control circuit 111, or in some embodiments, an external controller) determines whether the number of logic 1s in the second detected pattern is greater than a first specific number. In some embodiments, the first specific number may be the first specific number determined in step 804. If the number of logic 1s is greater than the first specific number (e.g., "yes" to step 814), the process may proceed to step 816. If the number of logic 1s is not greater than the first specific number (e.g., "no" to step 814), the process may proceed to step 818.

[0083] In step 816, the control circuit (e.g., control circuit 111 in Figure 1) reduces the second reference drive voltage. In some embodiments, this reduction may be based on how much greater the bit count of logic 1 is compared to a first specific number. For example, the greater the bit count of logic 1 (i.e., the further the bit count of logic 1 is from the first specific number), the further the second reference drive voltage deviates from the optimal second reference drive voltage. Thus, if the first specific number of word lines for 18,000 memory cells is, for example, 10,000 logic 1, and the result of the bit count is 15,000 logic 1, then a greater reduction in the second reference drive voltage may occur compared to, for example, the result of a bit count of 11,000 logic 1. The process may then proceed to step 822.

[0084] In step 818, a control circuit (e.g., control circuit 111, or an external controller in some embodiments) determines whether the number of logic 1s in the detected pattern is less than a second specific number. In some embodiments, the second specific number may be the second specific number determined in step 808. If the number of logic 1s is less than the second specific number (e.g., "yes" to step 818), the process may proceed to step 820. If the number of logic 1s is not less than the second specific number (e.g., "no" to step 818), the process may proceed to step 822.

[0085] In step 820, the control circuit (e.g., control circuit 111 in Figure 1) increases the second reference drive voltage. In some embodiments, this increase may be based on how much smaller the bit count of logic 1 is compared to a second specific number. For example, the smaller the bit count of logic 1 (i.e., the further the bit count of logic 1 is from the second specific number), the further the second reference drive voltage deviates from the optimal second reference drive voltage. Thus, if the second specific number of word lines for 18,000 memory cells is, for example, 8,000 logic 1, and the result of the bit count is 3,000 logic 1, then a larger increase in the second reference drive voltage may occur compared to, for example, the result of a bit count of 6,000 logic 1. The process may then proceed to step 822.

[0086] In step 822, the control circuit (e.g., control circuit 111 in Figure 1) applies the modified (or, if determined to be "no" in step 808, step 818, or both) first and second reference drive voltages to the word line of the memory cell. In some embodiments, the application of the modified reference drive voltages occurs in a subsequent read operation (e.g., when the process may return to 802 as the next output bit value from the word line is counted). In some embodiments using more than two reference drive voltages (e.g., CSB reads), an additional step may be included in flowchart 800 to determine whether the additional reference drive voltages should be increased, decreased, or left unchanged, and to apply the modified additional reference drive voltages in subsequent reads.

[0087] In some embodiments utilizing more than two reference voltages, it will be understood that the steps in Figure 8 may be repeated. Since the first and second reference drive voltages are relative, the steps in Figure 8 may be repeated for any nth actual reference voltage and (n+1)th actual reference voltage, respectively. For example, in a second iteration of the steps in Figure 8, the first reference drive voltage may refer to the second actual reference voltage, and the second reference drive voltage may refer to the third actual reference voltage. In some embodiments, the steps in Figure 8 may be repeated until all actual reference voltages have been corrected.

[0088] The matters described above are merely illustrative of the principles of this disclosure, and various modifications may be made by those skilled in the art without departing from the scope of this disclosure. The embodiments described above are presented for illustrative purposes and are not limiting. This disclosure can take many forms other than those expressly described herein. Accordingly, it should be emphasized that this disclosure is not limited to the methods, systems, and apparatus expressly disclosed, but is intended to include variations and modifications thereof, within the spirit of the following paragraphs.

[0089] While some parts of this disclosure may refer to examples, such references are solely for the purpose of providing context to this disclosure and do not constitute any determination of the state of the art.

Claims

1. A method for enabling the reading of data from memory, wherein the method is A step of applying a first reference drive voltage to the word line of a memory cell to generate a first resulting voltage level from each cell in the word line; A step of storing in memory a first logical value indicated by each first resulting voltage level output by each cell in the word line; A step of applying a second reference drive voltage to the word line of the memory cell to generate the respective second resulting voltage levels from each cell in the word line; A step of detecting a pattern of logical values ​​stored in the memory; For each second resulting voltage level output by each cell of the word line, the memory is modified based on the respective second logical value indicated by the respective second resulting voltage level: and A step of modifying at least one of the first reference drive voltage and the second reference drive voltage based on the detected pattern data. A method that includes [a certain feature].

2. The method according to claim 1, wherein the step of detecting the pattern of logical values ​​is performed in parallel with the step of applying the second reference drive voltage to the word line of the memory cell.

3. The method described above is The method according to claim 1 or 2, further comprising the step of applying the modified first reference drive voltage and the second reference drive voltage to the word line of the memory cell in a subsequent read operation.

4. The step of detecting the aforementioned pattern of logical values ​​is The method according to claim 1 or 2, further comprising the step of detecting the pattern of logical values ​​while applying the second reference drive voltage to the word line of the memory cell and before modifying the memory based on each of the second logical values.

5. The method according to claim 1 or 2, wherein the step of detecting the pattern of logical values ​​stored in the memory includes the step of calculating the number of logical values ​​stored in the memory.

6. The method according to claim 5, wherein the step of modifying at least one of the first reference drive voltage and the second reference drive voltage based on the detected pattern data includes the step of reducing the first reference drive voltage in response to the determination that the number of logic 1s in the pattern of logic values ​​is greater than a first specific number.

7. The method according to claim 5, wherein the step of modifying at least one of the first reference drive voltage and the second reference drive voltage based on the detected pattern data includes the step of increasing the first reference drive voltage in response to the determination that the number of logic 1s in the pattern of logic values ​​is smaller than a second specific number.

8. The method according to claim 1 or 2, wherein the step of detecting the pattern of logical values ​​stored in the memory includes the step of calculating the number of logical zeros stored in the memory.

9. The method according to claim 1 or 2, wherein the step of detecting the pattern of logical values ​​stored in the memory includes the step of calculating the ratio of logical 1 and logical 0 stored in the memory.

10. The method according to claim 1 or 2, wherein the memory has an array of latches, and each latch in the array of latches stores a logical value.

11. The aforementioned pattern of logical values ​​is the first pattern, and the method is The method according to claim 1 or 2, further comprising the step of detecting a second pattern of logical values ​​based on each of the second logical values ​​stored in the memory.

12. The method described above is A step of applying a third reference drive voltage to the word line of memory cells to generate a third resulting voltage level from each cell in the word line; A step of detecting a second pattern of logical values ​​stored in the modified memory; For each third resulting voltage level output by each cell of the word line, the memory is modified based on the respective third logical value indicated by the respective third resulting voltage level: and A step of modifying at least one of the first reference drive voltage, the second reference drive voltage, or the third reference drive voltage based on the detected first pattern data or the detected second pattern data. The method according to claim 11, further comprising:

13. The memory cell has a multilevel flash memory cell including at least two reference bits and up to seven reference bits, and the method is The method according to claim 1 or 2, further comprising the step of reading at least one bit of each memory cell using more than one reference drive voltage.

14. The memory cell has a triple-level cell (TLC) flash memory cell, and the method is The method according to claim 12, further comprising the step of reading the intermediate bit (CSB) of each of the memory cells.

15. The step of modifying the memory based on each of the second logical values ​​includes storing the result of a first bitwise logical operation between each of the stored first logical values ​​and each of the second logical values, and The method according to claim 12, wherein the step of modifying the memory based on each of the third logical values ​​includes the step of storing the result of a second bitwise logical operation between each of the logical values ​​stored in the modified memory based on each of the third logical values ​​and each of the second logical values.

16. The first bitwise logical operation between each stored first logical value and each of the second logical values ​​comprises the steps of negating each of the second logical values, and then performing an OR operation between the negated second logical value and each of the stored first logical values; and The method according to claim 15, wherein the second bitwise logical operation between each third logical value and each of the logical values ​​stored in the modified memory based on each of the second logical values ​​comprises the step of performing an AND operation between each of the third logical values ​​and each of the logical values ​​stored in the modified memory.

17. The step of detecting the first pattern of logical values ​​stored in the memory includes the step of calculating the number of logical values ​​stored in the memory before modifying the memory based on each of the second logical values; and The method according to claim 12, wherein the step of detecting the second pattern of logical values ​​stored in the memory includes the step of calculating the number of logical 1s stored in the memory after modifying the memory based on each of the second logical values ​​and before modifying the memory based on each of the third logical values.

18. The method described above is (a) A step of applying a fourth reference drive voltage to the word line of the memory cell to generate a fourth resulting voltage level from each of the cells in the word line; (b) The step of detecting a third pattern of logical values ​​stored in the modified memory; (c) For each fourth resulting voltage level output by each cell in the word line, modify the memory based on the respective fourth logical value indicated by the respective fourth resulting voltage level; A step of repeating steps (a) to (c) for any additional reference drive voltage; and A step of correcting at least one of the reference drive voltages based on at least one of the detected pattern data. The method according to claim 12, further comprising:

19. Memory; Wordline of a memory cell configured to store data; A first reference drive voltage is applied to the word line of the memory cell to generate a first resulting voltage level from each cell in the word line; For each first resulting voltage level output by each cell in the word line, the memory stores the respective first logical value indicated by each of the first resulting voltage levels; A second reference drive voltage is applied to the word line of the memory cell to generate the second resulting voltage levels from each cell in the word line; The pattern of logical values ​​stored in the memory is detected; For each second resulting voltage level output by each cell of the word line, the memory is modified based on the respective second logical value indicated by each second resulting voltage level: and Based on the detected pattern data, at least one of the first reference drive voltage and the second reference drive voltage is modified. Control circuit configured in such a way A system that includes these features.

20. The control circuit, The system according to claim 19, further configured to apply the modified first reference drive voltage and the second reference drive voltage to the word line of the memory cell during subsequent read operations.

21. The system according to claim 19 or 20, wherein the control circuit is configured to detect the pattern of logical values ​​stored in the memory by calculating the number of logical 1s stored in the memory.

22. The system according to claim 19 or 20, wherein the memory has an array of latches, and each latch in the array of latches is configured to store a logical value.

23. The pattern of logic 1 is the first pattern, and the control circuit is A third reference drive voltage is applied to the word line of the memory cell to generate the respective third resulting voltage levels from each cell in the word line; Based on the respective second logical values ​​stored in the modified memory, a second pattern of logical values ​​is detected; For each third resulting voltage level output by each cell of the word line, the memory is modified based on the respective third logical value indicated by each third resulting voltage level: and The system according to claim 19 or 20, further configured to modify at least one of the first reference drive voltage, the second reference drive voltage, or the third reference drive voltage based on the detected first pattern data or the detected second pattern data.

24. The memory cell has a multilevel flash memory cell including at least two reference bits and up to seven reference bits, and the control circuit is The system according to claim 19 or 20, further configured to read at least one bit of each memory cell using more than one reference drive voltage.

25. The control circuit, The memory is modified based on each of the second logical values ​​by storing the result of a first bitwise logical operation between each of the stored first logical values ​​and each of the stored second logical values, and The system according to claim 23, configured to modify the memory based on each of the third logical values ​​by storing the result of a second bitwise logical operation between each of the third logical values ​​and each of the second logical values ​​stored in the modified memory based on each of the second logical values.

26. The control circuit, (a) Apply a fourth reference drive voltage to the word line of the memory cell to generate a fourth resulting voltage level from each cell in the word line; (b) Detect a third pattern of logical values ​​stored in the modified memory; (c) For each fourth resulting voltage level output by each cell in the word line, the memory is modified based on the respective fourth logical value indicated by each of the fourth resulting voltage levels; Repeat steps (a) to (c) for any additional reference drive voltage; and The system according to claim 23, further configured to modify at least one of the reference drive voltages based on at least one of the detected pattern data.

27. In the circuit, A first reference drive voltage is applied to the word line of the memory cell to generate a first resulting voltage level from each cell in the word line; For each first resulting voltage level output by each cell in the word line, store in memory the first logical value indicated by each of the first resulting voltage levels; A second reference drive voltage is applied to the word line of the memory cell to generate the second resulting voltage level from each cell in the word line; The memory is used to detect patterns of logical values ​​stored in the memory; For each second resulting voltage level output by each cell of the word line, the memory is modified based on the respective second logical value indicated by each second resulting voltage level: and Based on the detected pattern data, at least one of the first reference drive voltage and the second reference drive voltage is modified. program.

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