Switching circuit

Abstract

This invention provides a switching circuit that prevents damage to integrated circuits caused by electrostatic discharge (ESD). [Solution] The switching circuit 300 includes a body switch 320 and a plurality of switching transistors M3_1 to M3_n. The switching transistors are connected in series between a first signal transmission port SP31 and a second signal transmission port SP32. The control terminal of each switching transistor is connected to a common gate node Ng3. The body terminal of each switching transistor is connected to a common body node Nb3. The control terminal of the body switch is connected to the body terminal or control terminal of one of the switching transistors. The first terminal of the body switch is connected to a common body node. The second terminal of the body switch is connected to a reference voltage rail REF3. When an electrostatic discharge event occurs, the body switch turns on, increasing the voltage at the common body node, which turns on the switching transistors and forms an electrostatic discharge path.

Description

Technical Field

[0005] , ,

[0001] The present disclosure relates to electronic circuits, and more particularly to switching circuits.

Background Art

[0002] One of the many factors that can damage an integrated circuit due to electrical overload (EOS) is electrostatic discharge (ESD). ESD can cause permanent damage to semiconductor devices within the integrated circuit and can affect the functionality of the integrated circuit (in some cases, preventing normal operation). How to avoid ESD damage to integrated circuits is one of the many technical problems in this field.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present disclosure relates to preventing damage to an integrated circuit due to electrostatic discharge (ESD).

Means for Solving the Problems

[0004] In one embodiment of the present disclosure, a switching circuit includes a first signal transmission port, a second signal transmission port, a plurality of switching transistors, and a body switch. The switching transistors are connected in series between the first signal transmission port and the second signal transmission port. The control terminal of each switching transistor is connected to a common gate node. The body terminal (bulk or body) of each switching transistor is connected to a common body node. The control terminal of the body switch is connected to one of the body terminals or the control terminals of the switching transistors. The first terminal of the body switch is connected to the common body node. The second terminal of the body switch is connected to a reference voltage rail.

Advantages of the Invention

[0006] To make the features and advantages of this invention easier to understand, the following will be described in detail with reference to the attached drawings and examples. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic diagram of a circuit block of a radio frequency integrated circuit according to one embodiment. [Figure 2] This is a schematic circuit diagram of a switching circuit according to one embodiment. [Figure 3A] This is a schematic circuit diagram of a switching circuit according to a different embodiment of the present disclosure. [Figure 3B] This is a schematic circuit diagram of a switching circuit according to a different embodiment of the present disclosure. [Figure 3C] This is a schematic circuit diagram of a switching circuit according to a different embodiment of the present disclosure. [Figure 3D] This is a schematic circuit diagram of a switching circuit according to a different embodiment of the present disclosure. [Figure 4] This is a schematic circuit diagram of a switching circuit according to another embodiment of the present disclosure. [Figure 5]This is a schematic circuit diagram of a switching circuit according to yet another embodiment of the present disclosure. [Figure 6] This is a schematic circuit diagram of a switching circuit according to another embodiment of the present disclosure. [Figure 7] This is a schematic circuit diagram of a switching circuit according to yet another embodiment of the present disclosure. [Figure 8] This is a schematic circuit diagram of a switching circuit according to yet another embodiment of the present disclosure. [Figure 9] This is a schematic circuit diagram of a switching circuit according to another embodiment of the present disclosure.

[0008] As used throughout this specification (including the claims for utility model registration), the term “combined (or connected)” may refer to direct or indirect means of connection. For example, where the specification states that the first device is connected to (or coupled to) the second device, it should be interpreted that the first device may be directly connected to the second device, or it may be indirectly connected to the second device through other devices or some means of connection. Terms such as “first,” “second,” etc., as used throughout the specification of this disclosure (including the scope of the patent application), are used solely for naming elements or distinguishing different embodiments or scopes, and are not intended to limit the number of elements or their order. Also, wherever possible, elements / components / steps that use the same reference numerals in the drawings and embodiments represent identical or similar parts. Elements / components / steps that use the same reference numerals or terms in different embodiments may refer to each other's relative descriptions. It should be understood that the features of the following embodiments can be combined with each other. For example, features of the second embodiment can be implemented in combination with features of the first embodiment. Those skilled in the art can select the appropriate combination of features according to their actual design needs.

[0009] Based on actual designs, the switching circuits described herein can be applied to any integrated circuit (IC). For example, the switching circuits described herein are applicable to the radio frequency (RF) integrated circuit 100 shown in Figure 1 and other integrated circuits. In the event of an electrostatic discharge (ESD) event, the switching circuits can prevent damage to the integrated circuit from ESD current.

[0010] Figure 1 is a schematic diagram of the circuit block of an RF integrated circuit 100 according to an embodiment. The RF integrated circuit 100 shown in Figure 1 includes an RF switch series path 110, an RF switch series path 120, an RF switch shunt path 130, and an RF switch shunt path 140. For the sake of simplicity, Figure 1 does not show circuits / elements other than the RF switch series paths 110, 120, 130, and 140. Other circuits / elements may be arbitrarily arranged based on the actual design.

[0011] The first terminals of the RF switch series paths 110 and 120 are connected to RF connection pad RFC. RF connection pad RF2 is connected to the second terminal of the RF switch series path 110 and the first terminal of the RF switch shunt path 130. RF connection pad RF1 is connected to the second terminal of the RF switch series path 120 and the first terminal of the RF switch shunt path 140. RF connection pads RFC, RF1, and / or RF2 may be bonding pads or other types of connection pads. The second terminals of the RF switch shunt paths 130 and 140 are connected to reference voltage rail REF1. Depending on the actual design, reference voltage rail REF1 may be a ground voltage terminal or other fixed voltage terminal.

[0012] Under normal operating conditions, the RF switch series paths 110 and 120 can function as signal transmission paths (e.g., signal transmission or reception). The RF switch shunt paths 130 and 140 can function as a shunt network to enhance isolation between different signal paths. The switching circuits described herein can be applied to one or more of the RF switch series paths 110, 120, 130, and 140. If an ESD event occurs in one or more of the RF connection pads RFC, RF1, and RF2, the ESD current can pass through the RF switch series paths 110, 120, 130, and / or 140 and be conducted to the reference voltage rail REF1. Thus, the RF switch series paths 110, 120, 130, and / or 140 can prevent the ESD energy from damaging the RF integrated circuit 100.

[0013] The following describes several implementation examples of switching circuits.

[0014] Figure 2 is a circuit diagram of a switching circuit 200 according to one embodiment. The switching circuit 200 shown in Figure 2 includes a signal transmission port SP21, a signal transmission port SP22, a plurality of switching transistors (for example, the switching transistors M2_1, M2_2, ..., M2_n-1, M2_n shown in Figure 2), and a plurality of gate resistors (for example, the gate impedance elements R2_1, R2_2, ..., R2_n-1, R2_n, etc. shown in Figure 2). Based on actual design, in some application examples, each gate impedance element R2_1 to R2_n is a resistor. In some embodiments, the resistance values ​​of each gate impedance element R2_1 to R2_n are the same. In other embodiments, the dimensions of the gate impedance elements R2_1 to R2_n may be different from each other.

[0015] The switching circuit 200 shown in Figure 2 can be applied to one or more of the RF switch series path 110, RF switch series path 120, RF switch shunt path 130, and RF switch shunt path 140 shown in Figure 1. When the switching circuit 200 is applied to the RF integrated circuit 100 shown in Figure 1, the switching circuit 200 can function as an RF switch circuit.

[0016] For example, when the switching circuit 200 shown in Figure 2 is applied to the RF switch series path 110 shown in Figure 1, the signal transmission ports SP21 and SP22 of the switching circuit 200 function as the first and second terminals of the RF switch series path 110, respectively. That is, the signal transmission port SP21 is connected to the RF connection pad RFC (corresponding to the connection pad PAD2 in Figure 2). The signal transmission port SP22 is connected to the first terminal of the RF switch shunt path 130. Furthermore, the signal transmission port SP22 is connected to the reference voltage rail REF1 (corresponding to the reference voltage rail REF2 in Figure 2) via the RF switch shunt path 130. Alternatively, in another embodiment, the signal transmission port SP21 is connected to the RF connection pad RFC (corresponding to the connection pad PAD2 in Figure 2). The signal transmission port SP22 may also be connected to the RF connection pad RF2, thereby allowing the switching circuit 200 to function as a circuit segment within the RF integrated circuit 100.

[0017] As another example, when the switching circuit 200 shown in FIG. 2 is applied to the RF switch shunt path 130 shown in FIG. 1, the signal transmission ports SP21 and SP22 of the switching circuit 200 function as the first terminal and the second terminal of the RF switch shunt path 130, respectively. The signal transmission port SP21 is connected between the first RF connection pad and the second RF connection pad. That is, the signal transmission port SP21 is connected to the RF connection pad RFC (corresponding to the connection pad PAD2 in FIG. 2) via the RF switch series path 110 or is connected to the RF connection pad RF2 (corresponding to the connection pad PAD2 in FIG. 2). The signal transmission port SP22 is connected to the reference voltage rail REF1 (corresponding to the reference voltage rail REF2 in FIG. 2).

[0018] The number n of the switching transistors M2_1 to M2_n can be determined according to the actual design and application. For example, the number n of the switching transistors M2_1 to M2_n can be an integer of 4 or more. Further, although the switching transistors M2_1 to M2_n shown in FIG. 2 are N-channel Metal-Oxide-Semiconductor (NMOS) transistors, the present embodiment does not limit the types of the switching transistors M2_1 to M2_n. In another embodiment, the switching transistors M2_1 to M2_n may be changed to P-channel Metal-Oxide-Semiconductor (PMOS) transistors or other types of transistors. Based on the actual design, in some embodiments, the dimensions of each of the switching transistors M2_1 to M2_n are the same. In other embodiments, the dimensions of the switching transistors M2_1 to M2_n may be different from each other.

[0019] In the embodiment shown in FIG. 2, the switching transistors M2_1 to M2_n are connected in series between the signal transmission port SP21 and the signal transmission port SP22. The first terminal (for example, drain) of the switching transistor M2_1 is connected to the signal transmission port SP21. The second terminal (for example, source) of the switching transistor M2_1 is connected to the first terminal (for example, drain) of the switching transistor M2_2. Similarly, the second terminal of the switching transistor M2_n is connected to the signal transmission port SP22. The first terminal of each gate impedance element R2_1 to R2_n is connected to a gate drive circuit 20 (a functional circuit within the integrated circuit) within the integrated circuit. The second terminal of each gate impedance element R2_1 to R2_n is connected to the control terminal (for example, gate) of a corresponding one of the switching transistors M2_1 to M2_n, as shown in FIG. 2. Depending on the design, in some embodiments, the gate drive circuit 20 may be implemented as a hardware circuit. In other embodiments, the gate drive circuit 20 may be implemented as a combination of multiple ones of hardware, firmware, and software (i.e., a program).

[0020] Regarding the hardware form, the aforementioned gate drive circuit 20 may be implemented as a logic circuit on an integrated circuit. For example, the related functions of the gate drive circuit 20 may be implemented as various logic blocks, modules, and circuits within one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing devices. The related functions of the gate drive circuit 20 may be implemented as hardware circuits such as various logic blocks, modules, and circuits within the integrated circuit using a hardware description language (for example, Verilog HDL or VHDL) or other suitable programming languages.

[0021] With regard to software and / or firmware forms, the associated functions of the gate drive circuit 20 described above may be implemented as programming code. For example, the gate drive circuit 20 may be implemented using a common programming language (such as C, C++, or assembly language) or another suitable programming language. The programming code may be recorded / stored in a "non-temporary machine-readable storage medium." In some embodiments, the non-temporary machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. An electronic device (e.g., a CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can realize the associated functions of the gate drive circuit 20 by reading and executing the programming code from the non-temporary machine-readable storage medium.

[0022] Under normal operating conditions, the gate drive circuit 20 (a functional circuit within the integrated circuit) controls switching transistors M2_1 to M2_n, enabling it to turn the path between signal transmission port SP21 and signal transmission port SP22 on or off. Signal transmission port SP21 can transmit radio frequency signals or other signals. If an ESD event occurs at connection pad PAD2, the ESD voltage of connection pad PAD2 is coupled to the gates of switching transistors M2_1 to M2_n via the parasitic capacitance between the gate and drain of switching transistor M2_1, causing switching transistor M2_n to turn on (because the gate-source voltage Vgs of switching transistor M2_n is greater than the threshold voltage). Once switching transistor M2_n is turned on, the ESD voltage further turns on switching transistor M2_n-1 (because the gate-source voltage Vgs of switching transistor M2_n-1 is greater than the threshold voltage). Similarly, under ideal conditions, the gate-coupled ESD voltage turns on all switching transistors M2_1 to M2_n. Therefore, the switched transistors M2_1 to M2_n, when turned on, transmit ESD current between signal transmission port SP21 and signal transmission port SP22, preventing damage to the integrated circuit due to ESD current.

[0023] However, in real-world situations, each switching transistor M2_1 to M2_n has its own on-resistance. The sum of these on-resistances can cause the gate-source voltage Vgs of switching transistors M2_1 to M2_n to be non-uniform (i.e., the gate-source voltage Vgs may differ for each switching transistor). Non-uniform gate-source voltage Vgs means that the drain-source voltage Vds of switching transistors M2_1 to M2_n are also non-uniform. Due to the non-uniformity of the gate-source voltage Vgs and drain-source voltage Vds, the gate-source voltage Vgs of some switching transistors (e.g., switching transistor M2_1) may fall below the threshold voltage or even become negative. In other words, if an ESD event occurs at connection pad PAD2, some switching transistors (e.g., switching transistor M2_1) may not turn on, resulting in a reduction or loss of ESD protection provided by the switching circuit 200.

[0024] Figures 3A, 3B, 3C, and 3D are schematic diagrams of switching circuits 300 according to different embodiments of the present disclosure. In some applications, the switching circuits 300 shown in Figures 3A to 3D are located on a silicon-on-insulator (SOI) chip. The switching circuit 300 shown in Figure 3A includes a capacitor C31, a gate drive circuit 310, a signal transmission port SP31, a signal transmission port SP32, a plurality of gate impedance elements (e.g., gate impedance elements R31_1, R31_2, ..., R31_n-1, R31_n shown in Figure 3), a plurality of switching transistors (e.g., switching transistors M3_1, M3_2, ..., M3_n-1, M3_n shown in Figure 3A), a plurality of body impedance elements (e.g., body impedance elements R33_1, R33_2, ..., R33_n-1, R33_n shown in Figure 3A), an impedance element R32, a body switch 320, and a body drive circuit 330. Switching transistors M3_1 to M3_n are connected in series between the signal transmission port SP31 and the signal transmission port SP32. The signal transmission port SP32 is connected to the reference voltage rail REF3. The specific voltage of the reference voltage rail REF3 can be determined according to the actual design and application. For example, the voltage of the reference voltage rail REF3 may be the ground voltage or another reference voltage.

[0025] Each switching transistor M3_1 to M3_n has a control terminal (e.g., gate) connected to a common gate node Ng3. Gate impedance elements R31_1 to R31_n are arranged in multiple conductive paths between the control terminals of the switching transistors M3_1 to M3_n and the common gate node Ng3. Based on actual designs, in some application examples, each gate impedance element R31_1 to R31_n is a resistor. The first terminal of each gate impedance element R31_1 to R31_n is connected to a corresponding control terminal of one of the switching transistors M3_1 to M3_n. The second terminal of each gate impedance element R31_1 to R31_n is connected to the common gate node Ng3. In other words, each switching transistor M3_1 to M3_n has a control terminal connected to the common gate node Ng3 via the gate impedance elements R31_1 to R31_n.

[0026] The first terminal of capacitor C31 is connected to the signal transmission port SP31. The second terminal of capacitor C31 is connected via a common gate node Ng3 and gate impedance element R31_1 to the control terminal of the switching transistor M3_1 to M3_n that is closest to the signal transmission port SP31 (i.e., the control terminal of switching transistor M3_1). By using capacitor C31, when an ESD event occurs, the generated ESD voltage is easily coupled to the gate terminals of switching transistors M3_1 to M3_n, making it easier to turn on switching transistors M3_1 to M3_n. In some application examples, capacitor C31 may be omitted.

[0027] The output terminal of the gate drive circuit 310 is connected to the common gate node Ng3. In some applications, the gate drive circuit 310 includes a buffer circuit, an inverter, a logic control circuit, or other drive circuit (not shown). In some applications, the input terminal of the gate drive circuit 310 may be connected to a level conversion circuit, a bias circuit, a voltage regulation circuit, or other circuit (not shown). The output terminal of the gate drive circuit 310 is connected to the control terminals of the switching transistors M3_1 to M3_n via the common gate node Ng3 and gate impedance elements R31_1 to R31_n, providing the gate voltage Vg3. The first terminal of the gate drive circuit 310 is connected to the operating voltage rail VCC3. The second terminal of the gate drive circuit 310 is connected to the reference voltage rail REF3. Regarding the gate drive circuit 310, switching circuit 300, signal transmission port SP31, signal transmission port SP32, gate impedance elements R31_1 to R31_n, and switching transistors M3_1 to M3_n shown in Figure 3A, the same details will not be repeated as they can be found in the related explanations of the gate drive circuit 20, common path A2, switching circuit 200, signal transmission port SP21, signal transmission port SP22, gate impedance elements R2_1 to R2_n, and switching transistors M2_1 to M2_n shown in Figure 2.

[0028] The switching circuit 300 shown in Figure 3A can be applied to one or more of the RF switch series path 110, RF switch series path 120, RF switch shunt path 130, and RF switch shunt path 140 shown in Figure 1. When the switching circuit 300 is applied to the RF integrated circuit 100 shown in Figure 1, the switching circuit 300 can function as an RF switching circuit. When the switching circuit 300 shown in Figure 3A functions as the RF switch shunt path 130 shown in Figure 1, the signal transmission port SP31 of the switching circuit 300 is connected to the RF connection pad RF2 (corresponding to the connection pad PAD3 in Figure 3A) or to the RF connection pad RFC (corresponding to the connection pad PAD3 in Figure 3A) via the RF switch series path 110. The signal transmission port SP32 is connected to the reference voltage rail REF1 (corresponding to the reference voltage rail REF3 in Figure 3A). When the switching circuit 300 shown in Figure 3A functions as the RF switch series path 110 shown in Figure 1, the signal transmission port SP31 of the switching circuit 300 is connected to the RF connection pad RFC (corresponding to the connection pad PAD3 in Figure 3A), and the signal transmission port SP32 is connected to the reference voltage rail REF1 (corresponding to the reference voltage rail REF3 in Figure 3A) via the RF switch shunt path 130.

[0029] The body terminals of each switching transistor M3_1 to M3_n are connected to the common body node Nb3. Body impedance elements R33_1 to R33_n are arranged in multiple conductive paths between the body terminals of the switching transistors M3_1 to M3_n and the common body node Nb3. Based on actual designs, in some application examples, each body impedance element R33_1 to R33_n is a resistor. The first terminal of each body impedance element R33_1 to R33_n is connected to one corresponding body terminal (bulk or body) of the switching transistors M3_1 to M3_n. The second terminal of each body impedance element R33_1 to R33_n is connected to the common body node Nb3. In other words, the body terminals of each switching transistor M3_1 to M3_n are connected to the common body node Nb3 via the corresponding body impedance elements R33_1 to R33_n. Based on actual designs, in some applications, the common body node Nb3 is directly connected to a reference voltage rail (e.g., reference voltage rail REF3 or another reference voltage source). In the application shown in Figure 3A, the output terminal of the body drive circuit 330 is connected to the common body node Nb3, supplying the body voltage Vb3 to the body terminals of each switching transistor M3_1 to M3_n.

[0030] The number n of switching transistors M3_1 to M3_n, the number n of gate impedance elements R31_1 to R31_n, and the number n of body impedance elements R33_1 to R33_n are equal to each other. The dimensions of each switching transistor M3_1 to M3_n are equal to each other. Based on actual designs, in some application examples, the impedance value of each gate impedance element R31_1 to R31_n is approximately equal to the impedance value of each body impedance element R33_1 to R33_n. "Approximately equal" means, for example, that the difference between the impedance values ​​of the gate impedance elements R31_1 to R31_n and the impedance values ​​of the body impedance elements R33_1 to R33_n is within ±10%.

[0031] The control terminal (e.g., gate) of the body switch 320 is connected via a conductive path to one of the body terminals of the switching transistors M3_1 to M3_n. For example, the control terminal of the body switch 320 is connected between one of the body terminals of the switching transistors M3_1 to M3_n and the corresponding first terminal of one of the body impedance elements R33_1 to R33_n. In actual applications, the dimensions of the body switch 320 are smaller than the dimensions of one of the switching transistors M3_1 to M3_n.

[0032] The impedance element R32 is placed in the conductive path. Based on actual designs, in some application examples, the impedance element R32 is a resistor. The first terminal of the impedance element R32 is connected to one of the body terminals of the switching transistors M3_1 to M3_n. The second terminal of the impedance element R32 is connected to the control terminal of the body switch 320. By using the impedance element R32, the impact of the generated ESD voltage can be mitigated if an ESD event occurs in the body switch 320. For example, in the application example shown in Figure 3A, the control terminal of the body switch 320 is connected via the impedance element R32 to the body terminal of the switching transistor M3_n that is closest to the signal transmission port SP32 among the switching transistors M3_1 to M3_n. The first terminal of the body switch 320 (e.g., drain) is connected to the common body node Nb3. The second terminal of the body switch 320 (e.g., source) is connected to a reference voltage rail (such as reference voltage rail REF3 or another reference voltage source). In some applications, the impedance element R32 may be omitted.

[0033] Corresponding to the switching circuit 300 being in off mode, if no ESD event occurs, the gate voltage Vg3 is a negative voltage (e.g., -3V) and the body voltage Vb3 is the first voltage. To solve the problem of poor harmonic characteristics and power handling characteristics, the first voltage can be set to a negative voltage (e.g., -3V). A negative body voltage Vb3 can cause the problem of being unable to trigger a parasitic bipolar junction transistor (BJT).

[0034] Corresponding to the switching circuit 300 being in off mode, if an ESD event occurs at the connection pad PAD3, the gate voltage Vg3 becomes a negative voltage (e.g., -3V). The body voltage Vb3 changes from a first voltage to a second voltage (the second voltage being greater than the first voltage). Specifically, the ESD energy coupled to the common body node Nb3 passes through the impedance element R32, instantly turning on the body switch 320. The turned-on body switch 320 can instantly raise the body voltages of the switching transistors M3_1 to M3_n from a negative voltage (e.g., -3V) to a voltage close to the reference voltage rail REF3 (e.g., ground voltage). Raising the body voltages of transistors M3_1 to M3_n facilitates the activation of the parasitic BJTs of transistors M3_1 to M3_n, further improving the current tolerance of the switching circuit 300.

[0035] In summary, if an ESD event occurs at connection pad PAD3, the ESD energy coupled to the body terminals of switching transistors M3_1~M3_n can turn on body switch 320. Therefore, the voltage at common body node Nb3 is raised to a voltage level close to the reference voltage rail REF3, thereby raising the voltage at the body terminals of switching transistors M3_1~M3_n. The increase in the body voltage of switching transistors M3_1~M3_n means that the parasitic BJTs of switching transistors M3_1~M3_n turn on more easily, turning on the switching transistors M3_1~M3_n and forming an electrostatic discharge path. If an ESD event occurs, switching transistors M3_1~M3_n can transmit ESD current between signal transmission ports SP31 and SP32, preventing damage to the integrated circuit by ESD. Therefore, the ESD immunity of switching circuit 300 can be further improved.

[0036] The switching circuit 300 shown in Figure 3B includes a capacitor C32, a gate drive circuit 310, a signal transmission port SP31, a signal transmission port SP32, gate impedance elements R31_1 to R31_n, switching transistors M3_1 to M3_n, body impedance elements R33_1 to R33_n, impedance element R32, a body switch 320, and a body drive circuit 330. The embodiment shown in Figure 3B can be described by referring to the related explanation in Figure 3A, so the same details will not be repeated. The first terminal of the capacitor C32 shown in Figure 3B is connected to the signal transmission port SP31. The second terminal of the capacitor C32 is connected to the control terminal of the switching transistor M3_1 to M3_n closest to the signal transmission port SP31 (i.e., the control terminal of switching transistor M3_1). The capacitor C32 shown in Figure 3B has a similar effect to the capacitor C31 shown in Figure 3A, although its position is slightly different. By using capacitor C32, when an ESD event occurs, the generated ESD voltage is easily coupled to the gate terminals of switching transistors M3_1 to M3_n, making it easier to turn on the switching transistors M3_1 to M3_n. Furthermore, the second terminal of capacitor C32 shown in Figure 3B is connected between the control terminal of switching transistor M3_1 and the first terminal of gate impedance element R31_1. The second terminal of capacitor C31 shown in Figure 3A is connected to the second terminal of gate impedance element R31_1 and the common gate node Ng3.

[0037] The switching circuit 300 shown in Figure 3C includes a capacitor C33, a gate drive circuit 310, a signal transmission port SP31, a signal transmission port SP32, gate impedance elements R31_1 to R31_n, switching transistors M3_1 to M3_n, body impedance elements R33_1 to R33_n, impedance element R32, a body switch 320, and a body drive circuit 330. The embodiment shown in Figure 3C can be described by referring to the related explanation in Figure 3A, so the same details will not be repeated. The capacitor C33 shown in Figure 3C has the same effect as the capacitor C31 shown in Figure 3A, although its placement is slightly different. By using the capacitor C33, when an ESD event occurs, the generated ESD voltage is easily coupled by the body terminals of the switching transistors M3_1 to M3_n, making it easier to turn on the switching transistors M3_1 to M3_n. Unlike the embodiment shown in Figure 3A, the second terminal of capacitor C33 shown in Figure 3C is connected by a common body node Nb3 and a body impedance element R33_1 to the body terminal of switching transistors M3_1 to M3_n that is closest to the signal transmission port SP31 (i.e., the body terminal of switching transistor M3_1).

[0038] The switching circuit 300 shown in Figure 3D includes a capacitor C34, a gate drive circuit 310, a signal transmission port SP31, a signal transmission port SP32, gate impedance elements R31_1 to R31_n, switching transistors M3_1 to M3_n, body impedance elements R33_1 to R33_n, impedance element R32, a body switch 320, and a body drive circuit 330. The embodiment shown in Figure 3D can be described by referring to the related explanation in Figure 3A, so the same details will not be repeated. The capacitor C34 shown in Figure 3D has the same effect as the capacitor C31 shown in Figure 3A, although its placement is slightly different. By using capacitor C34, when an ESD event occurs, the generated ESD voltage is easily coupled to the body terminals of the switching transistors M3_1 to M3_n, making it easier to turn on the switching transistors M3_1 to M3_n. Unlike the embodiment shown in Figure 3A, the second terminal of capacitor C34 shown in Figure 3D is connected to the body terminal of switching transistors M3_1 to M3_n that is closest to the signal transmission port SP31 (i.e., the body terminal of switching transistor M3_1). Furthermore, compared to the embodiment shown in Figure 3C, the second terminal of capacitor C34 shown in Figure 3D is connected between the body terminal of switching transistor M3_1 and the first terminal of body impedance element R33_1. The second terminal of capacitor C33 shown in Figure 3C is connected to the second terminal of body impedance element R33_1 and the common body node Nb3.

[0039] Figure 4 is a schematic diagram of a switching circuit 400 according to another embodiment of the present disclosure. The switching circuit 400 shown in Figure 4 includes a gate drive circuit 410, a plurality of gate impedance elements (e.g., gate impedance elements R41_1, R41_2, ..., R41_n-1, R41_n shown in Figure 4), a gate switch 420, an impedance element R44, a signal transmission port SP41, a plurality of switching transistors (e.g., switching transistors M4_1, M4_2, ..., M4_n-1, M4_n shown in Figure 4), a signal transmission port SP42, a plurality of body impedance elements (e.g., body impedance elements R43_1, R43_2, ..., R43_n-1, R43_n shown in Figure 4), an impedance element R42 shown in Figure 4, a body switch 430, and a body drive circuit 440. The switching circuit 400, gate drive circuit 410, common gate node Ng4, gate impedance elements R41_1~R41_n, connection pad PAD4, signal transmission port SP41, switching transistors M4_1~M4_n, signal transmission port SP42, reference voltage rail REF4, body impedance elements R43_1~R43_n, impedance element R42, body switch 430, common body node Nb4, and body drive circuit 440 are shown in Figures 3A to 3D. Since the relevant descriptions of circuit 300, gate drive circuit 310, common gate node Ng3, gate impedance elements R31_1~R31_n, connection pad PAD3, signal transmission port SP31, switching transistors M3_1~M3_n, signal transmission port SP32, reference voltage rail REF3, body impedance elements R33_1~R33_n, impedance element R32, body switch 320, common body node Nb3, and body drive circuit 330 can be found, the same details will not be repeated.

[0040] Unlike the embodiments shown in Figures 3A to 3D, the switching circuit 400 shown in Figure 4 further includes a gate switch 420 and an impedance element R44. The first terminal of the impedance element R44 is connected to the control terminal (e.g., gate) of the gate switch 420. The second terminal of the impedance element R44 is connected to the control terminal (e.g., gate) of the body switch 430. In other words, the control terminal of the gate switch 420 is connected to the control terminal of the body switch 430 via the impedance element R44. By using the impedance element R44, the impact of the generated ESD voltage on the gate switch 420 in the event of an ESD event can be reduced. The first terminal (e.g., drain) of the gate switch 420 is connected to a common gate node Ng4. The second terminal (e.g., source) of the gate switch 420 is connected to a reference voltage rail (e.g., reference voltage rail REF4 or another reference voltage source). In some applications, the dimensions of the gate switch 420 are smaller than the dimensions of any one of the switching transistors M4_1 to M4_n. In some applications, the impedance element R44 may be omitted.

[0041] If an ESD event occurs at the connection pad PAD4, the ESD energy coupled to the body terminals of switching transistors M4_1 to M4_n can turn on the gate switch 420 and the body switch 430. Thus, the voltages at the common gate node Ng4 and the common body node Nb4 are instantaneously raised from a negative voltage (e.g., -3V) to a voltage close to the reference voltage rail REF4 (e.g., ground voltage). The rise in the gate and body voltages of switching transistors M4_1 to M4_n means that the switching transistors M4_1 to M4_n turn on more easily, forming an electrostatic discharge path. If an ESD event occurs, the switching transistors M4_1 to M4_n can transmit the ESD current between the signal transmission port SP41 and the signal transmission port SP42, preventing damage to the integrated circuit by ESD. Thus, the ESD immunity of the switching circuit 400 can be further improved.

[0042] Figure 5 is a schematic diagram of a switching circuit 500 according to yet another embodiment of the present disclosure. The switching circuit 500 shown in Figure 5 includes a gate drive circuit 510, a plurality of gate impedance elements (e.g., gate impedance elements R51_1, R51_2, ..., R51_n-1, R51_n shown in Figure 5), a signal transmission port SP51, a plurality of switching transistors (e.g., switching transistors M5_1, M5_2, ..., M5_n-1, M5_n shown in Figure 5), a signal transmission port SP52, a plurality of body impedance elements (e.g., body impedance elements R53_1, R53_2, ..., R53_n-1, R53_n shown in Figure 5), an impedance element R52, a body switch 520, and a body drive circuit 530. Figure 5 shows the switching circuit 500, gate drive circuit 510, common gate node Ng5, gate impedance elements R51_1~R51_n, connection pad PAD5, signal transmission port SP51, switching transistors M5_1~M5, connection pad PAD5, signal transmission port SP51, switching transistors M5_1~M5_n, signal transmission port SP52, reference voltage rail REF5, body impedance elements R53_1~R53_n, impedance element R52, and body switch. For details regarding 520, the common body node Nb5, and the body drive circuit 530, please refer to the related descriptions of the switching circuit 300, gate drive circuit 310, common gate node Ng3, gate impedance elements R31_1~R31_n, connection pad PAD3, signal transmission port SP31, switching transistors M3_1~M3_n, signal transmission port SP32, reference voltage rail REF3, body impedance elements R33_1~R33_n, impedance element R32, body switch 320, common body node Nb3, and body drive circuit 330 shown in Figures 3A to 3C; therefore, the same details will not be repeated.

[0043] Unlike the embodiments shown in Figures 3A to 3D, the control terminal (e.g., gate) of the body switch 520 shown in Figure 5 is connected via a conductive path to one of the control terminals (e.g., gate) of the switching transistors M5_1 to M5_n. The first terminal of the impedance element R52 is connected to one of the control terminals of the switching transistors M5_1 to M5_n. The second terminal of the impedance element R52 is connected to the control terminal of the body switch 520. In other words, the control terminal of the body switch 520 shown in Figure 5 is connected via resistor R52 to one of the control terminals of the switching transistors M5_1 to M5_n. Specifically, the control terminal of the body switch 520 is connected between one of the control terminals of the switching transistors M5_1 to M5_n and the corresponding first terminal of the gate impedance elements R51_1 to R51_n. For example, the control terminal of the body switch 520 is connected to the control terminal of the switching transistor M5_n that is closest to the signal transmission port SP52 among the switching transistors M5_1 to M5_n.

[0044] If an ESD event occurs at connection pad PAD5, the ESD energy coupled to the gate terminals of switching transistors M5_1~M5_n turns on body switch 520, and the voltage at common body node Nb5 is instantaneously raised from a negative voltage (e.g., -3V) to a voltage close to the reference voltage rail REF5 (e.g., ground voltage). The increase in the body voltage of switching transistors M5_1~M5_n means that the parasitic BJTs of switching transistors M5_1~M5_n turn on more easily, turning on the switching transistors M5_1~M5_n and forming an electrostatic discharge path. If an ESD event occurs, switching transistors M5_1~M5_n can transmit the ESD current between signal transmission ports SP51 and SP52, preventing damage to the integrated circuit by ESD. Thus, the ESD immunity of the switching circuit 500 can be further improved.

[0045] Figure 6 is a schematic diagram of a switching circuit 700 according to another embodiment of the present disclosure. The switching circuit 700 shown in Figure 6 includes a gate drive circuit 710, a plurality of gate impedance elements (e.g., gate impedance elements R71_1, R71_2, ..., R71_n-1, R71_n shown in Figure 6), a signal transmission port SP71, a plurality of switching transistors (e.g., switching transistors M7_1, M7_2, ..., M7_n-1, M7_n shown in Figure 6), a signal transmission port SP72, a plurality of body impedance elements (e.g., body impedance elements R73_1, R73_2, ..., R73_n-1, R73_n shown in Figure 6), an impedance element R72, a body switch 720, and a body drive circuit 730. The switching circuit 700, gate drive circuit 710, common gate node Ng7, gate impedance elements R71_1~R71_n, connection pad PAD7, signal transmission port SP71, switching transistors M7_1~M7_n, signal transmission port SP72, reference voltage rail REF7, body impedance elements R73_1~R73_n, impedance element R72, body switch 720, common body node Nb7, and body drive circuit 730 shown in Figure 6 are as shown in Figures 3A to 3D. The relevant descriptions of the switching circuit 300, gate drive circuit 310, common gate node Ng3, gate impedance elements R31_1~R31_n, connection pad PAD3, signal transmission port SP31, switching transistors M3_1~M3_n, signal transmission port SP32, reference voltage rail REF3, body impedance elements R33_1~R33_n, impedance element R32, body switch 320, common body node Nb3, and body drive circuit 330 can be found in the provided documentation; therefore, the same details will not be repeated.

[0046] Unlike the embodiments shown in Figures 3A to 3D, the control terminal (e.g., gate) of the body switch 720 shown in Figure 6 is connected to a common gate node Ng7 via a conductive path. The first terminal of the impedance element R72 is connected to the common gate node Ng7. The second terminal of the impedance element R72 is connected to the control terminal of the body switch 720. In other words, the control terminal of the body switch 720 shown in Figure 6 is connected to the control terminals of the switching transistors M71 to M7n via the resistor R72, the common gate node Ng7, and the gate impedance elements R71_1 to R71_n.

[0047] If an ESD event occurs at the connection pad PAD7, the ESD energy coupled to the gate terminals of switching transistors M7_1~M7_n can turn on the body switch 720. Thus, the voltage at the common body node Nb7 is instantaneously raised from a negative voltage (e.g., -3V) to a voltage close to the reference voltage rail REF7 (e.g., ground voltage). The increase in the body voltage of switching transistors M7_1~M7_n means that the parasitic BJTs of switching transistors M7_1~M7_n are more easily turned on, turning on the switching transistors M7_1~M7_n and forming an electrostatic discharge path. If an ESD event occurs, switching transistors M7_1~M7_n can transmit the ESD current between the signal transmission ports SP71 and SP72, preventing damage to the integrated circuit by ESD. Thus, the ESD immunity of the switching circuit 700 can be further improved.

[0048] Figure 7 is a schematic diagram of a switching circuit 900 according to another embodiment of the present disclosure. The switching circuit 900 shown in Figure 7 includes a gate drive circuit 910, a gate impedance element R91, a signal transmission port SP91, a plurality of switching transistors (for example, the switching transistors M9_1, M9_2, ..., M9_n-1, M9_n shown in Figure 7), a signal transmission port SP92, an impedance element R92, a body switch 920, a body impedance element R93, and a body drive circuit 930. For the switching circuit 900, gate drive circuit 910, common gate node Ng9, gate impedance element R91, connection pad PAD9, signal transmission port SP91, switching transistors M9_1~M9_n, signal transmission port SP92, reference voltage rail REF9, body impedance element R93, impedance element R92, body switch 920, common body node Nb9, and body drive circuit 930 shown in Figure 7, refer to the related explanations of the switching circuit 300, gate drive circuit 310, common gate node Ng3, gate impedance elements R31_1~R31_n, connection pad PAD3, signal transmission port SP31, switching transistors M3_1~M3_n, signal transmission port SP32, reference voltage rail REF3, body impedance elements R33_1~R33_n, impedance element R32, body switch 320, common body node Nb3, and body drive circuit 330 shown in Figures 3A to 3D, and therefore the same details will not be repeated.

[0049] Compared with the gate impedance elements R31_1 to R31_n shown in Figures 3A to 3D, the gate impedance element R91 shown in Figure 7 is located in the conductive path between the output terminal of the gate drive circuit 910 and the common gate node Ng9. The first terminal of the gate impedance element R91 is connected to the common gate node Ng9. The second terminal of the gate impedance element R91 is connected to the output terminal of the gate drive circuit 910. Compared with the body impedance elements R33_1 to R33_n shown in Figures 3A to 3D, the body impedance element R93 shown in Figure 7 is located in the conductive path between the output terminal of the body drive circuit 930 and the body terminals of each switching transistor M9_1 to M9_n. The first terminal of the body impedance element R93 is connected to the body terminal of each switching transistor M9_1 to M9_n. The second terminal of the body impedance element R93 is connected to the output terminal of the body drive circuit 930.

[0050] The first terminal of the impedance element R92 is connected to one of the body terminals of the switching transistors M9_1 to M9_n. The second terminal of the impedance element R92 is connected to the control terminal (e.g., gate) of the body switch 920. In other words, the control terminal of the body switch 920 is connected via the impedance element R92 between one of the body terminals of the switching transistors M9_1 to M9_n and the first terminal of the body impedance element R93. For example, the control terminal of the body switch 920 is connected to the body terminal of the switching transistor M9_n. The first terminal of the body switch 920 (e.g., drain) is connected to the common body node Nb9 between the second terminal of the body impedance element R93 and the output terminal of the body drive circuit 930. The second terminal of the body switch 920 (e.g., source) is connected to a reference voltage rail (e.g., reference voltage rail REF9 or another reference voltage source).

[0051] If an ESD event occurs at the connection pad PAD9, the ESD energy coupled to the body terminals of switching transistors M9_1~M9_n can turn on the body switch 920. Thus, the voltage at the common body node Nb9 is instantaneously raised from a negative voltage (e.g., -3V) to a voltage close to the reference voltage rail REF9 (e.g., ground voltage), which also raises the voltage at the body terminals of switching transistors M9_1~M9_n. The rise in the body voltage of switching transistors M9_1~M9_n means that the parasitic BJTs of switching transistors M9_1~M9_n turn on more easily, turning on the switching transistors M9_1~M9_n and forming an electrostatic discharge path. If an ESD event occurs, switching transistors M9_1~M9_n can transmit the ESD current between the signal transmission port SP91 and the signal transmission port SP92, preventing damage to the integrated circuit by ESD. Thus, the ESD immunity of the switching circuit 900 can be further improved.

[0052] Figure 8 is a schematic diagram of a switching circuit 1000 according to another embodiment of the present disclosure. The switching circuit 1000 shown in Figure 8 includes a gate drive circuit 1010, a gate impedance element R101, a gate switch 1020, an impedance element R104, a signal transmission port SP101, a plurality of switching transistors (e.g., switching transistors M10_1, M10_2, ..., M10_n-1, M10_n shown in Figure 8), a signal transmission port SP102, a body impedance element R103, an impedance element R102, a body switch 1030, and a body drive circuit 1040. For the switching circuit 1000, gate drive circuit 1010, common gate node Ng10, gate impedance element R101, connection pad PAD10, signal transmission port SP101, switching transistors M10_1~M10_n, signal transmission port SP102, reference voltage rail REF10, body impedance element R103, impedance element R102, body switch 1030, common body node Nb10, and body drive circuit 1040 shown in Figure 8, please refer to the related explanations for the switching circuit 900, gate drive circuit 910, common gate node Ng9, gate impedance element R91, connection pad PAD9, signal transmission port SP91, switching transistors M9_1~M9_n, signal transmission port SP92, reference voltage rail REF9, body impedance element R93, impedance element R92, body switch 920, common body node Nb9, and body drive circuit 930 shown in Figure 7; therefore, the same details will not be repeated.

[0053] Unlike the embodiment shown in Figure 7, the switching circuit 1000 shown in Figure 8 further includes a gate switch 1020 and an impedance element R104. The first terminal of the impedance element R104 is connected to the control terminal (e.g., gate) of the gate switch 1020. The second terminal of the impedance element R104 is connected to the control terminal (e.g., gate) of the body switch 1030. In other words, the control terminal of the gate switch 1020 is connected to the control terminal of the body switch 1030 via the impedance element R104. By using the impedance element R104, the impact of the generated ESD voltage on the gate switch 1020 in the event of an ESD event can be reduced. The first terminal (e.g., drain) of the gate switch 1020 is connected to the common gate node Ng10. The second terminal (e.g., source) of the gate switch 1020 is connected to a reference voltage rail (e.g., reference voltage rail REF10 or another reference voltage source). In some applications, the impedance element R104 may be omitted. In some applications, the dimensions of the gate switch 1020 are smaller than the dimensions of any one of the switching transistors M10_1 to M10_n.

[0054] If an ESD event occurs at the connection pad PAD10, the ESD energy coupled to the body terminals of switching transistors M10_1 to M10_n can turn on the gate switch 1020 and the body switch 1030. Thus, the voltages at the common gate node Ng10 and the common body node Nb10 are instantaneously raised from a negative voltage (e.g., -3V) to a voltage close to the reference voltage rail REF10 (e.g., ground voltage). The rise in the gate and body voltages of switching transistors M10_1 to M10_n means that the switching transistors M10_1 to M10_n turn on more easily, and an electrostatic discharge path is formed. If an ESD event occurs, the switching transistors M10_1 to M10_n can transmit the ESD current between the signal transmission port SP101 and the signal transmission port SP102, preventing damage to the integrated circuit by ESD. Thus, the ESD immunity of the switching circuit 1000 can be further improved.

[0055] Figure 9 is a schematic diagram of a switching circuit 1100 according to another embodiment of the present disclosure. The switching circuit 1100 shown in Figure 9 includes a gate drive circuit 1110, a gate impedance element R111, a signal transmission port SP111, a plurality of switching transistors (switching transistors M11_1, M11_2, ..., M11_n-1, and M11_n shown in Figure 9), a signal transmission port SP112, a body impedance element R113, an impedance element R112, a body switch 1120, and a body drive circuit 1130. For the switching circuit 1100, gate drive circuit 1110, common gate node Ng11, gate impedance element R111, connection pad PAD11, signal transmission port SP111, switching transistors M11_1~M11_n, signal transmission port SP112, reference voltage rail REF11, common body node Nb11, and body drive circuit 1130 shown in Figure 9, please refer to the related descriptions of the switching circuit 900, gate drive circuit 910, common gate node Ng9, gate impedance element R91, connection pad PAD9, signal transmission port SP91, switching transistors M9_1~M9_n, signal transmission port SP92, reference voltage rail REF9, body impedance element R93, impedance element R92, body switch 920, common body node Nb9, and body drive circuit 930 shown in Figure 7; therefore, the same details will not be repeated.

[0056] Unlike the embodiment shown in Figure 7, the control terminal (e.g., gate) of the body switch 1120 shown in Figure 9 is connected via a conductive path to the control terminal (e.g., gate) of the switching transistors M11_1 to M11_n. The first terminal of the impedance element R112 is connected to the control terminal of the switching transistors M11_1 to M11_n. The second terminal of the impedance element R112 is connected to the control terminal of the body switch 1120. In other words, the control terminal of the body switch 1120 shown in Figure 9 is connected via the resistor R112 to the control terminal of the switching transistors M11_1 to M11_n.

[0057] If an ESD event occurs at the connection pad PAD11, the ESD energy coupled to the gate terminals of switching transistors M11_1~M11_n can turn on the body switch 1120. Thus, the voltage at the common body node Nb11 is instantaneously raised from a negative voltage (e.g., -3V) to a voltage close to the reference voltage rail REF11 (e.g., ground voltage). The increase in the body voltage of switching transistors M11_1~M11_n means that the parasitic BJTs of switching transistors M11_1~M11_n are more easily turned on, turning on the switching transistors M11_1~M11_n and forming an electrostatic discharge path. If an ESD event occurs, the switching transistors M11_1~M11_n can transmit the ESD current between the signal transmission ports SP111 and SP112, preventing damage to the integrated circuit by ESD. Thus, the ESD immunity of the switching circuit 1100 can be further improved.

[0058] Although the present invention is disclosed in the embodiments described above, these embodiments do not limit the present invention. Those skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention. Accordingly, the scope of protection of the present invention is defined by the appended utility model claims. [Industrial applicability]

[0059] The switch circuit of this disclosure can be applied to prevent damage to integrated circuits due to electrostatic discharge (ESD). [Explanation of Symbols]

[0060] 20, 310, 410, 510, 710, 910, 1010, 1110: Gate drive circuit 100: Radio frequency (RF) integrated circuit 110, 120: RF switch series path 130, 140: RF switch shunt path 200, 300, 400, 500, 700, 900, 1000, 1100: Switching circuits 320, 430, 520, 720, 920, 1030, 1120: Body switch 330, 440, 530, 730, 930, 1040, 1130: Body drive circuit 420, 1020: Gate switch C31, C32, C33, C34: Capacitors M2_1, M2_2, M2_n-1, M2_n, M3_1, M3_2, M3_n-1, M3_n, M4_1, M4_2, M4_n-1, M4_n, M5_1, M5_2, M5_n-1, M5_n, M7_1 , M7_2, M7_n-1, M7_n, M9_1, M9_2, M9_n-1, M9_n, M10_1, M10_2, M10_n-1, M10_n, M11_1, M11_2, M11_n-1, M11_n: switching transistor Nb3, Nb4, Nb5, Nb7, Nb9, Nb10, Nb11: Common body node Ng3, Ng4, Ng5, Ng7, Ng9, Ng10, Ng11: Common gate nodes PAD2, PAD3, PAD4, PAD5, PAD7, PAD9, PAD10, PAD11: Connection pads R2_1, R2_2, R2_n-1, R2_n, R31_1, R31_2, R31_n-1, R31_n, R41_1, R41_2, R41_n-1, R41_n, R51_1, R51_2, R51_n-1, R51_n, R71_1, R71_2, R71_n-1, R71_n, R91, R101, R111: Gate impedance elements R32, R42, R44, R52, R72, R92, R102, R104, R112: Impedance elements R33_1, R33_2, R33_n-1, R33_n, R43_1, R43_2, R43_n-1, R43_n, R53_1, R53_2, R53_n-1, R53_n, R73_1, R73_2, R73_n-1, R73_n, R93, R103, R113: Body impedance elements REF1, REF2, REF3, REF4, REF5, REF7, REF9, REF10, REF11: Reference voltage rails RF1, RF2, RFC: RF connection pads SP21, SP22, SP31, SP32, SP41, SP42, SP51, SP52, SP71, SP72, SP91, SP92, SP101, SP102, SP111, SP112: Signal transmission ports Vb3: Body voltage VCC3: Operating voltage rail Vg3: Gate voltage

Claims

1. The first signal transmission port, A second signal transmission port, A plurality of switching transistors, each connected in series between the first signal transmission port and the second signal transmission port, with the control terminal of each switching transistor connected to a common gate node and the body terminal of each switching transistor connected to a common body node, A body switch, wherein the control terminal of the body switch is connected to the body terminal of one of the switching transistors or to the control terminal, the first terminal of the body switch is connected to the common body node, and the second terminal of the body switch is connected to the reference voltage rail, Switching circuit.

2. The control terminal of the body switch is connected via a conductive path to one of the body terminals or the control terminal of the switching transistor. The aforementioned switching circuit is The system further includes a first impedance element arranged in the conductive path, the first terminal of the first impedance element being connected to one of the body terminals or control terminals of the switching transistor, and the second terminal of the first impedance element being connected to the control terminal of the body switch. The switching circuit according to claim 1.

3. A body drive circuit, wherein the output terminal of the body drive circuit is connected to the common body node and provides a body voltage to the body terminal of each of the switching transistors, A gate drive circuit, wherein the output terminal of the gate drive circuit is connected to the common gate node and provides a gate voltage to the control terminal of each of the switching transistors, The switching circuit according to claim 1, further comprising:

4. In response to the switching circuit being in the off mode, If no electrostatic discharge event occurs, the body voltage is a first voltage, and the first voltage is a negative voltage. When the electrostatic discharge event occurs, the body voltage changes from the first voltage to the second voltage, and the second voltage is greater than the first voltage. The switching circuit according to claim 3.

5. When an electrostatic discharge event occurs, the body switch turns on. The switching circuit according to claim 1.

6. A plurality of body impedance elements arranged in a plurality of conductive paths between the body terminals of the switching transistor and the common body node, wherein the first terminal of each body impedance element is connected to a corresponding body terminal of the switching transistor, and the second terminal of each body impedance element is connected to the common body node, A plurality of gate impedance elements arranged in a plurality of conductive paths between the control terminal of the switching transistor and the common gate node, wherein the first terminal of each gate impedance element is connected to a corresponding control terminal of the switching transistor, and the second terminal of each gate impedance element is connected to the common gate node, The switching circuit according to claim 1, further comprising:

7. The control terminal of the body switch is connected between one of the body terminals of the switching transistor and the corresponding first terminal of the body impedance element. The switching circuit according to claim 6.

8. The present invention further includes a gate switch, wherein the control terminal of the gate switch is connected to the control terminal of the body switch, the first terminal of the gate switch is connected to the common gate node, and the second terminal of the gate switch is connected to the reference voltage rail. The switching circuit according to claim 7.

9. The present invention further includes a second impedance element, the first terminal of the second impedance element being connected to the control terminal of the gate switch, and the second terminal of the second impedance element being connected to the control terminal of the body switch. The switching circuit according to claim 8.

10. The control terminal of the body switch is connected between one of the control terminals of the switching transistor and the corresponding first terminal of the gate impedance element. The switching circuit according to claim 6.

11. The control terminal of the body switch is connected to the common gate node, and the control terminal of the body switch is connected to one of the control terminals of the switching transistor via a corresponding gate impedance element. The switching circuit according to claim 6.

12. A body impedance element is arranged in the conductive path between the output terminal of the body drive circuit and the body terminal of each of the switching transistors, wherein the first terminal of the body impedance element is connected to the body terminal of each of the switching transistors, and the second terminal of the body impedance element is connected to the output terminal of the body drive circuit, A gate impedance element is arranged in the conductive path between the output terminal of the gate drive circuit and the common gate node, wherein the first terminal of the gate impedance element is connected to the common gate node and the second terminal of the gate impedance element is connected to the output terminal of the gate drive circuit, The switching circuit according to claim 3, further comprising:

13. The control terminal of the body switch is connected between the body terminal of one of the switching transistors and the first terminal of the body impedance element, and the first terminal of the body switch is connected between the second terminal of the body impedance element and the output terminal of the body drive circuit. The switching circuit according to claim 12.

14. The present invention further includes a gate switch, wherein the control terminal of the gate switch is connected to the control terminal of the body switch, the first terminal of the gate switch is connected to the common gate node, and the second terminal of the gate switch is connected to the reference voltage rail. The switching circuit according to claim 13.

15. The present invention further includes a second impedance element, the first terminal of the second impedance element being connected to the control terminal of the gate switch, and the second terminal of the second impedance element being connected to the control terminal of the body switch. The switching circuit according to claim 13.

16. The control terminal of the body switch is connected between the control terminal of the switching transistor and the first terminal of the gate impedance element. The switching circuit according to claim 12.

17. The dimensions of the body switch are smaller than the dimensions of any one of the switching transistors. The switching circuit according to claim 1.

18. The switching circuit is located within a radio frequency switch shunt path, the first signal transmission port is connected between a first radio frequency connection pad and a second radio frequency connection pad, and the second signal transmission port is connected to the reference voltage rail. The switching circuit according to claim 1.

19. The switching circuit is placed on a silicon-on-insulator chip. The switching circuit according to claim 1.

20. The control terminal of the body switch is connected to the body terminal or control terminal of one of the switching transistors closest to the second signal transmission port. The switching circuit according to claim 1.

21. The present invention further includes a capacitor, the first terminal of which is connected to the first signal transmission port, and the second terminal of which is connected to the body terminal or control terminal of one of the switching transistors closest to the first signal transmission port. The switching circuit according to claim 1.

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