Vibration Device

Abstract

To provide a vibration device capable of suppressing changes in oscillation characteristics.SOLUTION: A vibration device 1 includes a semiconductor substrate 20, a base 2, a vibration element 5 and a lid 7. The semiconductor substrate 20 has a first surface 21 and a second surface 22 that is opposite to the first surface 21. The base 2 includes an integrated circuit 10 placed on the first surface 21 or the second surface 22. The vibration element 5 is electrically connected to the integrated circuit 10 and placed on a first surface 21 side. The lid 7 is joined to the base 2 at a junction JA of the base 2 so as to accommodate the vibration element 5. The integrated circuit 10 includes a passive element, and the passive element is placed such that at least a part of the passive element overlaps with the junction JA, in plan view from a direction orthogonal to the first surface 21.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a vibration device and the like. [Background technology]

[0002] Conventionally, a vibration device such as an oscillator is known as a device using a vibration element. Patent Document 1 discloses that a piezoelectric vibrating piece is mounted as a vibration element on a semiconductor substrate such as a silicon substrate on which a circuit pattern of an integrated circuit is formed, and the piezoelectric vibrating piece is sealed with the semiconductor substrate and a lid to form a package. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-126052 A Summary of the Invention [Problem to be solved by the invention]

[0004] Since the materials constituting the device and the package have different thermal expansion coefficients, packaging causes stress. In addition, when the package is soldered to an external circuit board, stress occurs due to the difference in thermal expansion coefficients between the package and the circuit board, and stress occurs due to fixing the package and the circuit board with an underfill agent. If these stresses cause the integrated circuit to warp or deform, they will affect the characteristics of the device. Since the way in which stress occurs depends on the package structure, it is necessary to design the layout of the integrated circuit while taking into account the stress caused by the package structure. Patent Document 1 does not take such circumstances into account. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a vibration device including a base including a semiconductor substrate having a first surface and a second surface that is in a reverse relationship to the first surface, an integrated circuit arranged on the first surface or the second surface, a vibration element electrically connected to the integrated circuit and arranged on the first surface side, and a lid joined to the base at a joint of the base to accommodate the vibration element, wherein the integrated circuit includes a passive element, and the passive element is arranged such that at least a portion of the passive element overlaps the joint when viewed in a planar view from a direction perpendicular to the first surface.

[0006] Moreover, one aspect of the present disclosure relates to a vibration device including a semiconductor substrate having a first surface and a second surface that is in a reverse relationship to the first surface, a base including an integrated circuit arranged on the first surface or the second surface, a vibration element electrically connected to the integrated circuit and arranged on the first surface side, and a lid joined to the base at a joint of the base to accommodate the vibration element, wherein the integrated circuit includes at least one of a reference voltage generation circuit that generates a reference voltage used in the integrated circuit or a regulator circuit that generates a regulated voltage used in the integrated circuit, and at least a portion of a passive element or active element included in at least one of the reference voltage generation circuit or the regulator circuit is arranged to overlap the joint when viewed in a planar view from a direction perpendicular to the first surface.

[0007] Moreover, one aspect of the present disclosure relates to a vibration device including a base including a semiconductor substrate having a first surface and a second surface that is in a reverse relationship to the first surface, an integrated circuit arranged on the first surface or the second surface, a vibration element electrically connected to the integrated circuit and arranged on the first surface side, and a lid joined to the base at a joint of the base to accommodate the vibration element, wherein the integrated circuit includes at least one of a temperature sensor circuit that detects temperature or a temperature compensation circuit that performs temperature compensation for the oscillation frequency of the vibration element, and at least a portion of a passive element or active element included in at least one of the temperature sensor circuit or the temperature compensation circuit is arranged to overlap the joint when viewed in a planar view from a direction perpendicular to the first surface. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing an example of the configuration of a vibration device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view showing a specific configuration example of the vibration device according to the embodiment. [Diagram 3] FIG. 2 is a plan view showing an example of a vibration element of the vibration device. [Figure 4] FIG. 1 is a block diagram showing a configuration example of an integrated circuit. [Diagram 5] FIG. 4 is a cross-sectional view showing another configuration example of the vibration device of the present embodiment. [Figure 6] 1A to 1C are diagrams illustrating the influence of stress on a vibration device. [Figure 7] FIG. 4 is a diagram showing a configuration example of a resistor. [Figure 8] FIG. 2 is a diagram showing an example of the configuration of a capacitor. [Figure 9] FIG. 1 is a cross-sectional view showing a configuration example of a bipolar transistor. [Figure 10] FIG. 2 is a plan view showing an example of the arrangement of through electrodes, external connection terminals, integrated circuits, etc. [Figure 11] FIG. 2 is a diagram showing a configuration example of an oscillator circuit. [Figure 12] FIG. 2 is a cross-sectional view showing a configuration example of a reference voltage generating circuit. [Figure 13] FIG. 1 is a diagram showing an example of the configuration of a regulator circuit. [Figure 14] FIG. 2 is a diagram showing an example of the configuration of a temperature sensor. [Figure 15] FIG. 4 is a diagram showing a configuration example of a temperature compensation circuit. [Figure 16] FIG. 4 is a diagram showing an example of the configuration of a high-order correction circuit. [Figure 17] FIG. 13 is a plan view showing another example of the arrangement of the through electrodes, the external connection terminals, the integrated circuits, etc.; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the contents of the claims. Not all of the configurations described in the present embodiment are essential components. In addition, in the following drawings, some components may be omitted for convenience of explanation. In addition, in each drawing, the dimensional ratio of each component is different from the actual one for ease of understanding.

[0010] FIG. 1 is a cross-sectional view showing a configuration example of a vibration device 1 of the present embodiment. As shown in FIG. 1, the vibration device 1 of the present embodiment includes a base 2, a vibration element 5, and external connection terminals 91 and 92. The vibration device 1 may also include a lid 7 and a relocation wiring layer 8. The base 2 includes a semiconductor substrate 20 and a through electrode 40. The semiconductor substrate 20 has a first surface 21 and a second surface 22 that is opposite to the first surface 21. The first surface 21 is, for example, the upper surface of the semiconductor substrate 20, and the second surface 22 is, for example, the lower surface of the semiconductor substrate 20. The through electrode 40 is an electrode that penetrates the first surface 21 and the second surface 22 of the semiconductor substrate 20. The vibration element 5 is disposed on the first surface 21 side of the semiconductor substrate 20. For example, the vibration element 5 is disposed at a position spaced apart from the first surface 21 of the semiconductor substrate 20 by a given distance. Specifically, the vibration element 5 is fixed to the first surface 21 of the semiconductor substrate 20 via, for example, a conductive bonding member 60. The external connection terminals 91, 92 are provided via an insulating layer 80 or the like on the second surface 22 side of the semiconductor substrate 20. The insulating layer 80 is an insulating layer that constitutes the rearrangement wiring layer 8, for example.

[0011] In each figure described in this embodiment, the X-axis, Y-axis, and Z-axis are illustrated as three mutually orthogonal axes. The direction along the X-axis is called the "X-axis direction", the direction along the Y-axis is called the "Y-axis direction", and the direction along the Z-axis is called the "Z-axis direction". The tip side of the arrow in each axis direction is also called the "plus side", the base side is called the "minus side", the plus side of the Z-axis direction is called the "upper", and the minus side of the Z-axis direction is called the "lower". For example, the Z-axis direction is along the vertical direction, and the XY plane is along the horizontal plane. FIG. 1 is a cross-sectional view of the vibration device 1 as viewed from the Y-axis direction. The first surface 21 and the second surface 22 of the semiconductor substrate 20 are surfaces along the XY plane and perpendicular to the Z-axis. Note that "perpendicular" includes not only cases where the surfaces intersect at 90°, but also cases where the surfaces intersect at an angle slightly inclined from 90°.

[0012] The vibration device 1 is, for example, an oscillator. Specifically, the vibration device 1 is an oscillator such as a simple package crystal oscillator (SPXO), a voltage-controlled crystal oscillator (VCXO), a temperature-compensated crystal oscillator (TCXO), an oven-controlled crystal oscillator (OCXO), a surface acoustic wave (SAW) oscillator, a voltage-controlled SAW oscillator, or a micro electro mechanical systems (MEMS) oscillator. A MEMS oscillator can be realized by a MEMS vibration element in which a piezoelectric film and electrodes are arranged on a substrate such as a silicon substrate. However, the vibration device 1 may also be an inertial sensor such as an acceleration sensor or an angular velocity sensor, or a force sensor such as an inclination sensor.

[0013] The base 2 is composed of a semiconductor substrate 20. The semiconductor substrate 20 is, for example, a silicon substrate. Note that the semiconductor substrate 20 is not limited to a silicon substrate and may be a semiconductor substrate such as Ge, GaP, GaAs, or InP, but it is preferable to take into consideration the relationship with the lid 7 described later.

[0014] The base 2 also includes an integrated circuit 10. The integrated circuit 10, which is a semiconductor circuit, is formed on the second surface 22 of the semiconductor substrate 20. The integrated circuit 10 is composed of a plurality of circuit elements. The circuit elements are, for example, active elements such as transistors, or passive elements such as capacitors and resistors. Specifically, the integrated circuit 10 is composed of a plurality of circuit blocks, each of which includes a plurality of circuit elements. The integrated circuit 10 is also formed of a diffusion region, which is an impurity region formed by doping impurities into the semiconductor substrate 20, and a wiring layer in which a metal layer and an insulating layer are laminated. The diffusion region forms a source region and a drain region of a transistor, which is a circuit element of the integrated circuit 10, and the wiring region forms wiring that connects the circuit elements.

[0015] The base 2 also includes a through electrode 40. The through electrode 40 is made of a conductive material that penetrates the first surface 21 and the second surface 22 of the semiconductor substrate 20. For example, a through hole is formed in the semiconductor substrate 20, and the through hole is filled with a conductive material to form the through electrode 40. The conductive material may be a metal such as copper, or may be conductive polysilicon. Conductive polysilicon refers to polysilicon that is doped with impurities such as phosphorus (P), boron (B), and arsenic (As) to give it conductivity. If polysilicon is used as the conductive material, it is possible to realize a through electrode 40 that has sufficient resistance to heat applied in the process of forming the integrated circuit 10.

[0016] One end of the through electrode 40 is electrically connected to the vibration element 5 via a conductive bonding member 60. In FIG. 1, the conductive bonding member 60 is realized by a bump 62 having one end electrically connected to the vibration element 5 and the other end electrically connected to the through electrode 40. Specifically, the other end of the bump 62 is connected to the through electrode 40 via a terminal 64. The bump 62 is a conductive bump, specifically a metal bump. The conductive bonding member 60 may be realized by a conductive adhesive or the like.

[0017] The other end of the through electrode 40 is electrically connected to the integrated circuit 10. Specifically, the other end of the through electrode 40 is connected to a circuit element of the integrated circuit 10 via a contact pad 36 formed on the integrated circuit 10. In this manner, the vibration element 5 and the integrated circuit 10 can be electrically connected via the through electrode 40.

[0018] The lid 7 is joined to the joint JA of the base 2 via joining members 71, 72. The base 2 and the lid 7, which is a cover body, form an airtight storage space SP, and the vibration element 5 is accommodated in this storage space SP. The storage space SP is hermetically sealed, and the inside of the storage space SP is, for example, in a reduced pressure state. This allows the vibration element 5 to be suitably protected from impact, dust, heat, moisture, etc., and to be driven stably. Note that the state in the storage space SP is not limited to a reduced pressure state, and the inside of the storage space SP may be, for example, an inert gas atmosphere such as argon or nitrogen.

[0019] The lid 7 can be realized by a silicon substrate, like the base 2. This makes the thermal expansion coefficients of the base 2 and the lid 7 equal, and the occurrence of thermal stress due to thermal expansion can be suppressed. In addition, both the base 2 and the lid 7 can be formed by a semiconductor manufacturing process. This makes it possible to manufacture the vibration device 1 with high precision and to reduce its size. Note that the lid 7 is not limited to a silicon substrate and may be realized by a semiconductor substrate such as Ge, GaP, GaAs, InP, etc., but in this embodiment, it is preferable that the materials of the lid 7 and the base 2 are the same as each other, or are materials having the same thermal expansion coefficients as each other. Same includes approximately the same.

[0020] The relocation wiring layer 8 is provided on the second surface 22 side of the semiconductor substrate 20, and includes an insulating layer 80 and wiring 82 for relocation wiring. The insulating layer 80 is realized by a resin such as polyimide or epoxy glass, and the wiring 82 is realized by a metal wiring such as copper foil. The insulating layer 80 needs to have heat resistance that can withstand soldering when mounting the resonator device 1, and it is preferable to use polyimide. The material of the wiring 82 may be a metal material such as aluminum or silver other than copper. The thickness of the wiring layer and the terminal in the relocation wiring layer 8 is, for example, about 10 to 20 μm. By providing the relocation wiring layer 8, it becomes possible to electrically connect the contact pads 38 and 39 formed on the integrated circuit 10 to the external connection terminals 91 and 92. Then, by mounting the external connection terminals 91 and 92 of the resonator device 1 to terminals and wiring of a circuit board or the like on which the resonator device 1 is mounted, it becomes possible to incorporate the resonator device 1 into an electronic device. Furthermore, by providing such a relocation wiring layer 8, it is possible to mechanically protect the integrated circuit 10 and thermally protect the integrated circuit 10 etc. from heat in the soldering process when mounting the resonator device 1.

[0021] Fig. 2 is a cross-sectional view showing a specific configuration example of the vibration device 1, and Fig. 3 is a plan view showing an example of a vibration element 5 of the vibration device 1. First, the vibration element 5 will be described in detail with reference to Fig. 3.

[0022] The vibration element 5 is an element that generates mechanical vibration by an electrical signal. For example, as shown in FIG. 3, the vibration element 5 has a vibration substrate 50 and an electrode arranged on the surface of the vibration substrate 50. The vibration substrate 50 has a thickness-shear vibration mode, and is formed of an AT-cut quartz substrate in this embodiment. The AT-cut quartz substrate has a third-order frequency-temperature characteristic, and therefore the vibration element 5 has excellent temperature characteristics. The electrodes include an excitation electrode 52 arranged on the upper surface of the vibration substrate 50 and an excitation electrode 53 arranged on the lower surface opposite the excitation electrode 52. The upper surface is the surface on the positive side in the Z-axis direction, and the lower surface is the surface on the negative side in the Z-axis direction. One of the excitation electrodes 52 and 53 is a first excitation electrode, and the other of the excitation electrodes 52 and 53 is a second excitation electrode. The electrodes also have a pair of terminals 56, 57 arranged on the underside of the vibration substrate 50, a wiring 54 electrically connecting the terminal 56 and the excitation electrode 52, and a wiring 55 electrically connecting the terminal 57 and the excitation electrode 53.

[0023] The configuration of the vibration element 5 is not limited to the above configuration. For example, the vibration element 5 may be a mesa type in which the vibration region sandwiched between the excitation electrodes 52 and 53 protrudes from its surroundings, or conversely, may be an inverted mesa type in which the vibration region is recessed from its surroundings. In addition, the vibration substrate 50 may be subjected to bevel processing for grinding the periphery, or convex processing for making the upper and lower surfaces convex curved. In addition, the vibration element 5 is not limited to one that vibrates in a thickness-shear vibration mode. For example, the vibration element 5 may be a tuning fork type vibration element in which multiple vibration arms flexurally vibrate in an in-plane direction, a tuning fork type vibration element in which multiple vibration arms flexurally vibrate in an out-of-plane direction, a gyro sensor element that includes a driving arm that vibrates for driving and a detection arm that vibrates for detection and detects angular velocity, or an acceleration sensor element that includes a detection unit that detects acceleration. In addition, the vibration substrate 50 is not limited to one formed from an AT-cut quartz substrate, and may be formed from a quartz substrate other than an AT-cut quartz substrate, for example, an X-cut quartz substrate, a Y-cut quartz substrate, a Z-cut quartz substrate, a BT-cut quartz substrate, an SC-cut quartz substrate, an ST-cut quartz substrate, or the like. In the present embodiment, the vibration substrate 50 is made of quartz, but is not limited thereto, and may be made of, for example, a piezoelectric single crystal such as lithium niobate, lithium tantalate, lithium tetraborate, potassium niobate, gallium phosphate, or other piezoelectric single crystal. The vibration element 5 is not limited to a piezoelectric drive type vibration element, and may be an electrostatic drive type vibration element using electrostatic force.

[0024] As shown in FIG. 2 and FIG. 3, the vibration element 5 is fixed to the first surface 21, which is the upper surface of the semiconductor substrate 20, via conductive bonding members 60 and 61. Although not shown in FIG. 2, as shown in FIG. 3, for example, two bonding members 60 and 61 are provided along the Y-axis direction. As shown in FIG. 10 described later, the semiconductor substrate 20 is provided with two through electrodes 40 and 41 along the Y-axis direction, and these through electrodes 40 and 41 are electrically connected to the vibration element 5 via conductive bonding members 60 and 61. One of the through electrodes 40 and 41 is a first through electrode, and the other of the through electrodes 40 and 41 is a second through electrode. Specifically, one end of the through electrode 40 is electrically connected to the excitation electrode 52 of the vibration element 5 via the bonding member 60, the terminal 56 of the vibration element 5, and the wiring 54. One end of the through electrode 41 is electrically connected to the excitation electrode 53 of the vibration element 5 via the bonding member 61, the terminal 57 of the vibration element 5, and the wiring 55. The other ends of the through electrodes 40, 41 are electrically connected to the integrated circuit 10. This allows the vibration element 5 and the integrated circuit 10 to be electrically connected via the through electrodes 40, 41. Specifically, the other ends of the through electrodes 40, 41 are electrically connected to the oscillation circuit 11 of the integrated circuit 10 via contact pads 36, 37 shown in Figures 2 and 10. This allows the vibration element 5 and the oscillation circuit 11 to be electrically connected via the through electrodes 40, 41.

[0025] The bonding members 60 and 61 are not particularly limited as long as they have both electrical conductivity and bonding properties, and can be realized by various conductive bumps 62 such as gold bumps, silver bumps, copper bumps, solder bumps, and resin core bumps. Alternatively, the bonding members 60 and 61 may be conductive adhesives in which conductive fillers such as silver fillers are dispersed in various adhesives such as polyimide, epoxy, silicone, and acrylic adhesives.

[0026] In addition, the semiconductor substrate 20 is thermally oxidized after the through holes are formed, so that an insulating layer 44, which is an insulating film made of, for example, silicon oxide (SiO2), is formed on the first surface 21 of the semiconductor substrate 20 and the inner surface of the through holes. By forming the insulating layer 44 by thermal oxidation, a dense and homogeneous insulating layer 44 can be formed on the surface of the semiconductor substrate 20. In addition, the difference in linear expansion coefficient between the insulating layer 44 and the semiconductor substrate 20 can also be reduced. Therefore, thermal stress is less likely to occur, and a resonator device 1 having excellent oscillation characteristics can be realized. The constituent material of the insulating layer 44 is not particularly limited, and may be made of, for example, silicon nitride (SiN) or resin. In addition, the method of forming the insulating layer 44 is not limited to thermal oxidation, and may be formed by, for example, CVD (Chemical Vapor Deposition).

[0027] Then, the through-holes are filled with a conductive material such as copper or conductive polysilicon inside the insulating layer 44 to form the through-holes 40, 41. That is, the through-holes are filled with a conductive material to form the through-holes 40, 41. One end of the through-holes 40, 41 is electrically connected to the vibration element 5. Specifically, one end of the through-holes 40, 41 is electrically connected to the excitation electrodes 52, 53 of the vibration element 5. Meanwhile, the other end of the through-holes 40, 41 is electrically connected to the integrated circuit 10. Specifically, the other end of the through-holes 40, 41 is electrically connected to the oscillation circuit 11 of the integrated circuit 10 via the contact pads 36, 37.

[0028] As shown in FIG. 2, the integrated circuit 10 is composed of, for example, an N-type transistor 23 and a P-type transistor 24. These transistors 23 and 24 are composed of a source region and a drain region, which are diffusion regions formed in a semiconductor substrate 20, a gate electrode, and a gate oxide film. The transistors 23 and 24 are isolated by an element isolation film 25 called LOCOS (Local Oxidation of Silicon). The integrated circuit 10 also includes a wiring layer 30 that realizes connection wiring between a plurality of circuit elements such as the transistors 23 and 24. For example, the wiring layer 30 in FIG. 2 includes metal layers 31 and 32 and insulating layers 33, 34, and 35. The metal layers 31 and 32 are a first metal layer and a second metal layer, respectively, and the insulating layers 33, 34, and 35 are a first insulating layer, a second insulating layer, and a third insulating layer, respectively. The metal layer 31 is formed between the insulating layer 33 and the insulating layer 34, and the metal layer 32 is formed between the insulating layer 34 and the insulating layer 35. These metal layers 31 and 32 are realized by metals such as aluminum and copper. The metal layers 31 and 32 are electrically connected by contacts called via contacts, and the metal layers 31 and the source regions and drain regions of the transistors 23 and 24 are electrically connected by the contacts. As shown in FIG. 2, the contact pads 36 electrically connected to the other ends of the through electrodes 40 and 41 are formed by the lower metal layer 31. The contact pads 38 and 39 electrically connected to the external connection terminals 91 and 92 are formed by the upper metal layer 32. In the wiring layer 30, the layer closer to the transistors 23 and 24 in the integrated circuit 10 is the lower layer, and the layer farther from the transistors 23 and 24 is the upper layer. FIG. 2 shows a case where the wiring layer 30 has two metal layers 31 and 32, but this embodiment is not limited to this, and the wiring layer 30 may have three or more metal layers. In this case, the contact pads 36 and 37 are formed by the lowest metal layer among the multiple metal layers, and the contact pads 38 and 39 are formed by the highest metal layer. Moreover, a passivation film is formed by the uppermost insulating layer 35 made of insulating resin such as polyimide.

[0029] The rearrangement wiring layer 8 includes an insulating layer 80 realized by a resin layer such as polyimide or epoxy glass, and wiring 82 realized by copper foil or the like. The contact pad 38 is electrically connected to an external connection terminal 91, and the contact pad 39 is electrically connected to the external connection terminal 92 via the wiring 82.

[0030] 2, each of the external connection terminals 91, 92 has a two-layer structure having a first metal layer 84 and a second metal layer 86. For example, a titanium tungsten layer is used as the first metal layer 84 on the insulating layer 80 side in order to improve adhesion with the insulating layer 80. For example, a metal layer such as copper or gold is used as the second metal layer 86, which is easy to solder to external terminals and wiring.

[0031] FIG. 4 shows a configuration example of the integrated circuit 10 of this embodiment. The integrated circuit 10 of this embodiment can include a terminal TXA, a terminal TXB, a terminal TCK, a terminal TVDD, a terminal TGND, a terminal TOE, an oscillation circuit 11, an output circuit 12, a control circuit 13, a reference voltage generating circuit 14A, a regulator circuit 14B, a temperature compensation circuit 15, a temperature sensor 16, and a storage unit 17. The vibration device 1 of this embodiment also includes a vibration element 5 and an integrated circuit 10. The oscillation circuit 11 is a circuit that oscillates the vibration element 5. For example, the oscillation circuit 11 is electrically connected to the terminal TXA and the terminal TXB, and generates an oscillation signal OSC by oscillating the vibration element 5. For example, the oscillation circuit 11 drives the vibration element 5 via the wiring LA and the wiring LB connected to the terminal TXA and the terminal TXB, and oscillates the vibration element 5. For example, the oscillation circuit 11 includes a drive circuit for oscillation provided between the terminal TXA and the terminal TXB. Although details will be described later in FIG. 11, the oscillation circuit 11 can be realized by transistors such as bipolar transistors that realize the drive circuit 132, and passive elements such as capacitors and resistors. The drive circuit 132 is a core circuit of the oscillation circuit 11, and the drive circuit 132 drives the vibration element 5 with a current or voltage to oscillate the vibration element 5. As the oscillation circuit 11, various types such as Pierce type, Colpitts type, inverter type, and Hartley type can be used. In addition, although details will be described later in FIG. 11, a variable capacitance circuit or the like may be provided in the oscillation circuit 11, and the oscillation frequency may be adjusted by adjusting the capacitance of this variable capacitance circuit. More specifically, the oscillation circuit 11 may have a first variable capacitance circuit 136 electrically connected to the wiring LA to which the terminal TXA is connected, and a second variable capacitance circuit 137 electrically connected to the wiring LB to which the terminal TXB is connected. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that allows information to be transmitted by an electrical signal. The electrical connection may be via a passive element or the like.

[0032] The output circuit 12 outputs a clock signal CK based on the oscillation signal OSC from the oscillation circuit 11. For example, the output circuit 12 buffers the oscillation signal OSC from the oscillation circuit 11 and outputs the clock signal CK. For example, the output circuit 12 can also perform waveform shaping and voltage level shifting of the oscillation signal OSC. The signal format of the clock signal output by the output circuit 12 is, for example, a single-ended CMOS signal format, a clipped sine wave signal format, or the like, but is not limited to these. For example, the signal format may be LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed ​​Current Steering Logic), or differential CMOS (Complementary MOS) signal format.

[0033] The control circuit 13 performs various control processes. For example, the control circuit 13 controls the entire integrated circuit 10. For example, the control circuit 13 controls the operation sequence of the integrated circuit 10. The control circuit 13 also performs various processes for controlling the oscillator circuit 11. The control circuit 13 can also control the output circuit 12, etc. The control circuit 13 can be realized by an ASIC (Application Specific Integrated Circuit) circuit that is automatically placed and wired, such as a gate array.

[0034] The temperature sensor 16 is a sensor that detects temperature. Specifically, the temperature sensor 16 outputs a temperature-dependent voltage that changes according to the environmental temperature as a temperature detection voltage VT. For example, the temperature sensor 16 generates the temperature detection voltage VT by using a circuit element having temperature dependency. Specifically, the temperature sensor 16 uses the temperature dependency of the forward voltage of a PN junction to output the temperature detection voltage VT whose voltage value changes depending on temperature. For example, the base-emitter voltage of a bipolar transistor can be used as the forward voltage of the PN junction.

[0035] The temperature compensation circuit 15 performs temperature compensation for the oscillation frequency of the oscillation circuit 11. For example, the temperature compensation circuit 15 generates a temperature compensation voltage VCP based on the temperature detection voltage VT from the temperature sensor 16, and outputs the temperature compensation voltage VCP to the oscillation circuit 11, thereby performing temperature compensation for the oscillation frequency of the oscillation circuit 11. For example, the temperature compensation circuit 15 performs temperature compensation by outputting the temperature compensation voltage VCP, which becomes a capacitance control voltage for the variable capacitance circuit, to the variable capacitance circuit included in the oscillation circuit 11. Temperature compensation is a process for suppressing and compensating for fluctuations in the oscillation frequency due to temperature fluctuations.

[0036] For example, the temperature compensation circuit 15 performs analog temperature compensation by polynomial approximation. For example, when the temperature compensation voltage VCP for compensating the frequency-temperature characteristic of the vibration element 5 is approximated by a polynomial, the temperature compensation circuit 15 performs analog temperature compensation based on coefficient information of the polynomial. The analog temperature compensation is temperature compensation realized by, for example, addition processing of a current signal or a voltage signal, which is an analog signal. For example, when the temperature compensation voltage VCP is approximated by a high-order polynomial, the zero-order coefficient, the first-order coefficient, and the high-order coefficient of the polynomial are stored in the storage unit 17 as zero-order correction data, first-order correction data, and high-order correction data, respectively. For example, they are stored in the storage unit 17 realized by a non-volatile memory. The high-order coefficient is, for example, a coefficient of a higher order than the first order, and the high-order correction data is correction data corresponding to the high-order coefficient. For example, when the temperature compensation voltage VCP is approximated by a fifth-order polynomial, the zeroth-order coefficient, the first-order coefficient, the second-order coefficient, the third-order coefficient, the fourth-order coefficient, and the fifth-order coefficient of the polynomial are stored in the memory unit 17 as zeroth-order correction data, first-order correction data, second-order correction data, third-order correction data, fourth-order correction data, and fifth-order correction data.

[0037] The temperature compensation circuit 15 performs temperature compensation based on the zeroth-fifth order correction data. Temperature compensation based on the second-order correction data or the fourth-order correction data may be omitted. The degree of polynomial approximation is arbitrary, and for example, a third-order polynomial approximation or a polynomial approximation of an order greater than the fifth order may be performed. The zeroth order correction may be performed by the temperature sensor 16. Alternatively, the temperature sensor 16 may not be provided in the integrated circuit 10, and the temperature compensation circuit 15 may perform temperature compensation based on a temperature detection signal such as a temperature detection voltage input from the outside.

[0038] The temperature compensation circuit 15 may perform digital temperature compensation. In this case, the temperature compensation circuit 15 is realized by, for example, a logic circuit. Specifically, the temperature compensation circuit 15 performs digital temperature compensation processing based on temperature detection data, which is temperature detection information from the temperature sensor 16. For example, the temperature compensation circuit 15 obtains frequency adjustment data based on the temperature detection data. Then, the capacitance value of the variable capacitance circuit of the oscillation circuit 11 is adjusted based on the obtained frequency adjustment data, thereby achieving temperature compensation processing of the oscillation frequency of the oscillation circuit 11. In this case, the variable capacitance circuit of the oscillation circuit 11 is realized by a capacitor array having a plurality of binary-weighted capacitors and a switch array. The storage unit 17 also stores a lookup table indicating the correspondence between the temperature detection data and the frequency adjustment data, and the temperature compensation circuit 15 performs temperature compensation processing to obtain the frequency adjustment data from the temperature data using the lookup table read from the storage unit 17 by the control circuit 13.

[0039] When performing digital temperature compensation processing, the temperature sensor 16 measures a temperature such as an environmental temperature, and outputs the result as temperature detection data. The temperature detection data is, for example, data that monotonically increases or decreases with respect to temperature. In this case, the temperature sensor 16 may be one that utilizes the temperature dependency of the oscillation frequency of a ring oscillator. Specifically, the temperature sensor 16 includes a ring oscillator and a counter circuit. The counter circuit counts the output pulse signal, which is the oscillation signal of the ring oscillator, during a count period defined by a clock signal based on the oscillation signal OSC from the oscillation circuit 11, and outputs the count value as temperature detection data.

[0040] The control circuit 13 controls the temperature compensation circuit 15. The control circuit 13 can also control the oscillation circuit 11, the output circuit 12, the regulator circuit 14B, or the storage unit 17. For example, the control circuit 13 has a register, and at the start of normal operation in which the vibration element 5 is oscillated to output a clock signal CK, information stored in the storage unit 17 is read out and transferred to and stored in the register of the control circuit 13. Then, based on the information stored in the register, various control signals are generated and output to each circuit of the integrated circuit 10 to control each circuit. Therefore, since the control circuit 13 does not need to operate at high speed during normal operation, the noise generated by the control circuit 13 is low. The integrated circuit 10 may have a first mode in which temperature compensation is turned on and a second mode in which temperature compensation is turned off. In this case, the control circuit 13 can control switching between the first mode and the second mode.

[0041] The reference voltage generating circuit 14A generates a reference voltage VREF based on a power supply voltage VDD. For example, the reference voltage VREF is generated to be a constant voltage even when there is a power supply voltage fluctuation or a temperature fluctuation. The reference voltage generating circuit 14A can be realized by, for example, a bandgap reference circuit that generates the reference voltage VREF based on a bandgap voltage.

[0042] The regulator circuit 14B generates a regulated power supply voltage based on the power supply voltage VDD. For example, the regulator circuit 14B generates a regulated power supply voltage based on the power supply voltage VDD from the terminal TVDD and the reference voltage VREF from the reference voltage generation circuit 14A. By using the reference voltage VREF that remains constant even when the power supply voltage or temperature fluctuates, a regulated power supply voltage that is a step-down power supply voltage of the power supply voltage VDD and remains constant even when the power supply voltage or temperature fluctuates can be generated. The regulator circuit 14B then supplies the generated regulated power supply voltage to each circuit block of the integrated circuit 10. In this case, the regulator circuit 14B supplies an appropriate regulated power supply voltage according to each circuit block, for example, by making the voltage value of the regulated voltage supplied to the temperature compensation circuit 15 and the regulated voltage supplied to the control circuit 13 different.

[0043] An output enable signal OE is input to the terminal TOE. The terminal TOE is electrically connected to the external terminal TE7 of the vibration device 1. The control circuit 13 performs output enable control processing based on the output enable signal OE input from the terminal TOE. In the test mode, a test signal for the vibration element 5 may be input via the terminal TOE. In this case, a switch circuit is provided for connecting the terminal TOE and the wiring LA, and the test signal input from the terminal TOE is input to one end of the vibration element 5 via the switch circuit and the wiring LA. This enables testing and inspection of the vibration element 5, such as overdrive. In addition, when the storage unit 17 is realized by a nonvolatile memory, a high voltage for memory writing may be input via the terminal TOE when writing information to the nonvolatile memory, and supplied to the nonvolatile memory that is the storage unit 17.

[0044] The storage unit 17 is a circuit that stores various information, and can be realized by a semiconductor memory or the like. Specifically, the storage unit 17 can be realized by a nonvolatile memory. As the nonvolatile memory, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory) that allows data to be electrically erased, or an OTP (One Time Programmable) memory using a FAMOS (Floating gate Avalanche injection MOS) or the like can be used. Alternatively, the nonvolatile memory may be a memory using fuse cells. When the temperature compensation circuit 15 performs temperature compensation using polynomial approximation, the storage unit 17 realized by a nonvolatile memory or the like stores coefficient information of the polynomial approximation. For example, the storage unit 17 stores the above-mentioned zero-order correction data, first-order correction data, and high-order correction data as coefficient information of the polynomial approximation. Such coefficient information is written and stored in the storage unit 17 realized by a nonvolatile memory or the like, for example, at the time of manufacturing or shipping the integrated circuit 10 or the vibration device 1. This makes it possible to set the temperature compensation coefficient information according to the model of the integrated circuit 10 or the resonator device 1.

[0045] Next, a method for manufacturing the vibration device 1 of this embodiment will be described. Although the flow is not illustrated, the vibration device 1 can be manufactured, for example, by the following method. First, a wafer-shaped semiconductor substrate 20 having a standard thickness is prepared. The standard thickness is specifically 625 to 775 μm. This allows the semiconductor substrate 20 to be stably handled in the manufacturing process of the integrated circuit 10. Then, the integrated circuit 10 is formed on the second surface 22, which is the lower surface. The thickness of the integrated circuit 10 is 5 to 20 μm. Then, an insulating layer 80, a relocation wiring layer 8 having wiring 82, and external connection terminals 91, 92 are formed on the second surface 22, and the contact pads 38, 39, etc. of the integrated circuit 10 are electrically connected to the external connection terminals 91, 92, etc. The thickness of the relocation wiring layer 8 is 10 to 20 μm. Then, the first surface 21 side of the semiconductor substrate 20, which is the side on which the vibration element 5 is mounted, is ground by a back grinder or the like. That is, the thickness of the base 2 is thinned to a predetermined thickness. The predetermined thickness is a thickness that allows the formation of a through hole, which will be described later, by dry etching, and is specifically 20 μm to 100 μm. Then, a desired region of the base 2 is removed from the first surface 21 side by dry etching. Furthermore, a desired region of the element isolation film 25 is removed by wet etching. As a result, a through hole penetrating from the first surface 21 to the metal layer 31 of the wiring layer 30 is formed. Then, an insulating layer 44, which is an insulating film, is formed on the surface of the semiconductor substrate 20, particularly on the inner surface of the through hole, and further, the through hole is filled with a conductive material such as copper to form the through electrodes 40, 41. Then, the vibration element 5 is prepared, and the vibration element 5 is bonded to the first surface 21 of the semiconductor substrate 20 via the bonding members 60, 61. Then, a wafer having the same size as the semiconductor substrate 20 and on which the lid 7 is formed is prepared. Then, in a reduced pressure environment, the wafer including the base 2 and the wafer including the lid 7 are bonded to each other via the bonding members 71, 72. Thereafter, the bonded wafer is diced by a dicing saw or the like to separate the vibration devices 1. As a result, the vibration devices 1 having the vibration elements 5 and the integrated circuits 10 are collectively manufactured by wafer-level batch processing, which enables the vibration devices 1 to be manufactured at high throughput and low cost.That is, the resonation device 1 of the present embodiment is a WLP (Wafer Level Package).

[0046] The above description is an example of the configuration of the resonator device 1 in which the integrated circuit 10 is formed on the second surface 22, but the present embodiment is not limited to this, and various modifications are possible. For example, as shown in FIG. 5, the resonator device 101 may be configured to have the integrated circuit 110 formed on the first surface 121. The resonator device 101 includes a base 102, a resonator element 105, and external connection terminals 191 and 192. The resonator device 101 may also include a relocation wiring layer 108. The base 102 includes through electrodes 140 and 141. The resonator element 105 is disposed on the first surface 121 side. For example, the resonator element 105 is disposed at a position spaced apart from the first surface 121 by a given distance. The resonator element 105 is fixed to the first surface 121 via, for example, a conductive bonding member 160. The external connection terminals 191 and 192 are provided on the second surface 122 side via an insulating layer 180, wiring 182, or the like. The insulating layer 180 is an insulating layer that constitutes the relocation wiring layer 108. These can be formed by appropriately using the above-mentioned techniques.

[0047] The resonating device 101 may also include a lid 107. Third metal layers 171 and 172 are provided on the first surface 121. The third metal layers 171 and 172 are, for example, 100 nm thick, made of gold, but may be made of metal such as copper. Fourth metal layers 173 and 174 are provided on the surfaces of the lid 107 that contact the third metal layers 171 and 172. The fourth metal layers 173 and 174 are, for example, 20 nm thick, made of gold, but may be made of metal such as copper. The third metal layers 171 and 172 are bonded to the fourth metal layers 173 and 174 by activation bonding, whereby the lid 107 and the first surface 121 are bonded. The activation bonding is a method in which the surfaces of the third metal layers 171, 172 and the fourth metal layers 173, 174 are activated by irradiating the third metal layers 171, 172 and the fourth metal layers 173, 174 with a neutral argon ion beam or the like, and then the third metal layers 171, 172 and the fourth metal layers 173, 174 are brought into contact with each other to perform bonding. This allows the third metal layers 171, 172 and the fourth metal layers 173, 174 to be bonded at room temperature without the need for pressure. A fifth metal layer 176 may be further formed on the bottom surface of the recess of the lid 107. Sixth metal layers 177, 178 may be further formed on the side surfaces of the recess of the lid 107. The fifth metal layer 176 and the sixth metal layers 177, 178 are, for example, gold having a thickness of 20 nm, but may be metal such as copper. As a result, the fifth metal layer 176 and the sixth metal layers 177 and 178 can protect the integrated circuit 110 and the vibration element 105 from disturbances such as unwanted radiation as a shielding layer. In addition, by making the thickness of the fifth metal layer 176 and the sixth metal layers 177 and 178 about 20 nm, infrared rays can be transmitted. As a result, for example, by making the material of the lid 107 silicon, the vibration element 105 inside the vibration device 101 can be inspected using infrared rays. Although not shown, an adhesive layer such as titanium may be formed between the third metal layers 171 and 172, the fourth metal layers 173 and 174, the fifth metal layer 176, and the sixth metal layers 177 and 178 and the lid 107.

[0048] From the above, the vibration device 1 of this embodiment includes a semiconductor substrate 20, a base 2, a vibration element 5, and a lid 7. The semiconductor substrate 20 has a first surface 21 and a second surface 22 that is opposite to the first surface 21. The base 2 includes an integrated circuit 10 arranged on the first surface 21 or the second surface 22. The vibration element 5 is electrically connected to the integrated circuit 10 and arranged on the first surface 21 side. The lid 7 is joined to the base 2 at a joint JA of the base 2 so as to accommodate the vibration element 5. Note that the integrated circuit 10 being arranged on the first surface 21 or the second surface 22 includes the integrated circuit 10 being arranged on both the first surface 21 and the second surface 22.

[0049] A WLP such as the resonator device 1 of this embodiment has a unique problem described below. FIG. 6 shows the effect of stress on the resonator device 1 of this embodiment. For convenience, the resonator element 5 and the external connection terminals 91 and 92 are not shown in FIG. 6. Since the materials constituting the device have different thermal expansion coefficients, packaging causes stress. For example, the thermal expansion coefficient of silicon, which is the material of the base 2, is about 3 ppm / K, whereas the thermal expansion coefficient of copper, which is the wiring material, is about 17 ppm / K. Therefore, in the manufacturing process, the thermal contraction amount of the integrated circuit 10 and the relocation wiring layer 8 is larger than the thermal contraction amount of the base 2, so that stress is generated based on the difference in the thermal contraction amount. At this time, if the thickness of the base 2 is the above-mentioned standard thickness, it is sufficiently thicker than the integrated circuit 10 and the relocation wiring layer 8, so that even if stress is applied, the base 2 does not deform and maintains flatness. However, as described above, the base 2 is thinned to 20 μm to 100 μm in the manufacturing process, so the rigidity of the base 2 is lost and the effect of stress cannot be ignored. Specifically, as shown in B3, the base 2, the integrated circuit 10, and the relocation wiring layer 8 cannot maintain flatness and are warped. This causes distortion in the passive and active elements constituting the integrated circuit 10, affecting the characteristics of the passive and active elements, as will be described in detail later with reference to FIGS. 7, 8, and 9. This problem may also occur when the package is soldered to an external circuit board, or when the package and the circuit board are fixed with an underfill agent. On the other hand, the regions indicated by A1 and A2 in FIG. 6 are regions where the lid 7 is bonded, that is, regions including the joint JA. If the base 2 and the lid 7 are both made of silicon, they have the same thermal expansion coefficient, so that in the regions indicated by A1 and A2, the thickness of the base 2 plus the lid thickness TL is substantially the thickness of the base 2. In other words, the regions indicated by A1 and A2 are equivalent to the integrated circuit 10 and the relocation wiring layer 8 being formed on a base 2 with higher rigidity than the region indicated by A3. Therefore, the regions indicated by A1 and A2, i.e., the regions including the joint JA, are flat or have little warping, as indicated by B1 and B2.

[0050] 7 shows a schematic structure of the resistor R of this embodiment. If the resistor R is a rectangular parallelepiped with a length RL, a width RW, and a thickness RT, the resistance value of the resistor R is (ρ×RL) / (RW×RT), where ρ is resistivity. Then, due to the influence of the above-mentioned stress, the resistor R is deformed into a rectangular parallelepiped with a length (RL+ΔRL), a width (RW+ΔRW), and a thickness (RT+ΔRT), and the resistance value of the resistor R changes. The specific influence of the change in the resistance value of the resistor R on the integrated circuit 10 will be described later.

[0051] FIG. 8 shows a schematic diagram of a structure example of the capacitor C of this embodiment. The capacitor C includes conductor layers 210A and 210B and an insulating layer 220 between the conductor layers 210A and 210B. If the length of the conductor layers 210A and 210B is CL, the width is CW, and the thickness of the insulating layer 220 is CD, the capacitance of the capacitor C is (ε×CL×CW) / CD, where ε is the dielectric constant. Due to the influence of the above-mentioned stress, the length of the conductor layers 210A and 210B changes to (CL+ΔCL) and the width changes to (CW+ΔCW). In addition, the thickness of the insulating layer 220 changes to (CD+ΔCD). As a result, the capacitance of the capacitor C changes. The specific influence of the change in capacitance of the capacitor C on the circuit will be described later.

[0052] 9 is a schematic diagram showing an example of the structure of the bipolar transistor BP according to the present embodiment. When stress is applied to the bipolar transistor BP, crystal defects 232 are generated in the base region 230 of the bipolar transistor BP. This increases the leakage recombination current, and changes the characteristics of the bipolar transistor BP.

[0053] FIG. 10 is a plan view showing an example of the arrangement of the through electrodes 40 and 41, the terminals TCK, TGND, TOE, TVC, TVDD, TXA, and TXB, and the integrated circuit 10 in the resonator device 1 of this embodiment. FIG. 10 shows the relationship between the arrangement positions of each circuit of the integrated circuit 10, the arrangement positions of the through electrodes 40 and 41, and the terminals TCK, TGND, TOE, TVC, TVDD, TXA, and TXB. FIG. 10 is a plan view of the base 2 as seen from the negative side in the Z-axis direction, and the outlines of the through electrodes 40 and 41 located on the positive side in the Z-axis direction with respect to the base 2 on which the integrated circuit 10 is formed are shown by dotted lines. In addition, the lid inner wall line 9L indicating the position of the inner wall portion 9 of the lid 7 is shown by dotted lines. In other words, the area between the lid inner wall line 9L and the base outer peripheral line 2L corresponds to the above-mentioned joint JA.

[0054] 10, the area surrounded by the product area line 3L is the product area, and the area between the product area line 3L and the base outer periphery line 2L indicating the outer periphery of the base 2 is the scribe area. The scribe area is an area where an accessory pattern is arranged, and is also a cutting area for singulating the wafer into individual vibration devices 1. The accessory pattern is a pattern consisting of an evaluation element for checking the electrical characteristics of the element, an electrode pad for supplying power to the evaluation element, etc.

[0055] A guard ring 27 is formed around the edge of the product area so as to surround the integrated circuit 10. The guard ring 27 is formed, for example, by forming and contacting dummy metal with each of the metal layers 31, 32 and the insulating layers 33, 34 constituting the wiring layer 30 in Fig. 2, and prevents the intrusion of moisture and the like from the outside world. This makes it possible to protect the entire integrated circuit 10. Note that the number of guard rings 27 is not limited to two as shown in Fig. 10, and may be one, or three or more.

[0056] In this embodiment, as shown in Fig. 10, the base 2 has a first side SD1 and a second side SD2 opposite the first side SD1. That is, the integrated circuit 10 has a first side SD1 and a second side SD2 opposite the first side SD1. The base 2 also has a third side SD3 and a fourth side SD4 opposite the third side SD3. For example, the base 2 has a rectangular shape having a first side SD1, a second side SD2, a third side SD3, and a fourth side SD4 in a plan view. Note that the rectangular shape does not need to be a strict rectangular shape, and may be a shape in which the corners are chamfered, for example.

[0057] As described above, the vibration device 1 of this embodiment includes a semiconductor substrate 20, a base 2 including a through electrode 40 penetrating between a first surface 21 and a second surface 22 of the semiconductor substrate 20, and a vibration element 5 disposed on the first surface 21 side of the semiconductor substrate 20. On the second surface 22 of the semiconductor substrate 20, as shown in FIG. 10, an oscillation circuit 11 is electrically connected to the vibration element 5 via the through electrodes 40 and 41, and the oscillation circuit 11 oscillates the vibration element 5 to generate an oscillation signal OSC, and an output circuit 12 outputs a clock signal CK based on the oscillation signal OSC. For example, the oscillation circuit 11 oscillates the vibration element 5 to generate an oscillation signal OSC, and the oscillation signal OSC is buffered by the output circuit 12 and output as a clock signal CK. In addition, the clock signal CK from the output circuit 12 is output from the external connection terminal 91. That is, the clock signal CK from the output circuit 12 in FIG. 4 is output from a terminal TCK realized by the contact pad 38.

[0058] In the resonator device 1 of this embodiment, the integrated circuit 10 includes a passive element, and the passive element is arranged so that at least a part of the passive element overlaps the joint JA in a plan view from a direction perpendicular to the first surface 21. Details will be described later in FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG. 16, etc., but the oscillator circuit 11, the reference voltage generating circuit 14A, the regulator circuit 14B, the temperature compensation circuit 15, and the temperature sensor 16 include resistors or capacitors that are passive elements. As described above in FIG. 6, the area that does not overlap with the joint JA is greatly affected by stress. In other words, if a passive element exists in the area that does not overlap with the joint JA, the passive element is deformed by the influence of stress, and the characteristics exhibited by the passive element deviate from the designed characteristics. As a result, arranging the oscillator circuit 11, the reference voltage generating circuit 14A, the regulator circuit 14B, the temperature compensation circuit 15, and the temperature sensor 16 in the area that does not overlap with the joint JA affects the characteristics of the resonator device 1 because it is a circuit that includes a passive element. In this regard, in the resonator device 1 of this embodiment, the oscillator circuit 11, the reference voltage generating circuit 14A, the regulator circuit 14B, the temperature compensation circuit 15, and the temperature sensor 16 are arranged so as to overlap with the joint JA. In this manner, the passive elements are arranged in an area overlapping with the joint JA, and thus the passive elements are arranged in an area less affected by stress, so that deformation of the passive elements can be minimized. This makes it possible to stabilize the characteristics of the passive elements. This makes it possible to stabilize the oscillation characteristics of the resonator device 1 after packaging.

[0059] In addition, the passive element in this embodiment is at least one of a capacitive element and a resistive element. For example, a reference voltage generating circuit 14A in FIG. 12 described later includes resistors RD1 to RD3 which are resistive elements. Also, for example, a regulator circuit 14B in FIG. 13 described later includes resistors RD1 to RD3 which are resistive elements and a capacitor CA which is a capacitive element. In this way, it is possible to suppress deformation of these resistors and capacitors. This makes it possible to suppress changes in the capacitance of the capacitor or the resistance value of the resistor. This makes it possible to suppress changes in the oscillation frequency of the resonating device 1.

[0060] Moreover, the capacitive element of this embodiment is at least one of a MIM (Metal-Insulator-Metal) capacitor, a PIP (Polysilicon-Insulator-Polysilicon) capacitor, or a MOS (Metal-Oxide-Semiconductor) capacitor. In order to obtain a larger capacitance in the resonator device 1, a MIM capacitor or a PIP capacitor is used. In addition, in order to temperature compensate the oscillation frequency, a MOS capacitor is used as a variable capacitance element whose capacitance value changes according to the applied voltage. That is, these capacitors are usually often used in the resonator device 1. By applying the above-mentioned method of this embodiment and arranging these capacitors in a position where the influence of stress is small, it is possible to suppress the deformation of these capacitors. This makes it possible to suppress the change in the capacitance of these capacitors. This makes it possible to suppress the change in the oscillation frequency of the resonator device.

[0061] In addition, in this embodiment, the control circuit 13 and the memory unit 17 are arranged inside the lid inner wall line 9L in a plan view. That is, the integrated circuit 10 includes a predetermined circuit arranged in an area that does not overlap with the joint JA in a plan view, and the predetermined circuit includes at least one of the control circuit 13 and the memory unit 17, which is a memory circuit. For example, the influence of stress on the part of the control circuit 13 where the high level and low level of the signal are determined is sufficiently small, so that the contribution of the stress to affect the oscillation frequency of the vibration device is small. Therefore, arranging the control circuit 13 and the like at a position overlapping the joint JA narrows the room for arranging a circuit that is greatly affected by stress at a position overlapping the joint JA. Therefore, by arranging the control circuit 13 and the memory unit 17, which are less affected by the influence of stress, at a position where the influence of stress is large, the room for arranging a circuit that is greatly affected by stress can be increased at a position where the influence of stress is small.

[0062] In this embodiment, as shown in FIG. 10, the oscillation circuit 11 is disposed at a position closer to the first side SD1 than the second side SD2 in a plan view. Specifically, the oscillation circuit 11 is disposed between the first side SD1 and the through electrodes 40 and 41 in a plan view. That is, the oscillation circuit 11 is disposed in a region between the first side SD1 and a line connecting the through electrodes 40 and 41. For example, the oscillation circuit 11 is disposed along the first side SD1, and is disposed so that its longitudinal direction is along the first side SD1. The oscillation circuit 11 is electrically connected to the vibration element 5 via the terminals TXA and TXB realized by the wiring LA and LB and the contact pads 36 and 37, and causes the vibration element 5 to oscillate. For example, the circuit elements such as transistors, capacitors, and resistors constituting the oscillation circuit 11 have conductive layers such as metal layers and diffusion layers having an area in a plan view. Therefore, due to capacitive coupling between the conductive layer in the oscillation circuit 11 and the external connection terminal 91, the signal component of the clock signal CK output from the external connection terminal 91 may be transmitted to the oscillation circuit 11 as noise, which may adversely affect the oscillation characteristics. In this regard, in this embodiment, the oscillation circuit 11 is disposed at a position close to the first side SD1 in a plan view, so that it is possible to increase the distance between the oscillation circuit 11 and the external connection terminal 91 disposed at a position close to the second side SD2 in a plan view. Therefore, the capacitance of the capacitive coupling between the oscillation circuit 11 and the external connection terminal 91 can be reduced, so that it is possible to suppress the occurrence of deterioration of the oscillation characteristics of the oscillation circuit 11.

[0063] 11 shows a configuration example of the oscillator circuit 11. The oscillator circuit 11 includes a drive circuit 132, DC-cut capacitors C1 and C2, a reference voltage supply circuit 134, and a first variable capacitance circuit 136. The oscillator circuit 11 may also include a DC-cut capacitor C4 and a second variable capacitance circuit 137. Note that the capacitor C4 and the second variable capacitance circuit 137 are not essential components, and a modified embodiment in which they are not provided is also possible. Furthermore, capacitors C31 to C3n are provided between the first variable capacitance circuit 136 and the second variable capacitance circuit 137 and the GND node.

[0064] The driving circuit 132 is a circuit that drives the vibration element 5 to oscillate. The driving circuit 132 includes a current source ISA, a bipolar transistor BP0, and a resistor RB. The current source ISA is provided between a power supply node of a regulated power supply voltage VREG and the bipolar transistor BP0, and supplies a constant current to the bipolar transistor BP0.

[0065] The bipolar transistor BP0 is a transistor that drives the vibration element 5, with a base node serving as an input node NI of the drive circuit 132 and a collector node serving as an output node NQ of the drive circuit 132. The resistor RB is provided between the collector node and the base node of the bipolar transistor BP0.

[0066] The DC-cut capacitor C1 is provided between the input node NI of the drive circuit 132 and the wiring LA. By providing such a capacitor C1, the DC component of the oscillation signal is cut and only the AC component is transmitted to the input node NI of the drive circuit 132, allowing the bipolar transistor BP0 to operate properly. The DC-cut capacitor C1 may be provided between the output node NQ of the drive circuit 132 and the wiring LA.

[0067] The reference voltage supply circuit 134 supplies reference voltages VR1 to VRn to the first variable capacitance circuit 136 and the second variable capacitance circuit 137. The reference voltage supply circuit 134 includes, for example, a plurality of resistors arranged in series between a node of a regulated power supply voltage VREG and a node of a GND, and outputs voltages obtained by dividing the voltage of VREG as the reference voltages VR1 to VRn. The reference voltage supply circuit 134 also supplies a reference voltage VRB for setting a bias voltage to the line LA. This makes it possible to set the amplitude center voltage of the oscillation signal on the line LA to the reference voltage VRB. The amplitude center voltage of the oscillation signal on the line LB is set based on, for example, the base-emitter voltage of the bipolar transistor BP0 and the base current flowing through the resistor RB.

[0068] The DC cut capacitor C2 has one end electrically connected to the wiring LA, and the other end electrically connected to a supply node NS1 of the temperature compensation voltage VCP. The temperature compensation voltage VCP is supplied to the supply node NS1 via a resistor RC1. The first variable capacitance circuit 136 has one end electrically connected to the supply node NS1, and the temperature compensation voltage VCP is supplied to the supply node NS1. The reference voltage supply circuit 134 supplies reference voltages VR1 to VRn to the supply nodes NR1 to NRn at the other end of the first variable capacitance circuit 136. The capacitors C31 to C3n are provided between the supply nodes NR1 to NRn of the reference voltages VR1 to VRn and the GND node. The DC cut capacitor C4 has one end electrically connected to the wiring LB, and the other end electrically connected to a supply node NS2 of the temperature compensation voltage VCP. The temperature compensation voltage VCP is supplied to the supply node NS2 via a resistor RC2. A switch and capacitors C7 and C8 are provided between the wiring LA and the GND node, and the load capacitance of the wiring LA is adjusted. In addition, a switch and capacitors C5 and C6 are provided between the wiring LB and the GND node, and the load capacitance of the wiring LB is adjusted. One end of the second variable capacitance circuit 137 is electrically connected to the supply node NS2, and a temperature compensation voltage VCP is supplied to the second variable capacitance circuit 137. In addition, the reference voltage supply circuit 134 supplies reference voltages VR1 to VRn to the supply nodes NR1 to NRn at the other end of the second variable capacitance circuit 137. The first variable capacitance circuit 136 includes n variable capacitance elements, where n is an integer of 2 or more. The n variable capacitance elements are, for example, MOS type variable capacitance elements and are composed of n transistors. The reference voltages VR1 to VRn are supplied to the gates of the n transistors. In addition, the source and drain of each of the n transistors are short-circuited, and the temperature compensation voltage VCP is supplied to the supply node NS1 to which the short-circuited source and drain are connected. The capacitance of the DC cut capacitor C2 is sufficiently larger than the capacitance of the first variable capacitance circuit 136. By using the first variable capacitance circuit 136 having such a configuration, it is possible to ensure the linearity of the change in the total capacitance of the first variable capacitance circuit 136 over a wide voltage range of the temperature compensation voltage VCP.Since the configuration of second variable capacitance circuit 137 is similar to that of first variable capacitance circuit 136, a detailed description thereof will be omitted.

[0069] As described above, in the resonating device 1 of the present embodiment, the integrated circuit 10 includes the oscillation circuit 11 that oscillates the resonating element 5 to output an oscillation signal, and the passive element is at least one of the capacitance element or resistance element included in the oscillation circuit 11. As described above, when the resistor (not shown) included in the reference voltage supply circuit 134 is deformed by stress and the resistance value becomes unstable, the reference voltages VR1 to VRn supplied from the reference voltage supply circuit 134 also become unstable. As a result, the voltage applied to the first variable capacitance circuit 136 also becomes unstable. In addition, as described above in FIG. 8, the capacitances of the capacitors C1, C2, C31 to C3n, and C4 to C8 also become unstable due to the influence of stress. As a result, the load capacitance of the oscillation circuit 11 becomes unstable, and a problem occurs in which the frequency of the resonating device 1 fluctuates. In this regard, by applying the method of the present embodiment, the capacitance element or resistance element included in the oscillation circuit 11 is arranged at a position where it is less affected by stress, so that the deformation of the capacitance element or resistance element included in the oscillation circuit 11 can be suppressed. As a result, the change in the capacitance of the capacitance element or the resistance value of the resistance element included in the oscillation circuit 11 can be suppressed. This makes it possible to suppress changes in the oscillation frequency of the vibration device 1.

[0070] FIG. 12 shows a configuration example of the reference voltage generating circuit 14A. The reference voltage generating circuit 14A includes an N-type transistor TD1, resistors RD1, RD2, RD3, and bipolar transistors BP1 and BP2 that are provided between the VDD node and the GND node. The reference voltage generating circuit 14A also includes P-type transistors TD1 and TD2 to whose gates a bias voltage BS is input, and a bipolar transistor BP3 that is provided between the drain node of the transistor TD2 and the GND node. The reference voltage generating circuit 14A is a bandgap reference circuit that generates and outputs a reference voltage VREF based on a bandgap voltage. For example, the base-emitter voltages of the PNP bipolar transistors BP1 and BP2 are VBE1 and VBE2, and ΔVBE=VBE1-VBE2. The reference voltage generating circuit 14A outputs a reference voltage VREF that satisfies, for example, VREF=K×ΔVBE+VBE2. K is set by the resistance values ​​of the resistors RD1 and RD2. For example, since VBE2 has a negative temperature characteristic and ΔVBE has a positive temperature characteristic, it is possible to generate a constant reference voltage VREF without temperature dependency by adjusting the resistance values ​​of resistors RD1 and RD2. The generated reference voltage VREF is a constant voltage based on the ground voltage. Note that the reference voltage generating circuit 14A is not limited to the configuration shown in FIG. 12, and various circuits of various configurations can be used, such as a circuit that generates the reference voltage VREF using the work function difference voltage of a transistor.

[0071] As described above, in the resonating device 1 of the present embodiment, the integrated circuit 10 includes the reference voltage generating circuit 14A that generates the reference voltage used in the integrated circuit 10, and the passive element is a resistive element included in the integrated circuit 10. As described above, when the resistors RD1, RD2, and RD3 included in the reference voltage generating circuit 14A are deformed by stress and the resistance value becomes unstable, the reference voltage VREF also becomes unstable. As a result, the regulated power supply voltage VREG output from the regulator circuit 14B described later also becomes unstable, and the load capacitance of the oscillation circuit 11 fluctuates. This causes a problem that the frequency of the resonating device 1 fluctuates. In this regard, by applying the method of the present embodiment, the resistive element included in the reference voltage generating circuit 14A is arranged at a position where it is less affected by stress, so that the deformation of the resistive element included in the reference voltage generating circuit 14A can be suppressed. As a result, the change in the resistance value of the resistive element included in the reference voltage generating circuit 14A can be suppressed, and therefore the reference voltage VREF and the regulated power supply voltage VREG can be stabilized. As a result, the change in the oscillation frequency of the resonating device 1 can be suppressed.

[0072] FIG. 13 shows a configuration example of the regulator circuit 14B. The regulator circuit 14B includes an N-type driving transistor TA1 and resistors RA1 and RA2 that are connected in series between a VDD node and a GND node, and an operational amplifier OPA. The regulator circuit 14B may also include a resistor RA3 and a capacitor CA that are connected to the output terminal side of the operational amplifier OPA. A reference voltage VREF is input to the non-inverting input terminal of the operational amplifier OPA, and a voltage VDA obtained by dividing the regulated power supply voltage VREG1 by resistors RA1 and RA2 is input to the inverting input terminal. The output terminal of the operational amplifier OPA is input to the gate of the transistor TA1 via resistor RA3, and the regulated power supply voltage VREG is output from the drain node of the transistor TA1. The regulator circuit 14B outputs the regulated power supply voltage VREG, which is a fixed voltage, by setting the resistors RA1 and RA2 to fixed resistance values, but the resistance values ​​of the resistors RA1 and RA2 may be set variably. This makes it possible to adjust the resistance value to compensate for fluctuations in the regulated power supply voltage VREG due to process variations during manufacturing and shipping, for example.

[0073] As described above, in the resonator device 1 of this embodiment, the integrated circuit 10 includes the regulator circuit 14B that generates the regulated power supply voltage VREG, and the passive element is a resistive element included in the regulator circuit 14B. As described above, when the resistors RA1 and RA2 included in the regulator circuit 14B are deformed by stress and the resistance value changes, the ratio of the resistors RA1 and RA2 changes, and the regulated power supply voltage VREG changes. This causes a problem that the load capacity of the oscillator circuit 11 changes and the frequency of the resonator device 1 changes. In this regard, by applying the method of this embodiment, the resistive element included in the regulator circuit 14B is arranged at a position where it is less affected by stress, so that the deformation of the resistive element included in the regulator circuit 14B can be suppressed. As a result, the change in the resistance value of the resistive element included in the regulator circuit 14B can be suppressed, and therefore the change in the regulated power supply voltage VREG can be suppressed. As a result, the change in the oscillation frequency of the resonator device 1 can be suppressed.

[0074] As described above, the resonating device 1 of this embodiment includes at least one of the reference voltage generating circuit 14A that generates a reference voltage used in the integrated circuit 10 and the regulator circuit 14B that generates a regulated power supply voltage VREG that is used in the integrated circuit 10. At least a part of the passive elements or active elements included in at least one of the reference voltage generating circuit 14A or the regulator circuit 14B is arranged so as to overlap with the junction JA in a plan view from a direction perpendicular to the first surface 21. For example, the reference voltage generating circuit 14A includes bipolar transistors BP1 to BP3 as active elements in addition to the passive elements as described above. As described above in FIG. 9, if the bipolar transistors BP1 to BP3 are present in an area that does not overlap with the junction JA, the base currents of the bipolar transistors BP1 to BP3 change due to the influence of stress. As a result, the reference voltage VREF becomes unstable, and the problem of the frequency of the resonating device 1 changing occurs as described above. In this regard, by applying the method of the present embodiment, for example, by arranging the resistors RD1 to RD3 as passive elements or the bipolar transistors BP1 to BP3 as active elements in the region overlapping with the joint JA, it is possible to stabilize these characteristics. This makes it possible to stabilize the oscillation characteristics of the resonator device 1 after packaging.

[0075] FIG. 14 shows an example of the configuration of the temperature sensor 16. The temperature sensor 16 includes a bipolar transistor BP4, a resistor RE1, a variable resistor circuit REA, and a current source ISB. The current source ISB is provided between a power supply node NVD and a first node N1, and outputs a constant current IA to the first node N1. For example, the current source ISB is configured with a resistor provided between the power supply node NVD and a GND node, and a current mirror circuit that outputs the constant current IA by mirroring the current flowing through the resistor. The first node N1 is connected to the base node of the bipolar transistor BP4. The resistor RE1 is provided between the first node N1 and the collector node of the bipolar transistor BP4. That is, one end of the resistor RE1 is connected to the first node N1, and the other end of the resistor RE1 is connected to the collector node of the bipolar transistor BP4. The variable resistor circuit REA is provided between the emitter node of the bipolar transistor BP4 and the GND node. That is, one end of the variable resistance circuit REA is connected to the emitter node of the bipolar transistor BP4, and the other end of the variable resistance circuit REA is connected to the GND node. The variable resistance circuit REA receives zero-order correction data from the storage unit 17, and the resistance value of the variable resistance circuit REA is set by the zero-order correction data. As a result, a temperature detection voltage VT having temperature dependency is output from the collector node of the bipolar transistor BP4.

[0076] As described above, in the resonator device 1 of the present embodiment, the integrated circuit 10 includes the temperature sensor 16 for detecting temperature, and the passive element is a resistive element included in the temperature sensor 16. As described above, when the resistor RE1 and the like included in the temperature sensor 16 deforms due to stress and the resistance value changes, the temperature detection voltage VT fluctuates. This causes a problem that the load capacitance of the oscillator circuit 11 fluctuates and the frequency of the resonator device 1 fluctuates. In this regard, by applying the method of the present embodiment, the resistive element included in the temperature sensor 16 is disposed at a position where the influence of the stress is small, so that the deformation of the resistive element included in the temperature sensor 16 can be suppressed. This makes it possible to suppress the change in the resistance value of the resistive element included in the temperature sensor 16, and therefore the temperature detection voltage VT can be stabilized. This makes it possible to suppress the change in the oscillation frequency of the resonator device 1.

[0077] 15 shows a configuration example of the temperature compensation circuit 15. The temperature compensation circuit 15 includes a zero-order correction circuit 152, a first-order correction circuit 154, a high-order correction circuit 156, and a current-voltage conversion circuit 158. For example, when performing third-order correction, fourth-order correction, fifth-order correction, etc., a plurality of correction circuits, such as a third-order correction circuit, a fourth-order correction circuit, and a fifth-order correction circuit, are provided as the high-order correction circuit 156. The high-order correction circuit 156 is also called a function generating circuit, and generates a function current corresponding to a polynomial that approximates the characteristics of the temperature compensation voltage VCP. For example, the polynomial is a function that uses temperature as a variable.

[0078] The temperature compensation circuit 15 performs analog temperature compensation using polynomial approximation. Specifically, the temperature compensation circuit 15 generates and outputs a temperature compensation voltage VCP by approximating a polynomial, which is a function with temperature as a variable. For this purpose, the storage unit 17 stores the zeroth-order coefficient, the first-order coefficient, and the high-order coefficient of the polynomial that approximates the characteristics of the temperature compensation voltage VCP as zeroth-order correction data, first-order correction data, and high-order correction data. The zeroth-order correction circuit 152, the first-order correction circuit 154, and the high-order correction circuit 156 output a zeroth-order correction current signal, a first-order correction current signal, and a high-order correction current signal based on the zeroth-order correction data, the first-order correction data, and the high-order correction data stored in the storage unit 17. The zeroth-order correction current signal, the first-order correction current signal, and the high-order correction current signal can be said to be a zeroth-order component signal, a first-order component signal, and a high-order component signal of a function current. Based on the temperature detection voltage VT that changes linearly with temperature, the first-order correction circuit 154 and the high-order correction circuit 156 generate and output a first-order correction current signal and a high-order correction current signal. The current-voltage conversion circuit 158 ​​performs an addition process of the zero-order correction current signal, the first-order correction current signal, and the high-order correction current signal, and performs current-voltage conversion to output a temperature compensation voltage VCP. This realizes analog temperature compensation using polynomial approximation. Note that, when performing zero-order correction of temperature compensation using the temperature sensor 16 as described above, the configuration of the zero-order correction circuit 152 can be omitted. In this case, in order to correct the deviation of the temperature detection voltage characteristic caused by the fluctuation of the offset voltage of the temperature detection voltage VT, for example, a second-order correction circuit or a fourth-order correction circuit may be provided in the temperature compensation circuit 15 that performs temperature compensation using a fifth-order polynomial approximation.

[0079] 16 shows a configuration example of high-order correction circuit 156. High-order correction circuit 156 includes bipolar transistors BP51 to BP5(2N+1), bipolar transistors BP61 to BP6(2N+1), resistors RF1 to RF(2N+1), resistors RG1 to RG(2N+1), and current sources ISC1 to ISC(2N+1). N is a natural number. Note that reference voltages VS1 to VS(N+1) and a reference voltage VG, which will be described later, are output from a voltage generating circuit (not shown).

[0080] A differential pair is formed by bipolar transistors BP51 and BP61. The bipolar transistor BP51 has a base terminal to which a reference voltage VS1 is input, a collector terminal to which a reference voltage supply line 159 that supplies a reference voltage VG is connected, and an emitter terminal to which a current source ISC1 is electrically connected via a resistor RF1. The bipolar transistor BP61 has a base terminal to which a temperature detection voltage VT is input, a collector terminal to which a current-voltage conversion circuit 158 ​​is electrically connected, and an emitter terminal to which a current source ISC1 is electrically connected via a resistor RG1. The current source ISC1 passes a constant current IB1 through the differential pair formed by the bipolar transistors BP51 and BP61 via resistors RF1 and RG1. The same applies to the differential pair formed by the bipolar transistors BP5(2N+1) and BP6(2N+1).

[0081] Moreover, a differential pair is formed by the bipolar transistor BP52 and the bipolar transistor BP62. The bipolar transistor BP52 has a base terminal to which a reference voltage VS2 is input, a collector terminal electrically connected to the current-voltage conversion circuit 158, and an emitter terminal electrically connected to the current source ISC2 via a resistor RG1. The bipolar transistor BP62 has a base terminal to which a temperature detection voltage VT is input, a collector terminal electrically connected to the reference voltage supply line 159, and an emitter terminal electrically connected to the current source ISC2 via a resistor RG2. The current source ISC2 passes a constant current IB(2N) through the differential pair formed by the bipolar transistor BP52 and the bipolar transistor BP62 via resistors RF2 and RG2. The same applies to the differential pair formed by the bipolar transistor BP5(2N) and the bipolar transistor BP6(2N).

[0082] The value of the temperature detection voltage VT decreases almost linearly with respect to the temperature T, and is assumed to coincide with the reference voltages VS1, VR2, …, VSN, VS(2N + 1) when the temperature T is T1, T2, …, T(2N), T(2N + 1), respectively. It is also assumed that T1 < T2 < … < T(2N) < T(2N + 1). Although detailed description of the known method is omitted, by including such a differential pair configuration, the current value from the current-voltage conversion circuit 158 monotonically decreases, for example, in the vicinity of the temperature T being T1, and monotonically increases in the vicinity of the temperature T being T2, and thereafter, monotonic decrease and monotonic increase are alternately repeated according to the number of differential pairs. As a result, the temperature dependence of the current value from the current-voltage conversion circuit 158, although not shown in the figure, shows a pattern of repeating undulations.

[0083] As described above, in the vibration device 1 of the present embodiment, the integrated circuit 10 includes a temperature compensation circuit 15 that performs temperature compensation of the oscillation frequency of the vibration element 5, and the passive element is a resistance element included in the temperature compensation circuit 15. As described above, the higher-order correction circuit 156 of the temperature compensation circuit 15 includes the resistors RF1 to RF(2N + 1) and the resistors RG1 to RG(2N + 1) that constitute each differential pair. When these resistors are deformed by stress and the resistance value changes, the current value on the wiring connected to the current-voltage conversion circuit 158 fluctuates. As a result, since the temperature compensation voltage VCP fluctuates, the load capacitance of the oscillation circuit 11 fluctuates, and a problem occurs in that the frequency of the vibration device 1 fluctuates. In this regard, by applying the method of the present embodiment, by arranging the resistance elements included in the temperature compensation circuit 15 at positions where the influence of stress is small, deformation of the resistance elements included in the temperature compensation circuit 15 can be suppressed. Thereby, since the change in the resistance value of the resistance elements included in the temperature compensation circuit 15 can be suppressed, the temperature compensation voltage VCP can be stabilized. Thereby, the change in the oscillation frequency of the vibration device 1 can be suppressed.

[0084] The resonating device 1 of this embodiment also includes at least one of a temperature sensor 16 that detects temperature and a temperature compensation circuit 15 that performs temperature compensation of the oscillation frequency of the resonating element 5. At least a part of a passive element or an active element included in at least one of the temperature sensor 16 or the temperature compensation circuit 15 is arranged so as to overlap with the junction 73 in a plan view from a direction perpendicular to the first surface 21. As described above in FIG. 14 and FIG. 16, the temperature sensor 16 or the temperature compensation circuit 15 includes bipolar transistors BP4, BP51 to BP5 (2N+1), and BP61 to BP6 (2N+1) as active elements in addition to the passive elements described above. As described above in FIG. 9, if BP4, BP51 to BP5 (2N+1), and BP61 to BP6 (2N+1) are present in an area that does not overlap with the junction JA, the base currents of the bipolar transistors BP4, BP51 to BP5 (2N+1), and BP61 to BP6 (2N+1) change due to the influence of stress. Since the temperature compensation voltage VCP fluctuates, the load capacitance of the oscillation circuit 11 fluctuates, which causes a problem of fluctuating the frequency of the vibration device 1. In this regard, in the vibration device 1 of this embodiment, the temperature sensor 16 and the temperature compensation circuit 15 are arranged so as to overlap with the joint JA. In this way, the passive element or active element is arranged in the area overlapping with the joint JA, and the characteristics of the passive element or active element can be stabilized. This makes it possible to stabilize the oscillation characteristics of the vibration device 1 after packaging.

[0085] This embodiment is not limited to the above, and various modifications are possible. FIG. 17 is a plan view showing a modification of this embodiment. The vibration device 1 may further include a PLL circuit 18. For example, by providing a fractional-N type PLL circuit 18, it becomes possible to output a clock signal CK of an arbitrary frequency obtained by multiplying the frequency of the oscillation signal of the oscillation circuit 11. In addition, the PLL circuit 18 is disposed inside the lid inner wall line 9L in a planar view, similar to the control circuit 13 and the like. That is, the PLL circuit 18 is disposed at a position that does not overlap with the joint JA in a planar view. This is because the PLL circuit 18 is corrected within a feedback loop, and therefore is considered to be less affected by stress. In this way, by disposing the PLL circuit 18 at a position where the effect of stress is large, it is possible to increase the room for disposing a circuit that is more affected by stress at a position where the effect of stress is small.

[0086] As described above, the vibration device of this embodiment includes a semiconductor substrate, a base, a vibration element, and a lid. The semiconductor substrate has a first surface and a second surface that is opposite to the first surface. The base includes an integrated circuit disposed on the first surface or the second surface. The vibration element is electrically connected to the integrated circuit and disposed on the first surface side. The lid is bonded to the base at a joint of the base so as to accommodate the vibration element. The integrated circuit includes a passive element, and the passive element is disposed so that at least a portion of the passive element overlaps with the joint in a plan view from a direction perpendicular to the first surface.

[0087] Thus, the vibration device of this embodiment includes an integrated circuit arranged on the first surface or the second surface of the semiconductor substrate. The integrated circuit also includes a passive element, and the passive element is arranged such that at least a portion of the passive element overlaps with a joint that joins to the lid in a plan view from a direction perpendicular to the first surface. By arranging the passive element in this manner, the passive element can be less affected by stress compared to a case in which the passive element is arranged so as not to overlap with the joint in a plan view. This makes it possible to suppress deformation of the passive element due to the influence of stress. This makes it possible to suppress changes in the characteristics of the passive element, and therefore to effectively suppress changes in the frequency characteristics of the vibration device.

[0088] Moreover, the passive element may be at least one of a capacitive element and a resistive element.

[0089] In this way, by disposing the capacitive element or resistive element at a position where the effect of stress is small, deformation of the capacitive element or resistive element can be suppressed. This makes it possible to suppress changes in the capacitance of the capacitive element or the resistance value of the resistive element. This makes it possible to suppress changes in the oscillation frequency of the vibration device.

[0090] The capacitive element may be at least one of a metal-insulator-metal (MIM) capacitor, a polysilicon-insulator-polysilicon (PIP) capacitor, and a metal-oxide-semiconductor (MOS) capacitor.

[0091] In this way, by arranging the capacitors normally used in the vibration device in a position where they are less susceptible to the effects of stress, it is possible to suppress deformation of these capacitors, thereby suppressing changes in the capacitance of these capacitors, and thereby suppressing changes in the oscillation frequency of the vibration device.

[0092] The integrated circuit may also include an oscillation circuit that causes the vibration element to oscillate and outputs an oscillation signal, and the passive element may be at least one of a capacitance element and a resistance element included in the oscillation circuit.

[0093] In this way, by arranging the capacitive element or resistive element included in the oscillation circuit in a position where the effect of stress is small, deformation of the capacitive element or resistive element included in the oscillation circuit can be suppressed. This makes it possible to suppress changes in the capacitance of the capacitive element or the resistance value of the resistive element included in the oscillation circuit. This makes it possible to suppress changes in the oscillation frequency of the vibration device.

[0094] The base may also include a through electrode, the integrated circuit may have a first side and a second side opposite to the first side, and an oscillator circuit may be arranged between the first side and the through electrode when viewed in a planar view from a direction perpendicular to the first surface.

[0095] In this way, by arranging the oscillator circuit close to the first side, it is possible to increase the distance between the oscillator circuit and the external connection terminal which is arranged close to the second side, thereby reducing the capacitance of the capacitive coupling between the oscillator circuit and the external connection terminal.

[0096] The integrated circuit may also include a reference voltage generating circuit that generates a reference voltage used in the integrated circuit, and the passive element may be a resistive element included in the reference voltage generating circuit.

[0097] In this way, by disposing the resistive element included in the reference voltage generating circuit at a position where the influence of stress is small, deformation of the resistive element included in the reference voltage generating circuit can be suppressed. This makes it possible to suppress changes in the resistance value of the resistive element included in the reference voltage generating circuit. This makes it possible to suppress changes in the oscillation frequency of the vibration device.

[0098] The integrated circuit may also include a regulator circuit that generates a regulated power supply voltage used in the integrated circuit, and the passive element may be a resistive element included in the regulator circuit.

[0099] In this way, by disposing the resistive element included in the regulator circuit at a position where it is less affected by stress, it is possible to suppress deformation of the resistive element included in the regulator circuit. This makes it possible to suppress changes in the resistance value of the resistive element included in the regulator circuit. This makes it possible to suppress changes in the oscillation frequency of the vibration device.

[0100] The integrated circuit may also include a temperature sensor that detects temperature, and the passive element may be a resistive element included in the temperature sensor.

[0101] In this way, by disposing the resistive element included in the temperature sensor at a position where it is less affected by stress, it is possible to suppress deformation of the resistive element included in the temperature sensor. This makes it possible to suppress changes in the resistance value of the resistive element included in the temperature sensor. This makes it possible to suppress changes in the oscillation frequency of the vibration device.

[0102] The integrated circuit may also include a temperature compensation circuit that performs temperature compensation for the oscillation frequency of the vibration element, and the passive element may be a resistive element included in the temperature compensation circuit.

[0103] In this way, by disposing the resistive element included in the temperature compensation circuit at a position where it is less affected by stress, it is possible to suppress deformation of the resistive element included in the temperature compensation circuit. This makes it possible to suppress changes in the resistance value of the resistive element included in the temperature compensation circuit. This makes it possible to suppress changes in the oscillation frequency of the vibration device.

[0104] The integrated circuit may include a predetermined circuit disposed in a region that does not overlap with the joint in a plan view, and the predetermined circuit may include at least one of a control circuit or a memory circuit.

[0105] In this way, control circuits and memory circuits that are less affected by the effects of stress can be placed in locations where the effects of stress are greater, thereby providing more room for placing circuits that are more affected by stress in locations where the effects of stress are smaller.

[0106] The vibration device of this embodiment includes a semiconductor substrate, a base, a vibration element, and a lid. The semiconductor substrate has a first surface and a second surface that is opposite to the first surface. The base includes an integrated circuit arranged on the first surface or the second surface. The vibration element is electrically connected to the integrated circuit and arranged on the first surface side. The lid is joined to the base at a joint of the base so as to accommodate the vibration element. The integrated circuit includes at least one of a reference voltage generating circuit that generates a reference voltage used in the integrated circuit or a regulator circuit that generates a regulated power supply voltage used in the integrated circuit. At least a part of a passive element or an active element included in at least one of the reference voltage generating circuit or the regulator circuit is arranged so as to overlap with the joint in a plan view from a direction perpendicular to the first surface.

[0107] In this way, by arranging the passive or active elements included in the reference voltage generating circuit or the regulator circuit in a position where the influence of stress is small, it is possible to suppress deformation of the passive or active elements included in the reference voltage generating circuit or the regulator circuit. This makes it possible to suppress changes in the characteristics of the passive or active elements included in the reference voltage generating circuit or the regulator circuit. This makes it possible to suppress changes in the oscillation frequency of the vibration device.

[0108] The vibration device of this embodiment includes a semiconductor substrate, a base, a vibration element, and a lid. The semiconductor substrate has a first surface and a second surface that is opposite to the first surface. The base includes an integrated circuit disposed on the first surface or the second surface. The vibration element is electrically connected to the integrated circuit and disposed on the first surface side. The lid is bonded to the base at a joint of the base so as to accommodate the vibration element. The integrated circuit includes at least one of a temperature sensor that detects temperature or a temperature compensation circuit that performs temperature compensation for the oscillation frequency of the vibration element. At least a portion of a passive element or an active element included in at least one of the temperature sensor or the temperature compensation circuit is disposed so as to overlap with the joint in a plan view from a direction perpendicular to the first surface.

[0109] In this way, by arranging the passive or active element included in the temperature sensor or the temperature compensation circuit in a position where the effect of stress is small, it is possible to suppress deformation of the passive or active element included in the temperature sensor or the temperature compensation circuit. This makes it possible to suppress changes in the characteristics of the passive or active element included in the temperature sensor or the temperature compensation circuit. This makes it possible to suppress changes in the oscillation frequency of the vibration device.

[0110] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term at any point in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configuration and operation of the vibration device are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0111] 1,101...vibration device, 2,102...base, 5,105...vibration element, 7,107...lid, 8,108...relocation wiring layer, 10,110...integrated circuit, 11...oscillating circuit, 12...output circuit, 13...control circuit, 14A...power supply circuit, 14B...regulator circuit, 15...temperature compensation circuit, 16...temperature sensor, 17...memory unit, 18...PLL circuit, 20...semiconductor substrate, 21,121...first surface, 22,122...second surface, 23,24...transistor, 25...element isolation film, 27...guard ring, 30...wiring layer, 31,32...metal layer, 33,34,35...insulating layer, 36,37,38,39...contact pad, 40,41,140,141...through electrode, 44...insulating layer, 50...vibration substrate, 52,53...excitation electrode, 54...wiring, 56...terminal 60, 61, 160, 161 ... bonding member, 62, 162 ... bump, 64 ... terminal, 68, 69 ... contact pad, 71, 72 ... bonding member, 80, 180 ... insulating layer, 82, 182 ... wiring, 84 ... first metal layer, 86 ... second metal layer, 91, 92, 191, 192 ... external connection terminal, 132 ... drive circuit, 134 ... reference voltage supply circuit, 136 ... first variable capacitance circuit, 13 7...second variable capacitance circuit, 152...zeroth-order correction circuit, 154...first-order correction circuit, 156...high-order correction circuit, 158...current-voltage conversion circuit, 159...reference voltage supply line, 171, 172...third metal layer, 173, 174...fourth metal layer, 176...fifth metal layer, 177, 178...sixth metal layer, 210A, 210B...conductor layer, 220...insulating layer, 230...base region, 232...crystal defect,

[0112] BP,BP0,BP1,BP2,BP3,BP4,BP51,BP52,BP5(2N),BP5(2N+1),BP61,BP62,BP6(2N),BP6(2N+1)...bipolar transistor, C,C1,C2,C31,C3n,C4,C5,C6,C7,C8,CA...capacitor, CK...clock signal, IA,IB1,IB2,IB(2N),IB(2N+1)...constant current, ISA,ISB,ISC1,ISC2,ISC(2N),ISC(2N+1)...current source, JA...junction, LA,LB,...wiring, N1...first node, NR1,NR2,NRn,NS1,NS2...supply node, OE...output enable signal, OPA...operational amplifier, OSC...oscillating signal, R,RA1,RA2,RA3,RB,RC 1,RC2,RD1,RD2,RD3,RE1,RF1,RF2,RF(2N),RF(2N+1),RG1,RG2,RG(2N),RG(2N+1),RQ...resistor,REA...variable resistor circuit,SD1...first side,SD2...second side,SD3...third side,SD4...fourth side,SDA...data signal,SP...accommodation space,TA1,TD1,TD2,TD3...transistor,TE3,TE4,TE5,TE7...external terminal,TL...lid thickness,TCK,TGND,TOE,TVC,TVDD,TXA,TXB...terminal,VDD...power supply voltage,VG,VR1,VRB,VREF,VRn,VS1,VS2,VS(2N),VS(2N+1)...reference voltage,VCP...temperature compensation voltage,VREG...regulated power supply voltage,VT...temperature detection voltage

Claims

1. a base including a semiconductor substrate having a first surface and a second surface opposite to the first surface, and an integrated circuit disposed on the first surface or the second surface; A vibration element electrically connected to the integrated circuit and disposed on the first surface side; a lid joined to the base at a joint of the base so as to accommodate the vibration element; Including, the integrated circuit includes a resistive element; The vibration device is characterized in that the resistive element is arranged so that at least a portion of the resistive element overlaps with the joint when viewed in a planar view from a direction perpendicular to the first surface.

2. 2. The vibrating device according to claim 1, The integrated circuit includes an oscillation circuit that oscillates the vibration element to output an oscillation signal, A vibration device, characterized in that the resistive element is a resistive element included in the oscillator circuit.

3. The vibration device according to claim 1 or 2, the integrated circuit includes a reference voltage generating circuit that generates a reference voltage used in the integrated circuit; A vibration device, characterized in that the resistive element is a resistive element included in the reference voltage generating circuit.

4. The vibration device according to claim 1 , the integrated circuit includes a regulator circuit that generates a regulated power supply voltage used by the integrated circuit; A vibration device, characterized in that the resistive element is a resistive element included in the regulator circuit.

5. The vibration device according to claim 1 , the integrated circuit includes a temperature sensor for detecting a temperature; A vibration device, characterized in that the resistive element is a resistive element included in the temperature sensor.

6. The vibration device according to claim 1 , the integrated circuit includes a temperature compensation circuit that performs temperature compensation for an oscillation frequency of the vibration element, A vibration device, characterized in that the resistive element is a resistive element included in the temperature compensation circuit.

7. The vibration device according to claim 1 , the integrated circuit includes a predetermined circuit that is disposed in a region that does not overlap with the joint in the plan view, The vibration device, wherein the predetermined circuit includes at least one of a control circuit or a memory circuit.

8. a base including a semiconductor substrate having a first surface and a second surface opposite to the first surface, and an integrated circuit disposed on the first surface or the second surface; A vibration element electrically connected to the integrated circuit and disposed on the first surface side; a lid joined to the base at a joint of the base so as to accommodate the vibration element; Including, the integrated circuit includes at least one of a reference voltage generating circuit that generates a reference voltage used in the integrated circuit and a regulator circuit that generates a regulated power supply voltage used in the integrated circuit; A vibration device characterized in that at least a portion of a resistive element or an active element included in at least one of the reference voltage generation circuit or the regulator circuit is arranged so as to overlap the joint when viewed in a planar view from a direction perpendicular to the first surface.

9. a base including a semiconductor substrate having a first surface and a second surface opposite to the first surface, and an integrated circuit disposed on the first surface or the second surface; A vibration element electrically connected to the integrated circuit and disposed on the first surface side; a lid joined to the base at a joint of the base so as to accommodate the vibration element; Including, The integrated circuit includes at least one of a temperature sensor that detects a temperature or a temperature compensation circuit that performs temperature compensation for an oscillation frequency of the vibration element, A vibration device characterized in that at least a portion of a resistive element or an active element included in at least one of the temperature sensor or the temperature compensation circuit is arranged so as to overlap the joint when viewed in a planar view from a direction perpendicular to the first surface.

Images