Image forming device

Abstract

To provide a technique for shortening a startup time of an image forming device.SOLUTION: A sub CPU 32 executes decryption and alteration check for a 32-bit boot loader program A and a 64-bit boot loader program B. A main CPU 31 switches to a 32-bit operation mode and executes a 32-bit main program M, after executing the 64-bit boot loader program B in a 64-bit operation mode.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an image forming apparatus. [Background technology]

[0002] The image forming apparatus includes a processor and a memory, and the memory stores a main program for causing the processor to function as the image forming apparatus, and a boot loader program for starting the main program. The main program and the boot loader program are stored in the memory in a rewritable manner in order to update the functions of the image forming apparatus. However, if the main program or the boot loader program is analyzed and a malicious program is written into the memory, this may lead to a decrease in security of the image forming apparatus. Therefore, the main program and the boot loader program may be encrypted and checked for tampering, which reduces the risk of the main program and the boot loader program being analyzed and reduces the security risk even if a malicious program is written. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-201932 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the process of decrypting an encrypted program and the process of checking for tampering place a large processing load on the processor, which increases the startup time of the image forming apparatus. The startup time here refers to the time required from when the image forming apparatus is turned on until the startup of the main program for causing the processor to function as the image forming apparatus is completed. Patent document 1 describes that the hardware / software information required to start up the image forming device is obtained before the hardware / software callback, thereby performing the startup process before the hardware / software initialization of the device is completed.

[0005] Therefore, the present invention has been created to solve the above-mentioned problems, and has an object to provide a technique for shortening the startup time of an image forming apparatus. [Means for solving the problem]

[0006] In order to achieve the above-mentioned object, the present invention provides an image forming apparatus including a first processor and a first memory, the first processor being capable of switching from one of a first operation mode in which it functions as an n (n is a natural number) bit processor and a second operation mode in which it functions as an m (m is a natural number of 2 or more)×n bit processor to the other, the first memory storing a rewritable first main program which is a program for the first operation mode, and a first boot loader program which is a program for the second operation mode and is used to start up the first main program, the first main program being a program for the first processor operating in the first operation mode. The first processor is started in a second operation mode to execute a first boot loader program, and further executes at least one of decrypting the encrypted first main program and checking for tampering with the first main program in accordance with the first boot loader program, and further switches to the first operation mode after executing at least one of decrypting the encrypted first main program and checking for tampering with the first main program, and further executes the first main program for which at least one of the decryption and tampering check has been performed after switching to the first operation mode.

[0007] The first processor executes a first boot loader program for the second operation mode and at least one of decrypting the encrypted first main program and checking for tampering with the first main program in the second operation mode. The first processor also executes the first main program that has been decrypted and checked for tampering after switching to the first operation mode. That is, the first processor executes at least one of the decryption of the first main program and the tamper check of the first main program, which has a relatively large processing load, in the second operation mode, which has a faster operation speed than the first operation mode.

[0008] The technology disclosed in this specification can be realized in various forms, for example, as a program, a recording medium on which a program is recorded, an image forming system, and the like. Effect of the Invention

[0009] According to the present invention, it is possible to provide a technique for shortening the startup time of an image forming apparatus. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is an explanatory diagram showing a main electrical configuration of an image forming apparatus according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is an explanatory diagram showing a processing sequence of a sub-CPU and a main CPU. [Diagram 3] 11 is a flowchart showing a flow of a start-up sequence of a sub-CPU. [Figure 4] 4 is a flowchart showing a flow of a start-up sequence of a main CPU. [Diagram 5] FIG. 11 is an explanatory diagram showing a processing sequence of a sub-CPU and a main CPU in a second embodiment of the present invention. [Figure 6] 11 is a flowchart showing a flow of a start-up sequence of a sub-CPU. [Figure 7] 13 is a flowchart showing the flow of a startup sequence of a core C0 of a main CPU. [Figure 8] 11 is a flowchart showing the flow of a start-up sequence of a core C1 of a main CPU. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] First embodiment The main electrical configuration of an image forming apparatus according to a first embodiment of the present invention will be described with reference to Fig. 1. The image forming apparatus 10 includes an image processing circuit 11, a print engine 12, a user IF (abbreviation of interface) 13, a communication IF 14, a USB IF 15, an NVRAM 16, a flash ROM 17, a RAM 18, a ROM 19, a bus 20, and a control unit 30.

[0012] The print engine 12 is an engine for printing an image on a recording medium such as a sheet, and employs a printing method such as an electrophotographic method, an inkjet method, or a thermal method. The image processing circuit 11 converts RIP (short for Raster Image Processor) processed image data into drawing data corresponding to pixels to be printed on a recording medium such as a sheet. The converted drawing data is output to the print engine 12. The RIP process is a process for converting image data described in a page description language such as PCL (short for Printer Command Language) or PS (short for Post Script) into raster image data. The NVRAM 16 is a non-volatile memory for storing print setting information and the like. The user IF 13 is, for example, a touch panel type operation panel, and has a function of displaying messages and a function of accepting operations by a user. The communication IF 14 is connected to the information processing device 40 via a LAN line L1 so that they can communicate with each other. As a communication method between the image forming device 10 and the information processing device 40, a communication protocol such as Bluetooth (registered trademark) can also be used. The information processing device 40 is, for example, a PC or a smartphone. The USBIF 15 is hardware for communicating with a connected device based on the USB standard. The image processing circuit 11, the print engine 12, the user IF 13, the communication IF 14, the USBIF 15, the NVRAM 16, the flash ROM 17, the RAM 18, the ROM 19, and the control unit 30 are connected to each other via a bus 20.

[0013] The control unit 30 includes a main CPU 31 and a sub-CPU 32. The sub-CPU 32 is a 32-bit CPU. The sub-CPU 32 executes processing to control the print engine 12 in accordance with print setting information stored in the NVRAM 16. The sub-CPU 32 also executes processing such as low power consumption control when the image forming apparatus 10 is in a sleep mode. The main CPU 31 can operate in a 32-bit operation mode in which it functions as a 32-bit CPU, or in a 64-bit operation mode in which it functions as a 64-bit CPU. The main CPU 31 can switch from one of the 32-bit operation mode and the 64-bit operation mode to the other. Here, 32 bits and 64 bits refer to the size of data that the CPU can handle at one time when performing calculations. In other words, a 64-bit CPU can handle more data at one time than a 32-bit CPU, and therefore has a faster calculation speed. A 32-bit CPU is a CPU that has a 32-bit register, address bus, and data bus, and a 64-bit CPU is a CPU that has a 64-bit register, address bus, and data bus. A register is a device that stores the object of calculation by the CPU and the result of calculation. Functioning as a 32-bit CPU means functioning according to an instruction set for 32-bit CPUs, and functioning as a 64-bit CPU means functioning according to an instruction set for 64-bit CPUs. The main CPU 31 when operating in a 32-bit operating mode is an example of an n (n is a natural number) bit processor of the present invention, and the main CPU 31 when operating in a 64-bit operating mode is an example of an m (m is a natural number greater than or equal to 2) × n bit processor of the present invention.

[0014] A 32-bit main program M is stored in an encrypted state in the flash ROM 17 and is rewritable (FIG. 2). The 32-bit main program M is a rewritable program for 32-bit operation, and is a program for causing the main CPU 31 operating in a 32-bit operation mode to function as the image forming apparatus 10. The 32-bit main program M is made up of a plurality of programs, and each program executes a process independently or in cooperation with each other. The processing according to the 32-bit main program M includes at least one of RIP processing, encryption processing, and decryption processing executed by the main CPU 31 in the 32-bit operation mode. The encryption processing is processing for encrypting image data stored in the image forming apparatus 10. For example, it is processing for encrypting image data stored in the flash ROM 17 to be transmitted through the communication IF 14. The decryption processing is processing for decrypting encrypted image data stored in the image forming apparatus 10. For example, it is processing for decrypting encrypted image data acquired through the USBIF 15 and stored in the flash ROM 17. In addition, the main CPU 31 in the 32-bit operating mode executes color correction processing of raster data after RIP processing, processing related to setting and using print setting information, processing to display a screen on the user IF 13, processing to accept operations from the user IF 13, various processing associated with the accepted operations, and processing to communicate various data such as image data using the communication IF 14 and USB IF 15.

[0015] Also stored in flash ROM 17 is an encrypted 64-bit boot loader program B, which is a rewritable program for 64-bit operation and is used to start up a 32-bit main program M (FIG. 2). Stored in ROM 19 is a 32-bit boot loader program 0, which is used to decrypt and check for tampering with the 64-bit boot loader program B (FIG. 2). RAM 18 has work areas into which the 32-bit boot loader program A, the 64-bit boot loader program B, and the 32-bit main program M read from flash ROM 17 are expanded, respectively.

[0016] At least one of the 32-bit boot loader program A, the 64-bit boot loader program B, and the 32-bit main program M may be stored in a computer-readable storage medium, provided to the image forming apparatus 10 from the storage medium, and executed by the control unit 30. A computer-readable storage medium is a non-transitory medium. Non-transitory media include recording media such as CD-ROMs, DVD-ROMs, and USB memories. A non-transitory medium is also a tangible medium. On the other hand, an electrical signal that carries a program downloaded from a server on the Internet is a computer-readable signal medium, which is a type of computer-readable medium, but is not included in a computer-readable non-transitory storage medium.

[0017] In the following description, processes such as "determination," "expansion," "output," "transmission," "acquisition," "control," and "setting" represent processes by the main CPU 31 or the sub-CPU 32. Processes by the main CPU 31 include hardware control via the OS. "Acquisition" is used as a concept that does not require a request. In other words, the concept of "CPU acquiring data" also includes a process in which the CPU receives data without making a request. In this specification, "data" is represented by a bit string that can be read by a computer. Data that has the same substantial meaning but different formats is treated as the same data. The same applies to "information" in this specification.

[0018] The main CPU 31 is an example of a first processor of the present invention, and the sub CPU 32 is an example of a second processor of the present invention. The flash ROM 17 is an example of a first memory of the present invention, and the ROM 19 is an example of a second memory of the present invention. The 32-bit operation mode is an example of a first operation mode of the present invention, and the 64-bit operation mode is an example of a second operation mode of the present invention. The 32-bit main program M is an example of a first main program of the present invention. The 64-bit boot loader program B is an example of a first boot loader program of the present invention, and the 32-bit boot loader program A is an example of a second boot loader program of the present invention.

[0019] Next, the start-up sequence of the sub-CPU 32 will be described with reference to Figs. 2 and 3. In the following description, the steps of the process executed by the sub-CPU 32 or the main CPU 31 are abbreviated as S. When the power switch of the image forming apparatus 10 is turned on, the sub-CPU 32 (Figs. 1 and 2) starts up (S1 in Fig. 3, (1) in Fig. 2). Next, the sub-CPU 32 executes the 32-bit boot loader program 0 stored in the ROM 19 (S2), thereby decrypting and checking for tampering with the 32-bit boot loader program A stored in the flash ROM 17 (S3). The tampering check is to inspect whether the program has been tampered with. In this way, the sub-CPU 32 executes the tampering check of the 32-bit boot loader program A, thereby enhancing the security of the image forming apparatus 10. Next, the sub CPU 32 judges whether or not tampering with the 32-bit boot loader program A has been found and whether or not the decryption of the 32-bit boot loader program A has been successful, that is, whether or not there has been no tampering and the decryption has been successful (S4). If the sub CPU 32 judges that there has been no tampering and the decryption has been successful (S4: Yes), it loads the 32-bit boot loader program A stored in the flash ROM 17 into the RAM 18 and executes the loaded 32-bit boot loader program A (S5, (2) in FIG. 2).

[0020] Next, the sub CPU 32 executes decryption and tamper check of the 64-bit boot loader program B stored in the flash ROM 17 (S6). Since the sub CPU 32 executes the tamper check of the 64-bit boot loader program B in this way, the security of the image forming apparatus 10 can be improved. Next, the sub CPU 32 judges whether or not tampering of the 64-bit boot loader program B is not found and the decryption of the 64-bit boot loader program B is successful, that is, whether or not there is no tampering and the decryption is successful (S7). Here, when the sub CPU 32 judges that there is no tampering and the decryption is successful (S7: Yes), it develops the 64-bit boot loader program B stored in the flash ROM 17 in the RAM 18 (S8, (3) of FIG. 2). Next, the main CPU 31 starts up in the 64-bit mode (S9, (4) of FIG. 2). Furthermore, if the sub-CPU 32 determines that the 32-bit boot loader program A has not been tampered with and has not been successfully decrypted (S4: No), or if the sub-CPU 32 determines that the 64-bit boot loader program B has not been tampered with and has not been successfully decrypted (S7: No), it stops the startup of the image forming apparatus 10 (S10). When the sub-CPU 32 executes S10 to stop the startup of the image forming apparatus 10, it can notify that the startup of the image forming apparatus 10 has been stopped. For example, the sub-CPU 32 can display a message such as "The program is corrupted. Please update the firmware" on an operation panel provided in the image forming apparatus 10. In other words, it notifies that the firmware including the boot loader program needs to be updated because the boot loader program may have been tampered with.

[0021] Next, the start-up sequence of the main CPU 31 will be described with reference to FIG. 2 and FIG. 4. The main CPU 31, which has been started in the 64-bit operation mode, executes the 64-bit boot loader program B expanded in the RAM 18 (S11 in FIG. 4, (5) in FIG. 2), thereby executing the decryption and tampering check of the 32-bit main program M stored in the flash ROM 17 (S12). In this way, the main CPU 31 executes the decryption and tampering check of the 32-bit main program M in the 64-bit operation mode, which has a faster operation speed than the 32-bit operation mode, so that the start-up time of the image forming apparatus 10 can be shortened compared to the case where the decryption and tampering check of the 32-bit main program M is executed in the 32-bit operation mode. According to an experiment conducted by the inventors of the present application, the start-up time of the image forming apparatus 10 could be shortened from 14 seconds to 2 seconds. In other words, the start-up time of the image forming apparatus 10 could be shortened by as much as 10 seconds. Furthermore, since the main CPU 31 executes the tampering check of the 32-bit main program M, the security of the image forming apparatus 10 can be improved. In addition, if the main CPU 31 has a cryptographic expansion function, it is possible to use that cryptographic expansion function to perform decryption and tamper checks on the 32-bit main program M. Even in this case, the processing time for decryption and tamper checks can be shortened when the main CPU 31 executes the cryptographic expansion function in 64-bit operating mode compared to when it executes in 32-bit operating mode.

[0022] Next, the main CPU 31 judges whether or not tampering of the 64-bit boot loader program B has been found and whether or not the decryption of the 64-bit boot loader program B has been successful, that is, whether or not there has been no tampering and the decryption has been successful (S13). Here, when the main CPU 31 judges that there has been no tampering and the decryption has been successful (S13: Yes), it loads the 32-bit main program M stored in the flash ROM 17 in the RAM 18 (S14, (6) of FIG. 2). Next, the main CPU 31 switches from the 64-bit operation mode to the 32-bit operation mode (S15, (7) of FIG. 2), and executes the 32-bit main program M loaded in the RAM 18 (S16, (8) of FIG. 2). In this way, the main CPU 31 that has switched from the 64-bit operation mode to the 32-bit operation mode executes the 32-bit main program M. Since the 32-bit main program M has a smaller program size than the 64-bit main program, it is less likely to strain the storage capacity of the flash ROM 17. In addition, main programs previously created for the 32-bit operating mode can be utilized as program assets, thereby reducing the manufacturing cost of the image forming apparatus 10. Furthermore, if the main CPU 31 determines that the 64-bit boot loader program B has not been tampered with and has not been successfully decrypted (S13: No), it stops the startup of the image forming apparatus 10 (S17). For example, the main CPU 31 can display a message such as "The program is corrupted. Please update the firmware" on a display device provided in the image forming apparatus 10. In other words, it notifies the user that the 32-bit main program M may have been tampered with and therefore that the firmware including the 32-bit main program M needs to be updated.

[0023] The encryption algorithm for encrypting the 32-bit main program M, the 32-bit boot loader program A, and the 64-bit boot loader program B can be an encryption algorithm using a common key or a public key. For example, AES-CMAC (Advanced Encryption Standard-Cipher-based Message Authentication Code) and HMAC (Hash-based Message Authentication Code) can be used as an encryption algorithm using a common key. For example, RSA encryption can be used as an encryption algorithm using a public key. Decryption can be performed using an algorithm used in the encryption algorithm and a common key or a public key used in the algorithm. A check for tampering is performed based on whether or not the decryption is successful. If the decryption is successful, it is determined that there is no tampering, and if the decryption is not successful, it is determined that there is tampering. If at least one of the 32-bit main program M, the 32-bit boot loader program A, and the 64-bit boot loader program B is digitally signed, it is possible to determine whether or not there is tampering by determining whether or not the digital signature is correct. Also, in at least one of steps S4, S7, and S13, only one of determining whether the program has been tampered with or not and determining whether the decryption was successful or not may be executed. Also, the program tamper check may be performed on the encrypted program, or the program may be decrypted and the decrypted program may be checked for tampering.

[0024] Second Embodiment Next, an image forming apparatus according to a second embodiment of the present invention will be described with reference to FIGS. 5 to 8. The same components as those in the image forming apparatus 10 according to the first embodiment described above will be designated by the same reference numerals, and the description thereof will be omitted. As shown in FIG. 5, the main CPU 31 has a dual-core configuration having a core C0 and a core C1. A core is an arithmetic and control device (circuit) that functions independently inside the CPU. The cores C0 and C1 can operate in a 32-bit operation mode or a 64-bit operation mode, and can switch from one of the 32-bit operation mode and the 64-bit operation mode to the other. The core C0 in the 32-bit operation mode executes processes related to setting and using print setting information, a process of displaying a screen on the user IF 13, a process of accepting an operation from the user IF 13, various processes associated with the accepted operation, a process of communicating various data such as image data using the communication IF 14 and the USB IF 15, and a color correction process for raster data after RIP processing. Furthermore, core C1 in the 64-bit operating mode executes relatively time-consuming processes such as RIP processing, encryption processing and decryption processing of image data stored in image forming apparatus 10. Furthermore, sub-CPU 32 executes control of print engine 12 (FIG. 1), low power consumption control when image forming apparatus 10 is in a sleep state, etc. Core C0 is an example of the first core of the present invention, and core C1 is an example of the second core of the present invention.

[0025] The flash ROM 17 stores a 32-bit main program M0 and a 64-bit main program M1. The 32-bit main program M0 includes a program for the core C0 in the 32-bit operation mode to execute the above-mentioned processes, and a program for the sub-CPU 32 to execute the above-mentioned processes. The 32-bit main program M0 is composed of a plurality of programs, each of which executes each process independently or in cooperation with the other programs. In other words, the 32-bit main program M0 is a program for the core C0 in the 32-bit operation mode to execute the above-mentioned processes to function as the image forming apparatus 10. The 64-bit main program M1 also includes a program for the core C1 in the 64-bit operation mode to execute each of the processes described above. The 64-bit main program M1 is also composed of a plurality of programs, and each program executes each process independently or in cooperation with each other. In other words, the 64-bit main program M1 is a program for the core C1 in the 64-bit operation mode to function as the image forming apparatus 10 by executing each of the processes described above. Furthermore, a 64-bit boot loader program B for starting the 32-bit main program M0 and the 64-bit main program M1 is stored in the flash ROM 17. The 64-bit main program M1 is an example of the second main program of the present invention.

[0026] Next, the start-up sequence of the sub-CPU 32 will be described with reference to Figures 5 and 6. When the power switch of the image forming apparatus 10 is turned on, the sub-CPU 32 (Figures 1 and 5) starts up (S20 in Figure 6, (1) in Figure 5). Next, the sub-CPU 32 executes the 32-bit boot loader program 0 stored in the ROM 19 (S21), thereby executing the decryption and tamper check of the 32-bit boot loader program A stored in the flash ROM 17 (S22). Next, the sub-CPU 32 determines whether or not tampering of the 32-bit boot loader program A has been found and the decryption of the 32-bit boot loader program A has been successful, that is, whether or not there has been no tampering and the decryption has been successful (S23). Here, if the sub-CPU 32 determines that there has been no tampering and that the decryption has been successful (S23: Yes), it expands the 32-bit boot loader program A stored in the flash ROM 17 into the RAM 18 and executes the expanded 32-bit boot loader program A (S24, (2) of Figure 5).

[0027] Next, the sub CPU 32 executes decryption and tamper check of the 64-bit boot loader program B stored in the flash ROM 17 (S25). Next, the sub CPU 32 judges whether or not tampering of the 64-bit boot loader program B is not found and the decryption of the 64-bit boot loader program B is successful, that is, whether or not there is no tampering and the decryption is successful (S26). Here, when the sub CPU 32 judges that there is no tampering and the decryption is successful (S26: Yes), it develops the 64-bit boot loader program B stored in the flash ROM 17 in the RAM 18 (S27, (3) in FIG. 5). Next, the core C0 of the main CPU 31 starts up in the 64-bit mode (S28, (4) in FIG. 5). Furthermore, when the sub CPU 32 determines that the 32-bit boot loader program A has not been tampered with and has not been successfully decrypted (S23: No), or when the sub CPU 32 determines that the 64-bit boot loader program B has not been tampered with and has not been successfully decrypted (S26: No), the sub CPU 32 stops the startup of the image forming apparatus 10 (S29). When the sub CPU 32 executes S29 to stop the startup of the image forming apparatus 10, it can notify that the startup of the image forming apparatus 10 has been stopped. For example, the sub CPU 32 can display a message such as "The program is corrupted. Please update the firmware" on a display device provided in the image forming apparatus 10. In other words, it notifies that the firmware including the boot loader program needs to be updated because the boot loader program may have been tampered with.

[0028] Next, the start-up sequence of the main CPU 31 will be described with reference to Figures 5 and 7. The core C0 started in the 64-bit operation mode executes the 64-bit boot loader program B expanded in the RAM 18 (S30 in Figure 7, (5) in Figure 5) to decrypt and check for tampering of the 32-bit main program M0 stored in the flash ROM 17 (S31). In this way, the core C0 of the main CPU 31 executes the decryption and check for tampering of the 32-bit main program M0 in the 64-bit operation mode, which has a faster operation speed than the 32-bit operation mode, and therefore the start-up time of the image forming apparatus 10 can be shortened compared to the case where the decryption and check for tampering of the 32-bit main program M0 are executed in the 32-bit operation mode. Next, the core C0 of the main CPU 31 judges whether or not tampering of the 32-bit main program M0 has been found and whether or not the decryption of the 32-bit main program M0 has been successful, that is, whether or not there has been no tampering and the decryption has been successful (S32). If the core C0 of the main CPU 31 judges that there has been no tampering and the decryption has been successful (S32: Yes), it loads the 32-bit main program M0 stored in the flash ROM 17 into the RAM 18 (S33, (6) of FIG. 5). Next, the core C0 of the main CPU 31 executes the decryption and tampering check of the 64-bit main program M1 stored in the flash ROM 17 in accordance with the 64-bit boot loader program B (S34). In this way, the core C0 of the main CPU 31 performs decryption and tamper checking of the 64-bit main program M1 in the 64-bit operating mode, which has a faster calculation speed than the 32-bit operating mode, and therefore the startup time of the image forming device 10 can be shortened compared to when the decryption and tamper checking of the 64-bit main program M1 is performed in the 32-bit operating mode.

[0029] Next, the core C0 of the main CPU 31 judges whether or not tampering of the 64-bit main program M1 has been found and whether or not the decryption of the 64-bit main program M1 has been successful, that is, whether or not there has been no tampering and the decryption has been successful (S35). Here, when the core C0 of the main CPU 31 judges that there has been no tampering and that the decryption has been successful (S35: Yes), it loads the 64-bit main program M1 stored in the flash ROM 17 into the RAM 18 (S36, (7) of FIG. 5). Next, the core C1 starts up in the 64-bit operation mode (S37, (8) of FIG. 5), and the core C0 switches from the 64-bit operation mode to the 32-bit operation mode (S38, (9) of FIG. 5). Next, the core C0 of the main CPU 31 executes the 32-bit main program M0 (S39, (10-1) of FIG. 5). In this way, since the core C0 that has switched from the 64-bit operating mode to the 32-bit operating mode executes the 32-bit main program M0, a main program that was previously created for the 32-bit operating mode can be utilized as a program asset, thereby reducing the manufacturing cost of the image forming device 10. Next, the core C1 of the main CPU 31, which has been started in the 64-bit operation mode, executes the 64-bit main program M1 (S50 in FIG. 8, (10-2) in FIG. 5). Also, in at least one of steps S23, S26, S32, and S35, only one of determining whether the program has been tampered with or not and determining whether the decryption was successful or not may be executed. Also, the program tamper check may be performed on the encrypted program, or the program may be decrypted and the decrypted program may be checked for tampering.

[0030] Other Embodiments (1) The order of S37 and S38 in Fig. 7 may be reversed. That is, before the core C1 of the main CPU 31 starts up in the 64-bit operation mode, the core C0 of the main CPU 31 may switch from the 64-bit operation mode to the 32-bit operation mode. (2) In the second embodiment described above, the processes executed in the 32-bit operation mode or the processes executed in the 64-bit operation mode may be executed by either the core C0 or the core C1. For example, the core C1 may execute the 64-bit boot loader program B and execute the 32-bit main program M0 in the 32-bit operation mode, or the core C0 may execute the 64-bit main program M1 in the 64-bit operation mode. (3) At least one of the 32-bit boot loader program A, the 64-bit boot loader program B, the 32-bit main program M0, and the 64-bit main program M1 can be obtained from the web, as well as from a storage medium such as a USB memory, a CD-ROM, etc. Furthermore, it can also be obtained by communicating with another image forming apparatus or information processing apparatus in which at least one of the above programs is stored. (4) The main CPU 31 may be any CPU that operates as an n-bit CPU (n is a natural number) or an m×n-bit CPU (m is a natural number of 2 or more), and may be configured to switch from one of a first operation mode in which it functions as an n-bit CPU and a second operation mode in which it functions as an m×n-bit CPU to the other. For example, the main CPU 31 may be configured to operate as a 64-bit CPU or a 128-bit CPU, and to switch from one of the 64-bit operation mode and the 128-bit operation mode to the other. Core 0 and core 1 may also be configured to operate as an n (n is a natural number) bit CPU or an m (m is a natural number of 2 or more) x n bit CPU, and may be configured to switch from one of a first operation mode in which they function as an n-bit CPU and a second operation mode in which they function as an m x n bit CPU to the other. For example, core C0 and core C1 may be configured to operate as a 64-bit core or a 128-bit core, respectively, and to switch from one of a 64-bit operation mode and a 128-bit operation mode to the other. Sub-CPU 32 may be configured similarly to main CPU 31. (5) The number of cores constituting main CPU 31 may be four, six, eight, or ten or more, and any two or more of these may be configured to serve as core C0 and core C1. [Explanation of symbols]

[0031] 10 image forming device, 17 flash ROM, 18 RAM, 19 ROM, 30 control unit, 31 main CPU, 32 sub CPU, 0, A 32-bit boot loader program, B 64-bit boot loader program, C0, C1 core, M, M0 32-bit main program, M1 64-bit main program.

Claims

1. An image forming apparatus including a first processor and a first memory, The first processor, The device is capable of switching from one of a first operation mode in which the device functions as an n (n is a natural number) bit processor and a second operation mode in which the device functions as an m (m is a natural number of 2 or more)×n bit processor to the other, The first memory includes: a rewritable first main program which is a program for the first operation mode; a first boot loader program for starting up the first main program, the first boot loader program being a program for the second operation mode; The first main program a program for causing the first processor operating in the first operation mode to function as the image forming apparatus, The first processor, The device is started in the second operating mode and executes the first boot loader program; further performing at least one of decrypting the encrypted first main program and checking whether the first main program has been tampered with in accordance with the first boot loader program; and switching to the first operation mode after at least one of decrypting the encrypted first main program and checking whether the first main program has been tampered with is performed; The image forming apparatus further comprises: executing the first main program, on which at least one of decryption and tamper checking has been performed, after switching to the first operation mode.

2. The first boot loader program the encrypted data is stored in the first memory in a rewritable manner; The first processor, Executing the first boot loader program that has been started in the second operating mode and has undergone at least one of decryption and tamper checking; and performing at least one of decrypting the encrypted first main program and checking for tampering with the first main program in accordance with the first boot loader program on which at least one of the decryption and the tampering check has been performed; and switching to the first operation mode after at least one of decrypting the encrypted first main program and checking whether the first main program has been tampered with is performed; 2. The image forming apparatus according to claim 1, further comprising: a processor configured to execute the first main program after switching to the first operation mode, the first main program having been subjected to at least one of decryption and tamper checking.

3. The process according to the first main program is as follows: The first processor executes at least one of a RIP process, an encryption process, and a decryption process in the first operation mode; The RIP process is a process for converting image data described in a page description language into raster image data, the encryption process is a process of encrypting image data stored in the image forming apparatus, 3. The image forming apparatus according to claim 1, wherein the decryption process is a process for decrypting encrypted image data stored in the image forming apparatus.

4. a second processor that functions as an n-bit processor (n being a natural number); a second memory, The second memory includes: a second boot loader program is stored for performing at least one of decrypting the first boot loader program and checking for tampering with the first boot loader program; The second processor, performing at least one of decrypting the encrypted second boot loader program and checking for tampering with the second boot loader program; and executing the second boot loader program on which at least one of decryption and tamper checking has been performed; and performing at least one of decrypting the first boot loader program and checking for tampering with the first boot loader program according to the second boot loader program on which at least one of decryption and tampering check has been performed; The first processor, execute the first boot loader program that is started in the second operating mode and that has been decrypted and / or checked for tampering by the second processor; and performing at least one of decrypting the encrypted first main program and checking for tampering with the first main program in accordance with the first boot loader program on which at least one of the decryption and the tampering check has been performed; and switching to the first operation mode after at least one of decrypting the encrypted first main program and checking whether the first main program has been tampered with is performed; 4. The image forming apparatus according to claim 1, further comprising: a processor for executing the first main program, the first main program having undergone at least one of decryption and tamper checking, after switching to the first operation mode.

5. The first processor, when activated in the second operation mode, switching to the first operation mode after both decrypting the encrypted first main program and checking whether the first main program has been tampered with, 5. The image forming apparatus according to claim 1, further comprising: a processor configured to execute the first main program, the first main program having been both decrypted and checked for tampering, after switching to the first operation mode.

6. The first processor includes: A first core and a second core are provided, At least one of the first core and the second core is capable of switching from one of the first operating mode and the second operating mode to the other of the first core and the second core; The first memory includes: a second main program for the second operation mode is rewritably stored; The second main program is a program for causing at least one of the first core and the second core to function as the image forming apparatus when the at least one of the first core and the second core operates in the second operating mode, One of the first core and the second core that has switched to the second operating mode, Executing a first boot loader program that has been decrypted and / or tamper checked; Furthermore, one of the first core and the second core that has switched to the second operating mode switches to the first operating mode in accordance with the first boot loader program; The first main program executed by one of the first core and the second core that has switched to the first operating mode; The second main program is 6. The image forming apparatus according to claim 1, wherein the processing is executed by one of the first core and the second core that has switched to the second operation mode.

7. At least one of the decryption and the tamper checking of the first main program is 7. The image forming apparatus according to claim 6, wherein one of the first core and the second core that has switched to the second operating mode is executed according to the first boot loader program.

8. At least one of the decryption and the tamper checking of the second main program is 8. The image forming apparatus according to claim 6, wherein one of the first core and the second core that has switched to the second operating mode is executed according to the first boot loader program.

9. The process according to the second main program is as follows: one of the first core and the second core includes at least one of a RIP process, an encryption process, and a decryption process executed in the second operating mode; The RIP process is a process for converting image data described in a page description language into raster image data, the encryption process is a process of encrypting data stored in the image forming device, 9. The image forming apparatus according to claim 6, wherein the decryption process is a process of decrypting encrypted image data stored in the image forming apparatus.

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