Capacitor

Abstract

This capacitor (1A) comprises an insulating substrate (10), a capacitance forming unit (20) provided so as to face a first principal surface (10a) of the insulating substrate (10), and a first external connection wiring and a second external connection wiring that are connected to the capacitance forming unit (20). The capacitance forming unit (20) includes conductive metallic porous bodies (21) connected to the first external connection wiring, a dielectric film (22) that covers the surface of the metallic porous bodies (21), and a conduction film (23) that covers the dielectric film (22) and is connected to the second external connection wiring. The first external connection wiring and the second external connection wiring each have a first via conductor (13) and a second via conductor (14) that pass through the insulating substrate, and the second external connection wiring has an internal conductor (18) that covers the conduction film (23) so as to fill a space inside the capacitance forming unit (20). The conduction film (23) and the second via conductor (14) are connected by means of at least the internal conductor (18).

Description

[Technical field]

[0001] The present invention relates to a capacitor having a capacitance forming portion made of a porous metal body, a dielectric film, and a conductive film. [Background technology]

[0002] For example, US Patent Publication No. 2018 / 0277306 (Patent Document 1) discloses a capacitor having a capacitance forming portion provided by a metal porous body, a dielectric film covering the surface of the metal porous body, and a conductive film covering the dielectric film. In this capacitor, the metal porous body is composed of a sintered body of metal particles, and both the dielectric layer and the conductive film are formed by atomic layer deposition (ALD). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Publication No. 2018 / 0277306 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the capacitor disclosed in Patent Document 1, the conductive film in the capacitance forming portion described above is very thin, which reduces the cross-sectional area of ​​the conductive film. As a result, a problem occurs in that the so-called ESR (equivalent series resistance) becomes high when a current flows through this conductive film.

[0005] Therefore, the present invention has been made to solve the above-mentioned problems, and aims to achieve a low ESR in a capacitor having a capacitance forming portion consisting of a metal porous body, a dielectric film, and a conductive film. [Means for solving the problem]

[0006] The capacitor according to the present invention includes an insulating substrate, a capacitance forming portion, a first external connection wiring, and a second external connection wiring. The insulating substrate has a first main surface and a second main surface located on the opposite side to the first main surface, and the capacitance forming portion is provided so as to face the first main surface. The first external connection wiring and the second external connection wiring are connected to the capacitance forming portion. The capacitance forming portion includes a conductive metal porous body connected to the first external connection wiring, a dielectric film covering the surface of the metal porous body, and a conductive film covering the dielectric film and connected to the second external connection wiring. The first external connection wiring has a first via conductor penetrating the insulating substrate so as to reach from the first main surface to the second main surface, and the second external connection wiring has a second via conductor penetrating the insulating substrate so as to reach from the first main surface to the second main surface, and an internal conductor covering the conductive film so as to fill the space inside the capacitance forming portion. The conductive film and the second via conductor are connected at least via the internal conductor.

[0007] In the capacitor based on the present invention, the second external connection wiring may have a columnar conductor protruding from the first main surface toward the capacitance forming portion and surrounded by the capacitance forming portion, and in that case, it is preferable that the internal conductor and the second via conductor are connected at least via the columnar conductor.

[0008] In the capacitor according to the present invention, the columnar conductor may extend along a normal direction of the first main surface, in which case the columnar conductor may be connected to the second via conductor by overlapping at least a portion of the columnar conductor with the second via conductor when viewed along the normal direction of the first main surface.

[0009] In the capacitor based on the present invention, the capacitance forming portion may include a first capacitance forming portion and a second capacitance forming portion stacked and spaced apart from each other in the normal direction of the first main surface, and in that case, it is preferable that the conductive film of the first capacitance forming portion and the conductive film of the second capacitance forming portion are connected by the internal conductor and the columnar conductor.

[0010] In the capacitor according to the present invention, it is preferable that a thickness of the internal conductor at a portion located between the first capacitance forming portion and the second capacitance forming portion is greater than a thickness of the conductive film.

[0011] In the capacitor according to the present invention, the thickness of the internal conductor at a portion located between the first capacitance forming portion and the second capacitance forming portion may be three times or more the thickness of the conductive film.

[0012] In the capacitor based on the present invention, the insulating substrate may be provided with a support portion that protrudes from the first main surface towards the capacitance forming portion and is surrounded by the capacitance forming portion, thereby supporting the capacitance forming portion by being joined to the capacitance forming portion.

[0013] In the capacitor based on the present invention, the first external connection wiring may have a support conductor that constitutes the support portion, and in that case, it is preferable that the support conductor is connected to the metal porous body.

[0014] In the capacitor based on the present invention, the support conductor may extend along a normal direction of the first main surface, in which case the support conductor may be connected to the first via conductor by overlapping at least a portion of the support conductor with the first via conductor when viewed along the normal direction of the first main surface.

[0015] In the capacitor according to the present invention, a support portion protruding from the first main surface toward the capacitance forming portion and being surrounded by the capacitance forming portion to support the capacitance forming portion by being joined to the capacitance forming portion may be provided on the insulating substrate. In addition, the first external connection wiring may have a support conductor constituting the support portion, and in this case, it is preferable that the support conductor is connected to the metal porous body. In addition, the support conductor may extend along a normal direction of the first main surface, and in this case, the support conductor may be connected to the first via conductor by at least partially overlapping the first via conductor when viewed along the normal direction of the first main surface. In addition, the capacitor according to the present invention may further include a sealing portion provided on the first main surface, sealing the capacitance forming portion, and defining an outer surface located on the opposite side of the capacitance forming portion to the insulating substrate side. In that case, the supporting conductor may be exposed at the outer surface by penetrating the capacitance forming portion and the sealing portion, and the columnar conductor may be exposed at the outer surface by penetrating the capacitance forming portion and the sealing portion.

[0016] In the capacitor based on the present invention, the support conductor may extend along a normal direction of the first main surface, in which case the support conductor may not overlap the first via conductor when viewed along the normal direction of the first main surface.

[0017] In the capacitor according to the present invention, it is preferable that the supporting conductor contains a material that is at least a part of the same material as that contained in the porous metal body.

[0018] In the capacitor according to the present invention, a support portion that protrudes from the first main surface toward the capacitance forming portion and is surrounded by the capacitance forming portion to support the capacitance forming portion by being joined to the capacitance forming portion may be provided on the insulating substrate, and in this case, the first external connection wiring may have a support conductor that constitutes the support portion. The support conductor may extend along a normal direction of the first main surface and be connected to the metal porous body, and further, when viewed along the normal direction of the first main surface, the support conductor may overlap at least a part of the first via conductor, thereby connecting the support conductor to the first via conductor. In addition, the capacitance forming portion may include a first capacitance forming portion and a second capacitance forming portion that are stacked and spaced apart from each other in the normal direction of the first main surface. In that case, the metal porous body of the first capacitance forming portion and the metal porous body of the second capacitance forming portion may be connected by the supporting conductor, and the conductive film of the first capacitance forming portion and the conductive film of the second capacitance forming portion may be connected by the internal conductor and the columnar conductor.

[0019] The capacitor according to the present invention may further include a sealing portion provided on the first main surface, sealing the capacitance forming portion and defining an outer surface located on the opposite side of the capacitance forming portion from the insulating substrate side. In this case, the supporting conductor may penetrate the capacitance forming portion and the sealing portion to expose the supporting conductor at the outer surface, or the columnar conductor may penetrate the capacitance forming portion and the sealing portion to expose the columnar conductor at the outer surface.

[0020] In the capacitor based on the present invention, when viewed along the normal direction of the first main surface, it is preferable that the first via conductor and the second via conductor are both arranged within the area in which the capacitance forming portion is arranged.

[0021] In the capacitor according to the present invention, each of the first via conductors may be provided in plurality, and each of the second via conductors may be provided in plurality.

[0022] In the capacitor based on the present invention, the first via conductor and the second via conductor may be arranged in an array when viewed along the normal direction of the first main surface, and in that case, it is preferable that the polarity of one via conductor is different from the polarity of the via conductor adjacent to it at the closest distance.

[0023] In the capacitor according to the present invention, the internal conductor preferably contains at least one of Ag and a conductive polymer as a main material. Effect of the Invention

[0024] According to the present invention, a capacitor having a capacitance forming portion made of a porous metal body, a dielectric film, and a conductive film has a low ESR. [Brief description of the drawings]

[0025] [Figure 1] 1 is a schematic front view of a capacitor in accordance with a first embodiment. [Diagram 2] FIG. 2 is a schematic bottom view of the capacitor shown in FIG. [Diagram 3] FIG. 2 is a schematic cross-sectional view of the capacitor shown in FIG. [Figure 4] 4 is an enlarged schematic cross-sectional view of the vicinity of a second via conductor shown in FIG. 3. [Diagram 5] 4 is a schematic cross-sectional view showing an enlarged portion of the internal conductor shown in FIG. [Figure 6] 4 is a schematic cross-sectional view showing an enlarged view of the vicinity of a first main surface of the insulating substrate shown in FIG. [Figure 7] 4 is a schematic cross-sectional view showing an enlarged portion of the sealing portion shown in FIG. [Figure 8] 4 is a flow diagram showing a method for manufacturing the capacitor according to the first embodiment. [Figure 9]9 is a schematic cross-sectional view showing a state after step S4 of the manufacturing flow shown in FIG. 8 is completed. [Figure 10] 9 is a schematic cross-sectional view for explaining step S5 of the manufacturing flow shown in FIG. 8. [Figure 11] 9 is a schematic cross-sectional view for explaining step S6 of the manufacturing flow shown in FIG. 8. [Figure 12] 9 is a schematic cross-sectional view for explaining step S7 of the manufacturing flow shown in FIG. 8. [Figure 13] 9 is a schematic cross-sectional view for explaining step S8 of the manufacturing flow shown in FIG. 8. [Figure 14] 9 is a schematic cross-sectional view for explaining step S9 in the manufacturing flow shown in FIG. 8. [Figure 15] 9 is a schematic cross-sectional view for explaining step S10 of the manufacturing flow shown in FIG. 8. [Figure 16] 9 is a schematic cross-sectional view for explaining step S11 of the manufacturing flow shown in FIG. 8. [Figure 17] 9 is a schematic cross-sectional view for explaining step S12 of the manufacturing flow shown in FIG. 8. [Figure 18] 9 is a schematic cross-sectional view for explaining step S13 in the manufacturing flow shown in FIG. 8. [Figure 19] 9 is a schematic cross-sectional view for explaining step S14 in the manufacturing flow shown in FIG. 8. [Figure 20] 9 is a schematic cross-sectional view for explaining step S15 in the manufacturing flow shown in FIG. 8. [Figure 21] 9 is a schematic cross-sectional view for explaining step S16 in the manufacturing flow shown in FIG. 8. [Figure 22] 9 is a schematic cross-sectional view for explaining step S17 in the manufacturing flow shown in FIG. 8. [Diagram 23] 9 is a schematic cross-sectional view for explaining step S18 in the manufacturing flow shown in FIG. 8. [Figure 24] 4 is a schematic cross-sectional view showing one embodiment of a columnar conductor in the capacitor shown in FIG. [Diagram 25] FIG. 11 is a schematic cross-sectional view of a capacitor according to a first modified example. [Figure 26] FIG. 11 is a schematic cross-sectional view of a capacitor according to a second modified example. [Figure 27] FIG. 13 is a schematic cross-sectional view of a capacitor according to a third modified example. [Figure 28] FIG. 13 is a schematic cross-sectional view of a capacitor according to a fourth modified example. [Figure 29] FIG. 11 is a schematic cross-sectional view of a capacitor in accordance with a second embodiment. [Diagram 30] 10 is a flow diagram showing a method for manufacturing a capacitor according to a second embodiment. [Diagram 31] 31 is a schematic cross-sectional view for explaining step S7 of the manufacturing flow shown in FIG. 30. [Diagram 32] 31 is a schematic cross-sectional view for explaining step S9 of the manufacturing flow shown in FIG. 30. [Diagram 33] 31 is a schematic cross-sectional view for explaining step S15B of the manufacturing flow shown in FIG. 30. [Diagram 34] 31 is a schematic cross-sectional view for explaining step S16 in the manufacturing flow shown in FIG. 30. [Diagram 35] 31 is a schematic cross-sectional view for explaining step S17 in the manufacturing flow shown in FIG. 30. [Diagram 36] FIG. 11 is a schematic cross-sectional view of a capacitor in accordance with embodiment 3. [Figure 37] FIG. 11 is a flow diagram showing a method for manufacturing a capacitor according to a third embodiment. [Figure 38] FIG. 13 is a schematic cross-sectional view of a capacitor according to a fifth modified example. [Figure 39] 39 is an enlarged schematic cross-sectional view of the vicinity of a second via conductor shown in FIG. 38. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiments described below, the same or common parts are denoted by the same reference numerals in the drawings, and the description thereof will not be repeated. In addition, in the embodiments described below, the terms "anode" and "cathode" are used for convenience of explanation, but the electrical polarity of the capacitor in the embodiments described below is not uniquely determined by these terms, and the electrical polarity is appropriately determined according to the usage environment of the capacitor.

[0027] (Embodiment 1) FIG. 1 is a schematic front view of the capacitor according to the first embodiment, and FIG. 2 is a schematic bottom view of the capacitor as viewed from the direction of the arrow II shown in FIG. 1. FIG. 3 is a schematic cross-sectional view of the capacitor taken along the line III-III shown in FIG. 2, and FIG. 4 is a schematic cross-sectional view enlarging the vicinity of the second via conductor shown in FIG. 3. FIG. 5 is a schematic cross-sectional view enlarging a portion of the internal conductor shown in FIG. 3, and FIG. 6 is a schematic cross-sectional view enlarging the vicinity of the first main surface of the insulating substrate shown in FIG. 3. FIG. 7 is a schematic cross-sectional view enlarging a portion of the sealing portion shown in FIG. 3. First, the configuration of a capacitor 1A according to the present embodiment will be described with reference to FIGS. 1 to 7.

[0028] 1 to 3, capacitor 1A has a flat, substantially rectangular parallelepiped outer shape, and is a so-called surface-mounted electronic component whose bottom surface is configured as a mounting surface for a wiring board or the like. Capacitor 1A mainly comprises an insulating substrate 10, a capacitance forming portion 20, and a sealing portion 30. Of these, capacitance forming portion 20 is provided so as to face insulating substrate 10. Capacitor forming portion 20 is located inside capacitor 1A by being sealed by insulating substrate 10 and sealing portion 30 provided on insulating substrate 10.

[0029] The insulating substrate 10 is provided with a first via conductor 13 and a second via conductor 14, a support conductor 15, a first bump 16 and a second bump 17, an internal conductor 18, and a columnar conductor 19. The first via conductor 13, the second via conductor 14, the support conductor 15, the first bump 16, the second bump 17, the internal conductor 18, and the columnar conductor 19 constitute a pair of external connection wirings as lead-out wirings for electrically connecting the capacitance forming portion 20 located inside the capacitor 1A to an external circuit. The pair of external connection wirings includes a first external connection wiring as an anode and a second external connection wiring as a cathode.

[0030] As shown in Figures 1 to 4 and 6, the insulating substrate 10 is a flat plate-shaped member having a first main surface 10a and a second main surface 10b located on the opposite side to the first main surface 10a. As the insulating substrate 10, it is preferable to use a substrate having electrical insulation properties, and it is preferable to use a substrate mainly composed of an inorganic material. More specifically, as the insulating substrate 10, it is possible to use a substrate mainly composed of any of Si, Al2O3, ZrO2, BN, Si3N4, AlN, MgO, Mg2SiO4, BaTiO3, SrTiO3, and CaTiO3.

[0031] The thickness and size of the insulating substrate 10 are not particularly limited, but it is preferable to use an alumina substrate that is rectangular in plan view, for example, with a thickness of 5 μm or more and 50 μm or less and a side length of 500 μm or more and 2000 μm or less.

[0032] The insulating substrate 10 is provided with a plurality of first through holes 11, each of which penetrates the insulating substrate 10 from the first main surface 10a to the second main surface 10b. Each of the plurality of first through holes 11 is filled with a first via conductor 13 (see FIG. 3). Each of the plurality of first via conductors 13 has a shape, for example, substantially cylindrical.

[0033] The insulating substrate 10 is provided with a plurality of second through holes 12, each of which penetrates the insulating substrate 10 from the first main surface 10a to the second main surface 10b. Each of the second through holes 12 is filled with a second via conductor 14 (see FIG. 3). The shape of each of the second via conductors 14 is, for example, substantially cylindrical.

[0034] Each of the multiple first via conductors 13 constitutes a part of the above-mentioned first external connection wiring. Each of the multiple second via conductors 14 constitutes a part of the above-mentioned second external connection wiring. In other words, the multiple first via conductors 13 and the multiple second via conductors 14 respectively constitute the first external connection wiring and the second external connection wiring of different polarities.

[0035] Here, in this embodiment, the first via conductor 13 and the second via conductor 14 are both arranged within the area in which the capacitance forming portion 20 is arranged (i.e., the area indicated by the dashed line in Figure 2) when viewed along the normal direction of the first main surface 10a of the insulating substrate 10.

[0036] In this embodiment, four first via conductors 13 and five second via conductors 14 are provided in the insulating substrate 10, so that a total of nine via conductors penetrate the insulating substrate 10. These nine via conductors are arranged in an array with a layout of three rows and three columns. Here, the polarity of one via conductor is different from the polarity of the via conductor adjacent to it at the shortest distance. Note that the number and arrangement of these first via conductors 13 and second via conductors 14 are not particularly limited to this.

[0037] The first via conductor 13 and the second via conductor 14 can be made of various wiring materials, but are preferably made of metal materials with particularly high electrical conductivity. The material of the first via conductor 13 and the second via conductor 14 can be a metal material mainly made of, for example, any of Ni, Ag, Cu, Au, Pt, Mo, and W, but is preferably Cu. Here, the material of the first via conductor 13 and the second via conductor 14 can be appropriately changed according to the mounting environment of the capacitor 1A according to this embodiment, and the material of the first via conductor 13 and the material of the second via conductor 14 do not necessarily have to be the same. In this embodiment, the first via conductor 13 and the second via conductor 14 are made of Ni.

[0038] The second via conductors 14 may be formed together with the columnar conductors 19, which will be described later, by a thick-film formation method such as electrolytic plating or screen printing. In this case, the material of the second via conductors 14 is the same as the material of the columnar conductors 19, which will be described later.

[0039] The axial length and size of the first via conductor 13 and the second via conductor 14 are not particularly limited and are set appropriately according to the thickness and size of the insulating substrate 10. Here, the axial length of the first via conductor 13 and the second via conductor 14 is preferably, for example, 5 μm or more and 50 μm or less, and their diameters are preferably, for example, 15 μm or more and 150 μm or less.

[0040] 3, the insulating substrate 10 is provided with a plurality of substantially cylindrical supporting conductors 15 that protrude from the first main surface 10a toward the capacitance forming portion 20 and are surrounded by the capacitance forming portion 20. Each of the plurality of supporting conductors 15 thus configured is joined to the capacitance forming portion 20, thereby functioning as a supporting portion that supports the capacitance forming portion 20. In other words, the provision of the plurality of supporting conductors 15 as these supporting portions makes it possible to suppress the occurrence of warping of the insulating substrate 10 due to stress generated during the manufacturing process of the capacitor 1A, but this point will be described later.

[0041] Moreover, each of the multiple supporting conductors 15 extends along the normal direction of the first main surface 10a, and when viewed along the normal direction, is arranged so as to overlap with each of the multiple first via conductors 13. In this way, the supporting conductors 15 are connected to the first via conductors 13.

[0042] Here, each of the multiple supporting conductors 15 is preferably arranged to be substantially coaxial with each of the multiple first via conductors 13. Also, each of the multiple supporting conductors 15 is preferably configured such that a cross section perpendicular to the normal direction of the first main surface 10a is larger than a cross section of the corresponding first via conductor 13. Therefore, the diameter of each of the multiple supporting conductors 15 is preferably set to, for example, 15 μm or more and 100 μm or less.

[0043] With this configuration, even if the formation positions of the multiple support conductors 15 are shifted and the multiple support conductors 15 are not completely coaxial with the multiple first via conductors 13, the multiple support conductors 15 can be arranged to at least partially overlap with the multiple first via conductors 13 when viewed along the normal direction of the first main surface 10a. Therefore, this makes it possible to reliably connect the multiple support conductors 15 to the multiple first via conductors 13.

[0044] The axial length of the support conductor 15 is not particularly limited and is appropriately set according to the thickness of the capacitance forming portion 20, but it is preferable that the support conductor 15 has an axial length sufficient to penetrate the capacitance forming portion 20 in the thickness direction. In addition, as described later, when the capacitance forming portion 20 includes a plurality of capacitance forming portions stacked at a distance from each other in the normal direction of the first main surface 10a, it is necessary that the support conductor 15 has an axial length sufficient to be joined to at least a part of the layer located farthest from the first main surface 10a (i.e., the first capacitance forming portion 20a in FIG. 3). It is preferable that the axial length of the plurality of support conductors 15 has a lower limit of 15 μm and an upper limit of the thickness of the capacitor 1A minus 20 μm.

[0045] The supporting conductor 15 is preferably made of at least a part of the same material as that contained in the metal porous body 21 described later. The material of the supporting conductor 15 may be, for example, a metal material containing any one of Ni, Mo, W, Al, Ti, Ta, Nb, Cu, Pt, Au, and Ag as the main material. The supporting conductor 15 may also be made of an alloy material containing two or more selected from these metal materials as the main components. In this embodiment, the supporting conductor 15 is made of Ni.

[0046] The outer shape of the supporting conductor 15 in a plan view is not limited to a substantially circular shape, and may be, for example, a substantially elliptical shape, etc. Also, the supporting conductor 15 may extend in a direction tapered to a considerable extent with respect to the normal direction of the first main surface 10a.

[0047] The internal conductor 18 is continuously formed so as to cover a conductive film 23 (described later) constituting the capacitance forming portion 20. More specifically, the internal conductor 18 covers the conductive film 23 that defines the internal space of the capacitance forming portion 20 so as to fill the internal space, and also covers the conductive film 23 that covers the outer surface of the capacitance forming portion 20 and the tip portion of the supporting conductor 15. The internal conductor 18 also covers the conductive film 23 that covers the first main surface 10a of the insulating substrate 10.

[0048] 4, the internal conductor 18 covers a conductive film 23 that covers the surface of the insulating substrate 10 in a portion that defines the second through hole 12 provided in the insulating substrate 10. More specifically, at the boundary between the second via conductor 14 and the base material of the insulating substrate 10, the base material of the insulating substrate 10 is covered with a dielectric film 22 described below, the dielectric film 22 is covered with a conductive film 23, and the conductive film 23 is further covered with the internal conductor 18. The internal conductor 18 is further covered with the second via conductor 14, and thus the internal conductor 18 is directly connected to the second via conductor 14.

[0049] Furthermore, as shown in FIG. 3, the internal conductor 18 also covers the surfaces of each of a number of columnar conductors 19 described later, thereby connecting the conductive film 23, together with the internal conductor 18, to the second via conductor 14 via the columnar conductors 19.

[0050] The thickness of the internal conductor 18 is not particularly limited as long as it is thicker than the conductive film 23, but is preferably 30 μm or more, and more preferably 200 μm or more. For convenience of drawing, the internal conductor 18 is drawn to include a portion where the thickness is extremely different in Figures 3 to 6, etc., and therefore the thickness of a part of the internal conductor 18 (for example, the vicinity of the second via conductor 14, etc.) is approximately the same as the thickness of the conductive film 23, but in reality, the thicknesses of the conductive film 23 and the internal conductor 18 are configured to be significantly different from each other as described above (the same applies to Figures 19 to 29, Figures 33 to 36, Figures 38 and 39 described later).

[0051] When configured as described above, the conductive film 23 and the second via conductor 14 are connected through the internal conductor 18. This leads to a reduction in the ESR of the capacitor 1A, the details of which will be described later.

[0052] Furthermore, the internal conductor 18 is formed so as to fill the space between the layers of multiple capacitance forming parts that are stacked and spaced apart from each other in the normal direction of the first main surface 10a, which also contributes to reducing the ESR of the capacitor 1A, and the details of this will be described later.

[0053] Furthermore, by forming the internal conductors 18 in this manner, each layer of the capacitance forming portion 20 is held by the internal conductors 18 embedded between the layers, thereby improving the mechanical strength of the capacitance forming portion 20.

[0054] The internal conductor 18 may be mainly made of at least one of a metal material such as Ag and a conductive polymer. The internal conductor 18 may also be made of an alloy material mainly made of two or more of these metal materials. In the present embodiment, the internal conductor 18 is made of Ag.

[0055] The internal conductor 18 can be formed by, for example, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, a plating method, a bias sputtering method, a sol-gel method, a method using conductive polymer filling, or a method using a supercritical fluid.

[0056] The thickness of the internal conductor 18 is measured, for example, by observing a cross section perpendicular to the extending direction of the first main surface 10a of the insulating substrate 10 using a scanning electron microscope.

[0057] Specifically, when the capacitor 1A is viewed from above, the longitudinal direction of the capacitor 1A is Lx, the lateral direction is Ly, and the thickness direction of the capacitor 1A (i.e., the normal direction of the first main surface 10a) is Lz, first, the capacitor 1A is polished so that the Lx-Lz cross section of the capacitor 1A at the center in the Ly direction is exposed. The polishing is performed so that the exposed cross section is located within an error range of ±100 μm in the Ly direction with the center position as a reference.

[0058] Next, the exposed cross section is observed. The observation range of the cross section in the Lx direction is a range of ±50 μm from the center position of the cross section in the Lx direction, and the observation range of the cross section in the Lz direction is a range between the layer located closest to the first main surface 10a and the layer adjacent thereto, among the multiple capacitance forming parts stacked at a distance from each other in the Lz direction.

[0059] When measuring the thickness of the internal conductor 18, first, in a cross-sectional image of 100,000 times magnification obtained by a scanning electron microscope, the elements of the material defining the internal conductor 18 are mapped by energy dispersive X-ray spectroscopy, and the image is captured. Next, the mapping image is subjected to binarization processing. Next, in the binarized image, the thickness of the internal conductor 18 in the Lz direction is measured at 100 points at a pitch of 10 nm in the Lx direction, and the average value of these is calculated. The average value calculated in this manner is the thickness of the internal conductor 18. Here, in FIG. 5, three of the thicknesses of the internal conductor 18 in the Lz direction measured at these 100 points are illustrated as line segment lengths a1, a2, and a3. Note that FIG. 5 is a schematic diagram in which a part of the internal conductor 18 is enlarged to explain the measurement of the thickness of the internal conductor 18, and does not illustrate the above-mentioned mapping image or the binarized image.

[0060] The insulating substrate 10 is further provided with a plurality of substantially cylindrical columnar conductors 19 which protrude from the first main surface 10a towards the capacitance generating portion 20 and are surrounded by the capacitance generating portion 20 with internal conductors 18 interposed therebetween.

[0061] As described above, the surface of each of the columnar conductors 19 is covered with the internal conductor 18, and thus the columnar conductors 19 are connected to the internal conductor 18.

[0062] Moreover, each of the multiple columnar conductors 19 extends along the normal direction of the first main surface 10a, and when viewed along the normal direction of the first main surface 10a, is arranged so as to overlap with each of the multiple second via conductors 14. As a result, each of the multiple columnar conductors 19 is connected to the second via conductor 14 at its end on the insulating substrate 10 side.

[0063] In this configuration, the conductive film 23 and the second via conductor 14 are connected not only through the internal conductor 18 as described above, but also through the columnar conductor 19 together with the internal conductor 18. In other words, the internal conductor 18 and the second via conductor 14 are connected not only directly, but also through the columnar conductor 19.

[0064] Therefore, the second external connection wiring serving as the cathode described above is connected to the capacitance forming portion 20 through the second via conductor 14, the internal conductor 18, and the columnar conductor 19. This leads to a reduction in the ESR of the capacitor 1A, the details of which will be described later.

[0065] Here, each of the multiple columnar conductors 19 is preferably arranged substantially coaxially with each of the multiple second via conductors 14. Moreover, each of the multiple columnar conductors 19 is preferably configured such that a cross section perpendicular to the normal direction of the first main surface 10a is larger than a cross section of the corresponding second via conductor 14. Therefore, the diameter of each of the multiple columnar conductors 19 is preferably set to, for example, 15 μm or more and 150 μm or less.

[0066] With this configuration, even if the formation positions of the plurality of columnar conductors 19 are shifted and the plurality of columnar conductors 19 are not completely coaxial with the plurality of second via conductors 14, the plurality of columnar conductors 19 can be arranged to at least partially overlap with the plurality of second via conductors 14 when viewed along the normal direction of the first main surface 10a. Therefore, this makes it possible to reliably connect the plurality of columnar conductors 19 to the plurality of second via conductors 14.

[0067] The axial length of the columnar conductor 19 is not particularly limited and is appropriately set according to the thickness of the capacitance forming portion 20, but it is preferable that the columnar conductor 19 has an axial length sufficient to penetrate the capacitance forming portion 20 in the thickness direction. In addition, as described later, when the capacitance forming portion 20 includes a plurality of capacitance forming portions stacked at a distance from each other in the normal direction of the first main surface 10a, it is necessary that the columnar conductor 19 has an axial length sufficient to be joined to at least a part of the layer located farthest from the first main surface 10a (i.e., the first capacitance forming portion 20a in FIG. 3). The axial length of the plurality of columnar conductors 19 is preferably, for example, a lower limit of 15 μm and an upper limit of a length obtained by subtracting 20 μm from the thickness of the capacitor 1A.

[0068] The columnar conductor 19 is preferably made of at least a part of the same material as that contained in the metal porous body 21 described later. The material of the columnar conductor 19 may be a metal material containing, for example, any one of Ni, Mo, W, Al, Ti, Ta, Nb, Cu, Pt, Au, and Ag as the main material. The columnar conductor 19 may also be made of an alloy material containing two or more of these metal materials as the main components.

[0069] The columnar conductor 19 may be formed together with the second via conductor 14 by a thick film formation method such as electrolytic plating or screen printing. In that case, the material of the columnar conductor 19 is the same as the material of the second via conductor 14. In the present embodiment, the second via conductor 14 and the columnar conductor 19 made of Ni are both formed by electrolytic plating.

[0070] The outer shape of the columnar conductor 19 in a plan view is not limited to a substantially circular shape, and may be, for example, a substantially elliptical shape, etc. Furthermore, the columnar conductor 19 may extend in a direction tapered to a considerable extent with respect to the normal direction of the first main surface 10a.

[0071] The supporting conductor 15 described above constitutes a part of the first external connecting wiring, and the internal conductor 18 and the columnar conductor 19 constitute a part of the second external connecting wiring. That is, the supporting conductor 15, the internal conductor 18, and the columnar conductor 19 constitute the first external connecting wiring and the second external connecting wiring, respectively, which have different polarities.

[0072] 1 to 3, a plurality of first bumps 16 are provided on the second main surface 10b of the insulating substrate 10 so as to cover the plurality of first via conductors 13. The plurality of first bumps 16 serve as bonding materials for mounting the capacitor 1A as a surface mount electronic component on a wiring board or the like and for electrically connecting the capacitance forming portion 20 of the capacitor 1A to an external circuit, and are provided so as to protrude from the second main surface 10b of the insulating substrate 10. Each of the plurality of first bumps 16 has a substantially semispherical shape.

[0073] A plurality of second bumps 17 are provided on the second main surface 10b of the insulating substrate 10 so as to cover the plurality of second via conductors 14. The plurality of second bumps 17 serve as bonding materials for mounting the capacitor 1A as a surface mount electronic component on a wiring board or the like and for electrically connecting the capacitance forming portion 20 of the capacitor 1A to an external circuit, and are provided so as to protrude from the second main surface 10b of the insulating substrate 10. Each of the plurality of second bumps 17 has a substantially semispherical shape.

[0074] Each of the multiple first bumps 16 constitutes a part of the above-mentioned first external connection wiring. Each of the multiple second bumps 17 constitutes a part of the above-mentioned second external connection wiring. In other words, the multiple first bumps 16 and the multiple second bumps 17 respectively constitute the first external connection wiring and the second external connection wiring of different polarities.

[0075] The first bump 16 and the second bump 17 can be made of various wiring materials, but are preferably made of a metal material having particularly high electrical conductivity. The material of the first bump 16 and the second bump 17 can be a metal material mainly made of, for example, Ni, Ag, Cu, Au, or Sn. In this embodiment, the first bump 16 and the second bump 17 are made of Au.

[0076] The sizes of first bump 16 and second bump 17 are not particularly limited, and are set appropriately depending on the sizes of first via conductor 13 and second via conductor 14.

[0077] As a result, the first external connection wiring, which serves as the anode of the pair of external connection wirings, is composed of the first via conductor 13, the support conductor 15, and the first bump 16, and the second external connection wiring, which serves as the cathode of the pair of external connection wirings, is composed of the second via conductor 14, the internal conductor 18, the columnar conductor 19, and the second bump 17.

[0078] As shown in Figure 3, the capacitance forming portion 20 is arranged opposite the insulating substrate 10, and includes a metal porous body 21 having a plurality of fine pores therein, a dielectric film 22 covering the surface of the metal porous body 21, and a conductive film 23 further covering the surface of the dielectric film 22.

[0079] Although the capacitance forming portion 20 is provided so as to face the insulating substrate 10, it is not substantially directly bonded to the insulating substrate 10, or even if it is directly bonded, it is only slightly bonded to the insulating substrate 10. Here, a state in which the capacitance forming portion 20 is only slightly bonded to the insulating substrate 10 means a state in which a part of the capacitance forming portion 20 is bonded to the insulating substrate 10 at a predetermined ratio or less. In other words, a state in which the capacitance forming portion 20 is only slightly joined to the insulating substrate 10 means that, when looking at an arbitrary region on the first main surface 10a of the insulating substrate 10 in a cross section perpendicular to the extending direction of the first main surface 10a of the insulating substrate 10 as shown in Figure 6, the sum of the lengths of the line segments parallel to the first main surface 10a in the portion in which the metal porous body 21 is joined to the insulating substrate 10 directly or indirectly via the dielectric film 22 or the conductive film 23 in the arbitrary region (i.e., line segment length d1+d2 in the example shown in Figure 6) is 30% or less of the total line segment length in the arbitrary region of the first main surface (i.e., line segment length c in the example shown in Figure 6).

[0080] 3, the capacitance forming portion 20 includes a plurality of capacitance forming portions stacked at a distance from each other in the normal direction of the first main surface 10a. The number of layers of the stacked capacitance forming portions is not particularly limited and is appropriately set according to the desired capacitance. The capacitance forming portion 20 in this embodiment is composed of three layers, and for convenience of explanation, the layers will be referred to as the first capacitance forming portion 20a, the second capacitance forming portion 20b, and the third capacitance forming portion 20c in order from the layer located farthest from the first main surface 10a.

[0081] At least some of the multiple fine pores provided inside the metal porous body 21 are not closed by the metal porous body itself, and preferably most or all of the multiple fine pores provided inside the metal porous body 21 are not closed by the metal porous body itself. Such a metal porous body is, for example, composed of a sintered body of metal particles.

[0082] The porous metal body 21 is located on the first main surface 10a of the insulating substrate 10 except for the edge portion so as to surround the supporting conductor 15. The porous metal body 21 thus configured is fired together with the supporting conductor 15 containing at least a part of the same material as that contained in the porous metal body 21 in the formation process.

[0083] As a result, the porous metal body 21 is joined to the supporting conductor 15. That is, in the capacitor 1A according to the present embodiment, the porous metal body 21 of the first capacitance forming portion 20a, the porous metal body 21 of the second capacitance forming portion 20b, and the porous metal body 21 of the third capacitance forming portion 20c are connected by the supporting conductor 15. Therefore, the first external connection wiring serving as the anode described above is connected to the capacitance forming portion 20 via the supporting conductor 15.

[0084] The metal porous body 21 can be made of various conductive metal materials, but is preferably made of a metal material mainly made of any of Ni, Mo, W, Al, Ti, Ta, Nb, Cu, Pt, Au, and Ag. The metal porous body 21 may also be made of an alloy material mainly made of two or more selected from these metal materials. In this embodiment, the metal porous body 21 is made of Ni.

[0085] The thickness and size of the porous metal body 21 are not particularly limited, and the size thereof is appropriately set according to the size of the insulating substrate 10 .

[0086] Here, as described above, the metal porous body 21 is preferably composed of a sintered body of metal particles. In this case, the metal particles may have various shapes, such as a spherical shape, an oval spherical shape, a flat shape, a plate shape, a needle shape, etc. The particle size of the metal particles is not particularly limited, but the average particle size is preferably 600 nm or less, and more preferably 20 nm or more and 500 nm or less.

[0087] As described above, the dielectric film 22 covers the surface of the porous metal body 21. More specifically, the dielectric film 22 not only covers the surface of the porous metal body 21 in the portion located on the outermost side of the capacitance forming portion 20, but also covers the surface of the porous metal body 21 in the portion located inside the capacitance forming portion 20, which is defined by the above-mentioned fine pores that are not closed by the porous metal body itself. The dielectric film 22 also covers the surface of the supporting conductor 15.

[0088] The dielectric film 22 can be made of various insulating materials, for example, AlO x , SiO x , HfO x , TiO x , TaO x , ZrO x , SiAlO x , HfAlO x , ZrAlO x , AlTiO x , SrTiO x , HfSiO x , ZrSiO x , TiZrO x , TiZrO x , TiZrWO x , SrTiO x , BaTiO x , PbTiO x , BaSrTiO x , BaCaTiO x Metal oxides such as AlN x , SiN x , AlScN x Metal nitrides such as AlO x N y , SiO x Ny , HfO x N y , SiC x O y N z Among them, AlO x (e.g. Al2O3), SiO x (e.g. SiO2), HfO x , TiO x , SiAlO x , HfAlO x , ZrAlO x , HfSiO x and ZrSiO x It is preferable that the dielectric film 22 is made of any one of the above. Note that the above chemical formulas simply indicate the composition of the material and do not limit the composition. In other words, x, y, and z attached to O and N may be any value greater than 0, and the abundance ratio of each element including a metal element is arbitrary. The dielectric film 22 may be made of a laminated film consisting of a plurality of dielectric layers made of different materials. In this embodiment, the dielectric film 22 is made of AlSiO.

[0089] The dielectric film 22 can be preferably formed by a gas phase method such as a vacuum deposition method, a CVD method, a sputtering method, an ALD method, a PLD method, or the like, or a method using a supercritical fluid, and is particularly preferably formed by an ALD method.

[0090] The thickness of the dielectric film 22 is not particularly limited, but is preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less.

[0091] As described above, the conductive film 23 covers the surface of the dielectric film 22. More specifically, the conductive film 23 not only covers the surface of the dielectric film 22 in the portion located on the outermost side of the capacitance forming portion 20, but also covers the surface of the dielectric film 22 in the portion located inside the capacitance forming portion 20. The conductive film 23 also covers the surface of the dielectric film 22 that covers the surface of the supporting conductor 15.

[0092] The conductive film 23 can be made of various conductive materials, including metal materials mainly made of any of Ni, Cu, Ru, Al, W, Ti, Ag, Au, Zn, Ta, and Nb, alloy materials mainly made of two or more selected from these metal materials, metal nitrides such as TiN, TiAlN, TiSiN, TaN, NbN, and WN, metal oxynitrides such as TiON and TiAlON, conductive polymers such as PEDOT (poly(3,4-ethylenedioxythiophene)), polypyrrole, and polyaniline, and conductive oxide films such as RuO2, ZnO, (Zn,Al)O, and NiO. Among these, it is preferable to make the conductive film 23 of an oxide semiconductor such as TiN, TiON, ZnO, or RuO. In this embodiment, the conductive film 23 is made of TiN.

[0093] The conductive film 23 can be preferably formed by a CVD method, an ALD method, a PLD method, a plating method, a bias sputtering method, a sol-gel method, a method using conductive polymer filling, or a method using a supercritical fluid, and is particularly preferably formed by an ALD method. The conductive film 23 may also be configured as a laminated film consisting of multiple conductive layers made of different materials. In that case, a film can be formed by another method after the film is formed by the ALD method.

[0094] The thickness of the conductive film 23 is not particularly limited, but is preferably 3 nm or more, and more preferably 10 nm or more.

[0095] Here, as described above, the capacitance forming portion 20 includes a plurality of capacitance forming portions stacked at a distance from each other in the normal direction of the first main surface 10a, and the internal conductor 18 is formed so as to fill the space provided between these layers.

[0096] By forming the internal conductor 18 in this manner, the conductive film 23 of the first capacitance forming portion 20a, the conductive film 23 of the second capacitance forming portion 20b, and the conductive film 23 of the third capacitance forming portion 20c are connected by the internal conductor 18.

[0097] The thickness of the internal conductor 18 in the portion located between the first capacitance forming portion 20a and the second capacitance forming portion 20b is preferably configured to be greater than the thickness of the conductive film 23, and more preferably, the thickness of the internal conductor 18 is configured to be at least twice the thickness of the conductive film, more preferably, at least three times the thickness, more preferably, at least 10 times the thickness, and even more preferably, at least 100 times the thickness. This configuration is also true for the thickness of the internal conductor 18 in the portion located between the second capacitance forming portion 20b and the third capacitance forming portion 20c.

[0098] Such a configuration will enable the ESR of the capacitor 1A to be reduced, the details of which will be described later.

[0099] 1 and 3, the sealing portion 30 is provided on the first main surface 10a of the insulating substrate 10, and seals the capacitance forming portion 20 together with the insulating substrate 10, while defining an outer surface 30a located on the opposite side of the capacitance forming portion 20 from the insulating substrate 10. More specifically, the sealing portion 30 is located so as to cover the upper, side, and lower sides of the capacitance forming portion 20 provided to face the first main surface 10a of the insulating substrate 10, and further, when the space inside the capacitance forming portion 20 is not completely filled with the internal conductor 18, the sealing portion 30 is located so as to fill the space that is not filled with the internal conductor 18.

[0100] The sealing portion 30 can be made of various insulating materials, but is preferably made of an insulating material having excellent weather resistance. The material of the sealing portion 30 can be a resin material such as polyimide resin, polybenzoxazole resin, polyethylene terephthalate resin, benzocyclobutene resin, or epoxy resin. The resin material can contain various additives, and for example, SiO2 filler or Al2O3 filler may be contained to adjust the thermal expansion coefficient. In this embodiment, the sealing portion 30 is made of epoxy resin.

[0101] In addition, when it is difficult to ensure moisture resistance with only the sealing portion 30, a moisture-resistant protective film may be formed between the capacitance forming portion 20 and the sealing portion 30. The moisture-resistant protective film can be formed, for example, by providing an inorganic insulator made of SiN, SiO2, Al2O3, HfO2, ZrO2, or the like so as to cover the capacitance forming portion 20 by a CVD method, an ALD method, or the like, before forming the sealing portion 30, or by providing an organic insulator having water repellency, such as a fluorine-based resin or a silane coupling agent resin, so as to cover the capacitance forming portion 20. Here, the moisture-resistant protective film does not necessarily need to be formed inside the capacitance forming portion 20, and it is sufficient if it is formed so as to cover only the outer surface.

[0102] The sealing portion 30 can be formed by various coating methods, such as a method using a vacuum laminator, a method using an air dispenser, a method using a jet dispenser, a screen printing method, a vacuum printing method, an electrostatic coating method, an inkjet method, a photolithography method, etc.

[0103] The thickness and size of the sealing portion 30 are not particularly limited, and the size is set appropriately depending on the size of the insulating substrate 10. Here, the thickness of the sealing portion 30 is preferably set to, for example, 5 μm or more and 50 μm or less, and the size is preferably such that, for example, the entire first main surface 10a of the insulating substrate 10 is covered.

[0104] The thickness of the sealing portion 30 described above is measured, for example, by observing a cross section perpendicular to the extending direction of the first main surface 10a of the insulating substrate 10 using an optical microscope.

[0105] Specifically, when the capacitor 1A is viewed from above, the longitudinal direction of the capacitor 1A is Lx, the lateral direction is Ly, and the thickness direction of the capacitor 1A (i.e., the normal direction of the first main surface 10a) is Lz, first, the capacitor 1A is polished so that the Lx-Lz cross section of the capacitor 1A at the center in the Ly direction is exposed. The polishing is performed so that the exposed cross section is located within an error range of ±100 μm in the Ly direction with the center position as a reference.

[0106] Next, a portion of the exposed cross section near the outer surface 30a is observed using an optical microscope at a magnification of 1000. The observation range of the cross section in the Lx direction is a range of ±50 μm from the center position of the cross section in the Lx direction, and is a range in which neither the supporting conductors 15 nor the columnar conductors 19 are provided.

[0107] Next, in the observation range of the cross section, the thickness of the sealing portion 30 in the Lz direction is measured at 10 points equally spaced in the Lx direction, and the average value is calculated. The average value calculated in this manner is the thickness of the sealing portion 30. Here, in FIG. 7, three of the thicknesses of the sealing portion 30 in the Lz direction measured at these 10 points are illustrated as line segment lengths e1, e2, and e3.

[0108] By virtue of the above-described configuration, in the capacitor 1A of this embodiment, the capacitance forming portion 20 consisting of the metal porous body 21, the dielectric film 22 and the conductive film 23 is sealed by the insulating substrate 10 and the sealing portion 30, and the electrical extraction of the capacitance forming portion 20 is realized by a pair of external connection wiring.

[0109] Fig. 8 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment. Figs. 9 to 23 are schematic cross-sectional views for explaining each step of the manufacturing flow shown in Fig. 8. Next, an example of a specific manufacturing method for manufacturing the capacitor 1A according to this embodiment described above will be described with reference to Figs. 8 to 23.

[0110] The manufacturing method of capacitor 1A described below is a method in which an assembly of in-process capacitors is produced by performing processing all at once up to a mid-point of the manufacturing process, the assembly is then cut into individual pieces, and the individual pieces are further processed to mass-produce multiple capacitors 1A simultaneously.

[0111] First, as shown in Fig. 8, in step S1, a green sheet is produced. Specifically, Al2O3 powder and glass powder are weighed, and the Al2O3 powder and glass powder are mixed with an organic solvent such as toluene or ethanol, and a binder such as polyvinyl butyral. The mixture is then formed into a sheet, thereby producing a green sheet that is the base of an insulating substrate. After the green sheet is produced, it is cut to prepare multiple green sheets.

[0112] Next, in step S2, a first through hole and a second through hole are formed in some of the green sheets as shown in Fig. 8. Specifically, a first through hole to be filled later with a first via conductor that is a part of an anode is provided at a predetermined position of the green sheet, and a second through hole to be filled later with a second via conductor that is a part of a cathode is provided.

[0113] Here, the method of forming the first through hole and the second through hole is not particularly limited, but for example, the first through hole and the second through hole can be formed by irradiating the green sheet with a laser beam. In addition, the first through hole and the second through hole may be formed by processing using a mechanical puncher or sandblasting.

[0114] Next, as shown in Fig. 8, in step S3, a first via conductor is formed in the green sheet in which the first through hole and the second through hole are formed. Specifically, a conductive paste is applied to the green sheet so as to fill the first through hole. At this time, the second through hole is prevented from being filled with the conductive paste.

[0115] Here, the method for applying the conductive paste is not particularly limited, but for example, a screen printing method can be used.

[0116] Next, as shown in Fig. 8, in step S4, the green sheet is fired. Specifically, a green sheet not provided with the first through hole and the second through hole is superimposed on the green sheet after the conductive paste is applied in step S3, and these superimposed green sheets are pressed together. Then, the laminate of the pressed green sheets is degreased, and then the laminate of the degreased green sheets is fired.

[0117] Here, when stacking the green sheets, a green sheet not provided with the first through hole and the second through hole is stacked on the other main surface opposite to the one main surface of the green sheet coated with the conductive paste. In addition, when pressing the green sheets, for example, a uniaxial press machine can be used. Furthermore, the green sheets are fired, for example, in the air at a temperature condition of 700°C to 1000°C.

[0118] By going through steps S1 to S4 described above, an insulating substrate as shown in Fig. 9 is obtained. Here, the insulating substrate is a so-called multi-substrate in which insulating substrates which will ultimately be included in each of a plurality of capacitors are connected in a matrix form, but in Fig. 9, attention is focused on only one of them, insulating substrate 10, and its surrounding area is omitted and shown by dashed lines.

[0119] In addition, in the above, an example was given of the case where the first through hole and the second through hole are formed in step S2, and then the first via conductor is provided in step S3, but it is also possible to form only the first through hole first, and then form the second through hole after the first via conductor is formed.

[0120] In the above, the case where the green sheet and the conductive paste are fired at the same time has been described as an example, but the first via conductor and the second through hole may be provided after firing an insulating substrate without through holes, etc. In that case, the first through hole and the second through hole may be provided in the fired insulating substrate by, for example, a sandblasting method, a wet etching method, a dry etching method, etc., and then the conductive paste may be applied and fired. In addition, the first via conductor may be formed by sputtering, vapor deposition, plating, etc.

[0121] Next, as shown in Fig. 8, in step S5, a conductive paste layer is applied to form the porous metal body 21. More specifically, as shown in Fig. 10, a conductive paste layer 21p is applied onto the first main surface 10a of the insulating substrate 10 to form the porous metal body 21, which will be described later.

[0122] Here, prior to application of the conductive paste for forming the metal porous body 21, it is preferable that a blocking portion for blocking the second through hole 12 is provided in the insulating substrate 10 by applying an epoxy resin or the like (not shown) to the second through hole 12. This is to prevent the conductive paste from penetrating into the inside of the second through hole 12.

[0123] Next, conductive metal particles 21a and binder 21b made of an organic solvent such as terpineol and ethyl cellulose varnish are weighed and mixed, and a rolling machine is used to prepare a conductive paste from the mixture. The conductive paste thus prepared is applied to the first main surface 10a of the insulating substrate 10 so as to have a pattern shape that is rectangular in plan view as a whole, and is then dried. In this embodiment, a conductive paste containing metal particles 21a made of Ni is used.

[0124] At this time, the conductive paste is applied in multiple layers on the insulating substrate 10 to form a layer having a predetermined thickness. Each of the conductive pastes applied on the insulating substrate 10 undergoes a firing process described below to become the above-mentioned metal porous body 21. In the following description, the layer of conductive paste formed in this manner and consisting of the metal particles 21a and the binder 21b is referred to as the conductive paste layer 21p.

[0125] Next, in step S6, a resin paste layer is applied as shown in Fig. 8. More specifically, as shown in Fig. 11, a resin paste layer 21c is further applied onto the conductive paste layer 21p formed into a sheet shape on the first main surface 10a of the insulating substrate 10 so as to have a rectangular shape as a whole in a plan view, and then dried.

[0126] The resin paste layer 21c separates the conductive paste layers 21p from each other and disappears in a firing process, which will be described later, and is made of, for example, an acrylic resin, polyvinyl butyral (PVB), etc. In the present embodiment, the resin paste layer 21c made of an acrylic resin is used.

[0127] Next, in step S7, conductive paste layers and resin paste layers are further laminated as shown in Fig. 8. More specifically, as shown in Fig. 12, conductive paste layers 21p and resin paste layers 21c are further laminated on the conductive paste layers 21p and resin paste layers 21c already applied on the insulating substrate 10 so as to be alternately arranged in the normal direction of the first main surface 10a. As a result, a laminate made up of a plurality of conductive paste layers 21p and resin paste layers 21c is formed on the insulating substrate 10.

[0128] Here, in the present embodiment, the above-mentioned laminate is composed of a total of three conductive paste layers 21p and a total of two resin paste layers 21c, but the numbers of these conductive paste layers 21p and resin paste layers 21c are not particularly limited and are set appropriately according to the desired capacity.

[0129] In addition, in this embodiment, the layer located furthest from the first main surface 10a of the insulating substrate 10 is configured to be the conductive paste layer 21p, but the resin paste layer 21c may be configured to be the layer located furthest from the first main surface 10a of the insulating substrate 10.

[0130] Next, in step S8, support conductor holes are formed as shown in Fig. 8. More specifically, as shown in Fig. 13, a plurality of support conductor holes 15h are formed penetrating the laminate in a portion of the laminate overlapping with the first via conductor 13 when viewed along the normal direction of the first main surface 10a. The plurality of support conductor holes 15h will be filled with support conductors in a support conductor forming step described later. In this embodiment, the cross section of each of the plurality of support conductor holes 15h is configured to be larger than the cross section of each of the first via conductors 13.

[0131] Here, the method for forming the holes 15h for the supporting conductors is not particularly limited, but for example, the holes 15h for the supporting conductors can be formed by irradiating the laminate with a laser beam. Alternatively, the holes 15h for the supporting conductors can be formed by processing using a mechanical puncher or sandblasting.

[0132] Next, as shown in Fig. 8, in step S9, a support conductor is formed. More specifically, as shown in Fig. 14, a conductive paste is filled into the support conductor holes 15h so as to fill the support conductor holes 15h. The support conductors 15 thus formed protrude from the first main surface 10a toward the laminate and are surrounded by the laminate. Each of the support conductors 15 thus formed is connected to each of the first via conductors 13.

[0133] In the present embodiment, Ni paste is used as the conductive paste filled in the support conductor holes 15h. In this configuration, it is possible to form the support conductors 15 containing the same material as the material contained in the metal particles 21a (i.e., the material contained in the porous metal body 21), and thus the support conductors 15 and the porous metal body 21 are firmly metal-bonded to each other through a firing process described later.

[0134] Here, the method of applying the conductive paste to be filled in the supporting conductor holes 15h is not particularly limited, but for example, a screen printing method can be used.

[0135] Next, as shown in Fig. 8, in step S10, a columnar conductor hole is formed. More specifically, as shown in Fig. 15, a plurality of columnar conductor holes 19h are formed in a portion of the laminate overlapping with the second through hole 12 when viewed along the normal direction of the first main surface 10a, so as to penetrate the laminate and reach the second through hole 12. The plurality of columnar conductor holes 19h will be filled with a columnar conductor in a columnar conductor forming step described later. In this embodiment, the cross section of each of the plurality of columnar conductor holes 19h is configured to be larger than the cross section of each of the second through holes 12.

[0136] Here, the method for forming the columnar conductor holes 19h is not particularly limited, but for example, the columnar conductor holes 19h can be formed by irradiating the laminate with laser light. Alternatively, the columnar conductor holes 19h may be formed by processing using a mechanical puncher or sandblasting.

[0137] Next, in step S11, the laminate and the supporting conductor are fired as shown in Fig. 8. More specifically, as shown in Fig. 16, the laminate and the supporting conductor 15 are fired, whereby adjacent metal particles 21a contained in the conductive paste layer 21p are sintered to be metallically bonded, and the metal particles 21a are bonded to the supporting conductor 15 adjacent to the metal particles 21a. Furthermore, the resin paste layer 21c contained in the laminate disappears due to the heat generated during the firing, thereby forming a plurality of metal porous bodies 21 stacked at a distance from each other in the normal direction of the first main surface 10a.

[0138] During the above-mentioned baking, the blocking portion made of epoxy resin or the like that blocks the second through hole 12 is also burned away by the heat.

[0139] Prior to the above-mentioned firing, insulating substrate 10 is degreased, and then the laminate and supporting conductor 15 are fired at a temperature of 400°C to 900°C in a reducing atmosphere containing, for example, a mixture of nitrogen and hydrogen.

[0140] The firing atmosphere is preferably a reducing atmosphere as described above, but may be set to an atmosphere having an equilibrium oxygen partial pressure or lower of the metal selected as the main component of the metal particles 21a.

[0141] Here, as described above, the supporting conductor 15 is configured to contain Ni, which is the same material as that contained in the metal particles 21a in the conductive paste layer 21p. In this configuration, the metal particles 21a and the supporting conductor 15 are sintered by the above-mentioned firing to form a metallic bond, and this improves the mechanical strength of the bonded portion between the metal particles 21a and the supporting conductor 15.

[0142] Furthermore, if all or most of the capacitance forming portion 20 were directly bonded to the insulating substrate 10, unacceptable warping would occur in the insulating substrate 10 due to the thermal load during the firing process described above. In this embodiment, however, in order to suppress such warping, the above-mentioned supporting conductor 15 is provided, as will be described later.

[0143] Next, in step S12, a dielectric film is formed as shown in Fig. 8. More specifically, as shown in Fig. 17, a dielectric film 22 is formed so as to cover the first main surface 10a, the surfaces of the porous metal body 21, and the supporting conductor 15, and to cover the surface of the insulating substrate 10 in a portion that defines the second through hole 12 provided in the insulating substrate 10.

[0144] Here, the method for forming the dielectric film 22 is not particularly limited as described above, but the ALD method is preferably used. By using the ALD method, the raw material of the dielectric film 22 can be supplied as a gas, which makes it possible to select the material and adjust the film thickness at the atomic layer level. Therefore, even if the fine holes provided inside the metal porous body 21 are extremely small, a homogeneous and dense dielectric film 22 can be formed. In addition, by using the ALD method, it becomes possible to easily cover with the dielectric film 22 the surface of the insulating substrate 10 in the portion that defines the second through hole 12 provided in the insulating substrate 10.

[0145] When the dielectric film 22 is formed by using this ALD method, it is preferable to use a raw material gas that has a high vapor pressure and is easy to gasify, as well as high thermal stability and high reactivity, so that the raw material gas can reach the fine holes provided inside the metal porous body 21 and the inside of the second through-hole 12 provided in the insulating substrate 10. From this viewpoint, for example, AlO x When forming a film, it is preferable to use TMA (trimethylaluminum) as a raw material, and SiO x When forming a film, it is preferable to use TDMAS (trisdimethylaminosilane) as a raw material. In this embodiment, the dielectric film 22 is formed by using the ALD method.

[0146] Furthermore, the formation of the dielectric film 22 is performed, for example, under temperature conditions of 150° C. to 400° C., although this varies depending on the film formation method and film formation material. If all or most of the capacitance forming portion 20 were directly bonded to the insulating substrate 10, the thermal load generated when forming the dielectric film 22 would cause the insulating substrate 10 to warp unacceptably. In this embodiment, however, the above-mentioned supporting conductor 15 is provided to suppress this warp, which will be described later.

[0147] Next, in step S13, a conductive film is formed as shown in Fig. 8. More specifically, in step S13, a conductive film 23 is formed so as to cover the dielectric film 22 formed in step S12 as shown in Fig. 18.

[0148] Here, the method for forming the conductive film 23 is not particularly limited as described above, but the ALD method is preferably used. By using the ALD method, the raw material of the conductive film 23 can be supplied as a gas, which makes it possible to select the material and adjust the film thickness at the atomic layer level. Therefore, even if the fine holes provided inside the metal porous body 21 are extremely small, a homogeneous and dense conductive film 23 can be formed. In addition, by using the ALD method, it becomes possible to easily cover the dielectric film 22 provided inside the second through hole 12 of the insulating substrate 10 with the conductive film 23.

[0149] The conductive film 23 is formed at a temperature condition of, for example, 200° C. or more and 600° C. or less, although this varies depending on the film forming method and film forming material. If all or most of the capacitance forming portion 20 is directly bonded to the insulating substrate 10, the thermal load when forming the conductive film 23 would cause the insulating substrate 10 to warp unacceptably. In this embodiment, the above-mentioned supporting conductor 15 is provided to suppress this warp, which will be described later.

[0150] By going through steps S5 to S13 described above, as shown in FIG. 18, a capacitance forming portion 20 consisting of a metal porous body 21, a dielectric film 22 and a conductive film 23 is provided facing the first main surface 10a of the insulating substrate 10, and further, the capacitance forming portion 20 is configured to include a plurality of capacitance forming portions stacked and spaced apart from each other in the normal direction of the first main surface 10a.

[0151] Next, in step S14, an internal conductor is formed as shown in Fig. 8. Specifically, as shown in Fig. 19, the internal conductor 18 is formed so as to cover the conductive film 23 that covers the outer surface of the capacitance forming portion 20 and the tip portion of the supporting conductor 15, and the internal conductor 18 is also formed so as to cover the conductive film 23 that defines the internal space of the capacitance forming portion 20 so as to fill the internal space.

[0152] More specifically, the internal conductor 18 is formed so as to fill the internal space of each of the multiple capacitance forming portions stacked and spaced apart from each other in the normal direction of the first main surface 10a, and is also formed so as to fill the space provided between the layers of the multiple capacitance forming portions (i.e., the space provided between the first capacitance forming portion 20a and the second capacitance forming portion 20b, and the space provided between the second capacitance forming portion 20b and the third capacitance forming portion 20c).

[0153] Furthermore, the internal conductor 18 is formed so as to cover surfaces of the above-mentioned plurality of columnar conductor holes 19h provided in the capacitance forming portion 20. The internal conductor 18 is also formed so as to cover the conductive film 23 covering a predetermined portion on the first main surface 10a side of the insulating substrate 10, and also to cover the conductive film 23 covering the surface of the insulating substrate 10 in a portion that defines the plurality of second through holes 12 provided in the insulating substrate 10.

[0154] Here, as described above, the internal conductor 18 may be formed by, for example, the CVD method, the ALD method, the PLD method, the plating method, the bias sputtering method, the sol-gel method, the method using conductive polymer filling, or the method using supercritical fluid. In this embodiment, the internal conductor 18 made of Ag is formed by a dipping method using Ag nanopaste.

[0155] Next, second via conductors and columnar conductors are formed in step S15 as shown in Fig. 8. More specifically, a plurality of second via conductors 14 and columnar conductors 19 are formed so as to fill the second through holes 12 and columnar conductor holes 19h whose surfaces are covered with the internal conductors 18 in step S14 as shown in Fig. 20.

[0156] Here, as described above, the second via conductors 14 and the columnar conductors 19 may be formed by a thick film formation method such as electrolytic plating or a screen printing method. In the present embodiment, the second via conductors 14 and the columnar conductors 19 made of Ni are both formed by electrolytic plating.

[0157] The second via conductor 14 thus formed is joined to the internal conductor 18 covering its side surface. The plurality of columnar conductors 19 thus formed protrude from the first main surface 10a toward the capacitance forming portion 20, and are surrounded by the conductive film 23 of the capacitance forming portion 20 via the internal conductor 18, thereby being connected to the conductive film 23.

[0158] The second via conductor 14 formed as described above is joined to the columnar conductor 19 at the end of the second via conductor 14 on the capacitance forming portion 20 side. As a result, the second via conductor 14 is not only connected to the conductive film 23 via the internal conductor 18 that covers it, but also connected to the conductive film 23 via the columnar conductor 19 together with the internal conductor 18.

[0159] When the columnar conductor 19 is formed together with the second via conductor 14 by electrolytic plating, as shown in Fig. 20, a film portion 19a is simultaneously formed so as to cover not only the columnar conductor 19 but also the outer surface of the internal conductor 18. Therefore, the columnar conductor 19 and the film portion 19a are formed integrally and continuously from the same material.

[0160] Next, in step S16, a sealing portion is formed as shown in Fig. 8. More specifically, a sealing portion 30 is provided on the first main surface 10a of the insulating substrate 10 on which the capacitance forming portion 20 is provided, so as to cover the capacitance forming portion 20, as shown in Fig. 21.

[0161] The sealing portion 30 is formed, for example, by so-called compression molding. More specifically, a resin sheet is placed on the first main surface 10a of the insulating substrate 10, and in this state, a vacuum laminator is used to draw a vacuum, so that the resin sheet is adhered to the first main surface 10a of the insulating substrate 10. Then, in this state, the resin sheet is heated to 50°C to 100°C to laminate the capacitance forming portion 20, and thereafter, the resin sheet is heated to 100°C to 200°C to perform full curing, thereby forming the sealing portion 30. Note that the method of forming the sealing portion 30 is not limited to the above-mentioned compression molding, and may be performed by so-called transfer molding.

[0162] As a result, the capacitance forming portion 20 is sealed by the insulating substrate 10 and the sealing portion 30, preventing the intrusion of moisture into the capacitance forming portion 20 from the outside and ensuring moisture resistance. In addition, the capacitance forming portion 20 is covered by the sealing portion 30, and the capacitance forming portion 20 is physically protected by the sealing portion 30. Note that the curing conditions shown above are merely examples and can be changed in various ways.

[0163] Next, in step S17, the insulating substrate is ground, as shown in Fig. 8. More specifically, as shown in Fig. 22, a flat cutting is performed on the second main surface 10b side of the insulating substrate 10, which is located opposite to the side on which the capacitance forming portion 20 is provided.

[0164] Here, when grinding is performed, a grinding tape (not shown) is attached to the capacitance forming portion 20 side, and the insulating substrate 10 in the portions blocking the first via conductor 13 and the second through hole 12 is removed by plane cutting. As a result, the ends of the first via conductor 13 and the second via conductor 14 are exposed on the second main surface 10b side.

[0165] Next, in step S18, a first bump and a second bump are formed on the insulating substrate as shown in Fig. 8. More specifically, a first bump 16 and a second bump 17 are formed on the second main surface 10b of the insulating substrate 10 so as to cover the first via conductor 13 and the second via conductor 14 provided on the insulating substrate 10 as shown in Fig. 23.

[0166] The first bump 16 and the second bump 17 can be formed simultaneously by, for example, electrolytic plating. In this case, the portions other than the vicinity of the portions where the first via conductor 13 and the second via conductor 14 are exposed are covered with an ultraviolet-curable resin film as a mask (not shown), and electrolytic plating is performed in this state, whereby the first bump 16 and the second bump 17 can be formed to protrude from the second main surface 10b. After the electrolytic plating is completed, the ultraviolet-curable resin film as a mask is removed.

[0167] The method of forming the second via conductor 14, the first bump 16, and the second bump 17 described above is not limited to the method using electrolytic plating described above, but may also be a combination of a screen printing method, an inkjet method, a dispenser method, or the like using a conductive paste and firing. In this case, it is preferable that the conductive paste contains a metal or a sintering aid that can be fired at a low temperature so that firing can be performed under temperature conditions that do not affect the resin that constitutes the sealing portion 30.

[0168] Next, in step S19, the insulating substrate is divided into individual pieces, as shown in Fig. 8. More specifically, the insulating substrate 10 is divided into individual pieces of capacitors 1A that are connected to each other.

[0169] Here, when singulating, a groove is formed in at least one of the insulating substrate 10 and the sealing portion 30, and a force is applied to the insulating substrate 10 and the sealing portion 30 so as to bend the insulating substrate 10 and the sealing portion 30 from the groove, thereby breaking the insulating substrate 10 and the sealing portion 30. Note that diamond scribing, laser scribing, dicing, etc. can be used as a method for forming the groove. Alternatively, singulation may be performed by directly cutting the insulating substrate 10 and the sealing portion 30 by scribing or dicing.

[0170] Capacitor 1A according to the above-described first embodiment is manufactured through steps S1 to S19 described above.

[0171] In the above-described manufacturing method of the capacitor 1A according to the present embodiment, the case where the grinding process is performed after the sealing portion is formed has been exemplified, but the sealing portion may be formed after the grinding process. Also, the chip may be singulated immediately after the grinding process, or the chip may be singulated immediately after the grinding process.

[0172] Here, in capacitor 1A according to the present embodiment, by having the above-mentioned configuration, a low ESR is achieved.

[0173] Generally, in a capacitor, a lead-out wiring is provided to electrically connect the capacitance forming portion formed inside the capacitor to a circuit located outside the capacitor. In order to reduce the ESR of the capacitor, it is important to increase the contact area between the capacitance forming portion and the lead-out wiring, to increase the cross-sectional area of ​​the lead-out wiring perpendicular to the current flow direction, and to improve the continuity of the wiring.

[0174] In this regard, in the capacitor 1A of the present embodiment, as described above, the second external connection wiring as the lead-out wiring includes a second via conductor 14 and a columnar conductor 19 provided on the insulating substrate 10, and an internal conductor 18 sealed by the insulating substrate 10 and the sealing portion 30, and the conductive film 23 of the capacitance forming portion 20 is connected to the second via conductor 14 via the internal conductor 18, or via the columnar conductor 19 together with the internal conductor 18.

[0175] Here, the internal conductor 18 covers not only the conductive film 23 in a portion that defines the outer surface of the capacitance forming portion 20, but also the conductive film 23 in a portion that is exposed inside the capacitance forming portion 20. Therefore, the internal conductor 18 is connected to most of the conductive film 23, and this makes it possible to increase the contact area between the conductive film 23 and the internal conductor 18. The internal conductor 18 also covers each of the multiple columnar conductors 19 that protrude from the first main surface 10a toward the capacitance forming portion 20. Therefore, the contact area between the internal conductor 18 and the columnar conductor 19 can also be increased. Therefore, by configuring in this manner, the contact area can be increased at each interface formed by the conductive film 23, the internal conductor 18, and the columnar conductor 19.

[0176] In the capacitor 1A according to this embodiment, as described above, the thickness of the conductive film 23 is at most several hundred nm, whereas the thickness of the internal conductor 18 is at least twice the thickness of the conductive film 23, and the diameter of each of the plurality of columnar conductors 19 is at most several tens of μm. Therefore, with this configuration, the cross-sectional area of ​​the internal conductor 18 and the cross-sectional area of ​​the columnar conductor 19 become larger than the cross-sectional area of ​​the conductive film 23, and the continuity thereof can be ensured.

[0177] Therefore, by configuring as described above, not only can the contact area between the conductive film 23 and the second external connection wiring be increased, but the cross-sectional area perpendicular to the current flow direction of the second external connection wiring can be increased and its continuity can be improved, resulting in a low ESR.

[0178] In addition, in the capacitor 1A of this embodiment, as described above, it is preferable that the thickness of the internal conductor 18 formed in the space provided between the layers of the stacked multiple capacitance forming parts is configured to be greater than the thickness of the conductive film 23, and more preferably, the thickness of the internal conductor 18 is configured to be at least twice the thickness of the conductive film 23, more preferably, at least three times the above thickness, even more preferably, at least 10 times the above thickness, and even more preferably, at least 100 times the above thickness.

[0179] When configured in this manner, the internal conductor 18 located between the layers has a larger cross-sectional area than the internal conductor 18 located in other portions (for example, the internal conductor 18 covering the conductive film 23 that covers the surface of the insulating substrate 10 in the portion defining the second through hole 12), and the cross-sectional area of ​​the second external connection wiring can be further increased, thereby achieving a further reduction in ESR.

[0180] Furthermore, in capacitor 1A of this embodiment, as described above, the first external connection wiring as the lead-out wiring includes a first via conductor 13 and a supporting conductor 15 provided on insulating substrate 10, and metal porous body 21 of capacitance forming portion 20 is connected to first via conductor 13 via supporting conductor 15.

[0181] Here, the supporting conductor 15 is provided so as to protrude from the first main surface 10a towards the capacitance forming portion 20, and the contact area at the interface formed by the supporting conductor 15 thus provided and the porous metal body 21 is larger than the contact area at the interface formed by them when the porous metal body 21 is directly connected to the first via conductor 13. Therefore, by configuring in this manner, the contact area at the interface formed by the porous metal body 21 and the supporting conductor 15 can be increased.

[0182] Furthermore, as described above, the diameter of the supporting conductor 15 is as small as about several tens of μm. Therefore, by connecting the porous metal body 21 to the first via conductor 13 through the supporting conductor 15, the cross-sectional area of ​​the first external connection wiring can be made larger than when the porous metal body 21 is directly connected to the first via conductor 13, thereby achieving a lower ESR.

[0183] Therefore, by forming capacitor 1A according to the present embodiment, a capacitor having capacitance forming portion 20 made up of porous metal body 21, dielectric film 22, and conductive film 23 can have a low ESR.

[0184] Here, in the capacitor 1A of this embodiment, the capacitance forming portion 20 is joined to each of the multiple supporting conductors 15, but on the other hand, as described above, it is not substantially directly joined to the insulating substrate 10, or even if it is directly joined, it is only slightly joined.

[0185] In this configuration, it is possible to reduce stress caused by the difference in thermal expansion coefficient between insulating substrate 10 and capacitance forming portion 20 in the manufacturing process involving heat treatment of capacitor 1A (i.e., the firing process, the process of forming dielectric film 22, and the process of forming conductive film 23). This makes it possible to effectively prevent insulating substrate 10 from warping due to the stress, and also effectively prevents dielectric film 22 and conductive film 23 from peeling off from insulating substrate 10 caused by the warping of insulating substrate 10.

[0186] In capacitor 1A according to the present embodiment, as described above, a plurality of supporting conductors 15 protrude from first main surface 10a toward capacitance forming portion 20 and are surrounded by capacitance forming portion 20. As a result, each of the plurality of supporting conductors 15 is joined to capacitance forming portion 20.

[0187] In this configuration, a so-called anchor effect is obtained by the plurality of supporting conductors 15, and the warping that occurs in insulating substrate 10 described above can be further suppressed.

[0188] Furthermore, if all or most of the capacitance forming portion is directly bonded to the insulating substrate, stress will be generated after mounting due to the difference in thermal expansion coefficients between the insulating substrate and the capacitance forming portion due to the influence of heat applied from the outside or heat generated inside, and this stress may cause capacitor 1A to warp, resulting in damage to the joint between the insulating substrate and the metal porous body. However, by using capacitor 1A according to this embodiment, the occurrence of such problems can be effectively suppressed.

[0189] Therefore, by using capacitor 1A according to this embodiment, it is possible to improve mounting stability and reliability after mounting.

[0190] Furthermore, in capacitor 1A of this embodiment, as described above, when viewed along the normal direction of first main surface 10a of insulating substrate 10, first via conductor 13 and second via conductor 14 are both arranged within the area in which capacitance forming portion 20 is arranged (i.e., the area indicated by the dashed line in Figure 2).

[0191] In this configuration, neither the first external connection wiring nor the second external connection wiring is disposed to the side of the capacitance forming portion 20, so that it is possible to minimize the sealing portion 30 in the portion disposed to the side of the capacitance forming portion 20. As a result, not only can the capacitor 1A be made smaller than conventional capacitors, but the volume occupied by the portions of the capacitor 1A other than the capacitance forming portion 20 is reduced, so that the capacitance is increased.

[0192] In addition, in the above configuration, the first via conductor 13 and the second via conductor 14 are positioned so as to penetrate the insulating substrate 10 in the thickness direction, and therefore, the via conductors with different polarities are arranged close to each other with their current paths facing in opposite directions. Therefore, the magnetic fields generated in these via conductors by the current flow act to cancel each other out, so that the so-called ESL (equivalent series inductance) can be reduced.

[0193] Furthermore, in capacitor 1A according to the present embodiment, as described above, first via conductors 13 and second via conductors 14 are arranged in an array, and the polarity of one via conductor is different from the polarity of the via conductor adjacent thereto at the shortest distance. By configuring in this manner, the above-mentioned effect of reducing ESL can be maximized.

[0194] Furthermore, in capacitor 1A according to the present embodiment, as described above, each of a pair of external connection wirings that electrically extracts capacitance forming portion 20 is configured to include a plurality of via conductors. With this configuration, the cross-sectional area of ​​the current path can be made larger than when each of the pair of external connection wirings is configured with a single via conductor, thereby achieving a low ESR.

[0195] Furthermore, in capacitor 1A of this embodiment, as described above, at the boundary between second via conductor 14 and the base material of insulating substrate 10, the base material of insulating substrate 10 is covered with dielectric film 22, which is in turn covered with conductive film 23, and conductive film 23 is further covered by second via conductor 14.

[0196] With this configuration, the adhesion between the base material of insulating substrate 10 and second via conductor 14 is improved compared to when the base material of insulating substrate 10 and second via conductor 14 are directly bonded, and therefore the intrusion of moisture through this portion is suppressed, resulting in a capacitor with excellent moisture resistance.

[0197] In the capacitor 1A according to the present embodiment, the porous metal body 21 is made of a sintered body of metal particles, as described above. In this case, the metal particles are metallically bonded to each other, improving the mechanical strength of the capacitance forming portion 20, and the bonding area between the metal particles is also increased, thereby enabling a low ESR to be achieved. Furthermore, there is an effect that a porous metal body having open pores can be formed relatively easily.

[0198] Fig. 24 is a schematic cross-sectional view showing one embodiment of a columnar conductor in the capacitor shown in Fig. 3. In the capacitor 1A' according to this embodiment, for example, as shown in Fig. 24, one of a pair of ends of the columnar conductor 19, which is located on the opposite side to the insulating substrate 10 side as viewed from the capacitance forming portion 20, may be formed to be hollow, and the sealing portion 30 may be formed by fitting into this hollow portion. The capacitor 1A' including the columnar conductor 19 thus formed can also obtain the effects described above.

[0199] (First Modification) Fig. 25 is a schematic cross-sectional view of a capacitor according to a first modified example. Hereinafter, a capacitor 1A1 according to a first modified example based on the above-mentioned first embodiment will be described with reference to Fig. 25.

[0200] As shown in FIG. 25, capacitor 1A1 of the first modified example is different from capacitor 1A of the above-described first embodiment only in the position where supporting conductor 15 is formed.

[0201] Specifically, in the capacitor 1A1 according to the first modification, when viewed along the normal direction of the first main surface 10a of the insulating substrate 10, each of the multiple supporting conductors 15a is formed at a position that does not overlap either the first via conductor 13 or the second via conductor 14. For ease of explanation, the supporting conductors formed at a position that does not overlap either the first via conductor 13 or the second via conductor 14 are denoted by the symbol 15a to distinguish them from the supporting conductors 15 formed at a position that overlap the first via conductor 13. The number of supporting conductors 15a is not particularly limited, and is appropriately set according to the size of the insulating substrate 10 or the desired capacitance.

[0202] In the capacitor 1A1 configured in this manner, the support conductor 15a is not directly joined to the first via conductor 13. Therefore, the first via conductor 13 is electrically connected to the porous metal body 21 of the third capacitance forming portion 20c by being joined to at least a part of the end face of the first via conductor 13 on the capacitance forming portion 20 side. Moreover, the porous metal bodies 21 of the multiple stacked capacitance forming portions are connected to each other via the support conductor 15a which is joined to all of them.

[0203] Even in this configuration, as in the capacitor 1A according to the above-mentioned first embodiment, the second via conductor 14 is connected to the conductive film 23 of the capacitance forming portion 20 through the internal conductor 18, or through the columnar conductor 19 together with the internal conductor 18, so that the cross-sectional area of ​​the current path of the second external connection wiring can be increased. Therefore, an effect similar to that described in the above-mentioned first embodiment can be obtained, and the ESR can be reduced in the capacitor including the capacitance forming portion 20 consisting of the metal porous body 21, the dielectric film 22, and the conductive film 23.

[0204] In addition, with this configuration, the capacitance forming portion 20 is supported by the plurality of supporting conductors 15a, so that the capacitance forming portion 20 is not substantially directly joined to the insulating substrate 10, or even if it is directly joined, it is only slightly joined. Therefore, in a capacitor having the capacitance forming portion 20 composed of the metal porous body 21, the dielectric film 22, and the conductive film 23, the mounting stability and the reliability after mounting are improved.

[0205] (Second Modification) Fig. 26 is a schematic cross-sectional view of a capacitor according to a second modified example. Hereinafter, a capacitor 1A2 according to the second modified example based on the above-mentioned first embodiment will be described with reference to Fig. 26.

[0206] As shown in FIG. 26, capacitor 1A2 of the second modified example is different from capacitor 1A of the above-mentioned embodiment 1 only in the configuration of supporting conductor 15.

[0207] Specifically, in capacitor 1A2 according to the second modification, when viewed along the normal direction of first main surface 10a of insulating substrate 10, the multiple supporting conductors are composed of supporting conductors 15 formed at positions overlapping first via conductors 13 and supporting conductors 15a formed at positions not overlapping either first via conductor 13 or second via conductor 14. The number of supporting conductors 15a is not particularly limited, and is set appropriately depending on the size of insulating substrate 10 or the desired capacitance.

[0208] Even when configured in this manner, the same effect as that described in the above-mentioned embodiment 1 can be obtained, and a low ESR can be achieved in a capacitor having a capacitance forming portion 20 consisting of a metal porous body 21, a dielectric film 22, and a conductive film 23.

[0209] In addition, with this configuration, the capacitance forming portion 20 is supported by the plurality of supporting conductors 15, 15a, so that the capacitance forming portion 20 is not substantially directly joined to the insulating substrate 10, or even if it is directly joined, it is only slightly joined. Therefore, in a capacitor including the capacitance forming portion 20 made of the metal porous body 21, the dielectric film 22, and the conductive film 23, the mounting stability and the reliability after mounting are further improved.

[0210] (Third Modification) Fig. 27 is a schematic cross-sectional view of a capacitor according to a third modified example. Hereinafter, a capacitor 1A3 according to the third modified example based on the above-mentioned first embodiment will be described with reference to Fig. 27.

[0211] As shown in FIG. 27, the capacitor 1A3 of the third modified example differs in configuration from the capacitor 1A of the above-described embodiment 1 in that a moisture-resistant protective film 40 is further formed on the first main surface 10a of the insulating substrate 10, in a portion located between the capacitance forming portion 20 and the sealing portion 30.

[0212] The moisture-resistant protective film 40 can be formed, for example, before forming the sealing portion 30, by providing an inorganic insulator made of SiN, SiO2, Al2O3, HfO2, ZrO2, or the like by a CVD method, ALD method, or the like so as to cover the capacitance forming portion 20, or by providing an organic insulator having water repellency such as a fluorine-based resin or a silane coupling agent resin so as to cover the capacitance forming portion 20. Here, the moisture-resistant protective film does not necessarily need to be formed up to the inside of the capacitance forming portion 20, and it is sufficient if it is formed so as to cover only the outer surface.

[0213] When configured in this manner, not only can the effects described in the above-mentioned embodiment 1 be obtained, but the moisture-resistant protective film 40 in addition to the sealing portion 30 can also prevent moisture from entering the capacitance forming portion 20 from the outside, thereby further improving moisture resistance.

[0214] (Fourth Modification) Fig. 28 is a schematic cross-sectional view of a capacitor according to a fourth modified example. Hereinafter, a capacitor 1A4 according to the fourth modified example based on the above-mentioned first embodiment will be described with reference to Fig. 28.

[0215] As shown in FIG. 28, the capacitor 1A4 of the fourth modified example differs in configuration from the capacitor 1A of the above-described embodiment 1 only in that a lateral sealing portion 50 is further formed so as to surround the sides of the insulating substrate 10 and the capacitance forming portion 20.

[0216] The lateral sealing portion 50 can be formed by providing a sealing member made of an inorganic material such as glass or whose main material is, for example, any of Si, Al2O3, ZrO2, BN, Si3N4, AlN, MgO, Mg2SiO4, BaTiO3, SrTiO3, and CaTiO3, by an inkjet method or the like so as to cover the sides of the insulating substrate 10 and the capacitance forming portion 20.

[0217] The manufacturing method of capacitor 1A4 in which such a side sealing portion 50 is formed differs from the manufacturing method of capacitor 1A in that, after step S4 (i.e., firing the green sheet) shown in FIG. 8, step S19 (i.e., singulation) is performed, then side sealing portion 50 is formed, and then step S5 (i.e., application of a conductive paste layer onto an insulating substrate) is performed.

[0218] 8, when capacitance forming portion 20 is formed on first main surface 10a of insulating substrate 10, capacitance forming portion 20 is formed within an area surrounded by side sealing portion 50 when viewed along the normal direction of first main surface 10a. This not only provides the effects described in the first embodiment above, but also effectively prevents positional deviation of capacitance forming portion 20 when viewed along the normal direction (i.e., deviation in the up-down or left-right direction in FIG. 2), making it possible to manufacture capacitors with stable quality.

[0219] Moreover, since the side surfaces are surrounded by side sealing portions 50, not only is impact resistance increased, but also resistance to stress generated during processing of capacitor 1A4 is increased. Therefore, in capacitor 1A4, damage to dielectric film 22 and conductive film 23 in the vicinity of side sealing portions 50 is effectively prevented, thereby suppressing a decrease in the pressure resistance of capacitor 1A4.

[0220] (Embodiment 2) 29 is a schematic cross-sectional view of a capacitor according to embodiment 2. Hereinafter, a capacitor 1B according to the present embodiment will be described with reference to FIG.

[0221] Capacitor 1B of this embodiment differs in configuration from capacitor 1A of embodiment 1 described above in that both the front and back surfaces are configured as mounting surfaces for a wiring board or the like.

[0222] Specifically, in the capacitor 1B according to the present embodiment, the plurality of supporting conductors 15 constituting a part of the first external connection wiring and the plurality of columnar conductors 19 constituting a part of the second external connection wiring are both formed to penetrate the capacitance forming portion 20 and the sealing portion 30. As a result, the plurality of supporting conductors 15 and the columnar conductors 19 are configured to be exposed on the outer surface 30a of the sealing portion 30 located on the opposite side to the insulating substrate 10 side as viewed from the capacitance forming portion 20.

[0223] Furthermore, a plurality of first bumps 16 constituting a part of the first external connection wiring are provided on the outer surface 30a so as to cover end faces of a plurality of supporting conductors 15 exposed on the outer surface 30a. Similarly, a plurality of second bumps 17 constituting a part of the second external connection wiring are provided on the outer surface 30a so as to cover end faces of a plurality of columnar conductors 19 exposed on the outer surface 30a.

[0224] Fig. 30 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment, and Fig. 31 to Fig. 35 are schematic cross-sectional views for explaining each step of the manufacturing flow shown in Fig. 30. Next, an example of a specific manufacturing method for manufacturing the capacitor 1B according to this embodiment described above will be described with reference to Fig. 30 to Fig. 35.

[0225] 30, most of the method for manufacturing capacitor 1B is based on the method for manufacturing capacitor 1A. Therefore, in the following, a description of steps in the method for manufacturing capacitor 1B that are common to the method for manufacturing capacitor 1A will be omitted, and only steps that differ from the method for manufacturing capacitor 1A will be described.

[0226] As shown in FIG. 30, in step S7, the conductive paste layer 21p and the resin paste layer 21c are laminated on the insulating substrate, and at this time, as shown in FIG. 31, a portion of the laminated conductive paste layer 21p that corresponds to the supernatant portion of the binder 21b contained in the layer located farthest from the first main surface 10a is intentionally formed thick.

[0227] Furthermore, in step S9, a supporting conductor is formed as shown in Fig. 30. The supporting conductor 15 formed here is intentionally formed long in the axial direction by an amount corresponding to the above-mentioned supernatant portion which is intentionally formed thick in step S7 as shown in Fig. 32.

[0228] 30, in step S15B, a part of the film portion formed in step S15 and the conductive film covering the tip portion of the supporting conductor formed in step S13 are removed. More specifically, first, the film portion 19a located on the opposite side of the insulating substrate 10 as viewed from the capacitance forming portion 20 is selectively removed, and then, as shown in FIG 33, the conductive film 23 covering the end portion of a pair of ends of each of the plurality of supporting conductors 15 located on the opposite side of the insulating substrate 10 as viewed from the capacitance forming portion 20 is selectively removed.

[0229] The removal of such film portion 19a is performed, for example, by a so-called dipping method in which only the film portion 19a located on the opposite side of the insulating substrate 10 from the capacitance forming portion 20 is immersed in an etching solution to remove only the film portion 19a. The conductive film 23 is also removed in a similar manner by a dipping method.

[0230] In this manner, the conductive film 23 covering the tip of the supporting conductor 15 is removed, and thus when the tip of the supporting conductor 15 is ground as described below, the conductive film 23 is also ground together with the supporting conductor 15, causing a part of the conductive film 23 to be unintentionally joined to the supporting conductor 15, thereby effectively preventing a short circuit from occurring between the supporting conductor 15 and the conductive film 23.

[0231] As shown in Fig. 30, in step S16, sealing portions are formed. As shown in Fig. 34, sealing portions 30 formed here are formed so as to cover the tips of supporting conductors 15 that were intentionally formed long in step S9.

[0232] As shown in FIG. 30, in step S17, a grinding process is performed. The grinding process is performed not only on the insulating substrate 10 but also on the sealing portion, the supporting conductor, and the columnar conductor. More specifically, as shown in FIG. 35, not only the second main surface 10b side of the insulating substrate 10 located opposite to the side where the capacitance forming portion 20 is provided, but also the outer surface 30a side of the sealing portion 30, the end of the supporting conductor 15 on the outer surface 30a side, and the end of the columnar conductor 19 on the outer surface 30a side are removed by plane cutting. As a result, the end faces of the supporting conductor 15 and the columnar conductor 19 are exposed on the outer surface 30a.

[0233] In step S18 shown in FIG. 30, first bumps 16 and second bumps 17 are formed on outer surface 30a so as to cover the end faces of supporting conductors 15 and the end faces of columnar conductors 19 exposed on outer surface 30a in this manner.

[0234] Capacitor 1B according to the above-described second embodiment is manufactured through all steps S1 to S19, S15B including the steps individually described above.

[0235] Capacitor 1B of this embodiment configured as described above not only provides the effects described in embodiment 1 above, but also allows electrical extraction of capacitance forming portion 20 from either the front surface (i.e., outer surface 30a) or the back surface (i.e., second main surface 10b of insulating substrate 10), thereby providing a capacitor configured to be mountable on either the front surface or the back surface.

[0236] (Embodiment 3) Fig. 36 is a schematic cross-sectional view of a capacitor according to embodiment 3, and Fig. 37 is a flow diagram showing a method for manufacturing the capacitor according to the present embodiment. Hereinafter, a capacitor 1C according to the present embodiment will be described with reference to Figs. 36 and 37.

[0237] As shown in FIG. 36, capacitor 1C of the present embodiment differs from capacitor 1A of embodiment 1 described above only in that the capacitance forming portion is composed of a single layer.

[0238] The manufacturing method of capacitor 1C configured in this manner differs from the manufacturing method of capacitor 1A only in that it does not require the lamination step of conductive paste layer 21p and resin paste layer 21c, as shown in Fig. 37. Accordingly, as shown in Fig. 37, the manufacturing method of capacitor 1C does not perform steps S7 and S8 shown in Fig. 8 (i.e., applying a resin paste layer onto the conductive paste layer, and laminating the conductive paste layer and the resin paste layer), and in step S11C shown in Fig. 37, firing of the conductive paste layer and the supporting conductor is performed, unlike step S11 shown in Fig. 8 (i.e., firing of the laminate and the supporting conductor).

[0239] Even in this configuration, as in the capacitor 1A according to the first embodiment described above, the second via conductor 14 is connected to the conductive film 23 of the capacitance forming portion 20 via the internal conductor 18, or together with the internal conductor 18 via the columnar conductor 19, so that the cross-sectional area of ​​the current path of the second external connection wiring can be increased, and the first via conductor 13 is connected to the metal porous body 21 of the capacitance forming portion 20 via a plurality of support conductors 15, so that the cross-sectional area of ​​the current path of the first external connection wiring can be increased. Therefore, the same effect as that described in the first embodiment described above can be obtained, and the ESR can be reduced in the capacitor including the capacitance forming portion 20 consisting of the metal porous body 21, the dielectric film 22, and the conductive film 23.

[0240] When the characteristic configuration shown in capacitor 1B of embodiment 2 described above (i.e., a configuration in which both the front and back surfaces are used as mounting surfaces for a wiring board or the like) is applied to capacitor 1C of this embodiment, in addition to the effects described above, it becomes possible to electrically extract capacitance forming portion 20 from both the front surface (i.e., outer surface 30a) and the back surface (i.e., second main surface 10b of insulating substrate 10).

[0241] (Fifth Modification) Fig. 38 is a schematic cross-sectional view of a capacitor according to a fifth modified example, and Fig. 39 is a schematic cross-sectional view enlarging the vicinity of the second via conductor shown in Fig. 38. Hereinafter, a capacitor 1C1 according to a fourth modified example based on the above-mentioned third embodiment will be described with reference to Figs. 38 and 39.

[0242] As shown in Figure 38, capacitor 1C1 of the fifth modified example differs from capacitor 1C of embodiment 3 described above in that it does not include support conductor 15 and columnar conductor 19 (see Figure 36).

[0243] That is, in capacitor 1C1, the first external connection wiring is composed of a first via conductor 13 and a first bump 16, and the second external connection wiring is composed of a second via conductor 14, a second bump 17, and an internal conductor 18.

[0244] In the capacitor 1C1 configured in this manner, the first via conductor 13 is electrically connected to the metal porous body 21 of the capacitance forming portion 20 by being joined to at least a portion of its end portion on the capacitance forming portion 20 side.

[0245] In the capacitor 1C1, the side surface of the second via conductor 14 is covered by an internal conductor 18 that covers the surface of the insulating substrate 10 in a portion that defines the second through holes 12 provided in the insulating substrate 10, and the end portion of the second via conductor 14 on the first main surface 10a side is covered by the internal conductor 18 that covers the capacitance forming portion 20. As a result, the second via conductor 14 is connected to the internal conductor 18, and the above-mentioned second external connection wiring is connected to the capacitance forming portion 20 via the second via conductor 14 and the internal conductor 18.

[0246] As mentioned above, for convenience of drawing, in Figures 38 and 39, the thickness of the internal conductor 18 at the portion connected to the second via conductor 14 is approximately equal to the thickness of the conductive film 23, but in reality the thickness of the internal conductor 18 is configured to be considerably thicker than the thickness of the conductive film 23 (for example, more than three times as thick).

[0247] In this configuration, the second via conductor 14 is connected to the conductive film 23 of the capacitance forming portion 20 through the internal conductor 18, so that the cross-sectional area of ​​the current path of the second external connection wiring can be increased. Therefore, an effect similar to that described in the above-mentioned third embodiment can be obtained, and the ESR can be reduced in the capacitor including the capacitance forming portion 20 consisting of the metal porous body 21, the dielectric film 22, and the conductive film 23.

[0248] The manufacturing method of capacitor 1C1 according to this modification is different from the manufacturing method of capacitor 1C in that step S10 (i.e., formation of holes for columnar conductors) and formation of columnar conductors in step S15 shown in Fig. 37 are not performed, and the formation of second via conductors in step S15 is performed after step S17 (i.e., grinding). By forming the second via conductors in step S15 after step S17 in this manner, the second via conductors 14 can be formed from the second main surface 10b side of the insulating substrate 10.

[0249] (Other forms, etc.) The shape, configuration, size, number, material, and the like of each part shown in the above-mentioned embodiment of the present invention and its modified examples can be modified in various ways without departing from the spirit of the present invention.

[0250] Furthermore, the characteristic configurations shown in the above-mentioned embodiment of the present invention and its modified examples can naturally be combined with each other within the scope permitted in light of the spirit of the present invention.

[0251] As such, the above-mentioned embodiment and its modified examples disclosed herein are illustrative in all respects and are not restrictive. The technical scope of the present invention is defined by the claims, and includes all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0252] 1A to 1C, 1A1 to 1A4, 1C1, 1A' capacitor, 10 insulating substrate, 10a first main surface, 10b second main surface, 11 first through hole, 12 second through hole, 13 first via conductor, 14 second via conductor, 15, 15a support conductor, 15h support conductor hole, 16 first bump, 17 second bump, 18 internal conductor, 19 columnar conductor, 19a film portion, 19h columnar conductor hole, 20 capacitance forming portion, 20a first capacitance forming portion, 20b second capacitance forming portion, 20c third capacitance forming portion, 21 metal porous body, 21a metal particles, 21b binder, 21c resin paste layer, 21p conductive paste layer, 22 dielectric film, 23 conductive film, 30 sealing portion, 30a outer surface, 40 moisture-resistant protective film, 50 Lateral seal.

Claims

1. an insulating substrate having a first main surface and a second main surface located opposite to the first main surface; a capacitance generating portion provided so as to face the first main surface; a first external connection wiring and a second external connection wiring connected to the capacitance forming portion; the capacitance forming portion includes a conductive metal porous body connected to the first external connection wiring, a dielectric film covering a surface of the metal porous body, and a conductive film covering the dielectric film and connected to the second external connection wiring, the first external connection wiring has a first via conductor penetrating the insulating substrate so as to reach the second main surface from the first main surface; the second external connection wiring has a second via conductor penetrating the insulating substrate so as to reach the second main surface from the first main surface, and an internal conductor covering the conductive film so as to fill a space inside the capacitance forming portion, the conductive film and the second via conductor are connected through at least the internal conductor; the second external connection wiring has a columnar conductor protruding from the first main surface toward the capacitance forming portion and surrounded by the capacitance forming portion; The internal conductor and the second via conductor are connected to each other through at least the columnar conductor.

2. the columnar conductor extends along a normal direction of the first main surface, The capacitor described in claim 1 , wherein the columnar conductor is connected to the second via conductor by at least partially overlapping the second via conductor when viewed along a normal direction of the first main surface.

3. the capacitance forming portion includes a first capacitance forming portion and a second capacitance forming portion that are stacked and spaced apart from each other in a normal direction of the first main surface, 3. The capacitor according to claim 1, wherein the conductive film of the first capacitance forming portion and the conductive film of the second capacitance forming portion are connected by the internal conductor and the columnar conductor.

4. 4. The capacitor according to claim 3, wherein a thickness of the internal conductor at a portion located between the first capacitance forming portion and the second capacitance forming portion is greater than a thickness of the conductive film.

5. 5. The capacitor according to claim 4, wherein a thickness of the internal conductor at a portion located between the first capacitance forming portion and the second capacitance forming portion is three times or more a thickness of the conductive film.

6. a support portion is provided on the insulating substrate, the support portion protruding from the first main surface toward the capacitance forming portion and being surrounded by the capacitance forming portion to support the capacitance forming portion by being joined to the capacitance forming portion; the first external connection wiring has a support conductor that constitutes the support portion, the supporting conductor is connected to the metal porous body, The supporting conductor extends along a normal direction of the first main surface, when viewed along a normal direction of the first main surface, the supporting conductor at least partially overlaps with the first via conductor, whereby the supporting conductor is connected to the first via conductor; a sealing portion provided on the first main surface, sealing the capacitance forming portion and defining an outer surface located on an opposite side to the insulating substrate side as viewed from the capacitance forming portion; the supporting conductor penetrates the capacitance forming portion and the sealing portion, thereby exposing the supporting conductor at the outer surface; The capacitor according to claim 2 , wherein the columnar conductor penetrates the capacitance forming portion and the sealing portion, thereby exposing the columnar conductor at the outer surface.

7. a support portion is provided on the insulating substrate, the support portion protruding from the first main surface toward the capacitance forming portion and being surrounded by the capacitance forming portion to support the capacitance forming portion by being joined to the capacitance forming portion; the first external connection wiring has a support conductor that constitutes the support portion, the supporting conductor extends along a normal direction of the first main surface and is connected to the metal porous body; when viewed along a normal direction of the first main surface, the supporting conductor at least partially overlaps with the first via conductor, whereby the supporting conductor is connected to the first via conductor; the capacitance forming portion includes a first capacitance forming portion and a second capacitance forming portion that are stacked and spaced apart from each other in a normal direction of the first main surface, the metal porous body of the first capacitance forming portion and the metal porous body of the second capacitance forming portion are connected by the supporting conductor, 3. The capacitor according to claim 2, wherein the conductive film of the first capacitance forming portion and the conductive film of the second capacitance forming portion are connected by the internal conductor and the columnar conductor.

8. a sealing portion provided on the first main surface, sealing the capacitance forming portion and defining an outer surface located on an opposite side to the insulating substrate side as viewed from the capacitance forming portion; the supporting conductor penetrates the capacitance forming portion and the sealing portion, thereby exposing the supporting conductor at the outer surface; The capacitor according to claim 7 , wherein the columnar conductor penetrates the capacitance forming portion and the sealing portion, thereby exposing the columnar conductor at the outer surface.

9. an insulating substrate having a first main surface and a second main surface located opposite to the first main surface; a capacitance generating portion provided so as to face the first main surface; a first external connection wiring and a second external connection wiring connected to the capacitance forming portion; the capacitance forming portion includes a conductive metal porous body connected to the first external connection wiring, a dielectric film covering a surface of the metal porous body, and a conductive film covering the dielectric film and connected to the second external connection wiring, the first external connection wiring has a first via conductor penetrating the insulating substrate so as to reach the second main surface from the first main surface; the second external connection wiring has a second via conductor penetrating the insulating substrate so as to reach the second main surface from the first main surface, and an internal conductor covering the conductive film so as to fill a space inside the capacitance forming portion, the conductive film and the second via conductor are connected through at least the internal conductor; a support portion is provided on the insulating substrate, the support portion protruding from the first main surface toward the capacitance forming portion and being surrounded by the capacitance forming portion to support the capacitance forming portion by being joined to the capacitance forming portion; the first external connection wiring has a support conductor that constitutes the support portion, The supporting conductor is connected to the porous metal body.

10. The supporting conductor extends along a normal direction of the first main surface, The capacitor described in claim 9, wherein the support conductor is connected to the first via conductor by at least partially overlapping the first via conductor when viewed along a normal direction of the first main surface.

11. The supporting conductor extends along a normal direction of the first main surface, The capacitor according to claim 9 , wherein the supporting conductor does not overlap the first via conductor when viewed along a normal direction of the first main surface.

12. The capacitor according to claim 9 , wherein the supporting conductor contains the same material as at least a portion of the material contained in the porous metal body.

13. The capacitor according to claim 1 or 9, wherein when viewed along a normal direction of the first main surface, the first via conductor and the second via conductor are both provided within a region in which the capacitance forming portion is arranged.

14. The first via conductors are each provided in plurality, The capacitor according to claim 13 , wherein each of the second via conductors is provided in plurality.

15. the first via conductors and the second via conductors are arranged in an array when viewed along a normal direction of the first main surface, The capacitor according to claim 14 , wherein a polarity of one via conductor is different from a polarity of a via conductor adjacent thereto at the closest distance.

16. 10. The capacitor according to claim 1, wherein the internal conductor contains at least one of Ag and a conductive polymer as a main material.

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