BUS ARBITRATION CIRCUIT AND DATA TRANSFER SYSTEM INCLUDING THE SAME

Abstract

To provide a bus arbiter circuit that does not reduce a transmission speed of a bus.SOLUTION: A bus arbiter circuit comprises: a first bus terminal connected to a host bus; a second bus terminal connected to a local bus; a first output circuit whose output terminal is connected to the first bus terminal; a second output circuit whose output terminal is connected to the second bus terminal; a control circuit which includes a first input terminal, a second input terminal, a control signal output terminal and an output terminal, and in which data of the first bus terminal is input to the first input terminal, data of the second bus terminal is input to the second input terminal, and data is output from the output terminal to the input terminal of the first output circuit; and a switch circuit in which the input terminal is connected to the first bus terminal, the control terminal is connected to the control signal output terminal of the control circuit, and host bus data is output from the output terminal to the input terminal of the second output circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a bus arbitration circuit and a data transfer system equipped with the same. [Background technology]

[0002] The data transmission system is a serial data bus. 2 A system is known that transfers data between a master IC and a plurality of slave ICs via a C bus. Figure 3 shows the I 2 FIG. 1 is a block diagram showing a data transfer system conforming to the C protocol. In the data transfer system 200, a master IC 230 and a plurality of slave ICs 231 to 237 are connected by two bus lines, a serial data line 210 and a clock line 220. 2 It performs data transfer in compliance with the C protocol (see, for example, Patent Document 1). However, I 2 The data transfer system based on the C protocol was developed as an internal bus system with a simple configuration, and therefore did not assume a multi-layer system having a host bus and a local bus. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-189697 A Summary of the Invention [Problem to be solved by the invention]

[0004] A multi-layer system has a bus arbitration circuit between the host bus and the local bus. The bus arbitration circuit generally has a transmission gate, which is a bidirectional switch circuit for connecting the host bus and the local bus. However, since the transmission gate is closed during arbitration, the slave ICs connected to each local bus are directly connected to the host bus. Therefore, there is an issue that the data transmission speed of the bus decreases as the number of slave ICs in the entire system increases.

[0005] SUMMARY OF THE PRESENT INVETION The present invention has been made in consideration of the above problems, and has an object to provide a bus arbitration circuit that does not reduce the bus transmission speed. [Means for solving the problem]

[0006] The bus arbitration circuit of the present invention is characterized in that it comprises a first bus terminal connected to a host bus, a second bus terminal connected to a local bus, a first output circuit having an output terminal connected to the first bus terminal, a second output circuit having an output terminal connected to the second bus terminal, a first input terminal, a second input terminal, a control signal output terminal and an output terminal, a control circuit to which data of the first bus terminal is input to the first input terminal and data of the second bus terminal is input to the second input terminal and data is output from the output terminal to an input terminal of the first output circuit, and a switch circuit having an input terminal connected to the first bus terminal, a control terminal connected to the control signal output terminal of the control circuit, and outputting host bus data from the output terminal to the input terminal of the second output circuit. Effect of the Invention

[0007] According to the present invention, a switch circuit and an output circuit are used for output from the host bus to the local bus, and an output circuit is used for output from the local bus to the host bus. Therefore, a slave IC of the local bus is not directly connected to the host bus, and it is possible to provide a bus arbitration circuit in which the data transmission speed does not decrease. [Brief description of the drawings]

[0008] [Figure 1] 1 is a circuit diagram showing a bus arbitration circuit according to an embodiment of the present invention; [Diagram 2] 1 is a block diagram showing a multi-layer data transfer system including a bus arbitration circuit according to an embodiment of the present invention; [Diagram 3] FIG. 1 is a block diagram showing a data transfer system conforming to the I2C protocol. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0010] FIG. 2 is a block diagram showing a multi-layer data transfer system 100 including a bus arbitration circuit according to the present embodiment. The data transfer system 100 includes a serial data line 10 and a clock line 20 which are a host bus, a serial data line 11 and a clock line 21 which are a first local bus, a serial data line 12 and a clock line 22 which are a second local bus, a master IC 30, hub ICs 41 to 42 which are bus arbitration circuits, and slave ICs 51 to 56. These bus lines are connected to the power supply line by pull-up resistors, but in the figure, pull-up resistors are only shown for the serial data line 10 and the clock line 20, and the others are omitted.

[0011] The master IC 30 is connected to the host bus. The slave ICs 51 and 52 are connected to the host bus. The hub IC 41 is connected between the host bus and a first local bus. The hub IC 42 is connected between the host bus and a second local bus. The slave ICs 53 and 54 are connected to the first local bus. The slave ICs 55 and 56 are connected to the second local bus.

[0012] FIG. 1 is a circuit diagram showing a bus arbitration circuit according to the present embodiment. The following describes the hub IC41, which is a bus arbitration circuit. For simplicity, only serial data lines are shown for the host bus and local bus. The clock lines are connected in the same way as the serial data lines. Hub IC42 has the same configuration as hub IC41.

[0013] The hub IC 41 includes a first bus terminal to which the serial data line 10 connected to the power supply line via a pull-up resistor is connected, a second bus terminal to which the serial data line 11 connected to the power supply line via a pull-up resistor is connected, an NMOS transistor 411 which is a first output circuit connected to the first bus terminal, an NMOS transistor 412 which is a second output circuit connected to the second bus terminal, a control circuit 413, a switch circuit 414, a flip-flop circuit 415, and a multiplexer 416. In this embodiment, the switch circuit 414 is configured with a NOR circuit. The control circuit 413 includes an output terminal, a first input terminal, a second input terminal, a clock output terminal, a first control signal output terminal, a second control signal output terminal, and a data output terminal. The serial data line 10 and the serial data line 11 are connected to the same power supply line, but may be connected to different power supply lines.

[0014] The NMOS transistor 411 has a drain connected to a first bus terminal, a gate connected to an output terminal of the control circuit 413, and a source connected to a ground terminal. The NMOS transistor 412 has a drain connected to a second bus terminal, a gate connected to an output terminal of the multiplexer 416, and a source connected to a ground terminal. The control circuit 413 has a first input terminal connected to a first bus terminal, a second input terminal connected to an output terminal of the flip-flop circuit 415, a clock output terminal connected to a clock terminal of the flip-flop circuit 415, a first control signal output terminal connected to a control terminal of the switch circuit 414, a second control signal output terminal connected to a control terminal of the multiplexer 416, and a data output terminal connected to a first input terminal of the multiplexer 416. The switch circuit 414 has an input terminal connected to the first bus terminal, and an output terminal connected to a second input terminal of the multiplexer 416. The flip-flop circuit 415 has an input terminal connected to the second bus terminal via a NOT circuit. Since the output circuit is constructed of NMOS transistors, a NOT circuit is provided at the second bus terminal for the purpose of matching the logic, but the logic may be matched anywhere, such as in the control circuit.

[0015] The hub IC 41 of this embodiment configures an open drain output circuit for the serial data lines 10 and 11. The other hub ICs and slave ICs also configure similar output circuits. This configuration is necessary during arbitration, and is configured to be a CMOS output circuit during times other than arbitration, but is omitted in the figure. The multiplexer 416 is controlled to output a signal from the switch circuit 414 to the NMOS transistor 412 during arbitration, and to output a signal from the data output terminal of the control circuit 413 otherwise. Therefore, in the following explanation of arbitration, the multiplexer 416 will be explained as being controlled to output a signal from the switch circuit 414 to the NMOS transistor 412.

[0016] The master IC 30 outputs a start condition signal to inquire of each IC whether there is a request to the serial data line 10. When the start condition signal is input, the slave ICs 51 to 52 output their own address signals in sync with the clock signal if there is a request.

[0017] When a start condition signal is input, the hub ICs 41-42 output the start condition signal to each local bus. Then, the hub ICs 41-42 output the address signal of each local bus, and output an address signal that combines the address signal of the hub ICs with their own address signal if there is a request, to the host bus. At that time, the hub ICs have a function of controlling the connection between the host bus and each local bus so that the arbitration is performed stably.

[0018] When the start condition signal is input, the slave ICs 53 to 56 output their own address signals in sync with the clock signal if there is a request.

[0019] Next, the arbitration operation of the multi-layer data transfer system equipped with the bus arbitration circuit of this embodiment will be described with reference to Figures 1 and 2. The operation will be described for the hub IC 41, but it is assumed that the hub IC 42 also operates in the same way.

[0020] The master IC 30 outputs a start condition signal to the serial data line 10 to inquire of each IC whether or not there is a request. The start condition signal is input to the hub ICs 41-42 and the slave ICs 51-52 connected to the host bus. The start condition signal occurs, for example, when the serial data line 10 falls from Hi level to Lo level while the clock signal is maintained at Hi level.

[0021] A start condition signal is input to the hub IC 41 from the first bus terminal. The start condition signal is input to a first input terminal of the control circuit 413 and an input terminal of the switch circuit 414. In the standby state, the switch circuit 414 is controlled to a closed state by a control signal from the control circuit 413. In Fig. 1, since the switch circuit 414 is configured with a NOR circuit, the control circuit 413 outputs a Lo level to the control signal output terminal. Therefore, the start condition signal input to the first bus terminal from the serial data line 10 is output from the second bus terminal to the serial data line 11 via the switch circuit 414 and the NMOS transistor 412.

[0022] That is, the start condition signal output by the master IC 30 is also input to the slave ICs 53 to 54 connected to the serial data line 11, which is the local bus. Therefore, the slave ICs 51 to 56 can determine that they have received an inquiry about the presence or absence of a request by receiving the start condition signal output by the master IC 30.

[0023] Next, when the clock signal falls, the hub IC and slave IC that have a request output their own address data to the serial data line in response to the input clock signal. At this time, the hub IC combines the address data of the local bus with its own address data and outputs the result to the host bus.

[0024] The operation of the hub IC 41 at this time will now be described in detail.

[0025] The control circuit 413 outputs a Hi level to the first control signal output terminal in synchronization with the falling edge of the clock signal to control the switch circuit 414 to an open state. By controlling the switch circuit 414 to an open state, the address data on the serial data line 10 is not transmitted to the serial data line 11. By controlling in this way, arbitration can be performed only within the serial data line 11, i.e., the local bus.

[0026] The control circuit 413 outputs a clock signal to the clock output terminal after a first predetermined time has elapsed since the falling edge of the clock signal. Here, the first predetermined time is the time until the address data of the serial data line 11 becomes stable. When the clock signal is input to the clock terminal, the flip-flop circuit 415 latches a signal corresponding to the arbitration result of the local bus and outputs it to the output terminal. When the arbitration result of the local bus is input from the flip-flop circuit 415 to the second input terminal of the control circuit 413, if there is a request from the hub IC 41, the control circuit 413 combines it with its own address data and outputs the address data to the gate of the NMOS transistor 411.

[0027] Therefore, since the address data on the serial data line 11 is transmitted to the serial data line 10, arbitration is performed on the host bus by the address data of all the hub ICs and slave ICs connected to the host bus and the local bus.

[0028] After a second predetermined time has elapsed since the falling edge of the clock signal, the control circuit 413 outputs a Lo level to the control signal output terminal to control the switch circuit 414 to the closed state. When the switch circuit 414 is in the closed state, the address data on the serial data line 10 is transmitted to the serial data line 11, that is, the arbitration results by all the hub ICs and slave ICs are transmitted to the slave ICs 53 and 54. Here, the second predetermined time is the time until the flip-flop circuit 415 finishes latching the signal corresponding to the arbitration result of the local bus.

[0029] Arbitration based on address data will be explained assuming that the hub IC or slave IC with the smallest address data has priority for requests. In other words, a hub IC or slave IC whose current address data is 0 (Lo level) can output address data at the falling edge of the next clock signal. A hub IC or slave IC whose current address data is 1 (Hi level) cannot output address data at the falling edge of the next or subsequent clock signals if the serial data line is Lo level. In other words, those ICs will not participate in arbitration from then on.

[0030] The master IC 30 then outputs a clock signal equal to the number of bits of the address data and repeats the above-mentioned operations, thereby performing arbitration on the serial data line 10. The master IC 30 then accepts a request from the IC determined by arbitration.

[0031] As described above, the bus arbitration circuit of this embodiment uses a switch circuit and an output circuit for output from the host bus to the local bus, and an output circuit for output from the local bus to the host bus, so that the slave ICs of the local bus are not directly connected to the host bus. Therefore, even if the number of slave ICs connected to the local bus increases, the data transmission speed will not decrease.

[0032] Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention.

[0033] For example, the flip-flop circuit 415 is provided between the second input terminal of the control circuit 413 and the second bus terminal, but is not limited to this, and may be any circuit that latches a signal. Also, if the control circuit 413 is configured to control so that the data at the second input terminal is enabled after a first predetermined time, the flip-flop circuit 415 may not be provided. Also, for example, the switch circuit 414 is configured with a NOR circuit, but is not limited to this, as long as it is configured according to input logic and output logic. Also, for example, the arbitration has been described as being started by the master IC transmitting a start condition signal, but it may be a signal output by a hub IC or a slave IC, or another signal. [Explanation of symbols]

[0034] 10, 11, 12 Serial Data Lines 20, 21, 22 Clock lines 30 Master IC 41, 42 Hub IC 51, 52, 53, 54, 55, 56 Slave IC 100 Data Transfer System 411, 412 NMOS transistors 413 Control circuit 414 Switch Circuit 415 Flip-flop circuit 416 Multiplexer

Claims

1. a first bus terminal connected to a host bus; a second bus terminal connected to the local bus; a first output circuit having an output terminal connected to the first bus terminal; a second output circuit having an output terminal connected to the second bus terminal; a control circuit including a first input terminal, a second input terminal, a control signal output terminal, and an output terminal, wherein data of the first bus terminal is input to the first input terminal, data of the second bus terminal is input to the second input terminal, and data is output from the output terminal to an input terminal of the first output circuit; a switch circuit having an input terminal connected to the first bus terminal, a control terminal connected to a control signal output terminal of the control circuit, and outputting data of the host bus from an output terminal to an input terminal of the second output circuit; Equipped with the switch circuit outputs, in a standby state, a start condition signal input to the input terminal from the output terminal; a control circuit that, when the start condition signal is input to the first input terminal in the standby state, causes the switch circuit to be in a state not to output data of the host bus after a predetermined time has elapsed, using a control signal.

2. a flip-flop circuit is provided between the second input terminal of the control circuit and the second bus terminal; the flip-flop circuit has an input terminal to which data from the second bus terminal is input, a clock terminal to which a clock signal from the control circuit is input, and an output terminal connected to the second input terminal of the control circuit; 2. The bus arbitration circuit according to claim 1.

3. The first output circuit and the second output circuit are configured with NMOS transistors.

3. The bus arbitration circuit according to claim 1, wherein:

4. A master IC and a slave IC connected to a host bus; A bus arbitration circuit according to any one of claims 1 to 3, which is connected to the host bus; a local bus connected to the bus arbitration circuit; a slave IC connected to the local bus; A data transfer system comprising:

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