Semiconductor Device

Abstract

To provide a semiconductor device that can be easily miniaturized in a configuration with an electric fuse element.SOLUTION: An interlayer insulating layer I1 covers the electric fuse element EH. A resistive layer RL made of silicon metal is placed on the interlayer insulating layer I1, directly above the electric fuse element EH.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and can be suitably used, for example, in a semiconductor device having an electrical fuse. [Background technology]

[0002] Electric fuses that are melted by an electric current are known. A technique for making such electric fuses easier to cut is disclosed in, for example, Japanese Patent Laid-Open Publication No. 2011-124370 (Patent Document 1).

[0003] In Patent Document 1, the electrical fuse is composed of a first wire. A second wire and a third wire are arranged on both sides of a blown portion of the electrical fuse. An air gap is provided between the blown portion and the second wire, and between the blown portion and the third wire.

[0004] The air gap provided on the side of the blown part functions as a heat blocking area when the electrical fuse is blown, which reduces heat dissipation from the blown part and effectively heats the blown part, making it easier to blow the electrical fuse. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2011-124370 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in Patent Document 1, it is necessary to arrange the second wiring and the third wiring on both sides of the electrical fuse with an air gap therebetween. This increases the planar area occupied by the configuration that makes the electrical fuse easier to blow. This increases the planar area occupied by the circuit that includes the electrical fuse and the blow transistor for blowing the electrical fuse.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] In the semiconductor device according to one embodiment, a resistive layer made of silicon metal is disposed directly above the electrical fuse. Effect of the Invention

[0009] According to one embodiment, it is possible to realize a semiconductor device having an electrical fuse element that can be easily miniaturized. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment in a chip state. [Diagram 2] FIG. 1 is a plan view illustrating a schematic configuration of a semiconductor chip in which a redundant circuit is formed. [Diagram 3] FIG. 1 is a diagram showing a circuit configuration having an electrical fuse. [Figure 4] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 4 is a diagram showing a temperature change of an electrical fuse element when a resistor is heated. [Figure 7] 4 is a cross-sectional view showing a configuration of a modified example of the semiconductor device according to the first embodiment. FIG. [Figure 8] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 9] 11 is a plan view showing a configuration in which a plurality of resistor portions are connected in series as a semiconductor device according to a second embodiment. FIG. [Figure 10] 13 is a plan view showing a configuration in which a plurality of resistance portions are connected in parallel as a modified example of the semiconductor device according to the second embodiment. FIG. [Figure 11]FIG. 11 is a diagram showing the relationship between the temperature change of a resistor and the temperature change of an electrical fuse element in a single resistor section with a narrow width, a single resistor section with a wide width, and a configuration in which multiple resistor sections with narrow widths are connected in parallel. [Figure 12] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. [Figure 13] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a third embodiment. [Figure 14] FIG. 13 is a perspective view for explaining a configuration used in a simulation. [Figure 15] 11 is a diagram showing the relationship between the ratio of the length of the electrical fuse element to the resistor and the efficiency of heat transfer from the resistor to the electrical fuse element. FIG. [Figure 16] 11 is a cross-sectional view showing a configuration of a first modified example of the semiconductor device according to the third embodiment. FIG. [Figure 17] 11 is a cross-sectional view showing a configuration of a second modified example of the semiconductor device according to the third embodiment. FIG. [Figure 18] FIG. 11 is a plan view showing a configuration of a second modified example of the semiconductor device according to the third embodiment. [Figure 19] FIG. 11 is a cross-sectional view showing a specific configuration having an electrical fuse element and a resistive layer in a semiconductor device according to another embodiment. [Figure 20] FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to another embodiment in which the electrical fuse element is made of a metal such as copper. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and redundant descriptions will not be repeated. In the drawings, the configuration may be omitted or simplified for convenience of explanation. In addition, at least a part of each embodiment and each modified example may be combined with each other in any desired manner.

[0012] In addition, the semiconductor device in the embodiments described below is not limited to a semiconductor chip, but may be a semiconductor wafer before being divided into semiconductor chips, or may be a semiconductor package in which a semiconductor chip is sealed with resin. In addition, in this specification, a plan view means a viewpoint seen from a direction perpendicular to the surface of a semiconductor substrate.

[0013] (Embodiment 1) <Configuration of Semiconductor Device in Chip State> First, the configuration of the semiconductor device according to the first embodiment in a chip state will be described with reference to FIG.

[0014] As shown in FIG. 1, the semiconductor device SC in this embodiment is, for example, a microcomputer. The semiconductor device SC is, for example, in a chip state, and has a semiconductor substrate. Electrical elements are arranged on the surface and above the semiconductor substrate. The semiconductor device SC has, for example, a RAM (Random Access Memory) region RA, a redundant circuit region RB, a power supply circuit region RC, a CPU (Central Processing Unit) region RD, and a peripheral circuit region RE. The power supply circuit region RC has, for example, an oscillator circuit region RF. The semiconductor device SC has a plurality of pad electrodes PD. Each of the plurality of pad electrodes PD is electrically connected to an electrical element arranged in the semiconductor device SC.

[0015] An oscillator circuit is disposed in the oscillator circuit region RF. The oscillator circuit generates an output signal with a predetermined oscillation period by an oscillation operation, for example, by repeatedly charging and discharging a capacitance element. The oscillator circuit is, for example, a high-speed on-chip oscillator (HOCO) circuit, but may also be a low-speed on-chip oscillator (LOCO) circuit, or may include both a HOCO circuit and a LOCO circuit.

[0016] A spare redundant circuit unit is arranged in the redundant circuit region RB. The spare redundant circuit unit has the same function as a specific circuit unit having a predetermined function. The redundant circuit region RB is provided with an electric fuse that is blown and removed in order to replace the specific circuit unit with the redundant circuit unit.

[0017] <Configuration and Function of Redundant Circuit and Electrical Fuse> Next, the configurations and functions of the redundant circuit section and the electrical fuses will be described with reference to FIGS.

[0018] As shown in Fig. 2, a plurality of blocks (specific circuit parts) N1, N2, ..., Nm are arranged in the semiconductor device SC. Each of the plurality of blocks N1, N2, ..., Nm has the same function as each other. Each of the plurality of blocks N1, N2, ..., Nm is composed of a plurality of memory cells in the RAM area RA (Fig. 1), for example.

[0019] A blowable fuse H1, H2, ..., Hm is formed to inactivate each of the multiple blocks N1, N2, ..., Nm. A spare redundant block (redundant circuit section) RED having the same function as any of the inactivated blocks N1, N2, ..., Nm is also arranged so that it can replace the inactivated blocks. The redundant block RED is arranged in a redundant circuit area RB (FIG. 1).

[0020] The potential of the ground power supply GD is applied to the gate electrode of the MOS (Metal Oxide Semiconductor) transistor TR via the fuse HS, so that the MOS transistor TR is held in a non-conductive state, and the redundant block RED is electrically isolated within the semiconductor device SC.

[0021] Further, in order to detect defects in each of the plurality of blocks N1, N2, . . . , Nm, test pad electrodes PDa and PDb are arranged.

[0022] Next, a functional test of the semiconductor device configured as above will be described, in which a fuse is blown and removed by energizing the device.

[0023] First, an electrical signal is applied from a functional testing device (hereinafter also referred to as a tester) (not shown) through the test pad electrodes PDa and PDb. If the semiconductor device SC is normal, an expected signal corresponding to the applied electrical signal is output from the test pad electrodes PDa and PDb. At this time, the tester judges whether the semiconductor device SC is good or bad based on the correlation between the electrical signal applied to the semiconductor device SC and the electrical signal output from the tester. If any of the blocks N1, N2, ..., Nm is judged to be bad, the bad block is replaced with a redundant block RED. This allows the semiconductor device SC to fulfill the functions that it should originally achieve, which creates the possibility that the semiconductor device SC will be a good product.

[0024] The replacement of the defective block with the redundant block RED is performed as follows: When a defect in, for example, block N1 is detected by the above-mentioned functional test, fuses H1 and HS are blown and removed by energization. The blowing of fuse H1 electrically isolates the defective block N1 within the semiconductor device SC.

[0025] On the other hand, when the fuse HS is blown, the voltage of the power supply PV is applied to the gate electrode of the MOS transistor TR through the resistor RR, which causes the MOS transistor TR to become conductive, and the defective block N1 is replaced by the redundant block RED.

[0026] Next, the melting and removal of the electrical fuse element, which is melted and removed by energization, will be described with reference to FIG.

[0027] 3, the electrical fuse element EH is a fuse that is blown by passing a current through it, rather than by irradiation with a laser beam. A blower transistor CT is provided as a switching element for passing a current through the electrical fuse element EH.

[0028] One end of the electrical fuse element EH is electrically connected to a power supply voltage (Vdd). The other end of the electrical fuse element EH is electrically connected to a drain D of the fusing transistor CT. The source S of the fusing transistor CT is connected to a ground voltage (GND).

[0029] A level shifter LS is electrically connected to the gate G of the fusing transistor CT. The level shifter LS inputs a signal for turning the fusing transistor CT on and off to the gate G of the fusing transistor CT. A core part CO is electrically connected to the other end of the electrical fuse element EH and the drain of the fusing transistor CT.

[0030] If any of the blocks N1, N2, ..., Nm (Fig. 2) is determined to be defective, the level shifter LS turns on the cutoff transistor CT. This causes a current to flow through the electrical fuse element EH, which is then blown and removed. The core part CO is a determination circuit that determines the state of the electrical fuse element EH, and if it is determined to have been blown and removed, replacement is performed based on this determination result.

[0031] <Configuration of Electrical Fuse Element> Next, the configuration of the electrical fuse element included in the semiconductor device according to this embodiment will be described with reference to FIGS.

[0032] 5, a trench TRE is formed on the surface of a semiconductor substrate SB. An insulating layer BI is embedded in the trench TRE. The trench TRE and the insulating layer BI form an STI (Shallow Trench Isolation) structure.

[0033] An electrical fuse element EH is disposed on the STI structure. The electrical fuse element EH is made of, for example, polycrystalline silicon doped with impurities (hereinafter referred to as "doped polysilicon").

[0034] An interlayer insulating layer I1 is disposed on the surface of the semiconductor substrate SB so as to cover the electrical fuse element EH. The interlayer insulating layer I1 is made of, for example, a silicon oxide film. The upper surface of the interlayer insulating layer I1 is flattened.

[0035] A resistive layer RL is disposed on the upper surface of the interlayer insulating layer I1 and directly above the electrical fuse element EH. The resistive layer RL is made of silicon metal. The silicon metal is, for example, silicon chromium (SiCr) or silicon chromium doped with carbon (SiCrC).

[0036] 4, the electrical fuse element EH has a first portion P1, a second portion P2, and a third portion P3. The second portion P2 is disposed at one end of the first portion P1. The third portion P3 is disposed at the other end of the first portion P1. The first portion P1 is sandwiched between the second portion P2 and the third portion P3.

[0037] At least one of the second portion P2 and the third portion P3 has a wiring width W2, W3 larger than the wiring width W1 of the first portion P1. In this embodiment, each of the maximum wiring width W2 of the second portion P2 and the maximum wiring width W3 of the third portion P3 is larger than the wiring width W1 of the first portion P1.

[0038] The second portion P2 has a tapered portion TP2 and a pad portion PD2 in a plan view. The tapered portion TP2 is connected to the first portion P1. The pad portion PD2 is connected to the tapered portion TP2. The tapered portion TP2 is disposed between the first portion P1 and the pad portion PD2. The tapered portion TP2 is configured such that the wiring width gradually increases from the first portion P1 toward the pad portion PD2 in a plan view. The pad portion PD2 has, for example, a rectangular shape in a plan view.

[0039] The third portion P3 has a tapered portion TP3 and a pad portion PD3 in a plan view. The tapered portion TP3 is connected to the first portion P1. The pad portion PD3 is connected to the tapered portion TP3. The tapered portion TP3 is disposed between the first portion P1 and the pad portion PD3. The tapered portion TP3 is configured such that the wiring width gradually increases from the first portion P1 toward the pad portion PD3 in a plan view. The pad portion PD3 has, for example, a rectangular shape in a plan view. The tapered portions TP2 and TP3 may not be present, and the pad portions PD2 and PD3 may be directly connected to the first portion P1.

[0040] The pad portion PD2 is electrically connected to the wiring layer ITA through a via hole VHA and a via conductive layer VCA that fills the via hole VHA. The pad portion PD3 is electrically connected to the wiring layer ITB through a via hole VHB and a via conductive layer VCB that fills the via hole VHB. Each of the wiring layers ITA and ITB is disposed in a layer above the electrical fuse element EH. The wiring layers ITA and ITB are layers formed separately from each other from the same layer. Each of the wiring layers ITA and ITB is made of a metal, such as aluminum (Al), copper (Cu), or aluminum-copper (AlCu).

[0041] The resistive layer RL is disposed above the wiring layers ITA and ITB. The resistive layer RL is disposed so as to overlap the electrical fuse element EH in a planar view. The resistive layer RL overlaps the entire electrical fuse element EH in a planar view. The resistive layer RL may overlap only the first portion P1 without overlapping the second portion P2 and the third portion P3 in a planar view.

[0042] The wiring width W4 of the resistive layer RL is preferably larger than the wiring width W1 of the first portion P1 of the electrical fuse element EH and is also preferably larger than the wiring width W2 of the second portion P2 and the wiring width W31 of the third portion P3 of the electrical fuse element EH.

[0043] <Effects> Next, the effects of the semiconductor device according to this embodiment will be described.

[0044] The present inventors investigated how the temperature of the electrical fuse element EH changes when a current is passed through the resistive layer RL made of silicon metal to generate heat in the configuration shown in Fig. 5. In this simulation, the wiring width W4 of the resistive layer RL was set to 9.5 µm, and the wiring width W1 of the first portion P1 in the electrical fuse element EH was set to 0.18 µm. The results are shown in Fig. 6.

[0045] The horizontal axis in the graph of Fig. 6 is the amount of current passed through the resistive layer RL, and the vertical axis is the temperature increase of each of the resistive layer RL and the electrical fuse element EH. From the results of Fig. 6, it was found that the greater the amount of current passed through the resistive layer RL, the higher the temperature of the resistive layer RL. It was also found that the temperature of the electrical fuse element EH increases with the increase in temperature of the resistive layer RL.

[0046] In this embodiment, as shown in Fig. 5, the resistive layer RL is made of silicon metal. Silicon metal is a material that generates heat more easily than polycrystalline silicon. Therefore, when a current is passed through the resistive layer RL, the resistive layer RL generates heat easily. The heat generated by the resistive layer RL heats the electrical fuse element EH located directly below the resistive layer RL. The heated electrical fuse element EH is more likely to melt when a current is passed through it.

[0047] When the electrical fuse element EH is made of, for example, doped polysilicon, the electrical fuse element EH is blown by utilizing electromigration caused by energization. When the electrical fuse element EH is heated by the heat generated by the resistive layer RL, electromigration in the electrical fuse element EH is promoted, making the electrical fuse element EH more likely to be blown.

[0048] As described above, the current flowing through the electrical fuse element EH when blowing the electrical fuse element EH can be reduced, which allows the fusing transistor CT (Figure 3) to be made smaller, making it possible to realize a configuration for blowing the electrical fuse element EH with a small planar occupation area.

[0049] Generally, no wiring or the like is arranged directly above the electrical fuse element EH. This is because if the electrical fuse element EH is blown, the wiring or the like arranged directly above the electrical fuse element EH will be damaged. However, in this embodiment, the resistive layer RL is used only for heating the electrical fuse element EH. For this reason, it is sufficient for the resistive layer RL to be able to heat the electrical fuse element EH when the electrical fuse element EH is blown, and it is acceptable for the resistive layer RL to be damaged when the electrical fuse element EH is blown.

[0050] (Modification of the first embodiment) Next, a modification of the semiconductor device according to the first embodiment will be described with reference to FIG.

[0051] As shown in Fig. 7, in this modification, an interlayer insulating layer I2 is formed on an interlayer insulating layer I1 so as to cover a resistance layer RL. The interlayer insulating layer I2 is made of, for example, a silicon oxide film. A metal layer ML is disposed on the interlayer insulating layer I2, for example, directly above the resistance layer RL. The metal layer ML is made of a metal, for example, aluminum, copper, or aluminum-copper. The metal layer ML is made of a material having a higher thermal conductivity than the interlayer insulating layer I2.

[0052] Other than the above, the configuration of this modified example is almost the same as that of the first embodiment, so the same elements are given the same reference numerals and their description will not be repeated.

[0053] In this modification, a metal layer ML is disposed directly above the resistive layer RL. The metal layer ML is made of a material with a higher thermal conductivity than the interlayer insulating layer I2. Therefore, a part of the heat generated in the resistive layer RL can be dissipated upward through the metal layer ML. This prevents the temperature of the resistive layer RL from becoming higher than necessary, and prevents the resistive layer RL from melting.

[0054] (Embodiment 2) Next, the configuration of the semiconductor device according to the second embodiment will be described with reference to FIGS.

[0055] 8, in this embodiment, the resistance layer RL has a plurality of resistance parts RLa, RLb, and RLc. Each of the plurality of resistance parts RLa, RLb, and RLc is made of silicon metal, for example, silicon chrome, or silicon chrome doped with carbon. The resistance layer RL is not limited to three resistance parts RLa to RLc, and may have two or four or more resistance parts.

[0056] Each of the multiple resistance parts RLa-RLc is formed in contact with the upper surface of the interlayer insulating layer I1. The arrangement area AR of the multiple resistance parts RLa-RLc is located directly above the electrical fuse element EH. It is preferable that at least one resistance part (e.g., resistance part RLb) of the multiple resistance parts RLa-RLc is located directly above the electrical fuse element EH.

[0057] 9, an arrangement region AR of the multiple resistance portions RLa-RLc overlaps with the electrical fuse element EH in a planar view. In addition, it is preferable that at least one resistance portion (e.g., resistance portion RLb) of the multiple resistance portions RLa-RLc overlaps with the electrical fuse element EH in a planar view.

[0058] The arrangement region AR of the plurality of resistor portions RLa to RLc is a region including the plurality of resistor portions RLa to RLc and spaces between the plurality of resistor portions RLa to RLc in a plan view.

[0059] When the resistive layer RL is composed of a plurality of resistive portions RLa to RLc, arranging the resistive layer RL directly above the electrical fuse element EH means that the arrangement region AR of the plurality of resistive portions RLa to RLc is arranged directly above the electrical fuse element EH.

[0060] The resistor portions RLa to RLc may be electrically connected in series, for example in the order of resistor portion RLa, resistor portion RLb, and resistor portion RLc.

[0061] Specifically, one longitudinal end of the resistor portion RLa is electrically connected to one longitudinal end of the resistor portion RLb via the wiring layer FI1, and the other longitudinal end of the resistor portion RLb is electrically connected to one longitudinal end of the resistor portion RLc via the wiring layer FI2.

[0062] Each of the multiple resistors RLa-RLc is preferably arranged so that the current path in the resistor layer RL meanders in a plan view. Specifically, the longitudinal direction of each of the multiple resistors RLa-RLc is, for example, along the same direction and parallel to each other. In this arrangement, the longitudinal ends of adjacent resistors RLa-RLc are electrically connected to each other via the wiring layers FI1 and FI2 as described above.

[0063] If the current path of the resistance layer RL is meandering in a plan view, the longitudinal directions of the resistance portions RLa to RLc do not have to be along the same direction as each other.

[0064] In plan view, the other end in the longitudinal direction of the resistor portion RLa is electrically connected to the wiring layer SI1 via the wiring layer FI3, and in plan view, the other end in the longitudinal direction of the resistor portion RLc is electrically connected to the wiring layer SI2 via the wiring layer FI4.

[0065] Each of the wiring layers FI1 to FI4 is a layer formed separately from one another from the same conductive layer FI, and is arranged, for example, below the resistor portions RLa to RLc. Each of the wiring layers SI1 and SI2 is a layer formed separately from one another from the same conductive layer SI, and is arranged, for example, above the resistor portions RLa to RLc. Each of the wiring layers FI1 to FI4 and the wiring layers SI1 and SI2 is made of, for example, aluminum, copper, or aluminum-copper.

[0066] Each of the resistors RLa and RLb is electrically connected to the wiring layer FI1 through a via hole V1. Each of the resistors RLb and RLc is electrically connected to the wiring layer FI2 through a via hole V1.

[0067] The resistor portion RLa is electrically connected to the wiring layer FI3 through a via hole V1. The resistor portion RLc is electrically connected to the wiring layer FI4 through a via hole V1. The wiring layer FI3 is electrically connected to the wiring layer SI1 through a via hole V2. The wiring layer FI4 is electrically connected to the wiring layer SI2 through a via hole V2.

[0068] Other than the above, the configuration of this embodiment is almost the same as that of the first embodiment, so the same elements are given the same reference numerals and the description thereof will not be repeated.

[0069] According to this embodiment, the resistive layer RL is divided into a plurality of resistive portions RLa-RLc as shown in Fig. 9. This allows the wiring width of each of the resistive portions RLa-RLc to be reduced, and the fusing resistance of the resistive layer RL to be improved.

[0070] However, the wiring width of each of the resistor parts RLa-RLc is reduced, which reduces the heat generation efficiency. Therefore, the resistor parts RLa-RLc are arranged so that they run parallel to each other in the longitudinal direction in a plan view. In particular, in this embodiment, the resistor parts RLa-RLc are arranged so that the current path of the resistance layer RL meanders in a plan view. This improves the arrangement density of the resistor parts RLa-RLc in the arrangement area AR in a plan view, and can improve the heat generation efficiency.

[0071] Furthermore, the resistors RLa to RLc are electrically connected in series, which reduces the current required for heat generation.

[0072] (Modification of the second embodiment) Next, a modified example of the semiconductor device according to the second embodiment will be described with reference to FIG.

[0073] As shown in Fig. 10, the multiple resistance parts RLa to RLc may be electrically connected in parallel. In this case, the longitudinal directions of the multiple resistance parts RLa to RLc are, for example, along the same direction and parallel to each other. In this arrangement, one ends of the multiple resistance parts RLa to RLc are electrically connected to each other by a wiring layer FI11 through a via hole V1. The other ends of the multiple resistance parts RLa to RLc are electrically connected to each other by another wiring layer FI12 through the via hole V1. The wiring layer FI11 is electrically connected to a wiring layer SI11 through a via hole V2. The wiring layer FI12 is electrically connected to a wiring layer SI12 through a via hole V2.

[0074] If the plurality of resistor portions RLa to RLc are connected in parallel with each other, the longitudinal directions of the plurality of resistor portions RLa to RLc do not have to be along the same direction.

[0075] The wiring layers FI11 and FI12 are layers formed separately from each other from the same conductive layer FI, and are arranged, for example, below the resistor portions RLa-RLc. The wiring layers SI11 and SI12 are layers formed separately from each other from the same conductive layer SI, and are arranged, for example, above the resistor portions RLa-RLc. The wiring layers FI11 and FI12 and the wiring layers SI11 and SI12 are each made of, for example, aluminum, copper, or aluminum-copper.

[0076] Other than the above, the configuration of this modification is almost the same as that of the second embodiment, so the same elements are given the same reference numerals and the description thereof will not be repeated.

[0077] The inventors measured the temperature change ΔT of the resistive layer RL when a current was passed through the resistive layer RL to generate heat in each of the samples A to C. RL The temperature change ΔT of the electrical fuse element EH EHThe resistive layer RL of each of the samples A and C has a configuration consisting of only a single resistive portion as shown in Fig. 5. The resistive layer RL of the sample B has a configuration in which a plurality of resistive portions RLa to RLc are connected in parallel as shown in Fig. 10.

[0078] In sample A, the wiring width W4 of the resistive layer RL shown in Fig. 5 was set to 1.9 μm. In sample C, the wiring width W4 of the resistive layer RL shown in Fig. 5 was set to 9.5 μm. In sample B, the wiring width W5 of each of the resistive portions RLa-RLc shown in Fig. 9 was set to 1.9 μm, and the spacing W6 between each of the resistive portions RLa-RLc was set to 1.9 μm. The results of the above simulation are shown in Fig. 11.

[0079] The horizontal axis in the graph of FIG. 11 is the temperature change ΔT of the resistive layer RL. RL The vertical axis represents the temperature change ΔT of the electrical fuse element EH. EH 11, it was found that in sample A, the temperature rise of the electrical fuse element EH relative to the temperature rise of the resistive layer RL was smaller than that in sample C. This shows that sample A, which has a single narrow resistive portion, has a lower efficiency in heating the electrical fuse element EH than sample C, which has a single wide resistive portion.

[0080] On the other hand, it was found that in sample B, the temperature rise of the electrical fuse element EH in response to the temperature rise of the resistive layer RL was about the same as in sample C. From this, it was found that when the resistive layer RL is divided into a plurality of resistive parts RLa-RLc and connected in parallel as in sample B, the efficiency of heating the electrical fuse element EH was about the same as in sample C even if the wiring width W5 of each of the resistive parts RLa-RLc was narrow.

[0081] As described above, according to this modified example, by dividing the resistive layer RL into multiple resistive sections RLa to RLc and connecting them in parallel, even if the wiring width W5 of each of the resistive sections RLa to RLc is narrow, the heating efficiency of the electrical fuse element EH can be made as high as when a wide resistive layer RL is used.

[0082] Furthermore, according to this modification, since the wiring width W5 of each of the resistance portions RLa to RLc is narrow, the meltdown resistance of the resistance layer RL itself can be improved compared to the case where the wiring width W4 is wide.

[0083] (Embodiment 3) Next, the configuration of a semiconductor device according to the third embodiment will be described with reference to FIGS.

[0084] 12, in this embodiment, a heat conductor HT is disposed between the electrical fuse element EH and the resistance layer RL. The heat conductor HT has a higher thermal conductivity than the interlayer insulating layer I1.

[0085] The heat transfer body HT has, for example, a plurality of heat transfer layers HT1, HT2, and HT3. The plurality of heat transfer layers HT1 to HT3 are stacked one on top of another. Each of the plurality of heat transfer layers HT1 to HT3 is made of, for example, aluminum, copper, or aluminum-copper.

[0086] The heat transfer layer HT1 is disposed in contact with the upper surface of the interlayer insulating layer I1a which covers the electrical fuse element EH. The heat transfer layer HT1 is covered by the interlayer insulating layer I1b. The heat transfer layer HT2 is disposed in contact with the upper surface of the interlayer insulating layer I1b. The heat transfer layer HT2 is covered by the interlayer insulating layer I1c. The heat transfer layer HT3 is disposed in contact with the upper surface of the interlayer insulating layer I1c. The heat transfer layer HT3 is covered by the interlayer insulating layer I1d. The resistance layer RL is disposed in contact with the upper surface of the interlayer insulating layer I1d.

[0087] The interlayer insulating layers I1a, I2b, I1c, and I1d constitute an interlayer insulating layer I1 disposed between the electrical fuse element EH and the resistor layer RL.

[0088] The heat transfer body HT has connection portions CT1 and CT2 that electrically connect the heat transfer layers HT1 to HT3 to one another. The connection portion CT1 has a plurality of via conductive layers CT1. The connection portion CT2 has a plurality of via conductive layers CT2.

[0089] The via conductive layers CT1 fill the via holes V3 provided in the interlayer insulating layer I1b. The via holes V3 reach the heat transfer layer HT1 from the upper surface of the interlayer insulating layer I1b. The via conductive layers CT1 electrically connect the heat transfer layer HT1 and the heat transfer layer HT2.

[0090] The via conductive layers CT2 fill the via holes V4 provided in the interlayer insulating layer I1c. The via holes V4 reach the heat transfer layer HT2 from the upper surface of the interlayer insulating layer I1c. The via conductive layers CT2 electrically connect the heat transfer layer HT2 and the heat transfer layer HT3.

[0091] Each of the via conductive layers CT1 and CT2 is made of, for example, tungsten (W), etc. Each of the via conductive layers CT1 and CT2 may have a barrier metal (for example, titanium nitride (TiN)) disposed between the tungsten and the interlayer insulating layers I1b and I1c.

[0092] The heat transfer layers HT1 to HT3 and the via conductive layers CT1 and CT2 form, for example, a multi-layer wiring structure. Each of the heat transfer layers HT1 to HT3 is a dummy wiring. The dummy wiring is a wiring that is electrically isolated from other electric elements and does not transmit electric signals.

[0093] 13, each of the heat transfer layers HT1 to HT3 included in the heat transfer body HT overlaps the entire electrical fuse element EH in a plan view. HT is the wiring length L of the resistive layer RL RL It is preferable that the wiring width W of each of the heat transfer layers HT1 to HT3 is equal to or larger than the wiring width W of each of the heat transfer layers HT1 to HT3. HT is the wiring width W of the resistive layer RL RL For example, the same as above.

[0094] The wiring length L of each of the heat transfer layers HT1 to HT3 HT and the wiring length L of the resistive layer RL RLEach of the wiring widths W of the heat transfer layers HT1 to HT3 is a dimension in a direction in which a current flows through the electric fuse element EH in a plan view. HT and the wiring width W of the resistive layer RL RL Each of the dimensions and represents a dimension in a direction perpendicular to the direction in which a current flows through the electrical fuse element EH in a plan view.

[0095] Other than the above, the configuration of this embodiment is almost the same as that of the first embodiment, so the same elements are given the same reference numerals and the description thereof will not be repeated.

[0096] As shown in FIG. 14, the present inventors have found that in a configuration in which a single-layer heat conductor HT is disposed between an electrical fuse element EH and a resistive layer RL, the wiring length L of the heat conductor HT is HT and wiring width W HT The change in the efficiency of heat transfer from the resistive layer RL to the electrical fuse element EH was investigated when the wiring length L of the resistive layer RL was changed. RL is fixed at 47.5 μm, and the wiring width W RL The results are shown in Figure 15.

[0097] The horizontal axis in the graph of FIG. 15 represents the wiring length L of the resistive layer RL. RL The wiring length L of the heat transfer body HT HT Ratio (L HT / L RL The vertical axis represents the ratio (ΔT(EH) / ΔT(RL)) of the temperature change ΔT(EH) of the electrical fuse element EH to the temperature change ΔT(RL) of the resistive layer RL, and indicates the efficiency of heat transfer from the resistive layer RL to the electrical fuse element EH.

[0098] From the results in Fig. 15, the wiring length L RL The wiring length L of the heat transfer body HT HT Ratio (L HT / L RL It was found that when the ratio (L) is 80% or more, the heat transfer efficiency (ΔT(EH) / ΔT(RL)) improves. HT / L RLThe improvement of the heat transfer efficiency (ΔT(EH) / ΔT(RL)) in the HT It was found that the larger the value, the more pronounced the effect.

[0099] Also, the wiring length L of the resistive layer RL RL and the wiring length L of the heat transfer body HT HT When the dimensions are the same, that is, the ratio (L HT / L RL It was found that the heat transfer efficiency (ΔT(EH) / ΔT(RL)) is maximized when the heat transfer efficiency (ΔT(EH) / ΔT(RL)) is 100%. Furthermore, it was found that by providing the heat transfer body HT, the heat transfer efficiency (ΔT(EH) / ΔT(RL)) is improved by about three times compared to the case without the heat transfer body HT.

[0100] As described above, in this embodiment, since the heat transfer body HT is disposed between the electrical fuse element EH and the resistive layer RL, the heat generated in the resistive layer RL can be efficiently transferred to the electrical fuse element EH. This makes it possible to further reduce the amount of current flowing through the electrical fuse element EH when blowing the electrical fuse element EH. This allows the fusing transistor CT to be further miniaturized.

[0101] The heat transfer body HT may be made of a single layer. For example, the heat transfer body HT may be made of only one of the heat transfer layers HT1 to HT3 in Fig. 12. This allows the structure of the heat transfer body HT to be simplified.

[0102] Furthermore, as shown in FIG. 12, since the heat transfer body HT includes multiple heat transfer layers HT1 to HT3, it is possible to efficiently transfer heat from the resistance layer RL to the electrical fuse element EH even if the distance between the electrical fuse element EH and the resistance layer RL becomes large.

[0103] Furthermore, as shown in FIG. 12, the heat transfer body HT includes connection portions CT1, CT2 that connect each of the multiple heat transfer layers HT1 to HT3 to one another, thereby making it possible to efficiently transfer heat between the multiple heat transfer layers HT1 to HT3.

[0104] 13, at least one of the heat transfer layers HT1 to HT3 overlaps with the entire resistance layer RL in a plan view and has a planar occupancy area larger than that of the resistance layer RL. Therefore, the heat generated from the resistance layer RL can be received widely by at least one of the heat transfer layers HT1 to HT3, and the received heat can be transferred to the electrical fuse element EH. Therefore, the heat can be transferred to the electrical fuse element EH more efficiently.

[0105] (Modification of the third embodiment) Next, a modification of the semiconductor device according to the third embodiment will be described with reference to FIG.

[0106] 16, the wiring width of the heat-transfer layers HT1-HT3 is smaller as the heat-transfer layer is closer to the electrical fuse element EH. Specifically, the heat-transfer layer HT2, which is located closer to the electrical fuse element EH than the heat-transfer layer HT3, has a smaller wiring width than the heat-transfer layer HT3. Also, the heat-transfer layer HT1, which is located closer to the electrical fuse element EH than the heat-transfer layer HT2, has a smaller wiring width than the heat-transfer layer HT2.

[0107] Other than the above, the configuration of this modification is substantially the same as that of the third embodiment, and therefore the same elements are given the same reference numerals and their description will not be repeated.

[0108] In this modification, the wiring width of the heat-transfer layers HT1 to HT3 is smaller as the heat-transfer layer is closer to the electrical fuse element EH, so that the heat generated from the resistance layer RL can be concentrated toward the electrical fuse element EH, thereby more efficiently heating the electrical fuse element EH.

[0109] 17 and 18, a configuration in which a heat transfer body HT is provided may be combined with a configuration in which a resistance layer RL has a plurality of resistance portions RLa-RLc as in embodiment 2. This makes it possible to obtain the effects of both embodiment 2 and embodiment 3. The plurality of resistance portions RLa-RLc in FIG. 17 and FIG. 18 may be connected in series or in parallel.

[0110] (others) Next, a specific configuration having the electrical fuse element EH and the resistive layer RL will be described with reference to FIG.

[0111] 19, this semiconductor device has an electrical fuse element EH, a heat conductor HT, a resistive layer RL, and a metal layer ML. The electrical fuse element EH is disposed on an STI structure of a semiconductor substrate SB. The electrical fuse element EH is made of, for example, doped polysilicon.

[0112] The electrical fuse element EH is covered with an interlayer insulating layer I1a. Each of the wiring layers ITA and ITB is disposed on the interlayer insulating layer I1a. The wiring layer ITA is electrically connected to the electrical fuse element EH through a via conductive layer VCA that fills a via hole VHA of the interlayer insulating layer I1a. The wiring layer ITB is electrically connected to the electrical fuse element EH through a via conductive layer VCB that fills a via hole VHB of the interlayer insulating layer I1a.

[0113] A heat transfer body HT is disposed directly above the electrical fuse element EH. The heat transfer body HT has, for example, a multi-layer wiring structure. The heat transfer body HT has a plurality of heat transfer layers HT1 to HT3 and connection parts CT1 and CT2. The heat transfer layer HT1 is formed separately from, for example, the same layer as the wiring layers ITA and ITB.

[0114] The configuration of the heat transfer body HT is almost the same as that of the heat transfer body HT shown in FIG. 12, so the same elements as those in FIG. 12 are given the same reference numerals and their description will not be repeated.

[0115] A resistive layer RL is disposed directly above the electrical fuse element EH and directly above the heat transfer body HT. The resistive layer RL is electrically connected to each of the wiring layers ITC and ITD. Specifically, the resistive layer RL is electrically connected to the wiring layer ITC through a via conductive layer VCC that fills the via hole VHC of the interlayer insulating layer I1d. The resistive layer RL is also electrically connected to the wiring layer ITD through a via conductive layer VCD that fills the via hole VHD of the interlayer insulating layer I1d. Each of the wiring layers ITC and ITD is formed, for example, separately from the same layer as the heat transfer layer HT3.

[0116] The resistive layer RL is covered with an interlayer insulating layer I2. The metal layer ML is disposed on the interlayer insulating layer I2. The metal layer ML is disposed directly above the resistive layer RL.

[0117] In the above description, the electrical fuse element EH is made of doped polysilicon, but the electrical fuse element EH may be made of a metal such as copper. In this case, the semiconductor device may have a configuration as shown in FIG.

[0118] 20, each of the multiple wiring layers IT1, IT2, IT3, and IT4 is made of, for example, copper or a copper alloy. The electrical fuse element EH is formed separately from the same layer as the wiring layer IT3, for example, and is made of copper or a copper alloy.

[0119] The wiring layer IT1 is disposed in a groove provided on the upper surface of the interlayer insulating layer IA. An interlayer insulating layer IB is disposed on the interlayer insulating layer IA. The wiring layer IT2 is disposed in a groove provided on the upper surface of the interlayer insulating layer IB. The wiring layer IT2 is electrically connected to the wiring layer IT1 through a via conductive layer that fills a via hole in the interlayer insulating layer IB.

[0120] An interlayer insulating layer IC is disposed on the interlayer insulating layer IB. The wiring layer IT3 and the electrical fuse element EH are each disposed in a groove provided on the upper surface of the interlayer insulating layer IC. The wiring layer IT3 is electrically connected to the wiring layer IT2 through a via conductive layer that fills a via hole in the interlayer insulating layer IC.

[0121] An interlayer insulating layer ID is disposed on the interlayer insulating layer IC. The wiring layer IT4 is disposed in a groove provided on the upper surface of the interlayer insulating layer ID. The wiring layer IT4 is electrically connected to the wiring layer IT3 through a via conductive layer that fills a via hole in the interlayer insulating layer ID.

[0122] An interlayer insulating layer IE is disposed on the interlayer insulating layer ID. A resistive layer RL is disposed on the interlayer insulating layer IE. The resistive layer RL is disposed directly above the electrical fuse element EH. The resistive layer RL is made of silicon metal. The resistive layer RL is electrically connected to the wiring layer IT4 through a via conductive layer that fills a via hole in the interlayer insulating layer IE.

[0123] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0124] AR placement area, BI insulation layer, CO core part, CT disconnection transistor, CT1, CT2, VCA, VCB, VCC, VCD via conductive layer, D drain, EH electric fuse element, FI1 to FI4, FI11, FI12, IT1 to IT4, ITA, ITB, ITC, ITD, SI1, SI2, SI11, SI12 wiring layer, G gate, GD ground power supply, H1, H2, Hm, HS fuse, HT heat conductor, HT1, HT2, HT3 heat transfer layer, I1, I1a, I1b, I1c, I1d, I2, IA, IB, IC, ID, IE interlayer insulation layer, LS level shifter, ML metal layer, N1, N2, Nm block, P1 first part, P2 second part, P3 third part, PD pad electrode, PD2, PD3 pad part, PDa test pad electrode, PV Power supply, RA RAM area, RB redundant circuit area, RC power supply circuit area, RD CPU area, RE peripheral circuit area, RED redundant block, RF oscillator circuit area, RL resistive layer, RLa, RLb, RLc resistive portion, RR resistor, S source, SB semiconductor substrate, SC semiconductor device, TP2, TP3 taper portion, TR transistor, TRE trench, V1, V2, V3, V4, VHA, VHB via holes.

Claims

1. An electrical fuse element; an interlayer insulating layer covering the electrical fuse element; a resistive layer made of silicon metal and disposed on the interlayer insulating layer directly above the electrical fuse element.

2. The semiconductor device of claim 1 , further comprising a metal layer disposed directly above the resistive layer.

3. the resistive layer has a plurality of resistive portions made of silicon metal; The semiconductor device according to claim 1 , wherein the plurality of resistance portions are electrically connected in series or in parallel.

4. The semiconductor device according to claim 3 , wherein each of said plurality of resistance portions is electrically connected in series so that a current path in said resistance layer meanders in a plan view.

5. 2. The semiconductor device according to claim 1, further comprising a heat conductor disposed between said electrical fuse element and said resistance layer, said heat conductor having a higher thermal conductivity than said interlayer insulating layer.

6. The semiconductor device according to claim 5 , wherein the heat transfer body is formed of a single layer.

7. The semiconductor device according to claim 5 , wherein the heat transfer body has a plurality of heat transfer layers stacked on top of each other.

8. The semiconductor device according to claim 7 , wherein the heat transfer body further includes a connection portion connecting each of the plurality of heat transfer layers to each other.

9. The semiconductor device according to claim 8 , wherein an area of ​​at least one of said plurality of heat transfer layers is larger than an area of ​​said resistance layer.

10. The semiconductor device according to claim 8 , wherein the wiring widths of the plurality of heat transfer layers are smaller as the heat transfer layers are closer to the electrical fuse element.

Images