Package structure with high density interconnection of chips and manufacturing method thereof

Abstract

To provide a chip high-density interconnection package structure.SOLUTION: A package structure includes: a glass carrier having a groove and a glass frame 100 surrounding the groove; a first via pillar 201 penetrating the glass frame; a second via pillar penetrating the groove; first and second circuit layers 3011, 3012 formed on the upper and lower surfaces of the glass frame and electrically connected via the first via pillar; third and fourth circuit layers 3021, 3022 formed on the upper and lower surfaces of the groove and electrically connected via the second via pillar; a chip connection bridge 500 mounted on the third circuit layer in the groove; a fifth circuit layer 702 formed on the first circuit layer; and at least two chips 901 mounted on the second circuit layer and the fourth circuit layer. The chip connection bridge has a first pad 501, and the first pad is connected to the third circuit layer. Pins of the two chips are connected to the fourth circuit layer and / or the second circuit layer, and the fifth circuit layer is connected to the first circuit layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present application relates to the field of semiconductor packaging technology, and more particularly to a package structure with high density interconnection of chips and a method for manufacturing the same. [Background technology]

[0002] With the development of electronic technology, the requirements for the performance of electronic products are becoming higher and higher, so that the circuits of electronic elements and wiring boards are becoming more and more complex, and the size of electronic products is required to be smaller and thinner. Therefore, the high density integration, miniaturization, and multi-function of electronic components such as chips, package substrates, and package structures is an inevitable trend. The line width and line distance of the chip are becoming smaller and smaller, so it is more and more difficult to continue miniaturizing the chip. In order to achieve high density integration, miniaturization, and multi-function, the wiring of the package substrate is becoming more and more complicated, and there is a demand for more layers and finer wiring. In order to achieve high performance of electronic products, multi-chips are integrated and packaged, and in order to achieve the miniaturization of the multi-chip integrated package, there is a trend to interconnect the multi-chips.

[0003] In related technologies, there are many methods for realizing multi-chip interconnection, and a representative method among them is, for example, 2.5D packaging, in which a TSV intervening layer is provided between a carrier and a chip, and the TSV intervening layer is used to realize interconnection between chips and between the chip and the package carrier.

[0004] However, in the related art, on the one hand, the TSV interposer significantly increases the cost of chip interconnection, and the thickness of the TSV interposer is relatively large, which increases the volume of the package module and does not truly realize the light, thin, short and small package module, on the other hand, the TSV interposer has low design freedom for realizing multi-chip interconnection, and the chip in the 2.5D package structure is mounted on the surface of the TSV interposer, and the interposer and the package carrier are welded to realize the interconnection, resulting in a relatively low integration degree. Summary of the Invention [Problem to be solved by the invention]

[0005] In view of this, an object of the present application is to provide a package structure in which chips are interconnected at high density and a manufacturing method thereof. [Means for solving the problem]

[0006] In a first aspect, the present application provides a package structure in which chips are interconnected at high density, comprising: a glass carrier of a glass frame having a groove and surrounding the groove; a first via pillar penetrating the glass frame; a second via pillar penetrating the groove; a first circuit layer and a second circuit layer formed on upper and lower surfaces of the glass frame and electrically connected through the first via pillar; a third circuit layer and a fourth circuit layer formed on upper and lower surfaces of the groove and electrically connected through the second via pillar; a chip connection bridge attached to the third circuit layer in the groove; a fifth circuit layer formed on the first circuit layer; and at least two chips attached to the second circuit layer and the fourth circuit layer, wherein the chip connection bridge has a first pad, and the first pad is connected to the third circuit layer, and pins of the two chips are respectively connected to the fourth circuit layer and / or the second circuit layer, and the fifth circuit layer is connected to the first circuit layer.

[0007] In a second aspect, the present application provides a method for manufacturing a high density interconnected chip packaging structure, comprising: partially etching the glass carrier to form a groove and a glass frame surrounding the groove, and forming a first via and a second via penetrating the glass frame and the groove along a height direction; metallizing the glass carrier, forming a first circuit layer and a second circuit layer on the upper and lower surfaces of the glass frame, forming a third circuit layer and a fourth circuit layer on the upper and lower surfaces of the groove, and filling the first via to form a first via pillar, filling the second via to form a second via pillar, electrically connecting the first via pillar to the first circuit layer and the second circuit layer, and electrically connecting the second via pillar to the third circuit layer and the fourth circuit layer; mounting a chip connecting bridge in the groove and connecting a first pad of the chip connecting bridge to the third circuit layer; compressing a package layer so that the package layer covers the first circuit layer and the chip connection bridge; forming a fifth circuit layer on the package layer and connecting the first circuit layer to the fifth circuit layer; forming an insulating layer on the fifth circuit layer, forming a sixth circuit layer on the insulating layer, and connecting the fifth circuit layer to the sixth circuit layer; The method includes a step of flip-chip mounting at least two chips, including a first chip and a second chip, on the second circuit layer and the fourth circuit layer, wherein pins of the first chip and the second chip are respectively connected to a portion of the second circuit layer and a portion of the fourth circuit layer, and allowing the chip connection bridge to play a role in connecting the first chip and the second chip. Effect of the Invention

[0008] The package structure with high density interconnection of chips and its manufacturing method provided by the present application have the following beneficial effects: The multi-chip interconnection is realized by using chip connection bridges embedded in the glass carrier, which significantly reduces the volume of the entire package structure compared to TSV intervening layers. The first and second via pillars allow the chip to be flexibly connected to the chip connection bridges and solder balls, providing high design freedom. The thermal expansion coefficient of the glass material as a carrier is close to that of silicon wafers, which increases the reliability of the multi-chip package. At the same time, the glass carrier has the ability to form micro, high-density vias, which can meet the high-density I / O demand of the chip connection bridges. [Brief description of the drawings]

[0009] In order to more clearly explain the technical solutions in the present application or related art, the following briefly introduces drawings necessary for the description of the embodiments or related art. It is obvious that the drawings in the following description are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without any creative work. [Figure 1] FIG. 2 is a schematic diagram of a package structure with high density interconnection of chips according to an embodiment of the present application. [Diagram 2] 1A is a schematic cross-sectional view showing an intermediate structure in each step of a manufacturing method of a package structure in which chips are interconnected at a high density according to an embodiment of the present application; FIG. 1B is a schematic cross-sectional view showing an intermediate structure in each step of a manufacturing method of a package structure in which chips are interconnected at a high density according to an embodiment of the present application; FIG. 1C is a schematic cross-sectional view showing an intermediate structure in each step of a manufacturing method of a package structure in which chips are interconnected at a high density according to an embodiment of the present application; [Figure 2-1]1A is a schematic cross-sectional view showing an intermediate structure in each step of a manufacturing method of a package structure in which chips are interconnected at a high density according to an embodiment of the present application; FIG. 1B is a schematic cross-sectional view showing an intermediate structure in each step of a manufacturing method of a package structure in which chips are interconnected at a high density according to an embodiment of the present application; FIG. 1C is a schematic cross-sectional view showing an intermediate structure in each step of a manufacturing method of a package structure in which chips are interconnected at a high density according to an embodiment of the present application; FIG. 1D is a schematic cross-sectional view showing an intermediate structure in each step of a manufacturing method of a package structure in which chips are interconnected at a high density according to an embodiment of the present application; FIG. 1G is a schematic cross-sectional view showing an intermediate structure in each step of a manufacturing method of a package structure in which chips are interconnected at a high density according to an embodiment of the present application; [Figure 2-2] 4A to 4H are schematic cross-sectional views illustrating intermediate structures in various steps of a manufacturing method for a package structure with high density interconnection of chips according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be described in more detail below with reference to the drawings in conjunction with specific embodiments.

[0011] Unless otherwise defined, technical or scientific terms used in the examples of the present application should have the common meaning understood by a person of ordinary skill in the field to which the present application belongs. The words "first", "second" and similar words used in the examples of the present application do not represent any order, quantity or importance, but are used to distinguish different components. Similar words such as "include" or "comprise" mean that the component or item appearing before the word covers the components or items listed after the word and their equivalents, and does not exclude other components or items. Similar words such as "connect" or "couple" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Top", "bottom", "left", "right", etc. indicate relative positional relationships, and if the absolute position of the object being described changes, the relative positional relationship may change accordingly.

[0012] Referring to FIG. 1, the package structure of high-density interconnected chips is shown, which includes a glass carrier, the thermal expansion coefficient of which is close to that of silicon wafer, which can achieve higher reliability in chip packaging; and the glass carrier has the ability to form high density and small vias, which can fully meet the demand for high density I / O.

[0013] In one embodiment, the package structure includes a glass carrier, which includes a groove 103, a glass frame 100 surrounding the groove, a first via pillar 201 penetrating the glass frame 100, and a second via pillar 202 penetrating the groove 103.

[0014] The package structure further includes a first circuit layer 3011 and a second circuit layer 3021 formed on the upper and lower surfaces of the glass frame 100 and electrically connected through the first via pillar 201, a third circuit layer 3012 and a fourth circuit layer 3022 formed on the upper and lower surfaces of the groove 103 and electrically connected through the second via pillar 202, and a fifth circuit layer 702 formed on the first circuit layer 3011. A sixth circuit layer 803 may be formed on the fifth circuit layer 702, and a solder resist layer may be further formed on the sixth circuit layer 803, and balls may be ball-mounted to form solder balls. Alternatively, a new circuit layer may be subsequently formed on the sixth circuit layer 803, and solder balls may be further formed on the new circuit layer. The solder balls allow the entire package structure to be soldered. Since multiple circuit layers can be stacked and formed on the fifth circuit layer 702, the design freedom of the package structure can be greatly improved.

[0015] The chip connection bridge 500 is fitted into the third circuit layer 3012 in the groove 103, the chip connection bridge 500 may have a first pad 501, and the first pad 501 is connected to the third circuit layer 3012. At least two chips 901 may be attached to the second circuit layer 3021 and the fourth circuit layer 3022, and the pins of the at least two chips 901 may be respectively connected to the second circuit layer 3021 and / or the fourth circuit layer 3022, for example, the pins of the at least two chips 901 may be respectively connected to a part of the fourth circuit layer 3022 and a part of the second circuit layer 3021, so that the chip connection bridge plays the role of connecting the at least two chips 901 to each other. Here, it should be noted that the embodiment of the present application provides a case where two chips 901 are connected to each other, and in practice, the number of chips can be set as needed to realize multi-chip interconnection of more than two.

[0016] The package structure further includes a package layer 601 covering the first circuit layer 3011 and the chip connecting bridge 500, thereby packaging and fixing the chip connecting bridge 500 in the groove 103 of the glass carrier. The material of the package layer 601 may be selected to be a thermosetting resin material or a photosensitive resin material. A fifth circuit layer 702 is provided on the package layer 601, and the fifth circuit layer 702 may be connected to the first circuit layer 3011 through a first blind hole 602 formed by opening a window in the package layer 601. When the chip connecting bridge 500 has double-sided pads, for example, when the chip connecting bridge 500 has a second pad 502 on the opposite side of the first pad 501, the fifth circuit layer 702 may be connected to the second pad 502 through the first blind hole 602.

[0017] In one embodiment, the spacing between the second via pillars 202 may be arranged to be smaller than the spacing between the first via pillars 201, and the diameter of the second via pillars 202 may be arranged to be smaller than the diameter of the first via pillars 201, thereby supporting a chip connection bridge 500 having higher density and finer pads, and meeting the high density wiring requirements of the package structure due to the high density I / O of the chip connection bridge 500.

[0018] In one embodiment, the chip connection bridge 500 includes a first pad 501 and an opposite second pad 502. The first pad 501 may be connected to the third circuit layer 3012 through the conductive paste 401, and the second pad 502 is connected to the fifth circuit layer 702. The double-sided pad chip connection bridge 500 can realize more complicated chip interconnection functions. When mounting the chip connection bridge 500, the conductive paste 401 can fix the chip connection bridge 500 and realize the electrical connection between the first pad 501 and the third circuit layer 3012.

[0019] In practice, the chip connection bridge 500 may have only the first pads 501 on one side, without the second pads 502 .

[0020] In one embodiment, the second circuit layer 3021 and the fourth circuit layer 3022 are located on the same plane, and the first circuit layer 3011 and the second pad 502 are located on the same plane. The second circuit layer 3021 and the fourth circuit layer 3022 are located on the same plane to facilitate flipping the chip 901 in the later stage, and the first circuit layer 3011 and the second pad 502 are located on the same plane to facilitate packaging the chip connection bridge 500 and the first circuit layer 3011.

[0021] On the other hand, reference is made to FIGS. 2a to 2h, which are schematic cross-sectional views illustrating intermediate structures at different steps of a manufacturing method of a packaging structure in which chips 901 are densely interconnected.

[0022] The manufacturing method includes the following steps, as shown in Fig. 2a, provide a glass carrier, etch the glass carrier to form a groove 103 and a glass frame 100 surrounding the groove 103, and respectively form a first via 101 and a second via 102 penetrating the glass frame 100 and the groove 103 along the height direction. Then, the predetermined positions of the first via 101 and the second via 102 are laser modified, and respectively etched to form the first via 101 and the second via 102. In addition, in order to meet the requirements of high-density wiring of the package structure due to the high-density I / O in the subsequent chip connection bridge 500, the interval and diameter of the second via 102 can be made smaller than those of the first via 101.

[0023] Then, as shown in Fig. 2b, a first circuit layer 3011, a second circuit layer 3021, a third circuit layer 3012 and a fourth circuit layer 3022 are manufactured. In general, the first via pillar 201 and the second via pillar 202 are plated in the first via and the second via, then a metal seed layer is manufactured on the upper and lower surfaces of the glass carrier, a photoresist is applied to cover the third metal seed layer, the photoresist is photolithographed, and the first circuit layer 3011, the second circuit layer 3021, the third circuit layer 3012 and the fourth circuit layer 3022 are plated in the positions corresponding to the photolithography areas, and then the photoresist is removed and the exposed metal seed layer is etched, so that the first circuit layer 3011 and the second circuit layer 3021 are connected through the first via pillar 201, and the third circuit layer 3012 and the fourth circuit layer 3022 are connected through the second via pillar 202.

[0024] Then, a conductive paste 401 is applied into the groove 103, and the conductive paste 401 contains conductive particles 402, and the conductive paste 401 should cover the third circuit layer 3012, as shown in FIG. 2c.

[0025] Then, the chip connection bridge 500 is mounted in the groove 103 by the conductive paste 401, and the first pad 501 and the third circuit layer 3012 are fixed to each other by the conductive paste 401 as shown in FIG. 2d, thereby realizing the connection between the chip connection bridge 500 and the third circuit layer 3012. According to actual requirements, the chip connection bridge 500 may be a thin film circuit layer, a silicon intervening layer, a glass intervening layer, or a chip, as long as it has a multi-chip interconnection function. The chip connection bridge 500 may have only a single-sided pad such as the first pad 501, or may have double-sided pads such as the first pad 501 and the opposing second pad 502 in this embodiment.

[0026] Then, as shown in Fig. 2d, the package layer 601 is compressed. After the package layer 601 is compressed, the package for the first circuit layer 3011 and the chip connecting bridge 500 is completed, and in the process of compressing the package layer 601, the conductive particles 402 in the conductive paste 401 are pressed against the first pads 501 of the chip connecting bridge 500 and the third circuit layer 3012, so as to realize the electrical connection between the chip connecting bridge 500 and the third circuit layer 3012.

[0027] The packaging layer 601 may be made of a thermosetting resin material or a photosensitive resin material, which packages the first circuit layer 3011 and the chip connecting bridge 500, and fills the gap between the chip connecting bridge 500 and the groove 103 to achieve packaging.

[0028] Then, a window is opened in the package layer 601 to form a first blind hole 602, which may be opened in the package layer 601 by a laser or exposure and development method, as shown in Fig. 2e. The first blind hole 602 exposes the first circuit layer 3011 and the second pad 502 of the chip connection bridge 500.

[0029] 2f, a fifth circuit layer 702 is formed on the package layer 601. First, a first metal seed layer 701 is manufactured on the upper surface of the package layer 601 and the first blind hole 602, and then a circuit pattern of the fifth circuit layer 702 is formed on the first metal seed layer 701. Then, the fifth circuit layer 702 is plated on the circuit pattern, and the exposed first metal seed layer 701 is etched away to complete the connection between the fifth circuit layer 702 and the first circuit layer 3011 and the second pad 502 of the chip-chip connection bridge 500.

[0030] 2g, an insulating layer 801 is laminated on the fifth circuit layer 702, and a sixth circuit layer 803 is formed on the insulating layer 801. Specifically, the insulating layer 801 is laminated covering the fifth circuit layer 702, a window is opened in the insulating layer 801, and a second blind hole 802 is formed. Then, a second metal seed layer 804 is manufactured on the upper surface of the insulating layer 801 and in the second blind hole 802. Further, a circuit pattern of the sixth circuit layer 803 is formed on the second metal seed layer 804. Then, the sixth circuit layer 803 is plated on the circuit pattern, and the exposed second metal seed layer 804 is etched away to connect the sixth circuit layer 803 and the fifth circuit layer 702.

[0031] According to actual needs, additional insulating layers and circuit layers may be subsequently laminated according to the above-mentioned method to form a desired multi-layer package structure.

[0032] Then, as shown in FIG. 2h, the chip 901 is mounted. After the solder resist layer is processed and the metal surface is treated on both sides of the package structure to form a solder resist opening window, the solder balls 902 are manufactured on the second circuit layer 3021 and the fourth circuit layer 3022 by the ball mounting method, and then the chip 901 is flip-chip mounted, and the pins of one chip 901 may be connected to a part of the second circuit layer 3021 and a part of the fourth circuit layer 3022 through the solder balls 902, and the pins of the other chip 901 are connected to a part of the second circuit layer 3021 and a part of the fourth circuit layer 3022 through the solder balls 902, thereby realizing the interconnection of the two chips 901. In addition, if necessary, the multi-chip 901 can be mounted, and each pin is connected to a part of the second circuit layer 3021 and a part of the fourth circuit layer 3022 through the solder balls 902, thereby realizing the interconnection of the multi-chip 901.

[0033] Finally, ball mounting is performed on the solder resist opening window of the sixth circuit layer 803 to form solder balls of a package structure electrically connected to the outside, thereby forming an entire package member in which multiple chips are interconnected via chip connection bridges embedded in the glass carrier, which not only significantly reduces the volume of the entire package structure, but also improves the design freedom of the multi-chip package structure, improves the reliability of the multi-chip package, and meets the demand for high-density I / O of the chip connection bridges.

[0034] Those skilled in the art should understand that the description of the above embodiments is merely illustrative, and does not imply that the scope of the present application (including the claims) is limited to these examples, and that the technical features of the above embodiments or different embodiments may be combined under the concept of the present application, steps may be performed in any order, and there are many other variations in the above different aspects of the embodiments of the present application, which have not been provided in detail for the sake of brevity.

[0035] While the present application has been described in conjunction with specific embodiments thereof, it will be apparent to those skilled in the art that many permutations, modifications, and variations of these embodiments based on the above description.

[0036] The embodiments of the present application are intended to embrace all such replacements, modifications, and variations that fall within the broad scope of the appended claims, so that any omissions, modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included within the scope of protection of the present application. [Explanation of symbols]

[0037] 100 Glass Frame 101 First Via 102 2nd Via 103 Groove 201 1st Via Pillar 202 2nd Via Pillar 3011 1st circuit layer 3012 3rd circuit layer 3021 2nd circuit layer 3022 4th circuit layer 401 Conductive Paste 402 Conductive particles 500 Chip Connection Bridge 501 1st pad 502 2nd Pad 601 Package Layer 602 First blind hole 701 First metal seed layer 702 5th circuit layer 801 Insulation layer 802 Second blind hole 803 6th circuit layer 804 2nd metal seed layer 901 Chip 902 Solder ball

Claims

1. a glass carrier of a glass frame having a groove and surrounding the groove; a first via pillar penetrating the glass frame; a second via pillar penetrating the groove; a first circuit layer and a second circuit layer formed on upper and lower surfaces of the glass frame and electrically connected through the first via pillar; a third circuit layer and a fourth circuit layer formed on upper and lower surfaces of the groove and electrically connected through the second via pillar; a chip connection bridge attached to the third circuit layer in the groove; a fifth circuit layer formed on the first circuit layer; and at least two chips attached to the second circuit layer and the fourth circuit layer, wherein the chip connection bridge has a first pad, and the first pad is connected to the third circuit layer, and pins of the two chips are respectively connected to the fourth circuit layer and / or the second circuit layer, and the fifth circuit layer is connected to the first circuit layer; the chip connection bridge further comprises a second pad located on an opposite side of the first pad, wherein the second pad is connected to the fifth circuit layer; a first pad of said chip connection bridge connected to said third circuit layer through a conductive paste;

2. 2. The high density chip interconnect package structure of claim 1, further comprising a package layer covering the first circuit layer and the chip connection bridge.

3. 2. The high density chip interconnect package structure of claim 1, further comprising an insulating layer located on the fifth circuit layer and a sixth circuit layer located on the insulating layer.

4. 2. The high density chip interconnect package structure of claim 1, wherein the spacing between the first via pillars is greater than the spacing between the second via pillars.

5. 2. The high density chip interconnect package structure of claim 1, wherein the second circuit layer and the fourth circuit layer are located on the same plane, and the first circuit layer and the second pad are located on the same plane.

6. 2. The package structure with high density interconnection of chips as described in claim 1, wherein the at least two chips include a first chip and a second chip, wherein pins of the first chip and the second chip are respectively connected to a portion of the second circuit layer and a portion of the fourth circuit layer, thereby making the chip connection bridge play a role of connecting the first chip and the second chip.

7. partially etching the glass carrier to form a groove and a glass frame surrounding the groove, and forming a first via and a second via penetrating the glass frame and the groove along a height direction; metallizing the glass carrier, forming a first circuit layer and a second circuit layer on the upper and lower surfaces of the glass frame, forming a third circuit layer and a fourth circuit layer on the upper and lower surfaces of the groove, and filling the first via to form a first via pillar, filling the second via to form a second via pillar, electrically connecting the first via pillar to the first circuit layer and the second circuit layer, and electrically connecting the second via pillar to the third circuit layer and the fourth circuit layer; mounting a chip connecting bridge in the groove and connecting a first pad of the chip connecting bridge to the third circuit layer; compressing a package layer so that the package layer covers the first circuit layer and the chip connection bridge; forming a fifth circuit layer on the package layer and connecting the first circuit layer to the fifth circuit layer; forming an insulating layer on the fifth circuit layer, forming a sixth circuit layer on the insulating layer, and connecting the fifth circuit layer to the sixth circuit layer; flip-chip at least two chips, including a first chip and a second chip, on the second circuit layer and the fourth circuit layer, where pins of the first chip and the second chip are respectively connected to a part of the second circuit layer and a part of the fourth circuit layer, and the chip connection bridge serves to connect the first chip and the second chip; the first pad of the chip connection bridge and the third circuit layer are connected and fixed via a conductive paste; 2. A method for manufacturing a package structure with high density interconnection of chips, wherein the chip connection bridge further has a second pad located on an opposite side of the first pad, and wherein the second pad is connected to the fifth circuit layer.

8. 8. The method of claim 7, further comprising the step of ball mounting the sixth circuit layer to form solder balls that connect the at least two chips.

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