Generative Models for Inverse Design of Materials, Devices, and Structures

Abstract

A photonic device for splitting an optical beam comprises an input port configured to receive an input beam having an input power; a power splitter including perturbation segments disposed in first and second regions of a guiding material having a first refractive index, each having a second refractive index, the first region configured to split the input beam into a first beam and a second beam, the second region configured to separately guide the first and second beams, the first refractive index being greater than the second refractive index; and first and second output ports connected to the power splitter, each receiving and transmitting the first and second beams.

Description

[Technical field]

[0001] The present invention relates generally to methods and systems for training device design networks to use conditional variation autoencoders to randomly generate designs of materials, devices, or structures. [Background technology]

[0002] In many areas of materials, devices, and structures, design is challenging because dozens, hundreds, or even more parameters need to be optimized simultaneously, and each simulation or experiment to validate updated features for a new set of parameters takes a long time, making efficient optimization methods desirable.

[0003] Inverse design of optical devices using deep neural networks for forward or backward regression has been done before. (Tahersima et al., Scientific Reports). The inverse model, once well trained, can theoretically generate the design parameters for us. However, previous inverse neural network models are for optimizing binary structures (such as 0 or 1) that reduce the dimensionality of the actual optimization problem. This can result in some limitations, such as narrower bandwidth and semi-optimized results that need to be further optimized. There is a need to build better generative models that can be used for more advanced optimization problems. Summary of the Invention

[0004] We propose to use a conditional variational autoencoder combined with an adversarial network to randomly generate device designs given the desired device performance. To further improve performance, active training (co-training) can be added.

[0005] Some embodiments of the present disclosure are silicon photonics splitters based on rectangular or square structures with periodic holes. The dimensions of the final square are 2.25 μm x 2.25 μm. There are 400 holes on the square, with variable hole diameters ranging from 40 μm to 90 μm. A well-trained conditional variational autoencoder (CVAE) model can generate different hole vector combinations based on different splitting ratio inputs. The overall transmission efficiency for all the generated devices is about 90% over a very wide bandwidth (1300 nm to 1800 nm) with negligible insertion loss (less than -25 dB). Such models can be applied to different devices, such as wavelength splitters, mode converters, directional couplers, etc.

[0006] Some of the embodiments are based on training data combined with two different data sets, the first data set is a "semi-optimized" result with a binary hole size (either no holes or 90nm holes). The bandwidth of these devices is relatively low (100nm). The second part of the data set is a combination of multiple patterns with their performance. According to the embodiments, it is shown that the above "semi-optimized" results can be used to train a model capable of generating devices with good performance (90% total transmission rate) over a wide bandwidth (500nm). According to some embodiments of the present disclosure, the model structure is a conditional variational autoencoder with adversarial blocks based on Bayes' theorem. It is desired that the model bases the probability distribution of the data and be able to sample new data from that distribution. Our training data is generated by running FDTD simulations. The data is constructed by several DBS simulations and several randomly generated patterns. The training patterns are all binary holes and have a relatively small bandwidth (1500-1600nm). The total training data is approximately 15,000.

[0007] According to some embodiments of the present invention, a system for training a device design network to generate a layout of a device is provided, the system comprising: an interface configured to acquire input data of a device; a memory storing the device design network including first and second encoders, first and second decoders, and first and second adversarial blocks; and a processor, the processor configured in association with the memory to: update the first and second encoders and the first and second decoders based on a first loss function and a third loss function to reduce a difference between input data and output data of the first and second decoders, and update the first and second adversarial blocks by maximizing the second loss function.

[0008] Further, some embodiments of the present invention may provide a computer-implemented training method for training a device design network, where the method includes: acquiring input data of the device through an interface; updating the first and second encoders and the first and second decoders based on a first loss function and a third loss function to reduce a difference between the input data and the output data of the first and second decoders; and updating the first and second adversarial blocks by maximizing the second loss function.

[0009] Further, some embodiments of the present invention are based on the recognition that a computer-implemented method for generating a layout of a device using a device generative network can be provided. The computer-implemented method may include obtaining input data of the device through an interface and providing the input data to the device generative network. The device generative network is pre-trained by a computer-implemented training method, the computer-implemented training method being configured to obtain the input data of the device through the interface, update the first and second encoders and the first and second decoders based on a first loss function and a third loss function, thereby reducing the difference between the input data and the output data of the first and second decoders, and updating the first and second adversarial blocks by maximizing the second loss function. The computer-implemented method further includes generating layout data of the layout of the device using the pre-trained device generative network, and storing the layout data in a memory.

[0010] The presently disclosed embodiments will be further described with reference to the accompanying drawings, in which the drawings are not necessarily to scale, emphasis instead generally being placed on illustrating the principles of the presently disclosed embodiments. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram showing an overall configuration of a system according to an embodiment of the present invention. [Diagram 2] FIG. 1 illustrates a general adversarial CVAE network according to an embodiment of the present invention. [Diagram 3] FIG. 2 is a diagram showing a detailed structure of a CVAE encoder block according to an embodiment of the present invention; [Figure 4] FIG. 2 is a diagram showing a detailed structure of a CVAE decoder block according to an embodiment of the present invention; [Diagram 5]FIG. 2 is a diagram showing a detailed structure of an adversarial block according to an embodiment of the present invention; [Figure 6] FIG. 1 illustrates a flowchart of a training process for a model according to an embodiment of the present invention. [Figure 7] FIG. 4 illustrates input data pre-processing steps according to an embodiment of the present invention. [Figure 8] FIG. 2 illustrates a detailed data flow through a CVAE model according to an embodiment of the present invention. [Figure 9] FIG. 1 illustrates an active learning process for generating a final model according to an embodiment of the present invention. [Figure 10] FIG. 1 illustrates a flowchart of a mapping algorithm for rendering a layout according to an embodiment of the present invention. [Figure 11a] FIG. 2 illustrates an overall device structure introduction according to an embodiment of the present invention. [Figure 11b] FIG. 2 shows a cross-sectional view of an overall device according to an embodiment of the present invention. [Figure 11c] FIG. 4 is a diagram showing a mode profile in a cross section of a device according to an embodiment of the present invention. [Figure 12a] FIG. 1 illustrates a resulting device having a 5:5 split ratio according to an embodiment of the present invention. [Figure 12b] FIG. 13 illustrates simulation results of a generated 5:5 splitter according to an embodiment of the present invention. [Figure 12c] FIG. 13 illustrates simulation results of a generated 5:5 splitter according to an embodiment of the present invention. [Figure 12d] FIG. 13 illustrates simulation results of a generated 5:5 splitter according to an embodiment of the present invention. [Figure 13a] FIG. 1 illustrates a resulting device having a 6:4 split ratio according to an embodiment of the present invention. [Figure 13b] FIG. 13 illustrates simulation results of a generated 6:4 splitter according to an embodiment of the present invention. [Figure 13c]FIG. 13 illustrates simulation results of a generated 5:5 splitter according to an embodiment of the present invention. [Figure 13d] FIG. 13 illustrates simulation results of a generated 5:5 splitter according to an embodiment of the present invention. [Figure 14a] FIG. 1 illustrates a produced device having a 7:3 split ratio according to an embodiment of the present invention. [Figure 14b] FIG. 13 illustrates simulation results of a generated 7:3 splitter according to an embodiment of the present invention. [Figure 14c] FIG. 13 illustrates simulation results of a generated 5:5 splitter according to an embodiment of the present invention. [Figure 14d] FIG. 13 illustrates simulation results of a generated 5:5 splitter according to an embodiment of the present invention. [Figure 15a] FIG. 1 illustrates a resulting device having a split ratio of 8:2, according to an embodiment of the present invention. [Figure 15b] FIG. 13 illustrates simulation results of a generated 8:2 splitter according to an embodiment of the present invention. [Figure 15c] FIG. 13 illustrates simulation results of a generated 5:5 splitter according to an embodiment of the present invention. [Figure 15d] FIG. 13 illustrates simulation results of a generated 5:5 splitter according to an embodiment of the present invention. [Figure 16] FIG. 13 illustrates a data processing procedure before being supplied to decoder #2 according to an embodiment of the present invention. [Figure 17] FIG. 2 is a graph showing the transmission loss characteristics of an optical fiber as a function of wavelength. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The following description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the following description of exemplary embodiments provides those skilled in the art with an enabling description for implementing one or more exemplary embodiments. Contemplated are various changes that may be made in the function and arrangement of elements without departing from the spirit and scope of the disclosed subject matter, as set forth in the appended claims.

[0013] Specific details are provided in the following description to provide a thorough understanding of the embodiments. However, those skilled in the art will appreciate that the embodiments may be practiced without these specific details. For example, systems, processes, and other elements in the disclosed subject matter may be shown as components in block diagram form in order to avoid obscuring the embodiments in unnecessary detail. In other instances, well-known processes, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments. Additionally, like reference numbers and names in the various drawings refer to like elements.

[0014] Also, the individual embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Moreover, the order of operations may be rearranged. A process may be terminated when its operations are completed, but may have other steps not discussed or included in the diagram. Moreover, not all operations in any process specifically described may occur in all embodiments. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, the end of the function may correspond to a return of the function to the calling function or to the main function.

[0015] Furthermore, embodiments of the disclosed subject matter may be implemented, at least in part, either manually or automatically. The manual or automated implementation may be performed or at least assisted through the use of machines, hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments to perform the necessary tasks may be stored on a machine-readable medium. A processor may perform the necessary tasks.

[0016] FIG. 1 is a schematic structure of a system 100 including a neural network module trained to provide a layout of a device according to some embodiments of the present invention. The system 100 includes an interface 115, a processor 120, a storage device 104, and a memory 106. The storage device 104 includes a device generation module 200, which includes encoder network modules 301 and 301', decoder network modules 401 and 401', and adversarial modules (blocks) 501 and 501'. The storage device 104 may include a mapping algorithm 108 configured to generate a layout of a real device 109, or the mapping algorithm 108 may be stored in another memory (not shown). The interface 115 is configured to communicate between the memory 106, the storage device 104, the processor 120, and the mapping algorithm 108. The interface 115 is also configured to receive input data including user desired transmission information 101 and a Gaussian distribution 102 via an input device external to the system 100. In some cases, the user desired transmission information 101 and the Gaussian distribution 102 may be stored in the memory 106 or the storage device 104. The desired transmission information (101) and the standard Gaussian distribution (102) are provided to the encoder and decoder neural network modules 301, 301', 401 and 401' via an interface. The neural network modules 301, 301', 401, 401', 501 and 501' are pre-trained so that the system 100 can generate the corresponding hole vector pattern (107) of the device. The system 100 applies a mapping algorithm (1000) to draw / generate the layout of the actual device. Such a network has been verified under a square-based splitter model (1100) as one embodiment of the present invention. It should be noted that although the following embodiment of the present invention illustrates a square-based splitter model as an example, the shape of the splitter (model) is not limited to a square.Other shapes may be used, including, by way of example, rectangular, circular, elliptical, symmetrical, asymmetrical, or any shape including any of them, where such a splitter is configured to include an input port configured to receive an input beam having an input power, a power splitter including a perturbation segment disposed in a first region of a guiding material having a first refractive index and a second region having a second refractive index, the first region configured to split the input beam into a first beam and a second beam, the second region configured to separately guide the first and second beams, the first refractive index being greater than the second refractive index, and output ports including first and second output ports connected to the power splitter, each receiving and transmitting the first and second beams.

[0017] Once the neural network module is fully trained, the system can generate splitters with any splitting ratio desired by the user immediately. Some results using the system 100 show that these devices have a total transmission rate of about 93% over a very wide bandwidth that is practically difficult (in terms of time and efficiency) to obtain by using conventional methods such as Direct Binary Search (DBS). Compared with another result obtained with our other system that includes only the encoder network module-1 301, the decoder network module-1 401, and the adversarial module-1 501 for the training process, but does not include the encoder network module-2 301', the decoder network module-2 401', and the adversarial module-2 501', the results according to the present invention show a significant improvement from our previous system.

[0018] FIG. 2 shows the overall configuration of the neural network model (device generation module) 200. The model 200 is composed of six parts, which are two encoders (301, 301'), two decoders (401, 401') and two adversarial blocks (501, 501) (shown in FIG. 1). The encoders #1 and #2 (30) have the same structure and share the same weights. The decoders #1 and #2 (401) have the same structure and share the same weights. The same standards are also applied to the adversarial block (501). The encoder #1 (301) is configured to extract input pattern features (801) and represent them using a probability distribution defined as a latent variable (806). The decoder #1 (401) has a similar structure to the encoder #1 (301), but in the reverse order. The decoder #1 is configured to generate device patterns using the latent variables and the encoded conditions (807). For the second decoder-encoder set, decoder #2 (401') takes the standard Gaussian samples along with the encoded terms (801) to generate a second output pattern (811) that is later used in the loss function. Encoder #2 (301) then takes the second output pattern (811) to generate a second latent variable set (506). Output pattern #2 and latent variables #2 are used only for training (to calculate the loss function). Use the trained decoder (401) for the final model.

[0019] FIG. 3 shows the detailed structure of the encoders 301, 301′, and the encoders 301 and 301′ have the same structure. The encoder 301 is composed of two convolutional layers (303 and 304), one with 8 channels and the second with 16 channels, followed by two parallel Multilayer Perceptron (MLP) layers (304 and 305). Each of the two parallel MLP layers may be a parallel fully connected layer. In some cases, each of the two parallel MLP layers includes three or more inputs. As an example, the two parallel MLP layers are configured to have an input-output dimension of 800->60 to generate the extracted patterns (mean (μ) and covariance (σ) of a Gaussian distribution). To obtain the latent variables, a reparameterization (306) of the mean and covariance needs to be applied. The formula for the reparameterization is shown in Equation 1 below.

number

[0020] FIG. 4 shows the detailed structure of the decoders 401 and 401', which have the same structure. The latent variables (806) and the encoded condition data (807) from the encoder are concatenated (808) to form the input to the decoder. The combined data is then fed to the decoder to generate the patterns. The decoder is combined with one multi-layer perceptron (MLP) layer (402) and two convolutional layers (403 and 404). The MLP layer has an input-to-output dimension of 69->800. In some cases, each of the two convolutional layers may be designed to have three or more channels. As an example, the two convolutional layers have the following specifications: the first convolutional layer (403) has 8 channels and the second convolutional layer (404) has 16 channels. The output of the second convolutional layer is the generated (or reconstructed) pattern (107). The final model is used to generate different devices.

[0021] Figure 5 shows the detailed structure of the adversarial blocks 501 and 501', and these adversarial blocks have the same structure. The adversarial block 501 has two MLP layers (502 and 503), the first MLP layer has an input-output dimension of 60->100, and the second MLP layer has an input->output dimension of 100->60. The output of the adversarial block is the adversarial condition (504). To better fit the device distribution, we add an adversarial block to separate the latent variables from the conditions.

[0022] FIG. 6 shows a detailed training process for a conditional variational autoencoder (CVAE) model 600 according to some embodiments of the present invention. First, data (input patterns and input conditions) are taken from a dataset (601), then they are processed into two channel inputs (301) and fed into the network. The processing steps are shown in 700. A complete training iteration includes two parts: updating the CVAE network (602) and updating the adversarial block (606). A first loss function Lossl is calculated after the above processing (603). Meanwhile, a second loss function Loss3 (Equation 4) is calculated after the second processing, and the random Gaussian sampled data (809) is then processed (1800) and then fed into the decoder encoder block (400) to obtain the second latent variable (506). The final loss is the sum of the two loss functions (loss1 and loss3), which is used to update the encoder and decoder blocks (604). A second loss function (Loss2) is calculated after every three updates of the encoder and decoder (607). It is used to update only the adversarial blocks (608) (shown in Equation 3).

number

[0023]

number

[0024] Fig. 7 shows the details of the input data processing. The input data (represented by the network's unique name) given to the network (ACVAE with cycle consistency) consists of two channels (two 20x20 matrices) (801), the first channel being the 20x20 input pattern (702) and the second channel being the decoded (3x20) input condition (701).

[0025] FIG. 8 illustrates a data flow 800 in a network according to some embodiments of the present invention. Input pattern data (702) and input condition data (803) form a two-channel input to the CVAE encoder (301). Encoder #1 then generates a latent variable #1 of dimension 60. The latent variable is then concatenated with the encoded condition (807) (having dimension 9) to form the input to decoder #1 (808). After processing by decoder #1, the generated (or reconstructed) pattern #1 (107) is the output. Meanwhile, the encoded condition is concatenated with random Gaussian sampling (809)-(1700) and fed to decoder #2 (811) to obtain output pattern #2. The output pattern #2 then becomes the input of encoder #2 to obtain latent variable #2.

[0026] To fully train the neural network model 200 (represented by the network's unique name if the number is incorrect) (ACVAE with cycle consistency), we used the concept of active learning. Figure 9 shows a flow chart of the process. What we do is train a preliminary use of the original 15,000 binary training data. After the first model is finished, we use it to generate 1,000 devices with different hole sizes and label them with their spectrum at each port (condition) through FDTD simulation. The new generated data is then combined with the existing data to form a new 16,000 data set and the model is retrained. The second model is then the final model used for device generation.

[0027]

number

[0028] 11a-11c show an optical device 110 obtained by using the system 100 according to some embodiments of the present invention. The optical device 110 is a square-based optical power splitter. The mechanism of splitting the power (of a light beam) is to draw different holes and guide the light propagation using the difference in refractive index. The device 110 is designed for TE0 mode use. The square structure has a footprint of 2.5 μm×2.5 μm with oxide cladding. The width of the waveguide is 500 nm and the height is 220 nm. The hole spacing is 130 nm, the minimum hole diameter is 76.5 nm and the maximum hole diameter is 42 nm.

[0029] The power splitter 110 is formed from nanostructured segments arranged within a guiding material to effectively guide an input light beam along a predesigned beam path towards an output port. In this case, the nanostructured segments are nanostructured holes having a refractive index smaller than the refractive index of the guiding material of the power splitter. The waveguides of the power splitter 110 are silicon and the material of the nanostructured holes is silicon dioxide (S). i O2).

[0030] 12a, 13a, 14a and 15a show schematic diagrams illustrating power splitters with different splitting ratios (5:5, 6:4, 7:3 and 8:2) generated by a fully trained model. As shown in the figures, the splitter includes an input port configured to receive an input beam having an input power, and a power splitter including perturbation segments disposed in a first region and a second region of a guide material having a first refractive index, each segment having a second refractive index, the first region configured to split the input beam into a first beam and a second beam, the second region configured to separately guide the first and second beams, the first refractive index being greater than the second refractive index, and the splitter further includes first and second output ports connected to the power splitter to receive and transmit the first and second beams, respectively.

[0031] Figures 12b, 13b, 14b and 15b show the beam propagation through the device. The total power at port 1 and port 2 is considered to be 100%. A 5:5 splitter means that port 1 holds 50% of the total output power and port 2 holds 50% of the total output power. A 6:4 splitter means that port 1 holds 60% of the total output power and port 2 holds 40% of the total output power. A 7:3 splitter means that port 1 holds 70% of the total output power and port 2 holds 30% of the total output power. An 8:2 splitter means that port 1 holds 80% of the total output power and port 2 holds 20% of the total output power.

[0032] Figures 12c-d, 13c-d, 14c-d, and 15c-d show the spectral response of these devices. The devices produced by our adversarial conditional autoencoder have very good performance (total transmission of about 90%) over a 550 nm bandwidth (1250 nm to 1800 nm).

[0033] 16 illustrates a computer-implemented method 1600 for designing a device according to some embodiments of the present invention. The method 1600 includes a data processing step of the input conditions 701 (input data / parameters) before being fed to the decoder #2. The random Gaussian sampled variables (809) are concatenated with the encoded conditions (807) to form a 3x24 matrix (1601) which is fed to the decoder #2 (301).

[0034] According to some embodiments of the present invention, the devices generated from the models have the following advantages: The devices can be manufactured in a very compact size. As an example, the footprint can be as small as 2.25 μm×2.25 μm or less, which is the smallest splitter known to us. With such a compact size, it has the potential to be integrated on a large scale in photonics chips with a relatively low area budget.

[0035] A device designed according to an embodiment of the present invention can operate over an ultra-wide bandwidth (1250 nm to 1800 nm) while maintaining excellent performance (approximately 90% transmission rate). Thus, the device can cover all optical communication bands (O-band to L-band, corresponding to wavelengths ranging from 1260 nm to 1625 nm). See Figure 17, which shows the transmission loss characteristics of an optical fiber as a function of wavelength.

[0036] This model has been proven to immediately generate any device the user wants without further optimization, which saves significant design time.

[0037] Note that nanophotonic devices with periodic holes have been described as examples. However, there are other types of optical devices. For example, adjoint methods can generally optimize a larger number of parameters. The present invention can use these types of devices as training data.

Claims

1. 1. A system for training a device design neural network model to generate a layout of a nanophotonic device having periodic holes, the layout including a hole vector pattern, the system comprising: and an interface configured to obtain input data for a device, the input data including user desired transmission information and a Gaussian distribution, the interface configured to provide the user desired transmission information and the Gaussian distribution to a first encoder neural network module, a second encoder neural network module, a first decoder neural network module, and a second decoder neural network module of the device design neural network model, the system further comprising: a memory for storing the device design neural network model including the first and second encoder neural network modules, the first and second decoder neural network modules, and first and second adversarial block neural network modules, the first and second encoder neural network modules having the same structure and sharing the same weights, the first and second decoder neural network modules having the same structure and sharing the same weights, the first encoder neural network module being configured to extract and represent input pattern features using first latent variables, and the first the decoder neural network module is configured to generate a first output pattern using the first latent variables and encoded conditions, the second decoder neural network module is configured to generate a second output pattern using standard Gaussian samples and the encoded conditions, the second encoder neural network module is configured to generate a second latent variable using the second output pattern, the first adversarial block neural network module is configured to output a first adversarial condition based on the first latent variables, and the second adversarial block neural network module is configured to output a second adversarial condition based on the second latent variables, and the system further comprises: a processor, associated with the memory, updating the weights in the first and second encoder neural network modules and the first and second decoder neural network modules based on a first loss function and a third loss function to reduce a difference between the input data and the output data of the first and second decoder neural network modules; and updating the weights in the first and second adversarial block neural network modules by minimizing a second loss function.

2. 2. The system of claim 1, wherein the first and second encoder neural network modules are configured with at least one convolutional layer followed by at least one parallel fully connected layer to extract features of the device's layout.

3. 3. The system of claim 2, wherein each of the at least one convolutional layer includes three or more channels.

4. The system of claim 2 , wherein each of the at least one parallel fully connected layer includes an input dimension and an output dimension.

5. 2. The system of claim 1, wherein the device is an optical power splitter and the extracted pattern features are the mean (μ) and covariance (σ) of the Gaussian distribution.

6. The system of claim 1 , wherein the device is a power splitter, or a wavelength splitter, or a mode converter.

7. The system of claim 1 , wherein the training data comprises device structures optimized by an adjoint method.

8. The at least one convolutional layer includes two convolutional layers, 4. The system of claim 3, wherein the two convolutional layers include 8 and 16 channels, respectively.

9. The at least one parallel fully connected layer includes two parallel fully connected layers, 5. The system of claim 4, wherein each of the two parallel fully connected layers includes an input dimension of 800 and an output dimension of 60.

10. 1. A computer-implemented training method for training a device design neural network model to generate a layout of a nanophotonic device having periodic holes, the layout including a hole vector pattern, the method comprising: obtaining input data for a device via an interface, the input data including user desired transmission information and a Gaussian distribution, the method further comprising: providing the user desired transmission information and the Gaussian distribution via the interface to a first encoder neural network module, a second encoder neural network module, a first decoder neural network module, and a second decoder neural network module of the device design neural network model; reducing a difference between input data and output data of the first and second encoder neural network modules and the first and second decoder neural network modules by updating weights in the first and second encoder neural network modules and the first and second decoder neural network modules based on a sum of a first loss function and a third loss function; The first and second adversarial block neural networks are optimized by minimizing the second loss function. updating weights in the network modules; the first and second encoder neural network modules have the same structure and share the same weights, the first and second decoder neural network modules have the same structure and share the same weights, and the first and second adversarial block neural network modules have the same structure and share the same weights; The first encoder neural network module extracts input pattern features. and representing the first latent variable using an encoded condition, the first decoder neural network module configured to generate a first output pattern using the first latent variable and an encoded condition, the second decoder neural network module configured to generate a second output pattern using a standard Gaussian sample and the encoded condition, the second encoder neural network module configured to generate a second latent variable using the second output pattern, the first adversarial block neural network module configured to output a first adversarial condition based on the first latent variable, and the second adversarial block neural network module configured to output a second adversarial condition based on the second latent variable.

11. 11. The method of claim 10, wherein the first and second encoder neural network modules are configured with at least one convolutional layer followed by at least one parallel fully connected layer to extract features of the device's layout.

12. 12. The method of claim 11, wherein each of the at least one convolutional layer includes three or more channels.

13. The method of claim 11 , wherein each of the at least one parallel fully connected layer includes an input dimension and an output dimension.

14. 11. The method of claim 10, wherein the first loss function is represented by a combination of a BCE loss between an input and an output of the first set of encoder and decoder neural network modules and a KL divergence between an encoded latent variable and a standard Gaussian distribution and between an encoded latent variable and an output of the first adversarial block neural network module, the second loss function is represented by a combination of a mean square root loss (MSE loss) between an encoded latent variable and an output from the first adversarial block neural network module and an MSE loss between a condition between an encoded latent variable and an output from the second adversarial block neural network module, and the third loss function is represented by a combination of an MSE loss between a standard Gaussian sample and a second latent variable and an MSE loss between an encoded latent variable and an output of the adversarial block neural network module.

15. 1. A computer-implemented method for generating a layout, including a hole vector pattern, of a nanophotonic device having periodic holes using a device generation neural network model, the method comprising: training the device generated neural network model using the method of claim 10; and obtaining input data for the device via an interface, the input data including user desired transmission information and a Gaussian distribution, the method further comprising: providing said input data to said device generated neural network model; generating layout data for a layout of the device using the pre-trained device generative network model and storing the layout data in a memory; Includes, a method.

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