Semiconductor memory device

Abstract

To provide a semiconductor storage device capable of reducing at least one of operating current and read time.SOLUTION: A semiconductor storage device includes: a memory string; a plurality of first wirings electrically connected to the memory string; a plurality of second wirings electrically connected to the plurality of first wirings; a plurality of transistors electrically connected between the plurality of first wirings and the plurality of second wirings; and a third wiring commonly connected to gate electrodes of the plurality of transistors. The memory string includes a plurality of memory transistors connected in series. The gate electrodes of the plurality of memory transistors are connected to the plurality of first wirings. In addition, this semiconductor storage device executes a first reading operation in response to an input of a first command set and executes a second reading operation in response to an input of a second command set. Further, a first voltage for turning on the plurality of transistors is supplied to the third wiring from the end of the first reading operation to the start of the second reading operation.SELECTED DRAWING: Figure 20

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that includes a memory string and a plurality of first wirings electrically connected to the memory string, the memory string including a plurality of memory transistors connected in series, and gate electrodes of the plurality of memory transistors connected to the plurality of first wirings. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-157260 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device capable of reducing at least one of an operating current and a time required for a read operation is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a memory string, a plurality of first wirings electrically connected to the memory string, a plurality of second wirings electrically connected to the plurality of first wirings, a plurality of transistors electrically connected between the plurality of first wirings and the plurality of second wirings, and a third wiring commonly connected to the gate electrodes of the plurality of transistors. The memory string includes a plurality of memory transistors connected in series. The gate electrodes of the plurality of memory transistors are connected to the plurality of first wirings. The semiconductor memory device also executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. A first voltage that turns the plurality of transistors to an ON state is supplied to the third wiring during the period from the end of the first read operation to the start of the second read operation.

[0006] A semiconductor memory device according to one embodiment includes a memory string, a plurality of first wirings electrically connected to the memory string, and a plurality of second wirings electrically connected to the plurality of first wirings. The memory string includes a plurality of memory transistors connected in series. Gate electrodes of the plurality of memory transistors are connected to the plurality of first wirings. The semiconductor memory device executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. A first voltage is supplied to the plurality of second wirings at a first timing when the first read operation is completed, and a second voltage is supplied to the plurality of second wirings at a second timing when the second read operation is completed. The first voltage is greater than the second voltage.

[0007] A semiconductor memory device according to one embodiment includes a first bonding pad electrode to which a first voltage is supplied, and executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. For example, when the second read operation is executed after the first read operation, the execution time of the second read operation is set to a first time, and the average value of a current flowing through the first bonding pad electrode during the execution of the second read operation is set to a first current. For example, when the second read operation is executed after the second read operation, the execution time of the second read operation is set to a second time, and the average value of a current flowing through the first bonding pad electrode during the execution of the second read operation is set to a second current. In this case, the first time is smaller than the second time, or the first current is smaller than the second current. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic block diagram showing a configuration of a memory system 10 according to a first embodiment. [Diagram 2] 1 is a schematic side view showing a configuration example of a memory system 10. FIG. [Diagram 3] 1 is a schematic plan view showing a configuration example of a memory system 10. FIG. [Figure 4] 1 is a schematic block diagram showing a configuration of a memory die MD according to a first embodiment. [Diagram 5] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 6] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 7] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 8] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 9] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 10] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 11] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 12] FIG. 2 is a schematic plan view of a memory die MD. [Figure 13] FIG. 2 is a schematic perspective view of a memory die MD. [Figure 14] FIG. 13 is a schematic enlarged view of a portion indicated by A in FIG. [Figure 15] FIG. 14 is a schematic enlarged view of a portion indicated by B in FIG. [Figure 16] FIG. 2 is a schematic diagram for explaining the threshold voltage of a memory cell MC in which 3-bit data is stored. [Figure 17] 11 is a timing chart for explaining a read operation. [Figure 18] FIG. 11 is a schematic cross-sectional view for explaining a read operation. [Figure 19] 11 is a timing chart for explaining a read operation. [Figure 20] 5 is a schematic timing chart for explaining a read standby mode according to the first embodiment. [Figure 21] 5 is a schematic timing chart for explaining a read standby mode according to the first embodiment. [Figure 22] 11 is a schematic timing chart for explaining an operating current of the memory die MD. [Figure 23] 11 is a schematic timing chart for explaining an operating current of the memory die MD. [Figure 24] 11 is a schematic timing chart for explaining an operating current of the memory die MD. [Diagram 25] 10 is a schematic timing chart for explaining a method of setting a read standby mode. [Figure 26] 10 is a schematic timing chart for explaining a method of setting a read standby mode. [Figure 27] 10 is a schematic timing chart for explaining a read standby mode according to the second embodiment. [Figure 28]13 is a schematic timing chart for explaining a read standby mode according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0010] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0011] In addition, in this specification, the term "control circuit" may refer to a peripheral circuit such as a sequencer provided on a memory die, or may refer to a controller die or controller chip connected to a memory die, or may refer to a configuration that includes both of these.

[0012] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0013] Furthermore, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0014] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0015] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0016] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0017] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0018] [First embodiment] [Memory System 10] FIG. 1 is a schematic block diagram showing the configuration of a memory system 10 according to the first embodiment.

[0019] The memory system 10 reads, writes, erases, etc. user data in response to a signal transmitted from a host computer 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes a plurality of memory dies MD and a controller die CD.

[0020] The memory die MD stores user data. The memory die MD includes a plurality of memory blocks BLK. Each memory block BLK includes a plurality of pages PG. The memory block BLK may be an execution unit of an erase operation. The page PG may be an execution unit of a read operation and a write operation.

[0021] 1, the controller die CD is connected to a plurality of memory dies MD and a host computer 20. The controller die CD includes, for example, a logical-physical conversion table 21, a FAT (File Allocation Table) 22, an erase count holding unit 23, an ECC circuit 24, and an MPU (Micro Processor Unit) 25.

[0022] The logical-physical conversion table 21 holds a logical address received from the host computer 20 in association with a physical address assigned to a page PG in the memory die MD. The logical-physical conversion table 21 is realized, for example, by a RAM (Random Access Memory) (not shown).

[0023] FAT22 holds FAT information indicating the state of each page PG. Such FAT information includes, for example, information indicating "valid", "invalid", and "erased". For example, a page PG that is "valid" stores valid data that is read in response to a command from the host computer 20. A page PG that is "invalid" stores invalid data that is not read in response to a command from the host computer 20. A page PG that is "erased" has not stored data since the erasure process was executed. FAT22 is realized, for example, by a RAM or the like (not shown).

[0024] The erase count holding unit 23 holds a physical address corresponding to the memory block BLK and the number of erase operations executed on the memory block BLK in association with each other. The erase count holding unit 23 is realized by, for example, a RAM (not shown) or the like.

[0025] The ECC circuit 24 detects errors in the data read from the memory die MD and corrects the data if possible.

[0026] The MPU 25 refers to the logical-physical conversion table 21, the FAT 22, the erase count holding unit 23, and the ECC circuit 24 to perform processes such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compaction), and wear leveling.

[0027] Fig. 2 is a schematic side view showing a configuration example of the memory system 10 according to this embodiment. Fig. 3 is a schematic plan view showing the same configuration example. For convenience of explanation, some components are omitted in Figs. 2 and 3.

[0028] As shown in FIG. 2, the memory system 10 according to the present embodiment includes a mounting substrate MSB, a plurality of memory dies MD, and a controller die CD. A pad electrode P is provided in an end region in the Y direction on the upper surface of the mounting substrate MSB. An area of ​​the upper surface of the mounting substrate MSB other than the end region in the Y direction is bonded to the lower surface of the memory die MD via an adhesive or the like. The plurality of memory dies MD are stacked on the mounting substrate MSB. A pad electrode P is provided in an end region in the Y direction on the upper surface of the memory die MD. An area of ​​the upper surface of the memory die MD other than the end region in the Y direction is bonded to the lower surface of another memory die MD or the controller die CD via an adhesive or the like. The controller die CD is stacked on the memory die MD. A pad electrode P is provided in an end region in the Y direction on the upper surface of the controller die CD.

[0029] 3, the mounting substrate MSB, the memory dies MD, and the controller die CD each include a plurality of pad electrodes P arranged in the X direction. The pad electrodes P provided on the mounting substrate MSB, the memory dies MD, and the controller die CD are connected to each other via bonding wires B.

[0030] 2 and 3 are merely examples, and the specific configuration can be adjusted as appropriate. For example, in the example shown in FIG. 2 and FIG. 3, a controller die CD is stacked on a plurality of memory dies MD. The memory die MD and the controller die CD are connected by a bonding wire B. The plurality of memory dies MD and the controller die CD are included in one package. However, the controller die CD may be included in a package separate from the memory die MD. The plurality of memory dies MD and the controller die CD may be connected to each other via a through electrode or the like, instead of the bonding wire B.

[0031] [Circuit configuration of memory die MD] Fig. 4 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figs. 5 to 11 are schematic circuit diagrams showing the configuration of a portion of the memory die MD.

[0032] FIG. 4 illustrates a plurality of control terminals. These control terminals may be represented as control terminals corresponding to high active signals (positive logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to low active signals (negative logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to both high active signals and low active signals. In FIG. 4, the reference numerals of the control terminals corresponding to low active signals include an overline. In this specification, the reference numerals of the control terminals corresponding to low active signals include a slash (" / "). The description in FIG. 4 is an example, and the specific embodiment can be appropriately adjusted. For example, it is also possible to make some or all of the high active signals low active signals, and to make some or all of the low active signals high active signals.

[0033] 4, the memory die MD includes a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC includes a voltage generating circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuit PC also includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. The peripheral circuit PC also includes an input / output control circuit I / O and a logic circuit CTR.

[0034] [Circuit configuration of memory cell array MCA] 5, the memory cell array MCA includes a plurality of memory blocks BLK as described above. Each of the memory blocks BLK includes a plurality of string units SU. Each of the string units SU includes a plurality of memory strings MS. One end of each of the memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other ends of each of the memory strings MS are connected to the peripheral circuit PC via a common source line SL.

[0035] The memory string MS includes a drain side select transistor STD, a plurality of memory cells MC (memory transistors), a source side select transistor STS, and a source side select transistor STSb. The drain side select transistor STD, the plurality of memory cells MC, the source side select transistor STS, and the source side select transistor STSb are connected in series between a bit line BL and a source line SL. Hereinafter, the drain side select transistor STD, the source side select transistor STS, and the source side select transistor STSb may be simply referred to as select transistors (STD, STS, STSb).

[0036] The memory cells MC are field-effect transistors. The memory cells MC include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage film. The memory cells MC store one or more bits of data. A word line WL is connected to each of the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all the memory strings MS in one memory block BLK.

[0037] The selection transistors (STD, STS, STSb) are field-effect transistors. The selection transistors (STD, STS, STSb) include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the selection transistors (STD, STS, STSb) are connected to selection gate lines (SGD, SGS, SGSb), respectively. One drain side selection gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK. One source side selection gate line SGSb is commonly connected to all memory strings MS in one memory block BLK.

[0038] [Circuit configuration of voltage generation circuit VG] The voltage generating circuit VG (FIG. 4) includes a plurality of voltage generating units vg1 to vg3, as shown in FIG. 6. The voltage generating units vg1 to vg3 generate voltages of a predetermined magnitude in a read operation, a write operation, and an erase operation, and supply the voltage to the voltage supply line L. VG For example, the voltage generation unit vg1 outputs a program voltage used in a write operation. The voltage generation unit vg2 outputs a read pass voltage V READ , standby voltage V READ_WAIT The voltage generation unit vg1 outputs a write pass voltage used in a write operation. The voltage generation unit vg3 outputs a read voltage, which will be described later, in a read operation. The voltage generation unit vg3 outputs a verify voltage, which will be described later, in a write operation. The voltage generation units vg1 to vg3 may be, for example, boost circuits such as charge pump circuits, or may be drop circuits such as regulators. These drop circuits and boost circuits are connected to the voltage supply line L P The voltage supply line L P is the power supply voltage V CC or ground voltage V SS (Figure 4) are provided. These voltage supply lines L P is connected to, for example, the pad electrode P described with reference to Figures 2 and 3. The operating voltage output from the voltage generating circuit VG is adjusted appropriately in accordance with a control signal from the sequencer SQC.

[0039] The charge pump circuit 32 (FIG. 7) in the voltage generating circuit VG includes a voltage output circuit 32a, a voltage dividing circuit 32b, and a comparator 32c. The voltage output circuit 32a is connected to a voltage supply line L VG Voltage V OUT The voltage divider circuit 32b outputs the voltage supply line L VG The comparator 32c is connected to the voltage V OUT ´ and the reference voltage V REF The feedback signal FB is output to the voltage output circuit 32a in accordance with the magnitude relationship between the input voltage FB and the output voltage FB.

[0040] 8, the voltage output circuit 32a includes a plurality of transistors 32a2a and 32a2b. The plurality of transistors 32a2a and 32a2b are connected to a voltage supply line L VG and voltage supply line L P The voltage supply line L shown in the figure is alternately connected between P is the power supply voltage V CC is supplied. The gate electrodes of the plurality of transistors 32a2a and 32a2b connected in series are connected to the drain electrodes of the respective transistors and the capacitor 32a3. The voltage output circuit 32a further includes an AND circuit 32a4, a level shifter 32a5a, and a level shifter 32a5b. The AND circuit 32a4 outputs a logical sum of the clock signal CLK and the feedback signal FB. The level shifter 32a5a boosts and outputs the output signal of the AND circuit 32a4. The output terminal of the level shifter 32a5a is connected to the gate electrode of the transistor 32a2a via the capacitor 32a3. The level shifter 32a5b boosts and outputs the inverted signal of the output signal of the AND circuit 32a4. The output terminal of the level shifter 32a5b is connected to the gate electrode of the transistor 32a2b via the capacitor 32a3.

[0041] When the feedback signal FB is in the “H” state, the AND circuit 32a4 outputs the clock signal CLK. VG From voltage supply line L P Electrons are transferred to the voltage supply line L VG On the other hand, when the feedback signal FB is in the "L" state, the clock signal CLK is not output from the AND circuit 32a4. VG The voltage at does not increase.

[0042] 7, the voltage dividing circuit 32b includes a resistive element 32b2 and a variable resistive element 32b4. The resistive element 32b2 is connected to the voltage supply line L VG and the voltage division terminal 32b1. The variable resistance element 32b4 is connected between the voltage division terminal 32b1 and the voltage supply line L P This voltage supply line L P The ground voltage VSS The resistance value of the variable resistance element 32b4 is supplied with the operating voltage control signal V CTRL Therefore, the voltage V of the voltage dividing terminal 32b1 OUT The magnitude of the operating voltage control signal V CTRL It can be adjusted according to the requirements.

[0043] 9, the variable resistance element 32b4 includes a plurality of current paths 32b5. The plurality of current paths 32b5 are connected to the voltage division terminal 32b1 and the voltage supply line L P The current paths 32b5 each include a resistor element 32b6 and a transistor 32b7 connected in series. The resistor elements 32b6 in the current paths 32b5 may have different resistance values. The gate electrodes of the transistors 32b7 are connected in parallel to the operation voltage control signal V CTRL Different bits of the first and second inputs are input to the variable resistance element 32b4. The variable resistance element 32b4 may have a current path 32b8 that does not include the transistor 32b7.

[0044] 7, the comparator 32c outputs a feedback signal FB. The feedback signal FB is, for example, a voltage V OUT ´ is the reference voltage V REF The feedback signal FB is in the “L” state when the voltage V OUT ´ is the reference voltage V REF If it is smaller than this, it will be in the “H” state.

[0045] [Circuit configuration of row decoder RD] As shown in FIG. 6, the row decoder RD includes a block decoder BLKD, a word line decoder WLD, a driver circuit DRV, and an address decoder (not shown).

[0046] The block decoder BLKD includes a plurality of block decode units blkd. The plurality of block decode units blkd correspond to a plurality of memory blocks BLK in the memory cell array MCA. The block decode unit blkd includes a plurality of transistors TBLK A plurality of transistors T BLK corresponds to a plurality of word lines WL in the memory block BLK. BLK is, for example, a field effect NMOS transistor. BLK The drain electrode of the transistor T is connected to the word line WL. BLK The source electrode of the transistor T is connected to the wiring CG. The wiring CG is connected to all the block decode units blkd in the block decoder BLKD. BLK The gate electrodes of the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T20, T21, T22, T30, T41, T19, T22, T31, T42, T19, T23, T18, T24, T19, T25, T30, T41, T19, T26, T18, T27, T31, T42, T19, T28, T19, T29, T30, T41, T19, T21, T31, T42, T19, T22, T19, T23, T31, T42, T19, T24, T18, T25, T31, T42, T19, T BLK is connected to.

[0047] In a read operation, a write operation, etc., for example, the voltage of one signal line BLKSEL corresponding to a block address in the address register ADR (FIG. 4) is in the “H” state, and the voltages of the other signal lines BLKSEL are in the “L” state. For example, a predetermined drive voltage having a positive magnitude is supplied to one signal line BLKSEL, and a ground voltage V SS As a result, all word lines WL in one memory block BLK corresponding to this block address are electrically connected to all wirings CG, and all word lines WL in the other memory blocks BLK are in a floating state.

[0048] The word line decoder WLD includes a plurality of word line decode units wld. The plurality of word line decode units wld correspond to a plurality of memory cells MC in the memory string MS. In the illustrated example, the word line decode unit wld includes two transistors T WLS ,T WLU The transistor T WLS ,T WLU is, for example, a field effect NMOS transistor. WLS ,T WLUThe drain electrode of the transistor T is connected to the wiring CG. WLS The source electrode of the wiring CG S Transistor T WLU The source electrode of the wiring CG U Transistor T WLS The gate electrode of the signal line WLSEL S Transistor T WLU The gate electrode of the signal line WLSEL U Signal line WLSEL is connected to S is one of the transistors T included in each word line decode unit wld. WLS A plurality of signal lines WLSEL are provided corresponding to the U The other transistor T included in each word line decode unit wld WLU A plurality of such sensors are provided corresponding to the number of sensors.

[0049] In a read operation, a write operation, etc., for example, a signal line WLSEL corresponding to one word line decode unit wld corresponding to a page address in the address register ADR (FIG. 4) is S The voltage of the WLSEL U The voltage of the signal line WLSEL corresponding to the other word line decode units wld is in the “L” state. S The voltage of the WLSEL U The voltage of the wiring CG S The selected word line WL S A voltage corresponding to the wiring CG U The unselected word lines WL U As a result, a voltage corresponding to the selected word line WL is supplied to one word line WL corresponding to the page address. S In addition, a voltage corresponding to the unselected word line WL is supplied to the other word lines WL. U A voltage corresponding to

[0050] The driver circuit DRV is, for example, a transistor T DRV1 ~TDRV6 The transistor T DRV1 ~T DRV6 is, for example, a field effect NMOS transistor. DRV1 ~T DRV4 The drain electrode of the S Transistor T DRV5 ,T DRV6 The drain electrode of the U Transistor T DRV1 The source electrode of the voltage supply line L VG1 , and is connected to the output terminal of the voltage generating unit vg1 via the transistor T DRV2 ,T DRV5 The source electrode of the voltage supply line L VG2 , and is connected to the output terminal of the voltage generating unit vg2 via the transistor T DRV3 The source electrode of the voltage supply line L VG3 , and is connected to the output terminal of the voltage generating unit vg3 via the transistor T DRV4 ,T DRV6 The source electrode of the voltage supply line L P 2 and 3. DRV1 ~T DRV6 The gate electrodes of these transistors are connected to signal lines VSEL1 to VSEL6, respectively.

[0051] In the read operation, the write operation, etc., for example, the wiring CG S The voltage of one of the signal lines VSEL1 to VSEL4 corresponding to the wiring CG U The voltage of one of the two corresponding signal lines VSEL5 and VSEL6 goes to the "H" state, and the voltage of the other goes to the "L" state.

[0052] An address decoder (not shown) sequentially refers to the row address RA of the address register ADR (FIG. 4) in accordance with a control signal from the sequencer SQC (FIG. 4). The row address RA includes the above-mentioned block address and page address. The address decoder uses the above-mentioned signal lines BLKSEL and WLSELS ,WLSEL U The voltage is controlled to be in the “H” or “L” state.

[0053] In the example of FIG. 6, the row decoder RD is provided with one block decode unit blkd for each memory block BLK. However, this configuration can be changed as appropriate. For example, one block decode unit blkd may be provided for two or more memory blocks BLK.

[0054] [Circuit configuration of the sense amplifier module SAM] The sense amplifier module SAM (FIG. 4) includes a plurality of sense amplifier units SAU, as shown in FIG. 10, for example. The plurality of sense amplifier units SAU correspond to a plurality of bit lines BL. Each of the sense amplifier units SAU includes a sense amplifier SA, a wiring LBUS, and latch circuits SDL, DL0 to DLn. L (n L A charging transistor 55 (FIG. 11) for precharging is connected to the line LBUS. The line LBUS is connected to the line DBUS via a switch transistor DSW.

[0055] 11, the sense amplifier SA includes a sense transistor 41. The sense transistor 41 discharges the charge on the line LBUS in response to the current flowing through the bit line BL. The source electrode of the sense transistor 41 is connected to the ground voltage V SS The sense node SEN is connected to a voltage supply line through which a voltage is supplied. The drain electrode is connected to the wiring LBUS via a switch transistor 42. The gate electrode is connected to the bit line BL via a sense node SEN, a discharge transistor 43, a node COM, a clamp transistor 44, and a voltage-resistant transistor 45. The sense node SEN is connected to an internal control signal line CLKSA via a capacitor 48.

[0056] The sense amplifier SA also includes a voltage transfer circuit. The voltage transfer circuit transfers the node COM and the sense node SEN to a voltage V DD The voltage supply line or voltage V SRC The voltage transfer circuit selectively connects the node N1 to a voltage supply line to which voltage V is supplied. The voltage transfer circuit includes a node N1, a charging transistor 46, a charging transistor 49, a charging transistor 47, and a discharging transistor 50. The charging transistor 46 is connected between the node N1 and a sense node SEN. The charging transistor 49 is connected between the node N1 and a node COM. The charging transistor 47 is connected between the node N1 and a voltage V DD A discharge transistor 50 is connected between the node N1 and the voltage supply line to which the voltage V SRC The gate electrodes of the charge transistor 47 and the discharge transistor 50 are commonly connected to a node INV_S of the latch circuit SDL.

[0057] The sense transistor 41, the switch transistor 42, the discharge transistor 43, the clamp transistor 44, the charge transistor 46, the charge transistor 49, and the discharge transistor 50 are, for example, enhancement type NMOS transistors. The voltage-resistant transistor 45 is, for example, a depletion type NMOS transistor. The charge transistor 47 is, for example, a PMOS transistor.

[0058] Also, the gate electrode of the switch transistor 42 is connected to a signal line STB. The gate electrode of the discharge transistor 43 is connected to a signal line XXL. The gate electrode of the clamp transistor 44 is connected to a signal line BLC. The gate electrode of the voltage-resistant transistor 45 is connected to a signal line BLS. The gate electrode of the charge transistor 46 is connected to a signal line HLL. The gate electrode of the charge transistor 49 is connected to a signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to a sequencer SQC.

[0059] The latch circuit SDL includes nodes LAT_S and INV_S, an inverter 51, an inverter 52, a switch transistor 53, and a switch transistor 54. The inverter 51 includes an output terminal connected to the node LAT_S and an input terminal connected to the node INV_S. The inverter 52 includes an input terminal connected to the node LAT_S and an output terminal connected to the node INV_S. The switch transistor 53 is provided in a current path between the node LAT_S and a wiring LBUS. The switch transistor 54 is provided in a current path between the node INV_S and a wiring LBUS. The switch transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of the switch transistor 53 is connected to the sequencer SQC via a signal line STL. The gate electrode of the switch transistor 54 is connected to the sequencer SQC via a signal line STI.

[0060] Latch circuits DL0 to DLn L The latch circuits DL0 to DLn are configured in almost the same manner as the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is electrically connected to the gate electrodes of the charge transistor 47 and the discharge transistor 50 in the sense amplifier SA. L differs from the latch circuit SDL in this respect.

[0061] The switch transistor DSW is, for example, an NMOS transistor. The switch transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switch transistor DSW is connected to the sequencer SQC via a signal line DBS.

[0062] As shown in FIG. 10, the above-mentioned signal lines STB, HLL, XXL, BLX, BLC, and BLS are commonly connected among all the sense amplifier units SAU included in the sense amplifier module SAM. DD The voltage supply line and voltage V SRCThe voltage supply lines to which the latch circuits DL0 to DLn are supplied are commonly connected to all the sense amplifier units SAU included in the sense amplifier module SAM. Also, the signal lines STI and STL of the latch circuits SDL are commonly connected to all the sense amplifier units SAU included in the sense amplifier module SAM. Similarly, the latch circuits DL0 to DLn L The signal lines TI0 to TIn correspond to the signal lines STI and STL in L ,TL0~TLn L are commonly connected among all the sense amplifier units SAU included in the sense amplifier module SAM. Meanwhile, a plurality of the signal lines DBS are provided corresponding to all the sense amplifier units SAU included in the sense amplifier module SAM.

[0063] [Circuit configuration of cache memory CM] The cache memory CM (FIG. 4) includes a plurality of latch circuits. The plurality of latch circuits are connected to the latch circuits in the sense amplifier module SAM via wiring DBUS. Data DAT included in the plurality of latch circuits is transferred sequentially to the sense amplifier module SAM or the input / output control circuit I / O.

[0064] In addition, a decode circuit and a switch circuit (not shown) are connected to the cache memory CM. The decode circuit decodes the column address CA held in the address register ADR. The switch circuit connects the latch circuit corresponding to the column address CA to the bus DB (FIG. 4) in response to the output signal of the decode circuit.

[0065] [Circuit configuration of sequencer SQC] The sequencer SQC (Figure 4) reads the command data D held in the command register CMR. CMD In accordance with the above, the sequencer SQC outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generating circuit VG. In addition, the sequencer SQC outputs status data D ST is output to the status register STR.

[0066] The sequencer SQC also generates a ready / busy signal and outputs it to the terminal RY / / BY. During the period when the voltage of the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is basically prohibited. During the period when the voltage of the terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted. The terminal RY / / BY is realized by, for example, the pad electrode P described with reference to FIGS. 2 and 3.

[0067] [Circuit configuration of input / output control circuit I / O] The input / output control circuit I / O includes data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS, / DQS, a plurality of input circuits, a plurality of output circuits, a shift register, and a buffer circuit. The plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are each connected to a power supply voltage V CCQ and ground voltage V SS is connected to the terminal supplied with

[0068] Data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS, / DQS, and power supply voltage V CCQ The terminals to which the data are supplied are realized by, for example, the pad electrodes P described with reference to Figures 2 and 3. Data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in response to an internal control signal from the logic circuit CTR. Data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit in response to an internal control signal from the logic circuit CTR.

[0069] The input circuits include, for example, a comparator connected to any one of the data signal input / output terminals DQ0 to DQ7 or both of the toggle signal input / output terminals DQS, / DQS. The output circuits include, for example, an OCD (Off Chip Driver) circuit connected to any one of the data signal input / output terminals DQ0 to DQ7 or either of the toggle signal input / output terminals DQS, / DQS.

[0070] [Circuit configuration of logic circuit CTR] The logic circuit CTR (FIG. 4) receives external control signals from the controller die CD via the external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit I / O in response to the external control signals. Note that the external control terminals / CEn, CLE, ALE, / WE, RE, and / RE are realized by, for example, the pad electrodes P described with reference to FIGS. 2 and 3.

[0071] [Memory Die MD Structure] FIG. 12 is a schematic plan view of the memory die MD. FIG. 13 is a schematic perspective view of the memory die MD. Note that FIG. 13 is a diagram for explaining a schematic configuration of the memory die MD, and does not show the number, shape, arrangement, etc. of specific configurations. FIG. 14 is a schematic enlarged view of a portion indicated by A in FIG. 12. FIG. 15 is a schematic enlarged view of a portion indicated by B in FIG. 13. Note that the bit lines BL are omitted in a part of FIG. 14. Also, the drain side selection gate lines SGD are omitted in a part of FIG. 14.

[0072] The memory die MD includes a semiconductor substrate 100, as shown in FIG. 12. In the illustrated example, the semiconductor substrate 100 includes four memory cell array regions R aligned in the X and Y directions. MCA will be established.

[0073] The memory die MD includes, for example, a semiconductor substrate 100 and a transistor layer L provided on the semiconductor substrate 100, as shown in FIG. TR and the transistor layer L TR A memory cell array layer L MCAand the memory cell array layer L MCA and a wiring layer (not shown) provided above the wiring layer.

[0074] [Structure of semiconductor substrate 100] The semiconductor substrate 100 is, for example, a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 100, an N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), a semiconductor substrate region in which the N-type well region and the P-type well region are not provided, and an insulating region 100I are provided.

[0075] [Transistor Layer L TR Structure of For example, as shown in FIG. 13, a wiring layer GC is provided on the upper surface of the semiconductor substrate 100 via an insulating layer. The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. These electrodes gc function as gate electrodes of a plurality of transistors Tr constituting the peripheral circuit PC, and the other electrodes of a plurality of capacitors, etc. These electrodes gc are each connected to a contact CS. The contact CS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, these contacts CS are connected to a plurality of wirings included in the wiring layers D0, D1, and D2. These wirings may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0076] [Memory cell array layer L MCA Structure of For example, as shown in FIG. MCA14, a plurality of memory blocks BLK arranged in the Y direction are provided. The memory blocks BLK include a plurality of string units SU arranged in the Y direction. An inter-block insulating layer ST made of silicon oxide (SiO2) or the like is provided between two memory blocks BLK adjacent to each other in the Y direction. An inter-string unit insulating layer SHE made of silicon oxide (SiO2) or the like is provided between two string units SU adjacent to each other in the Y direction, as shown in FIG. 14, for example.

[0077] As shown in FIG. 13, the memory block BLK includes a plurality of conductive layers 110 aligned in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0078] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 (FIG. 15) such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction. A contact electrode CC extending in the Z direction is provided at one end of the conductive layer 110 in the X direction.

[0079] 13, a conductive layer 111 is provided below the conductive layer 110. The conductive layer 111 may include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). In addition, an insulating layer 101 is provided between the conductive layer 111 and the conductive layer 110.

[0080] A conductive layer 112 is provided below the conductive layer 111. The conductive layer 112 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 112 may include, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. An insulating layer 101 is provided between the conductive layer 112 and the conductive layer 111.

[0081] The conductive layer 112 functions as a source line SL (FIG. 5). The conductive layer 112 is, for example, MCA This is provided commonly to all memory blocks BLK included in FIG.

[0082] The conductive layer 111 functions as a gate electrode of a source side select gate line SGSb (FIG. 5) and a plurality of source side select transistors STSb connected thereto. The conductive layer 111 is electrically independent for each memory block BLK.

[0083] Among the multiple conductive layers 110, one or more conductive layers 110 located in the lowest layer function as a source side select gate line SGS (FIG. 5) and the gate electrodes of multiple source side select transistors STS connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0084] Moreover, the multiple conductive layers 110 located above the word lines WL function as gate electrodes of the multiple memory cells MC (FIG. 5) connected thereto. The multiple conductive layers 110 are electrically independent for each memory block BLK.

[0085] Moreover, one or more conductive layers 110 located above the drain side select gate line SGD function as gate electrodes of the drain side select transistors STD (FIG. 5) connected thereto. SGD For example, as shown in FIG. 14, the width Y of the other conductive layer 110 in the Y direction WL14, the above-mentioned inter-string unit insulating layer SHE is provided between two conductive layers 110 adjacent to each other in the Y direction. Each of the multiple conductive layers 110 is electrically independent for each string unit SU.

[0086] The semiconductor layers 120 are arranged in a predetermined pattern in the X and Y directions, for example, as shown in FIG. 14. The semiconductor layers 120 function as channel regions of a plurality of memory cells MC and select transistors (STD, STS, STSb) included in one memory string MS (FIG. 5). The semiconductor layer 120 is, for example, a semiconductor layer made of polycrystalline silicon (Si). The semiconductor layer 120 has a substantially cylindrical shape, for example, as shown in FIG. 13, and an insulating layer 125 made of silicon oxide or the like is provided in the center portion.

[0087] The outer peripheral surface of the semiconductor layer 120 is surrounded by a plurality of conductive layers 110 and 111, and faces these plurality of conductive layers 110 and 111. The lower end of the semiconductor layer 120 is connected to the conductive layer 112. The upper end of the semiconductor layer 120 is connected to the bit line BL via contacts Ch and Vy. The bit line BL extends in the Y direction and is aligned in the X direction.

[0088] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110, as shown in FIG. 15, for example. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a film capable of storing charges such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 except for the contact portion between the semiconductor layer 120 and the conductive layer 112.

[0089] 15 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0090] [Threshold voltage of memory cell MC] Next, with reference to FIG. 16, the threshold voltage of the memory cell MC will be described.

[0091] Fig. 16(a) is a schematic histogram for explaining the threshold voltage of a memory cell MC in which 3 bits of data are recorded. The horizontal axis indicates the voltage of the word line WL, and the vertical axis indicates the number of memory cells MC. Fig. 16(b) is a table showing an example of the relationship between the threshold voltage of a memory cell MC in which 3 bits of data are recorded and the data recorded therein. Fig. 16(c) is a table showing another example of the relationship between the threshold voltage of a memory cell MC in which 3 bits of data are recorded and the data recorded therein.

[0092] In the example of FIG. 16(a), the threshold voltage of the memory cell MC is controlled to eight different states. The threshold voltage of the memory cell MC controlled to the Er state is equal to or lower than the erase verify voltage V VFYEr For example, the threshold voltage of the memory cell MC controlled to the A state is smaller than the verify voltage V VFYA Larger than the verify voltage V VFYB For example, the threshold voltage of the memory cell MC controlled to the B state is smaller than the verify voltage V VFYB Larger than the verify voltage V VFYC Similarly, the threshold voltages of the memory cells MC controlled to the C state to the F state are smaller than the verify voltage V VFYC ~Verify voltage V VFYF Larger than the verify voltage V VFYD ~Verify voltage V VFYG For example, the threshold voltage of the memory cell MC controlled to the G state is smaller than the verify voltage V VFYG Larger than the read pass voltage VREAD Less than.

[0093] In the example of FIG. 16(a), a read voltage V CGAR In addition, a read voltage V CGBR Similarly, between the threshold distribution corresponding to the B state and the threshold distribution corresponding to the C state, and between the threshold distribution corresponding to the F state and the threshold distribution corresponding to the G state, read voltages V CGCR ~Read voltage V CGGR is set.

[0094] For example, the Er state corresponds to the lowest threshold voltage. A memory cell MC in the Er state is, for example, a memory cell MC in an erased state. For example, data "111" is assigned to a memory cell MC in the Er state.

[0095] The A state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. For example, data "101" is assigned to the memory cells MC in the A state.

[0096] Moreover, the B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the above-mentioned A state. For example, data "001" is assigned to the memory cells MC in the B state.

[0097] Similarly, the C-state to G-state in the figure correspond to threshold voltages higher than the threshold voltages corresponding to the B-state to F-state. For example, data “011”, “010”, “110”, “100”, and “000” are assigned to the memory cells MC in these states.

[0098] In the case of the allocation illustrated in FIG. 16(b), the lower bit data is read at one read voltage V CGDRThe middle bit data can be read by three read voltages V CGAR ,V CGCR ,V CGFR The upper bit data can be read by three read voltages V CGBR ,V CGER ,V CGGR It can be distinguished by:

[0099] The number of bits of data recorded in the memory cells MC, the number of states, and the allocation of data to each state can be changed as appropriate.

[0100] For example, in the case of the allocation illustrated in FIG. 16(c), the lower bit data is read at one read voltage V CGDR The middle bit data can be read by two read voltages V CGBR ,V CGFR The upper bit data can be read by four read voltages V CGAR ,V CGCR ,V CGER ,V CGGR It can be distinguished by:

[0101] [Read operation] Next, the read operation of the semiconductor memory device according to this embodiment will be described.

[0102] FIG. 17 is a timing chart for explaining the read operation.

[0103] 17 illustrates a command set CS0 input to the memory die MD during a read operation. This command set CS0 includes data C101, A101, A102, A103, A104, A105, and data C102.

[0104] At timing t101, the controller die CD transmits command data D to the memory die MD. CMD(FIG. 4) and input data C101. That is, the voltages of the data signal input / output terminals DQ0 to DQ7 are set to "H" or "L" according to each bit of the data C101, "H" is input to the external control terminal CLE, and "L" is input to the external control terminal ALE. In this state, the input signal of the toggle signal input / output terminals DQS, / DQS is switched, or the external control terminal / WE is raised from "L" to "H". Data C101 is a command input at the start of a read operation.

[0105] At timing t102, the controller die CD transmits address data D to the memory die MD. ADD Data A101 is input as (FIG. 4). That is, the voltage of the data signal input / output terminals DQ0 to DQ7 is set to "H" or "L" according to each bit of the data A101, "L" is input to the external control terminal CLE, and "H" is input to the external control terminal ALE. In this state, the input signal of the toggle signal input / output terminals DQS, / DQS is switched, or the external control terminal / WE is raised from "L" to "H". The data A101 is part of the column address CA.

[0106] At timing t103, the controller die CD transmits address data D to the memory die MD. ADD Data A102 is input as shown in FIG. 4. Data A102 is a part of the column address CA.

[0107] At timing t104, the controller die CD transmits address data D to the memory die MD. ADD Data A103 is input as (FIG. 4). Data A103 is a part of row address RA. Data A103 includes, for example, a block address and a page address. The block address is data that specifies a memory block BLK. The page address is data that specifies a string unit SU and a word line WL.

[0108] At timing t105, the controller die CD transmits address data D to the memory die MD. ADD(FIG. 4) Data A104 is input as the row address RA. Data A104 includes, for example, a block address and a page address.

[0109] At timing t106, the controller die CD transmits address data D to the memory die MD. ADD Data A105 is input as shown in FIG. 4. The data A105 includes a chip address. The chip address is data for identifying one memory die MD from among multiple memory dies MD controlled by the controller die CD.

[0110] At timing t107, the controller die CD transmits command data D to the memory die MD. CMD Data C102 is input as (FIG. 4). Data C102 is a command indicating that input of command set CS0 relating to the read operation has ended.

[0111] At timing t108, the voltage of the terminal RY / / BY changes from the “H” state to the “L” state, and access to the memory die MD is prohibited. Also, a read operation is executed in the memory die MD.

[0112] At timing t109, the read operation on the memory die MD ends. Also, the voltage of the terminal RY / / BY changes from the “L” state to the “H” state, and access to the memory die MD is permitted.

[0113] Fig. 18 is a schematic cross-sectional view for explaining the read operation, and Fig. 19 is a timing chart for explaining the read operation.

[0114] In the following description, the word line WL that is the object of the operation is referred to as the selected word line WL S and the other word lines WL are called unselected word lines WL U In the following description, the selected word line WL SAn example will be described in which a read operation is performed on a memory cell connected to the selected page PG (hereinafter, sometimes referred to as a "selected memory cell MC"). In the following description, a configuration including such a plurality of selected memory cells MC may be referred to as a selected page PG.

[0115] In the following description, data is assigned to each memory cell MC in the manner described with reference to FIG. 16(c), and an example will be described in which data of the middle bit is read.

[0116] At timing t121 of the read operation, for example, as shown in FIG. S Read pass voltage V READ is supplied to the selected word line WL S and the two adjacent unselected word lines WL U Read pass voltage V READK , and supplies the other unselected word lines WL U Read pass voltage V READ The read pass voltage V READK is the read pass voltage V READ This causes all memory cells MC to be in the ON state. Also, the voltage V SG Supply voltage V SG has a size such that an electron channel is formed in the channel region of the select transistor (STD, STS, STSb), thereby turning the select transistor (STD, STS, STSb) into an ON state.

[0117] At timing t122 ​​of the read operation, the selected word line WL S For example, the read voltage V CGBR As a result, as shown in FIG. 18, for example, some of the selected memory cells MC are turned on, and the remaining selected memory cells MC are turned off.

[0118] At timing t122, for example, the bit line BL is charged. For example, the latch circuit SDL in FIG. 11 is caused to latch “H”, and the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to “L, L, H, H, H, H, H”. As a result, the bit line BL and the sense node SEN are applied with a voltage V DD is supplied to the source line SL (FIG. 5), and charging of these starts. SRC Supply voltage V SRC For example, the ground voltage V SS The voltage V SRC For example, the ground voltage V SS Slightly larger than the voltage V DD A voltage significantly smaller than this may also be used.

[0119] During the read operation from timing t123 to timing t124, as shown in FIG. 19, the sense amplifier module SAM (FIG. 11) detects the ON / OFF state of the memory cell MC and obtains data indicating the state of the memory cell MC. For example, in a state where a predetermined bit line voltage is supplied to the bit line BL (FIG. 5), the sense node of the sense amplifier SA (FIG. 11) is made conductive with the bit line BL for a certain period of time. After the sense operation is performed, the sense transistor is made conductive with the line LBUS (FIG. 11), and the charge of the line LBUS is discharged or maintained. In addition, any one of the latch circuits in the sense amplifier unit SAU is made conductive with the line LBUS, and the data of the line LBUS is latched by this latch circuit.

[0120] At timing t125 of the read operation, the selected word line WL S For example, the read voltage V CGFR As a result, some of the selected memory cells MC are turned ON, and the remaining selected memory cells MC are turned OFF.

[0121] At timing t126 to timing t127 of the read operation, as shown in FIG. 19, for example, the sense amplifier module SAM (FIG. 11) detects the ON / OFF state of the memory cell MC and obtains data indicating the state of this memory cell MC.

[0122] At timing t127 of the read operation, the selected word line WL S Read pass voltage V READ is supplied to turn all memory cells MC into the ON state.

[0123] At timing t128 of the read operation, the selected word line WL S , unselected word lines WL U and the select gate lines (SGD, SGS, SGSb) are connected to the ground voltage V SS supplies.

[0124] In the read operation, the data indicating the state of the memory cell MC is subjected to arithmetic operations such as AND and OR, thereby calculating the data recorded in the memory cell MC. This data is transferred to the cache memory CM (FIG. 4) via the wiring LBUS (FIG. 11), the switch transistor DSW, and the wiring dbus.

[0125] [Operating current during read operation] As described with reference to FIG. 19, during the read operation from timing t121 to timing t122, all the word lines WL included in the selected memory block BLK are supplied with the read pass voltage V READ Here, as the integration density of semiconductor memory devices increases, the number of conductive layers 110 (FIG. 13) stacked in the Z direction is increasing. Accordingly, the amount of charge required to charge the word line WL is increasing, and the power supply voltage V CCThe operating current flowing through the pad electrode P to which the charge is supplied is increasing. This may lead to an increase in power consumption and heat generation. In order to reduce this operating current, for example, it is possible to lengthen the time from timing t121 to timing t122 ​​to reduce the amount of charge moving per unit time. However, in such a case, the time required for the read operation may become longer.

[0126] [Read standby mode] Next, the read standby mode according to this embodiment will be described with reference to Fig. 20 and Fig. 21. Fig. 20 and Fig. 21 are schematic timing charts for explaining the read standby mode according to this embodiment.

[0127] In addition, in FIG. 20 and FIG. 21, five word lines WL are arranged in the Z direction. k ~Word line WL k+4 In the examples of FIGS. 20 and 21, the word line WL k+2 A read operation is performed on the selected page PG corresponding to the word line WL k+3 A read operation is executed on the selected page PG corresponding to the selected page PG.

[0128] The operations from timing t121 to timing t128 in FIG. 20 are executed in substantially the same manner as the operations from timing t121 to timing t128 in FIG.

[0129] However, in the example of Figure 20, at timing t108, the controller die CD inputs a command set CS1 (Figure 24) to be described later to the memory die MD instead of the command set CS0 described above. Also, in the example of Figure 20, at timing t128, the word line WL is supplied with a ground voltage V SS Instead of the standby voltage V READ_WAIT Supply the standby voltage V READ_WAIT For example, the read pass voltage V READ is smaller than the ground voltage V SS and the above-mentioned voltage V SRCMoreover, the semiconductor memory device according to this embodiment is set to a read standby mode at timing t129.

[0130] 19, at timing t108, the voltage of the internal signal / Cash Busy falls from "H" to "L". At timing t129, the voltage of the internal signal / Cash Busy rises from "L" to "H". The internal signal / Cash Busy can be read by a status read or the like.

[0131] In the read standby mode according to this embodiment, a standby voltage V READ_WAIT Therefore, in the read standby mode according to this embodiment, a plurality of transistors provided in the current path between the word line WL and the voltage generating unit vg2 (FIG. 6) are turned on. For example, in the read standby mode according to this embodiment, the voltage of the signal line BLKSEL is maintained in the “H” state even after the read operation is completed. Also, in the read standby mode according to this embodiment, the voltage of the terminal RY / / BY is maintained in the “L” state even after the read operation is completed. The voltage of the internal signal / Cash Busy is maintained in the “H” state.

[0132] The operations from timing t131 to timing t139 in FIG. 20 are executed in substantially the same manner as the operations from timing t121 to timing t129.

[0133] However, in the example of FIG. 20, the voltage of the word line WL is set to the ground voltage V SS to read pass voltage V READ Not up to the standby voltage V READ_WAIT to read pass voltage V READ Charge until

[0134] In the example of FIG. 20, at timing t138, the word line WL is supplied with a standby voltage V READ_WAIT Instead of the ground voltage VSS 20, after the read operation is performed from timing t131 to timing t139, the semiconductor memory device is not set to the read standby mode.

[0135] The operation illustrated in FIG. 21 is basically executed in the same manner as the operation described with reference to FIG.

[0136] However, in the example of Figure 21, between timing t129 and timing t131, the controller die CD inputs a command set CS1 (Figure 24) to be described later to the memory die MD instead of the command set CS0 described above. Also, in the example of Figure 21, at timing t138, the word line WL is supplied with a ground voltage V SS Instead of the standby voltage V READ_WAIT In addition, the semiconductor memory device is set to a read standby mode at timing t139.

[0137] In the example of FIG. 19, the voltage of the word line WL is set to the ground voltage V SS to read pass voltage V READ ,V READK At the timing t127 of the read operation, the word line WL is charged to the ground voltage V SS On the other hand, in the examples of FIGS. 20 and 21, at timing t127 of the read operation, the word line WL is supplied with the ground voltage V SS does not supply a standby voltage higher than this, V READ_WAIT When the next read operation is started, the voltage of the word line WL is supplied to the standby voltage V READ_WAIT to read pass voltage V READ or the read pass voltage V READK Charge until

[0138] According to this method, when performing multiple read operations on the same memory block BLK, it is possible to reduce the amount of charge required to charge the word line WL, thereby reducing at least one of the operating current and the time required for the read operation.

[0139] For example, when a read operation is performed twice using the method described with reference to FIG. 19, as illustrated in FIG. 22, the maximum and average values ​​of the operating current in the second read operation will be approximately the same as the maximum and average values ​​of the operating current in the first read operation.

[0140] On the other hand, when the read operation is performed twice using the method described with reference to FIG. 20 or FIG. 21, it is possible to make the maximum and average values ​​of the operating current in the second read operation smaller than the maximum and average values ​​of the operating current in the first read operation, as illustrated in FIG. 23.

[0141] On the other hand, when the read operation is performed twice using the method described with reference to FIG. 20 or FIG. 21, as illustrated in FIG. 24, it is possible to reduce the time required for charging the word line WL while keeping the maximum and average values ​​of the operating current in the second read operation approximately the same as the maximum and average values ​​of the operating current in the first read operation, thereby reducing the time required for the read operation.

[0142] [Read standby mode setting] There are various methods for setting the semiconductor memory device into the read standby mode.

[0143] As a method for setting the semiconductor memory device to the read standby mode, for example, command data D CMD A method using (Figure 4) can be considered.

[0144] Command Data D CMDAs a method using the above, for example, it is possible to adjust the command set used in the read operation. For example, as described with reference to FIG. 19, when the semiconductor memory device is not set to the read standby mode after the read operation is executed, the command set CS0 as described with reference to FIG. 17 may be used. On the other hand, when the semiconductor memory device is set to the read standby mode after the read operation is executed, as in the first read operation described with reference to FIG. 20, the command set CS1 as described with reference to FIG. 25 may be used. The command set CS1 shown in FIG. 25 is basically the same as the command set CS0 illustrated in FIG. 17. However, the command set CS1 shown in FIG. 25 includes data C201. When using this command set CS1, the controller die CD transmits command data D to the memory die MD. CMD The data C201 is input as the input data C201. Note that the data C201 is input before the data C101.

[0145] Also, command data D CMD As an example of a method using the predetermined command data D CMD For example, in the example of FIG. 26, at timing t208, the controller die CD sends the command data D CMD In addition, the memory die MD is set to a read standby mode.

[0146] As a method for setting the semiconductor memory device to the read standby mode, for example, a method using a parameter can be considered. For example, when a predetermined parameter is set to an active state, the memory die MD may be automatically set to the read standby mode after the read operation is performed.

[0147] Also, as a method of setting the semiconductor memory device to the read standby mode, for example, a method using a pad electrode P is considered. For example, when a command set CS0 instructing a read operation is input in a state where a specific pad electrode P is inputted at "H", the memory die MD may be set to the read standby mode after the read operation is executed. Also, when a command set CS0 instructing a read operation is input in a state where this pad electrode P is inputted at "L", the memory die MD may not be set to the read standby mode after the read operation is executed.

[0148] [Cancel read standby mode] There are various methods for releasing the read standby mode of the semiconductor memory device.

[0149] As a method for releasing the read standby mode of the semiconductor memory device, for example, a method for releasing the mode in response to the execution of a read operation, a write operation, or an erase operation can be considered.

[0150] For example, when the semiconductor memory device is set to a read standby mode by adjusting the command set used during a read operation as described above, the read standby mode may be released in response to the execution of a read operation corresponding to command set CS0 (a command set that does not include data C201 in FIG. 25) as described above with reference to FIG. 17.

[0151] It is also possible to cancel the read standby mode in response to input of a command set for executing a write operation or an erase operation, or a command set CS0, CS1 for executing a read operation on another memory block BLK.

[0152] As a method for releasing the read standby mode of the semiconductor memory device, for example, command data D CMD For example, a method using a predetermined command data D CMD For example, in the example of FIG. 26, at timing t130, the controller die CD sends the command data DCMD As a result, the read standby mode of the memory die MD is released.

[0153] As a method for releasing the read standby mode of the semiconductor memory device, for example, a method using a timer is considered. For example, when a predetermined time has elapsed since the memory die MD was set in the read standby mode, this is detected by the timer, and the read standby mode of the memory die MD is released accordingly.

[0154] [Second embodiment] Next, the read standby mode according to the second embodiment will be described with reference to Fig. 27. Fig. 27 is a schematic timing chart for explaining the read standby mode according to the second embodiment.

[0155] The read standby mode according to the second embodiment is basically the same as the read standby mode according to the first embodiment.

[0156] However, in the read standby mode according to the first embodiment, the signal line BLKSEL is maintained in the "H" state. On the other hand, in the read standby mode according to the second embodiment, the signal line BLKSEL is maintained in the "L" state. Also, in the second embodiment, when the semiconductor memory device selects one memory block BLK and transitions to the read standby mode, the read standby mode is maintained during that time even if a read operation, a write operation, or an erase operation is performed on another memory block BLK.

[0157] For example, in FIG. 27, signal lines BLKSELA and BLKSELB are illustrated as two signal lines BLKSEL (FIG. 6) corresponding to two memory blocks BLK. In addition, as a plurality of word lines WL included in these two memory blocks BLK, word lines WL BLKA ,W.L. BLKB In addition, these word lines WL BLKA ,W.L. BLKB 6 illustrates a wiring CG electrically connected to the

[0158] At timing t221 to timing t229, a read operation is executed on the memory block BLK corresponding to the signal line BLKSELA. The operations at timing t221 to timing t229 are executed in substantially the same manner as the operations at timing t121 to timing t129 in FIG.

[0159] However, in the example of FIG. 27, at timing t229 (the timing when the read operation ends), the voltage of the signal line BLKSELB falls from the "H" state to the "L" state.

[0160] In addition, from timing t229 to timing t201, the voltage of the wiring CG becomes the standby voltage V READ_WAIT to ground voltage V SS Here, the voltage of the signal line BLKSELA is “L” between timing t229 and timing t201. BLKA is electrically isolated from the wiring CG. BLKA The voltage is the standby voltage V READ_WAIT Moreover, the memory block BLK corresponding to the signal line BLKSELA in the semiconductor memory device according to this embodiment is set to a read standby mode at timing t201.

[0161] In the read standby mode according to this embodiment, the word line WL in the memory block BLK that is the target of the read operation is set to a standby voltage V READ_WAIT When the signal line BLKSEL is charged to 1 V, it is electrically disconnected from the wiring CG. Therefore, in the read standby mode according to this embodiment, the voltage of the signal line BLKSEL (for example, the signal line BLKSELA) is maintained in the "L" state. Also, in the read standby mode according to this embodiment, the voltage of the terminal RY / / BY is maintained in the "H" state, and the voltage of the internal signal / Cash Busy (not shown) is maintained in the "L" state.

[0162] At timing t202, the voltage of the terminal RY / / BY falls from the "H" state to the "L" state, and the voltage of the signal line BLKSELB rises from the "L" state to the "H" state.

[0163] At timing t231 to timing t239, a read operation is executed on the memory block BLK corresponding to the signal line BLKSELB. The operations at timing t231 to timing t239 are executed in the same manner as the operations at timing t121 to timing t129 in FIG.

[0164] At timing t239 (the timing when the read operation ends), the voltage of the signal line BLKSELB falls from the "H" state to the "L" state.

[0165] At timing t203, the voltage of the terminal RY / / BY rises from the "L" state to the "H" state.

[0166] At timing t204, the voltage of the terminal RY / / BY falls from the "H" state to the "L" state. Also, the voltage of the signal line BLKSELA rises from the "L" state to the "H" state. Accordingly, the word line WL BLKA The charge on the wire CG is then charged, and the voltage on the wire CG becomes the standby voltage V READ_WAIT It increases to a certain extent.

[0167] At timing t241 to timing t248, a read operation is again executed on the memory block BLK corresponding to the signal line BLKSELA. The operations at timing t241 to timing t248 are executed in substantially the same manner as the operations at timing t121 to timing t128 in FIG.

[0168] The above-mentioned methods exemplified as the method for setting and releasing the read standby mode according to the first embodiment can basically also be used as the method for setting and releasing the read standby mode according to the second embodiment. However, the read standby mode according to the second embodiment does not have to be released by, for example, inputting a command set for executing a read operation, a write operation, or an erase operation on another memory block BLK.

[0169] [Third embodiment] Next, the read standby mode according to the third embodiment will be described with reference to Fig. 28. Fig. 28 is a schematic timing chart for explaining the read standby mode according to the third embodiment.

[0170] The memory die MD described with reference to FIG. 12 has four memory cell array regions R MCA The semiconductor memory device according to the third embodiment has four memory cell arrays MCA corresponding to different memory cell array regions R MCA It is possible to execute a read operation simultaneously for a plurality of selected pages PG included in the memory 100 or execute a read operation in parallel at independent timings.

[0171] FIG. 28 illustrates such four memory cell arrays MCA as memory cell arrays MCA0, MCA1, MCA2, and MCA3.

[0172] The semiconductor memory device according to the third embodiment can independently control the setting and release of the read standby mode for such four memory cell arrays MCA. Note that in the third embodiment, the read standby mode according to the first embodiment may be used, or the read standby mode according to the second embodiment may be used.

[0173] For example, in the example of Fig. 28, the memory cell arrays MCA0, MCA1, and MCA2 are set to a read standby mode, and data is read continuously from the three memory blocks BLK corresponding to the memory cell arrays MCA0, MCA1, and MCA2. On the other hand, the memory cell array MCA3 is not set to the read standby mode, and executes a read operation as described with reference to Fig. 19.

[0174] [Other embodiments] The semiconductor memory devices according to the first to third embodiments have been described above. However, the semiconductor memory devices described above are merely examples, and the operation, configuration, and the like can be adjusted as appropriate.

[0175] For example, in the semiconductor memory devices according to the first to third embodiments, 3-bit data is recorded in each memory cell MC as described with reference to Fig. 16. However, the data recorded in the memory cell MC may be 1 bit, 2 bits, or 4 bits or more.

[0176] Here, as described with reference to FIG. 16 etc., when 3-bit data is recorded in the memory cell MC, it is necessary to supply one to four read voltages to the word line WL during the read operation. On the other hand, for example, when 1-bit data is recorded in the memory cell MC, only one read voltage is supplied to the word line WL during the read operation. In this manner, data can be read at high speed. However, when the word line WL is repeatedly charged and discharged for each read operation, the amount of charge movement per unit time increases, and there is a risk that the operating current increases. In such a case, when the read mode according to the first or second embodiment is applied, the operating current can be reduced more effectively.

[0177] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0178] 110...conductive layer, 120...semiconductor layer, 130...gate insulating film, WL...word line, MC...memory cell, MS...memory string, SU...string unit, BLK...memory block, MCA...memory cell array.

Claims

1. a memory string having a plurality of memory transistors connected in series; a plurality of first wirings connected to gate electrodes of the plurality of memory transistors; a plurality of second wirings electrically connected to the plurality of first wirings; a plurality of transistors electrically connected between the plurality of first wirings and the plurality of second wirings; a third wiring commonly connected to the gate electrodes of the plurality of transistors; Equipped with performing a first read operation in response to receiving a first set of commands; performing a second read operation in response to receiving a second set of commands; a first voltage is supplied to the second wirings during a period from the end of the first read operation to the start of the second read operation, and a second voltage that turns the transistors into an ON state is supplied to the third wirings; After the second read operation is completed, a third voltage is supplied to the second wirings, and a fourth voltage for turning the transistors into an OFF state is supplied to the third wirings; The first voltage is greater than the third voltage. Semiconductor memory device.

2. a fifth voltage is supplied to the second wirings during the first read operation and the second read operation; The fifth voltage is greater than the first voltage.

2. The semiconductor memory device according to claim 1.

3. a memory string having a plurality of memory transistors connected in series; a plurality of first wirings connected to gate electrodes of the plurality of memory transistors; a plurality of second wirings electrically connected to the plurality of first wirings; Equipped with performing a first read operation in response to receiving a first set of commands; performing a second read operation in response to receiving a second set of commands; a first voltage is supplied to the second wirings at a first timing when the first read operation is completed; a second voltage is supplied to the second wirings at a second timing when the second read operation is completed; The first voltage is greater than the second voltage. Semiconductor memory device.

4. a plurality of transistors electrically connected between the plurality of first wirings and the plurality of second wirings; a third wiring commonly connected to the gate electrodes of the plurality of transistors; Equipped with At the second timing, the voltage supplied to the third wiring is switched from a third voltage that turns the plurality of transistors to an ON state to a fourth voltage that turns the plurality of transistors to an OFF state.

4. The semiconductor memory device according to claim 3.

5. At the first timing, the voltage supplied to the third wiring is maintained at the third voltage.

5. The semiconductor memory device according to claim 4.

6. At the first timing, a voltage supplied to the third wiring is switched from the third voltage to the fourth voltage.

5. The semiconductor memory device according to claim 4.

7. a fifth voltage is supplied to at least one of the second wirings during the first read operation and the second read operation; The fifth voltage is greater than the first voltage.

7. The semiconductor memory device according to claim 3.

8. a first bonding pad electrode to which a first voltage is supplied; performing a first read operation in response to receiving a first set of commands; performing a second read operation in response to receiving a second set of commands; When the second read operation is executed after the first read operation, an execution time of the second read operation is defined as a first time, and an average value of a current flowing through the first bonding pad electrode during the execution of the second read operation is defined as a first current; When the second read operation is executed after the execution of the second read operation, an execution time of the second read operation is defined as a second time, and an average value of a current flowing through the first bonding pad electrode during the execution of the second read operation is defined as a second current, The first time is less than the second time, or the first current is less than the second current. Semiconductor memory device.

9. a memory string having a plurality of memory transistors connected in series; a plurality of first wirings connected to gate electrodes of the plurality of memory transistors; a plurality of second wirings electrically connected to the plurality of first wirings; Equipped with a first voltage is supplied to the second wirings at a first timing when the first read operation is completed; a second voltage is supplied to the second wirings at a second timing when the second read operation is completed; The first voltage is greater than the second voltage.

9. The semiconductor memory device according to claim 8.

10. the first command set includes first address data; the second command set includes second address data; a portion of the first command set other than the first address data includes first data; The portion of the second command set other than the second address data does not include the first data.

10. The semiconductor memory device according to claim 1.

11. the first command set includes first address data; the second command set includes second address data; A portion of the first command set other than the first address data matches a portion of the second command set other than the second address data.

10. The semiconductor memory device according to claim 1.

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